A chip with a reset circuit

Abstract

A chip containing a reset circuit, the reset circuit in the chip includes a reset threshold voltage generation module and a power-on reset signal output module; the reset threshold voltage generation module includes a power-on reset initial threshold voltage generation module and a power-on reset compensation threshold voltage generation module, wherein the direction of the power-on reset initial threshold voltage change with process-voltage-temperature (PVT) is opposite to the direction of the power-on reset compensation threshold voltage change with PVT; the reset threshold voltage generation module is used for generating a power-on reset threshold voltage, wherein the power-on reset threshold voltage is equal to the sum of the power-on reset initial threshold voltage and the power-on reset compensation threshold voltage; the power-on reset signal output module is used for outputting a power-on reset signal when the power supply voltage is greater than or equal to the power-on reset threshold voltage. It can be applied to the field of isolation chip, etc.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a chip containing a reset circuit. Background Technology

[0002] In integrated circuit design, the power-on reset (POR) circuit ensures a smooth transition and reliable initialization of the chip during the power-on phase. The POR circuit monitors the chip's power supply voltage in real time during the power-on process. When the power supply voltage rises to a stable threshold that meets the chip's operating requirements, it outputs a reset signal to trigger the reset and initialization of other functional devices inside the chip (such as the CPU, registers, peripheral interfaces, etc.).

[0003] A power-on reset (POR) circuit typically consists of transistors and resistors. When the transistor is turned on, the POR circuit triggers a power-on reset signal. At this time, the amplitude of the power supply voltage is the sum of the voltage across the resistor and the threshold voltage of the transistor. However, the threshold voltage of the transistor varies due to process-voltage-temperature (PVT) factors, which may cause the power supply voltage amplitude to trigger the power-on reset signal when the reset initialization requirements are not met, thus affecting the normal power-on of the chip. Summary of the Invention

[0004] This application provides a chip containing a reset circuit for generating a reset signal when the amplitude of the power supply voltage meets the requirements.

[0005] This application provides a chip containing a reset circuit, such as a memory chip. The chip may include a reset circuit and other functional circuits. The reset circuit can output a power-on reset signal to trigger other functional circuits to perform reset initialization. The chip's reset circuit may include a reset threshold voltage generation module and a power-on reset signal output module.

[0006] Specifically, the reset threshold voltage generation module includes a power-on reset initial threshold voltage generation module and a power-on reset compensation threshold voltage generation module, wherein the direction of change of the power-on reset initial threshold voltage with respect to the PVT is opposite to the direction of change of the power-on reset compensation threshold voltage with respect to the PVT; the reset threshold voltage generation module is used to generate a power-on reset threshold voltage, wherein the power-on reset threshold voltage is equal to the sum of the power-on reset initial threshold voltage and the power-on reset compensation threshold voltage; the power-on reset signal output module is used to output a power-on reset signal when the power supply voltage is greater than or equal to the power-on reset threshold voltage.

[0007] With the above design, the power-on reset threshold voltage of the reset threshold voltage generation module consists of two parts: the initial power-on reset threshold voltage and the compensation threshold voltage. When the transistor inside the initial power-on reset threshold voltage generation module is affected by PVT, causing the generated initial power-on reset threshold voltage to change, the compensation threshold voltage generated by the compensation threshold voltage generation module also changes with PVT. Moreover, the amplitude change direction of the initial power-on reset threshold voltage is opposite to that of the compensation threshold voltage. Therefore, the compensation threshold voltage can compensate for the difference caused by the change of the initial power-on reset threshold voltage with PVT, effectively suppressing the offset of the power-on reset threshold voltage caused by PVT, ensuring that the amplitude of the power supply voltage at the time of power-on reset signal output can meet the initialization voltage requirements of other functional devices inside the chip, and realizing the normal power-on of the chip.

[0008] In one possible design, the power-on reset initial threshold voltage generation module includes a first transistor, and the power-on reset compensation threshold voltage generation module includes a second transistor, wherein the first transistor and the second transistor are of the same type, and the power-on reset compensation threshold voltage is related to the difference between the threshold voltage of the first transistor and the threshold voltage of the second transistor.

[0009] In one possible design, the power-on reset compensation threshold voltage generation module further includes a first resistor and a second resistor.

[0010] The first resistor is connected in series between the control terminals of the first transistor and the second transistor, and the voltage across the first resistor is the difference between the threshold voltage of the first transistor and the threshold voltage of the second transistor. The second resistor, the first resistor, and the second transistor are connected in series between the power supply and the ground, and the voltage across the second resistor is the power-on reset compensation threshold voltage. The current flowing through the second resistor is the same as the current flowing through the first resistor.

[0011] With the above design, the voltage across the first resistor is the difference ΔV between the threshold voltages of the first and second transistors. The current flowing through the first resistor is ΔV divided by the resistance value of the first resistor. Since the first and second resistors are connected in series, the current amplitudes flowing through them are the same. When this current passes through the second resistor, it generates a voltage signal across it that is proportional to ΔV. Because the direction of change of the threshold voltage difference ΔV between the first and second transistors with PVT is opposite to the direction of change of the threshold voltage of the first transistor with PVT, the direction of change of the voltage across the second resistor with PVT is also opposite to the direction of change of the threshold voltage of the first transistor with PVT. The power-on reset initial threshold generation module, using the threshold voltage of the first transistor and the voltage of the second resistor, can effectively suppress the influence of the voltage amplitude PVT, ensuring that the power supply voltage amplitude at the time of power-on reset signal generation meets the initialization voltage requirements of other functional devices within the chip, thus ensuring normal power-on of the chip.

[0012] In one possible design, the power-on reset initial threshold voltage generation module is further configured to generate a power-off reset initial threshold voltage, and the power-on reset compensation threshold voltage generation module is further configured to generate a power-off reset compensation threshold voltage, wherein the direction of change of the power-off reset initial threshold voltage with respect to the PVT is opposite to the direction of change of the power-off reset compensation threshold voltage with respect to the PVT; the reset threshold voltage generation module is further configured to generate a power-off reset threshold voltage, which is equal to the sum of the power-off reset initial threshold voltage and the power-off reset compensation threshold voltage; the power-on reset signal output module is further configured to output a power-off reset signal when the power supply voltage is less than the power-off reset threshold voltage.

[0013] In one possible design, the power-on reset compensation threshold voltage generation module further includes a third resistor, a first switch, and a second switch.

[0014] Specifically, the third resistor, the second resistor, the first resistor, and the second transistor are connected in series between the power supply and the ground wire; the first terminal of the first switch is connected to the connection point of the second resistor and the third resistor, the second terminal of the first switch is connected to the control electrode of the first transistor, the control terminal of the first switch receives a first control signal, and the first switch is turned on when the first control signal is high; the first terminal of the second switch is connected to the connection point of the first resistor and the second resistor, the second terminal of the second switch is connected to the control electrode of the first transistor, the control terminal of the second switch receives a second control signal, and the second switch is turned on when the second control signal is high; wherein, the states of the first control signal and the second control signal are opposite, and the level states of the first control signal and the second control signal are related to the power-on reset signal.

[0015] With the above design, the first and second control signals are feedback signals to the power-on reset signal, and their signal states are opposite. Therefore, the states of the first and second switches are opposite. Taking the case where the power-on reset signal is not triggered (the first control signal is low and the second control signal is high) as an example, the power-on reset threshold voltage is composed of the voltages across the second and third resistors and the threshold voltage of the first transistor. When the reset circuit outputs the power-on reset signal, the change in the state of the power-on reset signal causes the states of the two control signals to reverse. At this time, the power-off reset threshold voltage is composed of the voltage across the third resistor and the threshold voltage of the first transistor. Through the above circuit structure, different values ​​can be configured for the power-on reset threshold voltage and the power-off reset threshold voltage.

[0016] In one possible design, the power-on reset initial threshold voltage generation module further includes a current mirror module.

[0017] Specifically, the input terminal of the current mirror module, the third resistor, the second resistor, the first resistor, and the second transistor are connected in series between the power supply and the ground; the output terminal of the current mirror module and the first transistor are connected in series between the power supply and the ground; the current mirror module is used to generate a first current based on the amplitude of the power supply voltage, and proportionally replicate the first current into a second current and output it, wherein the power-on reset initial threshold voltage is the sum of the voltage drop at the input terminal of the current mirror module and the threshold voltage of the first transistor.

[0018] With the above design, the current mirror module consists of at least two transistors. The transistor connected to the third resistor serves as the input terminal of the current mirror module, and the transistor connected to the first transistor serves as the output terminal. The current mirror module can proportionally replicate the current at the input terminal and output it through the output terminal. Using this circuit structure, after power-on, the power supply voltage is divided by the transistor at the input terminal of the current mirror module, the second transistor, and the three resistors. Since the power supply voltage is mainly divided by two transistors, the three resistors can be low-resistance devices, which helps to reduce the circuit size and cost. Furthermore, using low-resistance devices can further reduce the static losses of the circuit.

[0019] In one possible design, the power-on reset signal output module includes: a Schmitt trigger, a first inverter, and a second inverter.

[0020] In this design, the input terminal of the Schmitt trigger is connected to the output terminal of the current mirror module, and the output terminal of the Schmitt trigger is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the control terminal of the second switch. The input terminal of the second inverter is connected to the output terminal of the first inverter, and the output terminal of the second inverter is connected to the control terminal of the first switch. With this design, the first and second inverters are connected in series. Based on the operating characteristics of inverters, the first and second inverters can output two control signals with opposite signal states, and these two control signals can be used to control the switching states of the first and second switches respectively.

[0021] In one possible design, the first transistor and the second transistor are N-channel metal-oxide-semiconductor field-effect transistors.

[0022] Specifically, the drain of the first transistor is connected to the power supply through the output terminal of the current mirror module, the source of the first transistor is grounded, and the gate of the first transistor is connected to the connection point of the first resistor and the second resistor through the second switch, and also connected to the connection point of the third resistor and the second resistor through the first switch; the drain of the second transistor is connected to the power supply through the first resistor, the second resistor, the third resistor and the input terminal of the current mirror module, the source of the second transistor is grounded, and the gate of the second transistor is connected to the drain of the second transistor.

[0023] In one possible design, the first transistor and the second transistor are P-channel metal-oxide-semiconductor field-effect transistors.

[0024] Specifically, the drain of the first transistor is grounded through the output terminal of the current mirror module, the source of the first transistor is connected to the power supply, and the gate of the first transistor is connected to the connection point of the first resistor and the second resistor through the second switch, and also connected to the connection point of the third resistor and the second resistor through the first switch; the drain of the second transistor is grounded through the first resistor, the second resistor, the third resistor and the input terminal of the current mirror module, the source of the second transistor is connected to the power supply, and the gate of the second transistor is connected to the drain of the second transistor.

[0025] In one possible design, the first transistor and the second transistor are bipolar junction transistors.

[0026] Specifically, the collector of the first transistor is connected to the power supply through the output terminal of the current mirror module, the emitter of the first transistor is grounded, and the base of the first transistor is connected to the connection point of the first resistor and the second resistor through the second switch, and also connected to the connection point of the third resistor and the second resistor through the first switch; the collector of the second transistor is connected to the power supply through the first resistor, the second resistor, the third resistor and the input terminal of the current mirror module, the emitter of the second transistor is grounded, and the base of the second transistor is connected to the collector of the second transistor.

[0027] In one possible design, the first transistor and the second transistor are insulated-gate bipolar transistors.

[0028] Specifically, the collector of the first transistor is connected to the power supply through the output terminal of the current mirror module, the emitter of the first transistor is grounded, and the gate of the first transistor is connected to the connection point of the first resistor and the second resistor through the second switch, and also connected to the connection point of the third resistor and the second resistor through the first switch; the collector of the second transistor is connected to the power supply through the first resistor, the second resistor, the third resistor and the input terminal of the current mirror module, the emitter of the second transistor is grounded, and the gate of the second transistor is connected to the collector of the second transistor.

[0029] In one possible design, the current mirror module includes a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are of the same type.

[0030] In practical applications, if the third transistor and the fourth transistor are P-channel metal-oxide-semiconductor field-effect transistors, the gate and drain of the third transistor are connected to the gate of the fourth transistor, the source of the third transistor is connected to the power supply, the drain of the third transistor is grounded through the third resistor, the second resistor, the first resistor and the second transistor, the source of the fourth transistor is connected to the power supply, and the drain of the fourth transistor is grounded through the first transistor.

[0031] If the third transistor and the fourth transistor are N-channel metal-oxide-semiconductor field-effect transistors, the gate and drain of the third transistor are connected to the gate of the fourth transistor, the source of the third transistor is grounded, and the drain of the third transistor is connected to the power supply through the third resistor, the second resistor, the first resistor, and the second transistor. The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the power supply through the first transistor. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a POR circuit structure provided in an embodiment of this application; Figure 2 A schematic diagram of a reset circuit provided in an embodiment of this application. Figure 1 ; Figure 3 A schematic diagram of a power-on reset compensation threshold voltage generation module provided in this application embodiment. Figure 1 ; Figure 4 A schematic diagram of a power-on reset compensation threshold voltage generation module provided in this application embodiment. Figure 2 ; Figure 5 A schematic diagram of a reset circuit provided in an embodiment of this application. Figure 2 ; Figure 6 A schematic diagram of a reset circuit provided in an embodiment of this application. Figure 3 ; Figure 7 A schematic diagram of a reset circuit provided in an embodiment of this application. Figure 4 ; Figure 8A schematic diagram of a reset circuit provided in an embodiment of this application. Figure 5 ; Figure 9 A schematic diagram of a reset circuit provided in an embodiment of this application. Figure 6 . Detailed Implementation

[0034] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0035] The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "at least one" refers to one or more, where "multiple" refers to two or more. Therefore, in the embodiments of this invention, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0036] It should be noted that in the embodiments of this application, "connection" refers to electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as the connection between A and B. Alternatively, it can be a direct connection between A and C, a direct connection between C and B, with A and B connected through C.

[0037] It should be noted that the switches in the embodiments of this application are mainly fully controlled switching devices. The fully controlled switching devices can be one or more of various types of switches, such as relays, metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), gallium nitride field effect transistors (GaN), and silicon carbide (SiC) power transistors. These will not be listed one by one in the embodiments of this application.

[0038] Specifically, each fully controlled switching device may include a first electrode, a second electrode, and a control electrode, wherein the control electrode is used to control the switching on or off of the fully controlled switching device. When the fully controlled switching device is on, current can be transferred between the first and second electrodes; when the fully controlled switching device is off, no current can be transferred between the first and second electrodes. Taking a MOSFET as an example, the control electrode of the fully controlled switching device is the gate, the first electrode can be the source of the switching device, and the second electrode can be the drain of the switching device; alternatively, the first electrode can be the drain of the switching device, and the second electrode can be the source of the switching device.

[0039] Currently, electronic devices are equipped with one or more functional chips, such as memory chips. When these chips are required to run, the POR circuit inside the chip is used to perform a power-on reset initialization operation on the functional devices inside the chip.

[0040] See Figure 1 The diagram shown is a schematic of one type of POR circuit. Figure 1 As shown, during the chip's power-on process, the power supply voltage VDD gradually increases. When VDD exceeds the turn-on threshold voltage of transistor M1, transistor M1 turns on. However, the current is low at this time, and the voltage drop across the resistor is less than the turn-on threshold voltage of transistor M3. Therefore, transistor M3 is off, and node VC is at a high level. When VDD exceeds the turn-on threshold voltages of both transistors M1 and M3, transistor M3 turns on. During the turn-on process, the current flowing through transistor M3 gradually increases, and the current in transistor M3 also gradually increases with the increase of VDD. Transistors M1 and M2 form a current mirror, and transistor M2 outputs a mirrored current. In this case, transistor M2 can be considered a current source. Since transistors M3 and M2 are connected in series, when the current of transistor M3 is greater than the mirror current of transistor M2, in order to achieve a fixed amplitude current output from the current source, transistor M2 will pull the potential of node VC low. The input signal state of the Schmitt trigger connected to the back end of node VC changes, and therefore the output signal state of the Schmitt trigger also reverses, causing the POR circuit to output a high-level power-on reset signal to trigger other functional signals inside the chip to perform power-on reset initialization, ensuring the safe power-on of the chip.

[0041] See Figure 1 As shown, when the POR circuit outputs a power-on reset signal, the voltage amplitude of the power supply circuit VDD can be changed from... Figure 1The three arrows in the diagram represent the voltage drop components. When the POR circuit outputs a power-on reset signal, the power supply voltage VDD is the sum of the turn-on threshold voltage of transistor M1, the resistor voltage drop, and the turn-on threshold voltage of transistor M3. Ideally, the turn-on threshold voltages of transistors M1 and M3 remain constant. However, in actual use, these voltages change with the PVT, causing the amplitude of the power supply voltage VDD to change when the POR circuit triggers the power-on reset signal. If the power supply voltage VDD decreases, the POR circuit may trigger the power-on reset signal when the power supply voltage amplitude does not meet the requirements, potentially causing the system to operate in an undervoltage state. Conversely, if the power supply voltage VDD increases, the power supply voltage may stabilize, but the system may still not start.

[0042] To address the aforementioned issues, this application provides a chip containing a reset circuit, which generates a reset signal when the amplitude of the power supply voltage meets the requirements.

[0043] like Figure 2 The image shows a chip with a reset circuit provided in an embodiment of this application. See also... Figure 2 As shown, the reset circuit may include: a reset threshold voltage generation module and a power-on reset signal output module.

[0044] The reset threshold voltage generation module includes a power-on reset initial threshold voltage generation module and a power-on reset compensation threshold voltage generation module. The reset threshold voltage generation module generates the power-on reset threshold voltage. The power-on reset signal output module outputs a power-on reset signal when the power supply voltage is greater than or equal to the power-on reset threshold voltage. The direction of change of the power-on reset initial threshold voltage with respect to PVT is opposite to the direction of change of the power-on reset compensation threshold voltage with respect to PVT; the power-on reset threshold voltage is equal to the sum of the power-on reset initial threshold voltage and the power-on reset compensation threshold voltage.

[0045] When the reset circuit provided in this application generates a power-on reset signal, a transistor is generally configured in the power-on reset initial threshold generation module. When the transistor changes with the PVT, causing the generated power-on reset initial threshold voltage to change, the power-on reset compensation threshold voltage generated by the power-on reset compensation threshold voltage generation module will also change with the PVT. Moreover, the direction of the change of the power-on reset initial threshold voltage with the PVT is opposite to the direction of the change of the power-on reset compensation threshold voltage with the PVT. Therefore, the power-on reset compensation threshold voltage can compensate for the change value of the power-on reset initial threshold voltage, reduce the offset of the power-on reset threshold voltage affected by the PVT, and realize the normal power-on of the chip.

[0046] The compensation process for the power-on reset compensation threshold voltage will be explained in detail below, taking into account the specific circuit structure.

[0047] In practical applications, the power-on reset initial threshold voltage generation module is equipped with at least a first transistor, and the power-on reset compensation threshold voltage generation module is equipped with at least a second transistor. The power-on reset compensation threshold voltage generation module is also equipped with a first resistor R1 and a second resistor R2. The first transistor and the second transistor are of the same type.

[0048] See Figure 3 As shown, the first resistor R1 is connected in series between the control electrodes of the first and second transistors. Therefore, the voltage across the first resistor R1 is the voltage difference ΔV between the threshold voltages of the first and second transistors. The second resistor R2, the first resistor R1, and the second transistor are connected in series between the power supply VDD and the ground. The threshold voltage of the first transistor is the initial threshold voltage upon power-on reset, and the voltage across the second resistor R2 is the compensation threshold voltage upon power-on reset.

[0049] In practical applications, the power-on reset compensation threshold voltage is related to the voltage difference ΔV between the threshold voltages of the first transistor and the second transistor. Specifically, the power-on reset threshold voltage is the sum of the threshold voltage of the first transistor and the voltage U2 across the second resistor R2, where the threshold voltage of the first transistor is the initial power-on reset threshold voltage, and the voltage U2 across the second resistor R2 is the power-on reset compensation threshold voltage. When the first and second transistors are turned on, the voltage U1 across the first resistor R1 is the voltage difference ΔV between the threshold voltages of the first transistor and the second transistor M2. Therefore, the current flowing through the first resistor R1 is I = U1 / R1 = (Vgs1 - Vgs2) / R1 = ΔV / R1. Since the first resistor R1 and the second resistor R2 are connected in series, the current flowing through the first resistor R1 and the second resistor R2 is the same, and the voltage U2 across the second resistor R2 is U2 = I. R2=ΔV R2 / R1, therefore, the power-on reset compensation threshold voltage is in a fixed proportion to the voltage difference ΔV between the threshold voltage of the first transistor and the threshold voltage of the second transistor, and the proportion is related to the resistance values ​​of the first resistor R1 and the second resistor R2.

[0050] In practical applications, since the threshold voltage of the first transistor changes in the opposite direction to the change in voltage difference ΔV, the voltage U2 across the second resistor R2, which is proportional to the voltage difference ΔV, also changes in the opposite direction to the change in threshold voltage of the first transistor with respect to PVT. Therefore, the voltage U2 across the second resistor R2 can effectively compensate for the change in threshold voltage of the first transistor with respect to PVT, ensuring that the triggering time of the power-on reset signal meets the requirements and enabling the chip to power on normally.

[0051] It should be noted that, Figure 3The transistor connection structure shown is only an example. In actual applications, depending on the type of transistor, the transistor may have other connection methods.

[0052] In practical applications, the initial threshold voltage of power-on reset during the power-on reset process can be compensated by the second transistor, the first resistor R1, and the second resistor R2. In practical applications, the above reset circuit can also realize power-off reset.

[0053] Specifically, the power-on reset initial threshold voltage generation module is also used to generate the power-off reset initial threshold voltage; the power-on reset compensation threshold voltage generation module is also used to generate the power-off reset compensation threshold voltage; the reset threshold voltage generation module is also used to generate the power-off reset threshold voltage; and the power-on reset signal output module is also used to output a power-off reset signal when the power supply voltage is less than the power-off reset threshold voltage. The direction of change of the power-off reset initial threshold voltage with respect to PVT is opposite to the direction of change of the power-off reset compensation threshold voltage with respect to PVT, and the power-off reset threshold voltage is equal to the sum of the power-off reset initial threshold voltage and the power-off reset compensation threshold voltage.

[0054] In some implementations, different voltage values ​​can be configured for the power-on reset threshold voltage and the power-off reset threshold voltage to achieve hysteresis between the power-on reset threshold voltage and the power-off reset threshold voltage. To achieve the above function, the power-on reset compensation threshold voltage generation module also includes a third resistor R3, a first switch K1, and a second switch K2. See also Figure 4 As shown, the third resistor R3, the second resistor R2, the first resistor R2, and the second transistor are connected in series between the power supply and ground. The first terminal of the first switch K1 is connected to the junction of the second resistor R2 and the third resistor R3, and the second terminal of the first switch K1 is connected to the control electrode of the first transistor. The first terminal of the second switch K2 is connected to the junction of the first resistor R1 and the second resistor R2, and the second terminal of the second switch K2 is connected to the control electrode of the first transistor.

[0055] In this circuit, the control terminal of the first switch K1 receives the first control signal, and the first switch K1 is turned on when the first control signal is high. The control terminal of the second switch K2 receives the second control signal, and the second switch K2 is turned on when the second control signal is high. The states of the first control signal and the second control signal are opposite, and the level states of the first control signal and the second control signal are related to the state of the power-on reset signal feedback signal.

[0056] In practical applications, the third resistor R3 is used to generate the power-down reset compensation threshold. By controlling the cutoff and turn-on of the first switch K1 and the second switch K2, different bias voltages can be configured for the control electrode of the first transistor, thereby controlling the turn-on and cutoff times of the first transistor and achieving hysteresis of the power-on reset threshold voltage and the power-down reset threshold voltage.

[0057] Specifically, when the chip is powered on, the second switch K2 can be closed and the first switch K1 can be opened. At this time, the voltage across the second resistor R2 and the third resistor R3 is the power-on reset compensation threshold voltage, and the threshold voltage of the first transistor is the initial power-on reset threshold voltage. Therefore, the voltage across the second resistor R2 and the third resistor R3, along with the threshold voltage of the first transistor, constitutes the power-on reset threshold voltage. When the POR circuit outputs a power-on reset signal, the state of the power-on reset signal changes, thus changing the switching states of the first switch K1 and the second switch K2. At this time, the second switch K2 is open, and the first switch K1 is closed. The voltage across the third resistor R3 is the power-down reset compensation threshold voltage. The threshold voltage of the first transistor is the initial power-down reset threshold voltage. Therefore, the voltage across the third resistor R3, along with the threshold voltage of the first transistor, constitutes the power-down reset threshold voltage. Thus, the power-on reset threshold voltage and the power-down reset threshold voltage are composed of the voltage drops of different devices, thereby achieving hysteresis in the power-on reset threshold voltage and the power-down reset threshold voltage.

[0058] In some implementations, to reduce power consumption in the reset circuit, the power-on reset initial threshold voltage generation module further includes a current mirror module. The input terminal of the current mirror module, a third resistor R3, a second resistor R2, a first resistor R1, and a second transistor are connected in series between the power supply and ground. The output terminal of the current mirror module and the first transistor are connected in series between the power supply and ground. The current mirror module generates a first current based on the amplitude of the power supply voltage, proportionally replicates the first current as a second current, and outputs it. The power-on reset initial threshold voltage is the sum of the voltage drop at the input terminal of the current mirror module and the threshold voltage of the first transistor.

[0059] In practical applications, a current mirror module consists of two identical transistors. Taking a current mirror module including a third and fourth transistor as an example, the third transistor can be connected in series with the branch containing the third resistor, forming the input terminal of the current mirror module. The fourth transistor is connected in series with the first transistor, forming the output terminal of the current mirror module. Based on the proportional current replication effect of the current mirror module, the current value output by the current mirror module is proportional to the current value input by the current mirror.

[0060] The following describes in detail the structure of the reset circuit when the first transistor and the second transistor are selected from different transistor types, with reference to the embodiments.

[0061] Example 1: The first transistor M1 and the second transistor M2 are N-channel MOSFETs.

[0062] See Figure 5As shown, the third transistor M3 and the fourth transistor M4 can be P-type MOSFETs. The gate and drain of the third transistor M3 are connected to the gate of the fourth transistor M4. The source of the third transistor M3 is connected to the power supply. The drain of the third transistor M3 is connected to the drain of the second transistor M2 through the third resistor R3, the second resistor R2, and the first resistor R1. The source of the fourth transistor M4 is connected to the power supply, and the drain of the fourth transistor M4 is connected to the drain of the first transistor M1. The source of the first transistor M1 is grounded. The gate of the first transistor M1 is connected to the connection point of the first resistor R1 and the second resistor R2 through the second switch K2, and also to the connection point of the third resistor R3 and the second resistor R2 through the first switch K1. The source of the second transistor M2 is grounded, and the gate of the second transistor M2 is connected to the drain of the second transistor M2. The connection point A between the first transistor M1 and the fourth transistor M4 is sequentially connected to a Schmitt trigger, a first inverter, and a second inverter.

[0063] It should be noted that, Figure 5 The Schmitt trigger, first inverter, and second inverter structures shown are merely examples. In practical applications, other circuit structures with the above functions can also be used, and this application does not impose any specific limitations on them.

[0064] See Figure 5 As shown, the first control signal and the second control signal are the feedback signals of the second inverter and the first inverter, respectively. When the power supply is off, the first control signal is at a low level and the second control signal is at a high level. At this time, the second switch K2 is closed and the first switch K1 is open. When the power supply is on, if the power supply voltage VDD is less than the threshold voltage Vgs3 of the third transistor M3 and the threshold voltage Vgs2 of the second transistor M2, the second transistor M2 and the third transistor M3 are turned off. Ideally, no current flows through the branch connected in series with the second transistor M2 and the third transistor M3.

[0065] When leakage current exists in the aforementioned branches, the third transistor M3 and the fourth transistor M4 form a current mirror with a mirror ratio of 6:1, while the first transistor M1 and the second transistor M2 can be considered as a current mirror with a mirror ratio of 8:1. In this case, the third transistor M3 forms the input terminal of the 6:1 current mirror, and the current in the branch containing the third transistor M3 is the input current of this current mirror. The fourth transistor M4 forms the output terminal of the 6:1 current mirror, and the current in the branch containing the fourth transistor M4 is the output current of this current mirror. The second transistor M2 forms the input terminal of the 8:1 current mirror, and the current in the branch containing the second transistor M2 is the input current of this current mirror. The first transistor M1 forms the output terminal of this current mirror, and the current in the branch containing the first transistor M1 is the output current of this current mirror. The equivalent circuit of the reset circuit can be found in [reference needed]. Figure 6As shown, the output of the 6:1 current mirror can be regarded as a pull-up current source, and the output of the 8:1 current mirror can be regarded as a pull-down current source. Since the second transistor M2 and the third transistor M3 are connected in series, the current of the second transistor M2 and the third transistor M3 are the same. Therefore, the current of the fourth transistor M4, which is output proportionally through the 6:1 current mirror, is greater than the current of the second transistor M1, which is output proportionally through the 6:1 current mirror. That is, the current of the pull-up current source is greater than the current of the pull-down current source, and node A is set to a high level.

[0066] See also Figure 5 As shown, when the power supply voltage VDD is greater than the threshold voltage Vgs3 of the third transistor M3 and the threshold voltage Vgs2 of the second transistor M2, current flows through the branch where the second transistor M2 and the third transistor M3 are connected in series. The fourth transistor M4 mirrors the current of the third transistor M3 proportionally, that is, it replicates the first current of the third transistor M3 as the second current and outputs it. When the voltage drop generated by the first resistor R1 is low, the first transistor M1 can still be regarded as forming a current mirror with the second transistor M2. Therefore, the current flowing through the second transistor M2 is still lower than the current of the fourth transistor M4. When the power supply voltage VDD continues to rise, causing the voltage drop generated by the first resistor R1 to increase, the current flowing through the first transistor M1 increases due to the increased voltage of the first resistor R1. When the current of the pull-down current source is greater than the current of the pull-up current source, the pull-up current source will set the potential of node A to a low level in order to achieve a constant output current. The signal state of node A is reversed, and the output signal of the Schmitt trigger will also be reversed. The first inverter outputs a low-level signal, and the second inverter outputs a high-level signal. These signals are then output to the functional devices in the chip, the first switch K1, and the second switch K2, respectively. After receiving the signal from the inverter, the functional devices in the chip begin to perform power-on reset initialization processing.

[0067] Based on the above description, when the state of node A switches from high level to low level, the circuit outputs a power-on reset signal. At this time, the amplitude of the power supply voltage VDD satisfies the following formula:

[0068] Where I is the current in the branch connecting the second transistor M2 and the third transistor M3 in series, and Vgs1 is the threshold voltage of the first transistor. Since the first resistor R1 is connected in series with the second resistor R2 and the third resistor R3, the current in the second resistor R2 and the third resistor R3 is the same. See [reference needed]. Figure 5 From the connection position of the first resistor R1, it can be seen that the current in the first resistor R1 satisfies the following formula:

[0069] For ease of description, the voltage difference between the threshold voltage Vgs1 of the first transistor M1 and the threshold voltage Vgs2 of the second transistor M2 is referred to as ΔVgs. Combining the current calculation formula above, when the state of node A switches from a high level to a low level, triggering the back-end circuit to generate a power-on reset signal, the amplitude of the power supply voltage VDD satisfies the following formula:

[0070] Where N is greater than 0, the threshold voltage Vgs3 of the third transistor M3 constitutes the input voltage drop of the current mirror module, which together with the threshold voltage Vgs1 of the first transistor M1 constitutes the initial threshold voltage for power-on reset. The voltages across the second resistor R2 and the third resistor R3 constitute the compensation threshold voltage for power-on reset. As can be seen from the above formula, the compensation threshold voltage for power-on reset is N times the voltage difference ΔVgs. The direction of change of the voltage difference ΔVgs with PVT is exactly opposite to the direction of change of the threshold voltage of the transistor with PVT. Therefore, the compensation threshold voltage for power-on reset, which is proportional to the voltage difference ΔVgs, can effectively compensate for the offset of the initial threshold voltage for power-on reset caused by PVT, and can ensure that the amplitude of the power supply voltage at the trigger time of the power-on reset signal can meet the requirements.

[0071] In practical applications, the following is adopted: Figure 5 In the reset circuit shown, the power supply voltage VDD is divided by a series branch consisting of the third transistor M3, the third resistor R3, the second resistor R2, the first resistor R1, and the second transistor M2. Because two transistors are connected in series for voltage division, the three resistors in this branch can be low-resistance components, effectively reducing the circuit's size and cost. Furthermore, using low-resistance components also reduces losses in the resistors during circuit operation, thus minimizing static losses.

[0072] In this application, by Figure 5 The reset circuit structure shown can also be compensated during the power-down process; see [link / reference]. Figure 5As shown, when the reset circuit outputs a power-on reset signal, the first control signal changes from a low level to a high level, and the second control signal changes from a high level to a low level. Therefore, the first switch K1 changes from open to closed, and the second switch K2 changes from closed to open. When the power supply voltage VDD drops, if the voltage drop across the first resistor R1 and the second resistor R2 still makes the current of the first transistor M1 equal to the current of the fourth transistor M4, then node A remains in a low level state, and the output signal state of the circuit remains unchanged. When the power supply voltage VDD continues to decrease, causing the voltage drop across the first resistor R1 and the second resistor R2 to continue to decrease, if the voltage drop across the first resistor R1 and the second resistor R2 causes the current of the first transistor M1 to be lower than the current of the fourth transistor M4, node A changes from a low-level state to a high-level signal state. The Schmitt trigger output signal is inverted, the first inverter outputs a high-level signal, and the second inverter outputs a low-level signal. These signals are then output to the functional devices within the chip, the first switch K1, and the second switch K2, respectively. Upon receiving the signals from the inverters, the functional devices within the chip perform a power-down reset. Simultaneously, upon receiving the signals, the first switch K1 and the second switch K2 switch their states to prepare for the next power-on reset.

[0073] Based on the above description, when the state of node A switches from low to high, triggering the back-end circuit to generate a power-down reset signal, the amplitude of the power supply voltage VDD satisfies the following formula:

[0074] See Figure 5 As shown, since the third resistor R3 is connected in series with the first resistor R1 and the second resistor R2, the current in the third resistor R3 is the same as the current in the first resistor R1 and the current in the second resistor R2. (See [reference]) Figure 5 From the connection positions of the first resistor R1 and the second resistor R2, it can be seen that the current in the first resistor R1 and the second resistor R2 satisfies the following formula:

[0075] Based on the above current calculation formula, when the state of node A switches from a low level to a high level, triggering the back-end circuit to generate a power-down reset signal, the amplitude of the power supply voltage VDD satisfies the following formula:

[0076] Where M is greater than 0, the threshold voltage Vgs3 of the third transistor M3 and the threshold voltage Vgs1 of the first transistor M1 constitute the initial threshold voltage for power-down reset. The voltage across the third resistor R3 constitutes the compensation threshold voltage for power-down reset. Referring to the above formula, the compensation threshold voltage for power-down reset is N times the voltage difference ΔVgs. The direction of change of the difference ΔVgs with PVT is exactly opposite to the direction of change of the transistor's threshold voltage with PVT. Therefore, a compensation threshold voltage for power-down reset that is proportional to the voltage difference ΔVgs can effectively compensate for the offset of the initial voltage for power-down reset caused by the change in PVT, ensuring that the amplitude of the power supply voltage at the trigger moment of the power-down reset signal meets the requirements. Furthermore, combining the above calculation formulas for the power supply voltage VDD at the trigger moment of the power-on reset signal and the power supply voltage VDD at the trigger moment of the power-down reset signal, it can be seen that the amplitudes of the power supply voltages when triggering the power-on reset signal and the power-down reset signal are composed of different components and their values ​​are not the same. This also allows for hysteresis of the power-on reset threshold voltage and the power-down amplitude threshold voltage.

[0077] Example 2: The first transistor M1 and the second transistor M2 are P-channel MOSFETs.

[0078] See Figure 7 As shown, the third transistor M3 and the fourth transistor M4 can be N-channel MOSFETs. The source of the first transistor M1 is connected to the power supply, and the drain of the first transistor M1 is connected to the drain of the fourth transistor M4. The gate of the first transistor M1 is connected to the connection point of the first resistor R1 and the second resistor R2 through the second switch K2, and also connected to the connection point of the third resistor R3 and the second resistor R2 through the first switch K1. The source of the second transistor M2 is connected to the power supply, and the drain of the second transistor M2 is connected to the drain of the third transistor M3 through the first resistor R1, the second resistor R2, and the third resistor R3. The gate of the second transistor M2 is connected to the drain of the second transistor M2. The gate and drain of the third transistor M3 are connected to the gate of the fourth transistor M4, and the source of the third transistor M3 is grounded. The source of the fourth transistor M4 is grounded. The connection point A of the first transistor M1 and the fourth transistor M4 is sequentially connected to a Schmitt trigger, a first inverter, and a second inverter.

[0079] It should be noted that, Figure 7 The reset circuit shown utilizes the principle of voltage compensation based on the power-on reset compensation threshold voltage. Figure 5 The reset circuit shown operates on the same principle, and will not be described again here.

[0080] Example 3: The first transistor M1 and the second transistor M2 are selected from BJTs.

[0081] In practical applications, the third transistor M3 and the fourth transistor M4 can still be MOSFETs. Taking the third transistor M3 and the fourth transistor M4 as P-channel MOSFETs as an example, see [link to relevant documentation]. Figure 8 As shown, the gate and drain of the third transistor M3 are connected to the gate of the fourth transistor M4. The source of the third transistor M3 is connected to the power supply. The drain of the third transistor M3 is connected to the collector of the second transistor M2 through the third resistor R3, the second resistor R2, and the first resistor R1. The source of the fourth transistor M4 is connected to the power supply, and the drain of the fourth transistor M4 is connected to the collector of the first transistor M1. The emitter of the first transistor M1 is grounded, and the base of the first transistor M1 is connected to the connection point of the first resistor R1 and the second resistor R2 through the second switch K2, and also to the connection point of the third resistor R3 and the second resistor R2 through the first switch K1. The emitter of the second transistor M2 is grounded, and the base of the second transistor M2 is connected to the collector of the second transistor M2. The connection point A between the first transistor M1 and the fourth transistor M4 is sequentially connected to a Schmitt trigger, a first inverter, and a second inverter.

[0082] It should be noted that, Figure 8 The reset circuit shown utilizes the principle of voltage compensation based on the power-on reset compensation threshold voltage. Figure 5 The reset circuit shown operates on the same principle, and will not be described again here.

[0083] Example 4: The first transistor M1 and the second transistor M2 are IGBTs.

[0084] In practical applications, the third transistor M3 and the fourth transistor M4 can still be MOSFETs. Taking the third transistor M3 and the fourth transistor M4 as P-channel MOSFETs as an example, see [link to relevant documentation]. Figure 9 As shown, the gate and drain of the third transistor M3 are connected to the gate of the fourth transistor M4. The source of the third transistor M3 is connected to the power supply. The drain of the third transistor M3 is connected to the collector of the second transistor M2 through the third resistor R3, the second resistor R2, and the first resistor R1. The source of the fourth transistor M4 is connected to the power supply, and the drain of the fourth transistor M4 is connected to the collector of the first transistor M1. The emitter of the first transistor M1 is grounded. The gate of the first transistor M1 is connected to the connection point of the first resistor R1 and the second resistor R2 through the second switch K2, and also to the connection point of the third resistor R3 and the second resistor R2 through the first switch K1. The emitter of the second transistor M2 is grounded, and the gate of the second transistor M2 is connected to the collector of the second transistor M2. The connection point A between the first transistor M1 and the fourth transistor M4 is sequentially connected to a Schmitt trigger, a first inverter, and a second inverter.

[0085] It should be noted that, Figure 9The reset circuit shown utilizes the principle of voltage compensation based on the power-on reset compensation threshold voltage. Figure 5 The reset circuit shown operates on the same principle, and will not be described again here.

[0086] It should be noted that, Figures 5 to 9 The reset circuit shown is for illustrative purposes only. In actual applications, other devices can be used as transistors in the reset circuit, and this application does not impose any restrictions on them.

[0087] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A chip containing a reset circuit, characterized in that, The reset circuit includes: a reset threshold voltage generation module and a power-on reset signal output module; The reset threshold voltage generation module includes a power-on reset initial threshold voltage generation module and a power-on reset compensation threshold voltage generation module, wherein the direction of the power-on reset initial threshold voltage change with process-voltage-temperature (PVT) is opposite to the direction of the power-on reset compensation threshold voltage change with the PVT. The reset threshold voltage generation module is used to generate a power-on reset threshold voltage, wherein the power-on reset threshold voltage is equal to the sum of the power-on reset initial threshold voltage and the power-on reset compensation threshold voltage; The power-on reset signal output module is used to output a power-on reset signal when the power supply voltage is greater than or equal to the power-on reset threshold voltage.

2. The chip according to claim 1, characterized in that, The power-on reset initial threshold voltage generation module includes a first transistor, and the power-on reset compensation threshold voltage generation module includes a second transistor. The first transistor and the second transistor are of the same type, and the power-on reset compensation threshold voltage is related to the difference between the threshold voltage of the first transistor and the threshold voltage of the second transistor.

3. The chip according to claim 2, characterized in that, The power-on reset compensation threshold voltage generation module also includes a first resistor and a second resistor; The first resistor is connected in series between the control electrodes of the first transistor and the second transistor, wherein the voltage across the first resistor is the difference between the threshold voltage of the first transistor and the threshold voltage of the second transistor. The second resistor, the first resistor, and the second transistor are connected in series between the power supply and the ground. The voltage across the second resistor is the power-on reset compensation threshold voltage. The current flowing through the second resistor is the same as the current flowing through the first resistor.

4. The chip according to claim 3, characterized in that, The power-on reset initial threshold voltage generation module is further configured to generate a power-off reset initial threshold voltage, and the power-on reset compensation threshold voltage generation module is further configured to generate a power-off reset compensation threshold voltage, wherein the direction of change of the power-off reset initial threshold voltage with respect to PVT is opposite to the direction of change of the power-off reset compensation threshold voltage with respect to PVT; the reset threshold voltage generation module is further configured to generate a power-off reset threshold voltage, which is equal to the sum of the power-off reset initial threshold voltage and the power-off reset compensation threshold voltage; the power-on reset signal output module is further configured to output a power-off reset signal when the power supply voltage is less than the power-off reset threshold voltage.

5. The chip according to claim 4, characterized in that, The power-on reset compensation threshold voltage generation module also includes a third resistor, a first switch, and a second switch; The third resistor, the second resistor, the first resistor, and the second transistor are connected in series between the power supply and the ground wire; The first terminal of the first switch is connected to the connection point of the second resistor and the third resistor, the second terminal of the first switch is connected to the control electrode of the first transistor, the control terminal of the first switch receives a first control signal, and the first switch is turned on when the first control signal is high. The first terminal of the second switch is connected to the connection point of the first resistor and the second resistor, the second terminal of the second switch is connected to the control electrode of the first transistor, the control terminal of the second switch receives the second control signal, and the second switch is turned on when the second control signal is high. The first control signal and the second control signal have opposite states, and the level states of the first control signal and the second control signal are related to the power-on reset signal.

6. The chip according to claim 5, characterized in that, The power-on reset initial threshold voltage generation module also includes a current mirror module; The input terminal of the current mirror module, the third resistor, the second resistor, the first resistor, and the second transistor are connected in series between the power supply and the ground wire; The output terminal of the current mirror module and the first transistor are connected in series between the power supply and the ground line; The current mirror module is used to generate a first current based on the amplitude of the power supply voltage, and to proportionally copy the first current into a second current and output it. The power-on reset initial threshold voltage is the sum of the voltage drop at the input terminal of the current mirror module and the threshold voltage of the first transistor.

7. The chip according to claim 6, characterized in that, The power-on reset signal output module includes: a Schmitt trigger, a first inverter, and a second inverter; The input terminal of the Schmitt trigger is connected to the output terminal of the current mirror module, and the output terminal of the Schmitt trigger is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the control terminal of the second switch; The input terminal of the second inverter is connected to the output terminal of the first inverter, and the output terminal of the second inverter is connected to the control terminal of the first switch.

8. The chip according to claim 7, characterized in that, The first transistor and the second transistor are N-channel metal-oxide-semiconductor field-effect transistors; The drain of the first transistor is connected to the power supply through the output terminal of the current mirror module, the source of the first transistor is grounded, and the gate of the first transistor is connected to the connection point of the first resistor and the second resistor through the second switch and to the connection point of the third resistor and the second resistor through the first switch. The drain of the second transistor is connected to the power supply through the first resistor, the second resistor, the third resistor and the input terminal of the current mirror module, the source of the second transistor is grounded, and the gate of the second transistor is connected to the drain of the second transistor.

9. The chip according to claim 7, characterized in that, The first transistor and the second transistor are P-channel metal-oxide-semiconductor field-effect transistors; The drain of the first transistor is grounded through the output terminal of the current mirror module, the source of the first transistor is connected to the power supply, and the gate of the first transistor is connected to the connection point of the first resistor and the second resistor through the second switch and to the connection point of the third resistor and the second resistor through the first switch. The drain of the second transistor is grounded through the first resistor, the second resistor, the third resistor and the input terminal of the current mirror module, the source of the second transistor is connected to the power supply, and the gate of the second transistor is connected to the drain of the second transistor.

10. The chip according to claim 7, characterized in that, The first transistor and the second transistor are bipolar junction transistors; The collector of the first transistor is connected to the power supply through the output terminal of the current mirror module, the emitter of the first transistor is grounded, and the base of the first transistor is connected to the connection point of the first resistor and the second resistor through the second switch and to the connection point of the third resistor and the second resistor through the first switch. The collector of the second transistor is connected to the power supply through the first resistor, the second resistor, the third resistor and the input terminal of the current mirror module. The emitter of the second transistor is grounded and the base of the second transistor is connected to the collector of the second transistor.

11. The chip according to claim 7, characterized in that, The first transistor and the second transistor are insulated-gate bipolar transistors; The collector of the first transistor is connected to the power supply through the output terminal of the current mirror module, the emitter of the first transistor is grounded, and the gate of the first transistor is connected to the connection point of the first resistor and the second resistor through the second switch and to the connection point of the third resistor and the second resistor through the first switch. The collector of the second transistor is connected to the power supply through the first resistor, the second resistor, the third resistor and the input terminal of the current mirror module. The emitter of the second transistor is grounded and the gate of the second transistor is connected to the collector of the second transistor.

12. The chip according to any one of claims 8 to 10, characterized in that, The current mirror module includes a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are of the same type. If the third transistor and the fourth transistor are P-channel metal-oxide-semiconductor field-effect transistors, the gate and drain of the third transistor are connected to the gate of the fourth transistor, the source of the third transistor is connected to the power supply, the drain of the third transistor is grounded through the third resistor, the second resistor, the first resistor and the second transistor, the source of the fourth transistor is connected to the power supply, and the drain of the fourth transistor is grounded through the first transistor. If the third transistor and the fourth transistor are N-channel metal-oxide-semiconductor field-effect transistors, the gate and drain of the third transistor are connected to the gate of the fourth transistor, the source of the third transistor is grounded, and the drain of the third transistor is connected to the power supply through the third resistor, the second resistor, the first resistor, and the second transistor. The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the power supply through the first transistor.

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