Interface module transmitting end and signal conditioning method

Abstract

The present disclosure provides an interface module transmitting end and a signal adjusting method. An embodiment of the interface module transmitting end comprises a driver, which comprises: a signal input end configured to receive an input signal; a differential signal output end configured to output a differential signal; a main driving unit connected between the signal input end and the differential signal output end, configured to receive the input signal and generate a main output signal; a sub-driving unit connected between the signal input end and the differential signal output end, configured to receive the same input signal and generate a sub-output signal; and a delay adjusting module connected between the signal input end and the main driving unit and / or the sub-driving unit, configured to adjust the delay time of the sub-output signal relative to the main output signal. The differential signal is a linear superposition of the main output signal and the sub-output signal. The time domain waveform parameters of the differential signal are configured to be adjusted by adjusting the amplitude relationship and / or the time relationship of the output signals of the main driving unit and the sub-driving unit.

Description

Technical Field

[0001] This disclosure relates to the field of serial communication technology, and more specifically, to an interface module transmitter and a signal conditioning method in serial communication technology. Background Technology

[0002] In high-speed serial communication systems, the interface module's transmitter (TX) serializes parallel data and transmits it to the receiver (RX) via differential signals. In some video transmission protocols that require a synchronous clock output (such as LVDS, miniLVDS, HDMI, etc.), refer to... Figure 1 As shown, the data signal is transmitted through the data channel, and the synchronization clock signal is transmitted through the clock channel. The receiving end uses this clock signal to sample and recover the data. The transmitting end connects to the receiving end. To save chip pin resources, one or more data channels typically share a single transmitting channel to transmit the clock signal. The receiving end receives this clock signal through one or more channels to achieve parallel transmission of data and the synchronization clock. The timing offset (skew) between the data signal output by the transmitting end and the synchronization clock signal typically needs to be controlled within tens to hundreds of picoseconds. The higher the transmission rate, the more stringent the skew requirement.

[0003] Therefore, there is an urgent need for an interface module transmitter that can reduce timing offset between channels. Summary of the Invention

[0004] In view of the above problems, this disclosure provides an interface module transmitter and a signal conditioning method to overcome or at least partially solve the above problems. The technical solution is as follows: In a first aspect, this disclosure provides an interface module transmitter, including a driver, the driver comprising: The signal input terminal is used to receive input signals. Differential signal output terminal, used to output differential signals; The main drive unit is connected between the signal input terminal and the differential signal output terminal, and is used to receive the input signal and generate the main output signal; A sub-driving unit is connected between the signal input terminal and the differential signal output terminal, and is used to receive the same input signal and generate a sub-output signal; A delay adjustment module is connected between the signal input terminal and the main drive unit and / or the sub-drive unit, and is used to adjust the delay time of the sub-output signal relative to the main output signal; The differential signal is a linear superposition of the main output signal and the sub-output signal; the time-domain waveform parameters of the differential signal are configured to be adjusted by adjusting the amplitude relationship and / or time relationship of the output signals of the main driving unit and the sub-driving unit.

[0005] Secondly, based on the same inventive concept, this disclosure also provides a signal conditioning method for the transmitting end of an interface module, including: The signal input terminal receives the input signal; An input signal is provided to the main drive unit so that the main drive unit generates a main output signal at the differential signal output terminal; The delay adjustment module performs delay processing on the input signal; the delay adjustment module outputs the delayed input signal to the sub-drive unit, so that the sub-drive unit generates a sub-output signal with a delay relative to the main output signal at the differential signal output terminal; The time-domain waveform parameters of the differential signal are adjusted by adjusting the amplitude relationship and / or time relationship between the output signals of the main driving unit and the sub-driving unit. The differential signal is generated by linearly superimposing the main output signal and the sub-output signal.

[0006] The technical solution provided in this disclosure has the following advantages compared with the prior art: When the clock and data channels of existing high-speed serial communication interface modules operate simultaneously, significant timing skew occurs between the two signals due to the different drive loads of the clock and data channels. As transmission rates increase, the requirements for timing skew become increasingly stringent. In traditional transmitter structures, the output swing and slew rate of the clock and data channels cannot be adjusted independently, failing to effectively eliminate timing skew caused by edge differences.

[0007] The interface module transmitter provided in this disclosure adopts a dual-path parallel superposition structure of main drive unit and sub-drive unit through the driver, so that the differential signal is linearly superimposed with the main output signal and the sub-output signal. The time-domain waveform parameters of the differential signal are configured to be adjusted by adjusting the amplitude relationship and / or time relationship of the output signals of the main drive unit and the sub-drive unit. This allows the clock channel transmitter and the data channel transmitter to be configured with their respective drive parameters. By adjusting the amplitude relationship and / or time relationship of the output signals of the main drive unit and the sub-drive unit in each channel, the time-domain waveform parameters of the output signals of each channel can be flexibly adjusted.

[0008] In summary, the solution disclosed herein does not require significant modifications to the main circuit structure of the interface module's transmitting end. By simply adding a delay adjustment module to the main driving unit path and adopting a driving architecture with dual-path superposition of driving units, independent and flexible adjustment of the slew rate of each channel can be achieved. This effectively reduces the timing offset caused by signal edge differences from the root cause, improves the reliability of data sampling in high-speed serial communication, and the architecture can be integrated into existing chip designs, resulting in low cost, ease of implementation, and strong scalability.

[0009] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same devices throughout the drawings. In the drawings: Figure 1 A schematic diagram illustrating the channel connection principle between the transmitting and receiving ends in related technologies is shown. Figure 2 This diagram illustrates a timing offset between the data channel and the clock channel in a related technology. Figure 3 This diagram illustrates the structure of a transmitter according to an optional embodiment of the present disclosure. Figure 4 This diagram illustrates the structure of a drive unit according to an optional embodiment of the present disclosure; Figure 5 This diagram illustrates a signal waveform according to an embodiment of the present disclosure. Figure 6 This diagram illustrates the signal waveforms of different adjustable delay units applying different delays to the same input signal. Figure 7This diagram illustrates the signal waveforms of different adjustable delay units of this disclosure applying the same delay to the same input signal. Figure 8 This invention presents a schematic diagram of the signal waveforms of different adjustable delay units applying different delays to the same input signal. Figure 9 This diagram illustrates the structure of the transmitter used in different channels according to embodiments of the present disclosure. Figure 10 The diagram shows waveforms of the transmitter applied to different channels according to embodiments of the present disclosure.

[0013] Explanation of reference numerals in the attached figures: 10. Signal input terminal; 20. Differential signal output terminal; 30. Main drive unit; 40. Sub-drive unit; 50. Delay adjustment module; 60. Common mode feedback module; 70. Adjustable resistor module; 20+, positive differential output port; 20-, negative differential output port; 34. Driver unit; Input: Unit input terminal; Output: Unit output terminal; EN: Enable input terminal; 51. First adjustable delay unit; 52. Second adjustable delay unit; CLK TX, clock channel transmitter; DATA TX, data channel transmitter; CLK RX, clock channel receiver; DATA RX, data channel receiver. Detailed Implementation

[0014] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0015] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0016] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0017] In high-speed serial data transmission, the timing offset between the clock signal and the data signal mainly comes from the following aspects.

[0018] The driving loads of the clock channel and the data channel are different. This is because the clock signal typically needs to drive multiple channels at the receiving end simultaneously, such as... Figure 1 As shown, the clock channel transmitter CLK TX simultaneously drives multiple clock channel receivers CLK RX (including CLK RX0-CLK RX34 receivers), while the single data channel transmitter DATA TX generally only drives a single data channel receiver DATA RX. The difference between the load impedance of the clock channel transmitter CLK TX and the load impedance of the data channel transmitter DATA TX results in different signal transmission delays, thus introducing a timing offset between the clock and data.

[0019] The slew rate of the data signal and the slew rate of the synchronous clock signal (the rate of change of the signal edge voltage over time, measured in V / s) are inconsistent. When the slew rates of the clock signal and the data signal are different, even if the theoretical transition times of the two signals are the same, the arrival times of the signal edges of the clock signal and the data signal at the receiver's threshold voltage will differ. For example, the signal edge with a lower slew rate is slower and arrives at the threshold voltage later than the signal with a higher slew rate. (Refer to...) Figure 2 As shown, the rise and fall times of the two signals corresponding to the transmitting ends of different channels are different, which makes the timing of the signal edge reaching the threshold voltage of the receiving end inconsistent, thus introducing a large timing skew between the clock and the data.

[0020] Furthermore, when the load impedance at the receiving end changes, if the output impedance at the transmitting end remains fixed, impedance mismatch will cause signal reflection. The reflected energy superimposed on the original signal will cause signal edge distortion, further deteriorating the consistency of the slew rate and exacerbating the timing offset between the clock and data.

[0021] The transmitting ends of related technologies mainly include two types: current-mode (CML) and voltage-mode. Although current-mode differential signal transmission circuits are widely used, the output common-mode voltage and output swing are jointly determined by the tail current source and the load resistance. These two are coupled and cannot be adjusted independently, making it difficult to meet the different requirements of various protocols for common-mode voltage and swing. At the same time, in traditional structures, the output swing and slew rate of the clock channel and data channel cannot be adjusted independently, and the output impedance is also fixed, making it impossible to match and adjust according to load changes. Therefore, it cannot effectively solve the timing offset problem caused by load differences and inconsistent slew rates.

[0022] Related technologies also include current-mode differential signal transmission circuits with shared clock units. This circuit structure is based on traditional current-mode logic, and the output common-mode voltage and swing are fixed by the circuit topology. It is also impossible to flexibly adjust the output impedance and slew rate, and it cannot handle the timing offset problem caused by load differences and edge differences between the clock path and the data path.

[0023] In view of this, embodiments of this application provide an interface module transmitter and a signal conditioning method to solve one or more of the above problems.

[0024] The first embodiment of this application proposes an interface module transmitter, which includes a driver 100, such as... Figure 3 As shown, the driver 100 includes: Signal input terminal 10 is used to receive input signals; Differential signal output terminal 20 is used to output differential signals; The main drive unit 30 is connected between the signal input terminal 10 and the differential signal output terminal 20, and is used to receive the input signal and generate the main output signal. Sub-driving unit 40 is connected between the signal input terminal 10 and the differential signal output terminal 20, and is used to receive the same input signal and generate a sub-output signal; The delay adjustment module 50 is connected between the signal input terminal 10 and the main drive unit 30 and / or the sub-drive unit 40, and is used to adjust the delay time of the sub-output signal relative to the main output signal; The differential signal is a linear superposition of the main output signal and the sub-output signal; the time-domain waveform parameters of the differential signal are configured to be adjusted by adjusting the amplitude relationship and / or time relationship of the output signals of the main driving unit 30 and the sub-driving unit 40.

[0025] In this embodiment, the driver 100 adopts a dual-path parallel superposition structure of a main driving unit 30 and a sub-driving unit 40. The main driving unit 30 receives the input signal and generates a main output signal. The sub-driving unit 40 receives the same input signal and obtains an adjustable delay relative to the main output signal through the delay adjustment module 50. The two output signals are linearly superimposed at the differential signal output terminal 20 to form the final differential signal. The time-domain waveform parameters of the differential signal are configured to be adjusted by adjusting the amplitude relationship and / or time relationship of the output signals of the main driving unit 30 and the sub-driving unit 40.

[0026] By employing the above method, in contrast to the problem in related technologies where the output swing and slew rate of the clock channel and data channel cannot be independently adjusted, resulting in excessive timing offset, the clock channel transmitter CLK TX and the data channel transmitter DATA TX can be configured with their respective drive parameters. By adjusting the amplitude relationship and / or time relationship of the output signals of the main drive unit 30 and the sub-drive unit 40 in each channel, the time-domain waveform parameters of the output signals of each channel can be flexibly adjusted, thereby effectively reducing the timing offset introduced by the difference in signal edges and improving the reliability of data sampling in high-speed serial communication.

[0027] In an optional embodiment, both the main drive unit 30 and the sub-drive unit 40 include multiple drive unit chips 34 connected in parallel, and the enable states of the drive unit chips 34 are independent of each other. The number of drive unit chips 34 in the main drive unit 30 that are in the enabled state is greater than the number of drive unit chips 34 in the sub-drive unit 40 that are in the enabled state.

[0028] Reference Figure 4 As shown, both the main drive unit 30 and the sub-drive unit 40 are composed of multiple drive unit slices 34 connected in parallel. Each drive unit slice 34 has the same circuit structure, including a slice input terminal, a slice output terminal, and an enable input terminal EN.

[0029] Each drive unit chip 34 has an input terminal (Input) for receiving input signals, an output terminal (Output) for outputting the driven signal components, and an enable input terminal (EN) for receiving enable control signals to control the corresponding drive unit chip 34 to turn on or off. The enable states of each drive unit chip 34 are independent of each other, meaning that turning on or off any drive unit chip 34 does not affect the operating state of other drive unit chips 34.

[0030] In the main drive unit 30, the input terminals of each drive unit chip 34 are connected to the signal input terminal 10 to receive the input signal. In the sub-drive unit 40, the input terminals of each drive unit chip 34 are connected to the output terminal of the delay adjustment module 50 to receive the input signal after delay processing. The output terminals of all drive unit chips 34 in the main drive unit 30 and the sub-drive unit 40 are connected to the differential signal output terminal 20. The signal components output by each drive unit chip 34 are superimposed at the differential signal output terminal 20 to form the final differential signal.

[0031] The number of drive unit chips 34 in the main drive unit 30 that are in the enabled state is greater than the number of drive unit chips 34 in the sub-drive unit 40 that are in the enabled state. In a specific implementation, the main drive unit 30 may contain 15 to 20 drive unit chips 34 in the enabled state, and the sub-drive unit 40 may contain 1 to 2 drive unit chips 34 in the enabled state.

[0032] Because the main drive unit 30 has a larger number of activated drive unit chips 34, its output signal amplitude is larger, providing the main waveform and basic driving capability of the differential signal. The sub-drive unit 40, with fewer activated drive unit chips 34, has a smaller output signal amplitude. It performs component superposition on the level frame of the main drive unit 30 to refine the edge shape of the output signal. The main output signal and the sub-output signal are linearly superimposed at the differential signal output terminal 20 to form the final differential signal waveform.

[0033] The enable state of each driver unit chip 34 is configured through registers. Each driver unit chip 34 corresponds to an independent enable register bit. When the register bit is valid, the corresponding driver unit chip 34 is enabled, and its output contributes drive current / voltage to the differential signal output terminal 20. When the register bit is invalid, the corresponding driver unit chip 34 is disabled, its output is in a high-impedance state, and it does not contribute any signal components to the differential signal output terminal 20. By configuring different numbers of driver unit chips 34 to be enabled through registers, the output amplitude of the main driver unit 30 and the sub-driver unit 40 can be flexibly adjusted.

[0034] In this embodiment, by independently controlling the enable state of each drive unit chip 34 and configuring the ratio of the number of drive unit chips 34 in the main drive unit 30 and the sub-drive unit 40 that are in the enable state, the amplitude relationship between the two output signals can be flexibly adjusted, thereby adjusting the output swing of the differential signal. The structural design of having more enable chips in the main drive unit 30 than in the sub-drive unit 40 ensures that the main waveform of the differential signal is established by the main drive unit 30, while the sub-drive unit 40 performs edge trimming with a smaller amplitude. This avoids the nonlinear distortion that may occur when the amplitudes of the two signals are equal when they are superimposed, thus ensuring the quality and linearity of the output signal.

[0035] The parallel structure of multiple drive unit chips 34 gives the driver 100 good scalability. The overall driving capability range of the driver 100 can be adjusted by increasing or decreasing the number of drive unit chips 34 without redesigning the entire drive circuit, which is beneficial to the modular design and process migration of the chip.

[0036] In this application, time-domain waveform parameters refer to physical quantities that describe the voltage change characteristics of a differential signal in the time domain, including but not limited to output swing and slew rate. Output swing refers to the voltage difference between the positive and negative terminals of the differential signal, used to characterize the signal amplitude; slew rate refers to the rate of change of the signal edge voltage over time, used to characterize the steepness of the signal's rising or falling edge. This application adjusts at least one of the aforementioned time-domain waveform parameters by adjusting the amplitude relationship and / or time relationship of the output signals from the main drive unit 30 and the sub-drive unit 40.

[0037] In an optional embodiment, when the time-domain waveform parameters of the differential signal are configured to be adjusted by regulating the amplitude relationship between the output signals of the main driving unit 30 and the sub-driving unit 40, The greater the ratio of the number of activated drive unit chips 34 of the sub-drive unit 40 to the number of activated drive unit chips 34 of the main drive unit 30, the greater the amplitude of the output signal of the sub-drive unit 40 relative to the amplitude of the output signal of the main drive unit 30.

[0038] Reference Figure 5 As shown in the figure, from top to bottom, the output signals of the main drive unit (low level VOP and high level VON), the output signals of the sub-drive unit (low level VOPD and high level VOND), and the differential signals (low level VOUTP and high level VOUTN) of the driver 100 after their linear superposition are shown. The output amplitude of the sub-drive unit is smaller than that of the main drive unit 30, and the output of the sub-drive unit has a delay time t relative to the main drive unit 30.

[0039] As can be seen from the waveform of the differential signal, the rising and falling edges of the final output differential signal exhibit a "two-stage" characteristic: the main drive unit 30 responds first to the input signal transition, and the output signal reaches the intermediate level first; after a delay time t, the output signal of the sub-drive unit 40 is superimposed, and the output signal of the driver 100 continues to change to full amplitude. This process lengthens the equivalent rise and fall times of the output signal, reducing the slew rate.

[0040] With the total output swing remaining constant, a larger delay time t, or a larger output amplitude ratio of the sub-drive unit 40 relative to the main drive unit 30, results in smoother rising and falling edges of the output signal and a lower slew rate. Conversely, a smaller delay time t, or a smaller output amplitude ratio of the sub-drive unit 40 relative to the main drive unit 30, results in a higher slew rate. Therefore, by adjusting the delay time of the delay adjustment module 50 and the ratio of the number of drive unit chips 34 turned on in the two drive units, continuous adjustment of the output signal slew rate can be achieved.

[0041] In this embodiment, when adjusting the time-domain waveform parameters of the differential signal by adjusting the amplitude relationship between the output signals of the main driving unit 30 and the sub-driving unit 40, With the total output swing remaining constant—that is, the total number of drive unit chips 34 activated in both the main drive unit 30 and the sub-drive unit 40 remains unchanged—the larger the ratio of the number of activated drive unit chips 34 in the sub-drive unit 40 to that in the main drive unit 30, the larger the output signal amplitude of the sub-drive unit 40 relative to that of the main drive unit 30. This results in a lower intermediate level at the differential signal edge and a longer time required for the signal to change from the intermediate level to full amplitude, thus leading to a lower slew rate. Conversely, a smaller ratio results in a higher slew rate.

[0042] In a specific example, when the main drive unit 30 activates 15 drive unit chips 34 and the sub-drive unit 40 activates 1 drive unit chip 34, the output amplitude of the main drive unit 30 (15 units) is much larger than that of the sub-drive unit 40 (1 unit). The amplitude ratio between the sub-drive unit and the main drive unit is 1 / 15. The middle level of the differential signal edge rises close to the full amplitude, and the remaining amplitude that needs to be raised by the sub-drive unit 40 is only 1 unit. Therefore, the rise time in the second half is shorter, the slew rate is higher, and the edge is steeper.

[0043] In a specific example, when the number of enabled chips in sub-drive unit 40 increases from 1 to 2, if the total output swing remains unchanged, the number of enabled chips in main drive unit 30 needs to be reduced from 15 to 14 to maintain a total of 16 chips. At this time, the output amplitude of sub-drive unit 40 (2 units) increases relative to main drive unit 30 (14 units), and the amplitude ratio between sub-drive unit and main drive unit changes from 1 / 15 to 2 / 14, a significant increase compared to the sub-drive ratio in the previous example. The mid-level of the differential signal edge decreases, the latter half is raised by sub-drive unit 40, the equivalent rise time is prolonged, the slew rate decreases, and the edge becomes smoother.

[0044] Conversely, when the number of active chips in the sub-drive unit 40 decreases from 2 to 1, the number of active chips in the main drive unit 30 increases from 14 to 15. The amplitude ratio between the sub-drive unit and the main drive unit decreases from 2 / 14 to 1 / 15. The intermediate level rises, the amplitude required for the second half to rise decreases, the equivalent rise time is shortened, the slew rate increases, and the edge becomes steeper.

[0045] This embodiment achieves continuous adjustment of the slew rate without changing the total output swing by configuring the ratio of the number of enabled drive unit chips 34. This meets the requirements of different transmission protocols and application scenarios regarding the steepness of signal edges, thereby enabling adjustment of the time-domain waveform parameters of differential signals. The ratio of the number of enabled drive unit chips 34 can be configured via registers without changing the circuit topology. The adjustment process is simple and fast, and each channel can be configured independently without interference. The number of enabled drive unit chips 34 in the main drive unit 30 is greater than that in the sub-drive units 40, ensuring that the main drive unit 30 always provides sufficient basic driving capability. The sub-drive units 40 can effectively change the edge shape by adjusting within a small range, avoiding nonlinear distortion that may be introduced by large-scale adjustments.

[0046] In an alternative embodiment, such as Figure 3 As shown, the delay adjustment module 50 includes: The first adjustable delay unit 51 is connected between the signal input terminal 10 and the input terminal of the sub-driving unit 40. The second adjustable delay unit 52 is connected between the signal input terminal 10 and the input terminal of the main drive unit 30; The delay amount of the second adjustable delay unit 52 and the delay amount of the first adjustable delay unit 51 are configured independently.

[0047] like Figure 3 As shown, the delay adjustment module 50 includes a second adjustable delay unit 52 and a first adjustable delay unit 51.

[0048] The second adjustable delay unit 52 is connected between the signal input terminal 10 and the input terminal of the main drive unit 30. The input signal received by the signal input terminal 10 is delayed by the second adjustable delay unit 52 and then sent to the main drive unit 30. The main drive unit 30 generates a main output signal based on the input signal delayed by the second adjustable delay unit 52.

[0049] The first adjustable delay unit 51 is connected between the signal input terminal 10 and the input terminal of the sub-drive unit 40. The same input signal received by the signal input terminal 10 is delayed by the first adjustable delay unit 51 and then sent to the sub-drive unit 40. The sub-drive unit 40 generates a sub-output signal based on the input signal delayed by the first adjustable delay unit 51.

[0050] The delay amount of the second adjustable delay unit 52 and the delay amount of the first adjustable delay unit 51 are configured independently. In this embodiment, "independently configured" means that the delay time of the second adjustable delay unit 52 and the delay time of the first adjustable delay unit 51 can be independently set through registers. There is no fixed proportional relationship or linkage between them; that is, the delay amount of the second adjustable delay unit 52 can be adjusted independently without changing the delay amount of the first adjustable delay unit 51, and vice versa.

[0051] Therefore, this embodiment, by independently configuring the delay amounts of the two adjustable delay units, allows for both adjusting the relative delay between the main drive unit 30 and the sub-drive unit 40 to change the slew rate by configuring different delay amounts, and also shifting the overall channel timing without changing the slew rate by configuring the same delay amount. The two functions do not interfere with each other, providing high flexibility in adjustment. The delay amounts of both adjustable delay units can be independently configured via registers, achieving picosecond-level delay adjustment accuracy, meeting the stringent timing accuracy requirements of high-speed serial communication.

[0052] Based on the above dual adjustable delay unit structure, by configuring the delay amounts of the second adjustable delay unit 52 and the first adjustable delay unit 51, the following two operating scenarios can be achieved: Scenario 1: Adjust the slew rate of the time-domain waveform parameters.

[0053] In an optional embodiment, when the time-domain waveform parameters of the differential signal are configured to be adjusted by adjusting the time relationship between the output signals of the main drive unit 30 and the sub-drive unit 40, wherein the second adjustable delay unit 52 and the first adjustable delay unit 51 are configured with different delay amounts, the sub-output signal has a delay time relative to the main output signal to adjust the slew rate of the differential signal.

[0054] Reference Figure 6 As shown, when only the slew rate of the differential signal needs to be adjusted without changing the overall timing of the channel, the input signal can be delayed by the first adjustable delay unit 51, and the second adjustable delay unit 52 can be set to a fixed delay amount, such as zero delay or a basic delay level.

[0055] Specifically, the input signal received by the signal input terminal 10 is divided into two paths: one path is delayed by a fixed delay amount T1 by the second adjustable delay unit 52 and then sent to the main drive unit 30, which generates the main output signal; the other path is delayed by an adjustable delay amount T2 by the first adjustable delay unit 51 and then sent to the sub-drive unit 40, which generates the sub-output signal. At this time, the delay time t between the sub-output signal and the main output signal is t = T2 - T1. If T1 is fixed, then t changes with T2. By independently adjusting the delay amount T2 of the first adjustable delay unit 51, the relative delay time t between the main output signal and the sub-output signal can be changed.

[0056] Reference Figure 5 As shown, the main drive unit output signals (low level VOP and high level VON), the sub-drive unit output signals (low level VOPD and high level VOND), and the differential signals (low level VOUTP and high level VOUTNC) finally output by the driver 100 after the linear superposition of the two.

[0057] The main drive unit output signal VOP / VON responds to the input signal transition first, reaching the intermediate level first. The sub-drive unit output signal VOPD / VOND has a delay time t relative to the main drive unit output signal, and the output amplitude of the sub-drive unit 40 is smaller than the output amplitude of the main drive unit 30. The two signals are linearly superimposed at the differential signal output terminal 20 to form the final output differential signal VOUTP / VOUTN.

[0058] As can be seen from the differential signal, the rising and falling edges of the final output differential signal exhibit a "two-stage" characteristic: the first half is driven by the main drive unit 30, which changes the signal from the initial level to the middle level; the second half is driven by the sub-drive unit 40, which superimposes the drive signal, and continues to change the signal from the middle level to full amplitude. This process lengthens the equivalent rise and fall times of the output signal, thus reducing the slew rate.

[0059] based on Figure 5 and Figure 6 It can be seen that the relative delay time t determines the time interval between the rising edges of the main drive unit's output signal and the sub-drive unit's output signal. The larger the relative delay time t, the longer the time it takes for the sub-drive unit to superimpose the drive signal after the main drive unit's output signal reaches the intermediate level, resulting in smoother rising and falling edges of the final output signal and a lower slew rate. Conversely, the smaller t, the closer the rising and falling edges of the main drive unit's output signal and the sub-drive unit's output signal are, resulting in steeper rising and falling edges of the final output signal and a higher slew rate.

[0060] Therefore, by configuring the second adjustable delay unit 52 and the first adjustable delay unit 51 with different delay amounts, the delay time of the sub-output signal relative to the main output signal can be adjusted, thereby achieving the adjustment of the differential signal slew rate.

[0061] In the aforementioned embodiments, besides the delay time t, the amplitude ratio of the output signals of the main drive unit 30 and the sub-drive unit 40 also affects the slew rate. (Refer to...) Figure 4 As shown, the output amplitude of the sub-drive unit 40 is smaller than the output amplitude of the main drive unit 30. The larger the output amplitude of the sub-drive unit 40 is relative to the output amplitude of the main drive unit 30, that is, the larger the ratio of the number of drive unit chips 34 turned on in the sub-drive unit 40 to the number of drive unit chips 34 turned on in the main drive unit 30, the lower the middle level position of the differential signal edge, the larger the amplitude that needs to rise to full amplitude in the second half, the longer the equivalent rise time, and the lower the slew rate. Conversely, the smaller the output amplitude of the sub-drive unit 40 is relative to the output amplitude of the main drive unit 30, the higher the middle level position, the smaller the amplitude that needs to rise in the second half, and the higher the slew rate.

[0062] In other words, when this application aims to adjust the slew rate of the time-domain waveform parameters, it can adopt one or all of the following methods: changing the amplitude relationship and relative delay time between the two driving units, so that the slew rate of the input signals of different channels is consistent, and the clock signal and data signal are aligned at the receiving end, thereby effectively reducing the timing offset between channels.

[0063] Scenario 2: Adjust the overall timing shift of the time-domain waveform parameters.

[0064] In another alternative embodiment, when the time-domain waveform parameters of the differential signal are configured to be adjusted by regulating the time relationship between the output signals of the main driving unit 30 and the sub-driving unit 40, When the second adjustable delay unit 52 and the first adjustable delay unit 51 are configured with the same delay amount, the sub-output signal is synchronously delayed relative to the main output signal, and the offset timing of the differential signal in the channel where the interface module's transmitting end is located is adjusted.

[0065] Reference Figure 2 As shown, when it is only necessary to adjust the overall timing of the output signal of the channel where the interface module is located, for example, to correct the timing offset between the clock channel and the data channel, without changing the slew rate of the differential signal, the second adjustable delay unit 52 and the first adjustable delay unit 51 need to be configured with the same delay amount.

[0066] Specifically, the input signal received by the signal input terminal 10 is divided into two paths: one path is sent to the main drive unit 30 through the second adjustable delay unit 52 (delay amount is T1), and the main drive unit 30 generates the main output signal; the other path is sent to the sub-drive unit 40 through the first adjustable delay unit 51 (delay amount is T2), and the sub-drive unit 40 generates the sub-output signal.

[0067] When T1=T2, the input signal received by the main drive unit 30 and the input signal received by the sub-drive unit 40 are delayed by the same absolute time. Therefore, the absolute delay time of the main output signal and the sub-output signal is the same. The delay time of the sub-output signal relative to the main output signal is t=T2-T1=0. The relative time relationship between the output signals of the main drive unit 30 and the sub-drive unit 40 remains unchanged, and the slew rate of the differential signal remains unchanged.

[0068] When it is necessary to shift the channel output signal to the left (advance) on the time axis, the delay amount T1 of the second adjustable delay unit 52 and the delay amount T2 of the first adjustable delay unit 51 are reduced synchronously, while keeping T1=T2. At this time, the absolute delay time of the input signals received by the main drive unit 30 and the sub-drive unit 40 is reduced synchronously, and the main output signal and the sub-output signal are shifted to the left by the same amount of time on the time axis. The overall phase of the differential signal is advanced, but the waveform shape of the differential signal (including swing amplitude, slew rate and duty cycle) remains unchanged.

[0069] Reference Figure 7 As shown, when it is necessary to shift (delay) the channel output signal to the right as a whole on the time axis, the delay amount T1 of the second adjustable delay unit 52 and the delay amount T2 of the first adjustable delay unit 51 are increased synchronously, while keeping T1=T2. At this time, the absolute delay time of the input signals received by the main drive unit 30 and the sub-drive unit 40 increases synchronously, and the main output signal and the sub-output signal are shifted to the right by the same amount of time on the time axis. The overall phase of the differential signal is delayed, but the waveform shape of the differential signal remains unchanged.

[0070] This embodiment, by configuring the two adjustable delay units with the same delay amount, can shift the timing of the overall channel output signal while keeping the differential signal swing and slew rate constant, thus meeting the timing alignment accuracy requirements of high-speed serial communication. The delay amounts of the two adjustable delay units are independently configured through registers, achieving picosecond-level delay adjustment accuracy and meeting the stringent timing accuracy requirements of high-speed serial communication.

[0071] It is worth noting that, such as Figure 8 As shown, both the first scenario, which adjusts the slew rate of the time-domain waveform parameters, and the second scenario, which adjusts the overall time-series shift of the time-domain waveform parameters, exist simultaneously.

[0072] Reference Figure 8 As shown, the signal output by the second adjustable delay unit 52 has a delay of t2 relative to the original input signal, and the signal output by the first adjustable delay unit 51 has a delay of t1 relative to the original input signal. By configuring the delay amount T2 of the second adjustable delay unit 52 and the delay amount T1 of the first adjustable delay unit 51 respectively, the adjustment of the overall timing offset of the channel and the regulation of the slew rate can be realized simultaneously.

[0073] Taking timing offset correction between clock channel and data channel as an example, suppose that the data channel is 15ps behind the clock channel through system measurement or testing, and the slew rate of the data channel needs to be reduced to match the edge characteristics of the clock channel.

[0074] The adjustment parameters for the data channel can be configured as follows: The target overall timing shift is ΔT = +15ps, which means shifting the entire data channel to the right by 15ps to output earlier, in order to compensate for the lag relative to the clock channel. The target relative delay time is t=10ps, that is, the sub-output signal is delayed by 10ps relative to the main output signal to reduce the slew rate.

[0075] Baseline delay: Tbase = 0 ps. In this example, the baseline delay refers to the initial delay of the two adjustable delay units without any additional delay applied. A baseline delay is introduced to improve accuracy, as adjustable delay units typically have an inherent delay.

[0076] The delay amount T2 of the second adjustable delay unit 52 is 0 + 15 = 15 ps, and the delay amount T1 of the first adjustable delay unit 51 is 0 + 15 + 10 = 25 ps. At this time, the slew rate of the data channel output signal decreases, and the data channel output signal is shifted to the right by 15 ps, so that the data signal and the clock signal are aligned at the receiving end.

[0077] Therefore, this embodiment, through a structure with dual driving units and a delay unit in each driving unit, allows the same channel to simultaneously achieve slew rate adjustment and overall timing shift without adding extra circuitry. This results in high hardware resource utilization and low chip area overhead. In multi-channel applications, each channel can be independently configured with its own overall timing shift and slew rate, ensuring optimal timing alignment of all channels' signals at the receiver, thus improving the overall signal integrity and data sampling accuracy of the system.

[0078] In an alternative embodiment, such as Figure 3As shown, the interface module transmitting end also includes a common-mode feedback module 60, which is connected to the differential signal output end 20. It is used to detect the common-mode voltage of the differential signal and generate a feedback signal to the driver 100 to control the driver 100 to adjust the common-mode voltage of the differential signal to be equal to the reference voltage.

[0079] In this embodiment, the adjustments of the common-mode feedback module 60, the main drive unit 30, and the sub-drive unit 40 are independent of each other. The common-mode feedback module 60 only adjusts the common-mode voltage of the differential signal, without changing the output swing and slew rate of the differential signal; the amplitude and / or timing relationship adjustments between the main drive unit 30 and the sub-drive unit 40 only change the output swing and / or slew rate of the differential signal, without changing the common-mode voltage of the differential signal. Because the two adjustment functions are independent of each other, the interface module transmitter can independently optimize the output swing and slew rate of each channel to reduce timing offset while being compatible with the common-mode voltage requirements of different protocols, and the two do not interfere with each other.

[0080] In one specific implementation, the common-mode feedback module includes a common-mode voltage detection unit and an error amplification unit.

[0081] The common-mode voltage detection unit is connected to the differential signal output terminal to detect the positive and negative voltages of the differential signal, and obtains the common-mode voltage detection value through a resistor voltage divider. Specifically, the common-mode voltage detection unit consists of two resistors of equal resistance connected in series. The two ends of the series branch are connected to the positive and negative output terminals of the differential signal, respectively, and the voltage at the midpoint between the two resistors is the common-mode voltage detection value.

[0082] The error amplifier unit has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the error amplifier unit is connected to the output terminal of the common-mode voltage detection unit to receive the common-mode voltage detection value. The second input terminal of the error amplifier unit is used to receive the reference voltage VREF.

[0083] The error amplification unit compares and amplifies the common-mode voltage detection value with the reference voltage VREF, generates an error amplification signal as a feedback signal, and sends the feedback signal to the controlled node inside the driver through the output of the error amplification unit.

[0084] When the common-mode voltage detection value is lower than the reference voltage VREF, the feedback signal output by the error amplifier unit increases the current of the tail current source, and the common-mode voltage at the positive and negative output terminals of the differential signal increases accordingly.

[0085] When the common-mode voltage detection value is higher than the reference voltage VREF, the feedback signal output by the error amplifier unit reduces the current of the tail current source, and the common-mode voltage at the positive and negative output terminals of the differential signal decreases accordingly.

[0086] Through the above closed-loop feedback adjustment, the common-mode feedback module 60 ultimately makes the common-mode voltage of the differential signal stably follow the reference voltage VREF, even if the adjusted common-mode voltage is equal to the reference voltage VREF.

[0087] The reference voltage VREF can be configured via registers. The external host controller or upper-layer software writes the corresponding reference voltage value to the register according to the currently used transmission protocol (such as LVDS, miniLVDS, or HDMI). The reference voltage VREF can be configured to different voltage values ​​to adapt to the output common-mode voltage requirements of different video transmission protocols. For example, when the interface module transmitter is used for the miniLVDS protocol, the reference voltage VREF can be configured to 1.2V; when used for the LVDS protocol, the reference voltage VREF can be configured to 1.2V; and when used for the HDMI protocol, the reference voltage VREF can be configured to the corresponding standard value. By configuring different reference voltages VREF, the common-mode feedback module 60 can make the common-mode voltage of the differential signal follow the changes in the reference voltage, thereby achieving flexible and independent adjustment of the output common-mode voltage, enabling the same interface module transmitter to be compatible with multiple different video transmission protocols.

[0088] In other embodiments, the driver employs a voltage-mode structure, and the feedback signal can also be connected to the adjustable control terminal of the load resistor to adjust the common-mode voltage by changing the equivalent resistance of the load resistor.

[0089] In high-speed serial communication systems, the differential signal output terminal 20 of the interface module's transmitting end is connected to the receiving end. The differential signal output terminal 20 includes a positive differential output port 20+ and a negative differential output port 20-, used to transmit the differential signal to the receiving end. The receiving end typically has a terminating resistor to achieve impedance matching. However, in practical applications, the load impedance of the receiving end is not constant.

[0090] For example, the clock signal typically needs to drive multiple channels at the receiving end simultaneously, such as... Figure 1 As shown, a clock signal drives multiple data receiving channels simultaneously, while a data signal typically drives only a single receiving channel. When different numbers of receiving channels are connected in parallel, the equivalent load impedance presented at the receiving end is different; the more channels driven, the lower the equivalent load impedance.

[0091] Taking a 100Ω termination resistance for each receiving channel as an example, the equivalent load impedance is approximately 100Ω when driving one channel, approximately 50Ω when driving two channels, and approximately 25Ω when driving four channels.

[0092] Because the output impedance of the transmitting end in a traditional structure is fixed—for example, 100Ω—a mismatch occurs when the equivalent load impedance at the receiving end deviates from 100Ω due to changes in the number of drive channels. This impedance mismatch causes signal reflection at the end of the transmission line. The reflected energy superimposed on the original signal causes signal edge distortion, deteriorates signal quality, and further exacerbates the timing offset between the clock and data signals.

[0093] In view of this, in an alternative embodiment, such as Figure 3 As shown, the transmitting end of the interface module also includes an adjustable resistor module 70, which is connected between the positive differential output port 20+ and the negative differential output port 20-, and is used to adjust the output impedance of the transmitting end of the interface module according to the load impedance of the receiving end.

[0094] In one specific implementation, the adjustable resistor module 70 includes multiple resistor branches connected in parallel. Each resistor branch includes a resistor and a switching transistor connected in series, and the on / off state of each switching transistor is independently controlled. By configuring the on / off state of each switching transistor, the equivalent resistance value of the adjustable resistor module 70 can be changed, thereby adjusting the output impedance of the interface module's transmitting end at the differential signal output terminal 20 to match the load impedance of the receiving end.

[0095] Taking the equivalent load impedance of the receiving end as an example, the on / off state of each switch in the adjustable resistor module 70 is configured by the register, and the equivalent resistance value of the adjustable resistor module 70 is adjusted to 50Ω, so that the output impedance of the transmitting end matches the load impedance of the receiving end, thereby suppressing signal reflection.

[0096] When the equivalent load impedance of the receiving end changes to 25Ω, the on / off state of each switch in the adjustable resistor module 70 is reconfigured through the register, and the equivalent resistance value of the adjustable resistor module is adjusted to 25Ω, thus restoring impedance matching.

[0097] Based on the above embodiments, the adjustable resistor module 70 flexibly adjusts the output impedance of the transmitting end according to the load impedance of the receiving end, so that the output impedance of the transmitting end matches the load impedance of the receiving end, effectively suppressing signal reflection. By suppressing the signal edge distortion caused by reflection, the edge shapes of the clock signal and data signal are made more regular and consistent, thereby reducing the timing offset caused by reflection and improving the reliability of data sampling in high-speed serial communication.

[0098] In this embodiment, the equivalent resistance value of the adjustable resistor module 70 is configured through a register and can be flexibly adjusted according to different protocols and different receiver configurations. This eliminates the need to design a separate transmitter circuit for each application scenario, thereby improving the versatility and reusability of the interface module.

[0099] In an optional embodiment, such as Figure 9 As shown, the interface module transmitter includes an independently configured clock channel transmitter (CLK TX) and a data channel transmitter (DATA TX). The independent configuration means that the clock channel transmitter (CLK TX) and the data channel transmitter (DATA TX) are physically independent, with each channel having its own independent... Figure 3 The signal input terminal 10, driver 100 and differential signal output terminal 20 shown can all have their driving parameters configured independently through registers, including the number of driver unit chips 34 that are turned on and the delay amount of the adjustable delay unit, without interfering with each other.

[0100] The clock channel transmitter CLK TX includes the driver 100, and the signal input terminal 10 of the clock channel transmitter CLK TX is used to receive a clock signal. After the clock signal is processed by the driver 100 in the clock channel transmitter CLK TX, a differential clock signal is output to the clock channel of the receiving end through the differential signal output terminal 20 of the clock channel transmitter CLK TX.

[0101] The data channel transmitter DATA TX includes the driver 100, and the signal input terminal 10 of the data channel transmitter DATA TX is used to receive data signals. After the data signal is processed by the driver 100 in the data channel transmitter DATA TX, a differential data signal is output to the data channel of the receiver through the differential signal output terminal 20 of the data channel transmitter DATA TX.

[0102] In one example, the interface module transmitter provided in this application embodiment can be integrated into the SoC chip of a display device, such as a television, monitor, or portable display screen. The SoC transmits video data and control signals to the driver chip of the display panel through this interface module transmitter. The driver chip acts as the receiver, and the SoC acts as the transmitter. The two are connected via an LVDS or miniLVDS interface.

[0103] The signal input terminal 10 of the clock channel transmitter CLK TX receives pixel clock signals generated internally by the Scaler SoC, such as 74.25MHz and 148.5MHz. After processing by the driver 100 in the clock channel transmitter CLK TX, a differential clock signal is output to the clock receiver of the display panel driver chip. The signal input terminal 10 of the data channel transmitter DATA TX receives serialized video data signals, such as RGB data, internally by the Scaler SoC. After processing by the driver 100 in the data channel transmitter DATA TX, a differential data signal is output to the data receiver of the display panel driver chip.

[0104] Due to differences in display panel size and resolution, the required clock frequency and load characteristics of the driver chip also vary. At 4K resolution and a 60Hz refresh rate, taking HDMI 2.0 as an example, the pixel clock frequency is approximately 594MHz, resulting in a higher data rate and more stringent requirements for timing offset. By independently configuring the drive parameters of the clock channel transmitter (CLK TX) and the data channel transmitter (DATA TX), such as the ratio of the number of main driver units 30 and sub-driver units 40 enabled and their delay, the slew rates of the two signals can be made more consistent, thereby meeting the stringent timing accuracy requirements of 4K displays.

[0105] In another example, the interface module transmitter provided in this application embodiment can be integrated into the output port chip of a player, such as a set-top box, Blu-ray player, or game console. The player transmits audio and video signals to a display device, such as a television or projector, via an HDMI interface.

[0106] In the player, the interface module transmitter includes an independently configured clock channel transmitter (CLK TX) and multiple data channel transmitters (DATA TX). The clock channel transmitter (CLK TX) transmits the HDMI clock channel signal, and the multiple data channel transmitters (DATA TX) transmit the various HDMI data channel signals respectively. The player's output port is connected to the HDMI input port of the display device via an HDMI cable. The signal input terminal 10 of each data channel transmitter (DATA TX) receives the corresponding serialized video data signal, and the signal input terminal 10 of the clock channel transmitter (CLK TX) receives the TMDS clock signal.

[0107] When a player is connected to display devices of different brands and models, the load characteristics of the HDMI receivers on these devices may vary. By independently configuring the drive parameters of each channel's transmitter, the interface module's transmitter can adaptively match the load characteristics of different receivers, ensuring stable transmission of audio and video signals across various display devices.

[0108] like Figure 9 As shown, the interface module's transmitting end includes multiple independently configured data channel transmitters DATA TX, such as DATA TX0, DATA TX1, and DATA TX2, each used to transmit multiple parallel data signals. Each data channel transmitter DATA TX independently includes a driver 100, and its respective signal input terminal 10 receives the corresponding data signal. The driving parameters of each channel can be configured independently to adapt to the different load characteristics and timing requirements caused by differences in layout and wiring of different data channels.

[0109] In this embodiment, the clock channel transmitter CLK TX and the data channel transmitter DATA TX are each independently configured with a driver 100. The driving parameters of each channel can be adjusted independently, so that each channel can independently adjust the slew rate to the optimal state according to the actual load. This effectively reduces the timing offset caused by load differences and improves the reliability of data sampling in high-speed serial communication. At the same time, this architecture can flexibly adapt to the different electrical parameter requirements of different transmission protocols (such as LVDS, miniLVDS, HDMI), and is compatible with various receiver load characteristics. It does not require separate design of transmitter circuits for each application scenario, which improves the versatility and reusability of the chip and meets the strict timing accuracy requirements of high-speed video transmission such as 4K / 8K.

[0110] In an optional embodiment, the time-domain waveform parameters include slew rate, which is adjusted by adjusting the relative delay time between the main drive unit 30 and the sub-drive unit 40 in the clock channel transmitter CLK TX and / or the ratio of the number of drive unit chips 34 that are turned on; and by adjusting the relative delay time between the main drive unit 30 and the sub-drive unit 40 in the data channel transmitter DATA TX and / or the ratio of the number of drive unit chips 34 that are turned on, so that the difference between the slew rate of the clock signal and the slew rate of the data signal is within a preset threshold range.

[0111] Reference Figure 10 As shown in 10a, before adjustment, there is a large timing offset skew between the rising edges of the output signals of the first channel transmitter 1 and the second channel transmitter 2, and the edge steepness of the two signals is inconsistent. By adjusting the relative delay time between the main drive unit 30 and the sub-drive unit 40 in the first channel transmitter 1 and / or the ratio of the number of drive unit chips 34 turned on, the slew rate of the first channel transmitter 1 is slowed down, making the signal edge of the first channel transmitter 1 smoother.

[0112] Reference Figure 10 As shown in 10b, after adjustment, the rising edges of the first channel transmitter 1 and the second channel transmitter 2 are aligned, the steepness of the edges of the two signals tends to be consistent, and the timing offset skew between the two signals is effectively reduced.

[0113] In this embodiment, the preset threshold range can be determined based on the system's timing margin, thereby controlling the introduced timing offset within an acceptable range for the system. Those skilled in the art can set the specific value of this preset threshold range according to the actual transmission rate and system timing requirements.

[0114] In this embodiment, by adjusting the relative delay time between the main drive unit 30 and the sub-drive unit 40 in the first channel transmitter 1 and the second channel transmitter 2 respectively, and / or the ratio of the number of drive unit chips 34 turned on, the slew rate difference between the two signals is made to be within a preset threshold range, so that the steepness of the edges of the two signals tends to be consistent, thereby effectively reducing the timing offset introduced by the edge difference and improving the reliability of data sampling in high-speed serial communication.

[0115] It is worth noting that, based on Figure 9 As shown, with the clock channel transmitter CLK TX and the data channel transmitter DATA TX each independently configured with a driver 100, the output swing, slew rate, output impedance and common-mode voltage of each channel transmitter can be independently adjusted according to the actual needs of each channel, so that the time-domain waveform parameters and common-mode voltage of different channel transmitters tend to be consistent.

[0116] For example, each channel transmitter can independently adjust its output swing. This can be achieved by independently adjusting the ratio of the number of drive unit chips 34 enabled between the main drive unit 30 and the sub-drive unit 40, thereby adjusting the output swing of each channel. For instance, when the clock channel transmitter CLK TX needs to drive multiple receiving channels, the number of drive unit chips 34 enabled in the main drive unit 30 and / or sub-drive unit 40 of the clock channel transmitter CLK TX can be increased to improve the output swing of the clock signal and ensure that the clock signal can maintain a sufficient voltage amplitude for the receiver to correctly identify when driving a heavy load. When the data channel only drives a single receiving channel, the number of drive unit chips 34 enabled can be reduced to lower power consumption. By configuring the ratio of the number of drive unit chips 34 enabled for each channel transmitter, the output swing of different channel transmitters can be flexibly adjusted according to their respective load conditions, ensuring signal quality while optimizing overall power consumption.

[0117] For example, each channel transmitter can independently adjust its output impedance. Each channel transmitter can independently configure the equivalent resistance value of its adjustable resistor module 70 to adjust the output impedance of each channel, so that the output impedance of each channel matches the load impedance of its respective receiver. For example, when the clock channel transmitter CLK TX needs to drive multiple clock channel receivers CLK RX simultaneously, the equivalent load impedance of the clock channel transmitter is low. The equivalent resistance value of the adjustable resistor module 70 of this channel can be configured through the register to match the low impedance load to suppress signal reflection. However, when the single data channel transmitter DATA TX drives only the single data channel receiver DATA RX, the equivalent load impedance is high. The equivalent resistance value of the adjustable resistor module 70 of this data channel transmitter DATA TX can be configured to be higher.

[0118] The load impedance of the receiver can be different for different channels. The adjustable resistor module 70 of each channel transmitter can be independently configured to achieve optimal impedance matching for each channel transmitter, thereby effectively suppressing signal reflection from each channel transmitter.

[0119] For example, each channel transmitter can independently adjust its output impedance, and each channel transmitter can independently configure the reference voltage of its own common-mode feedback module 60 to adjust the output common-mode voltage of each channel transmitter, so that the output common-mode voltage of each channel meets the requirements of its respective transmission protocol. For example, when the clock channel uses the miniLVDS protocol to transmit clock signals, the reference voltage of this channel can be configured to 1.2V; while when the data channel uses the LVDS protocol to transmit data signals, the reference voltage of this channel can be configured to 1.2V; when different channels use different protocols, each channel can be configured with different reference voltages to meet the different requirements of different protocols for common-mode voltage.

[0120] In summary, the architecture of independently configured drivers 100 for both the clock channel transmitter (CLK TX) and the data channel transmitter (DATA TX) allows for independent optimization of the slew rate, output swing, output impedance, and common-mode voltage of each channel based on their respective protocol requirements and load conditions, without the need for trade-offs between channels. This architecture offers high flexibility and configurability, meeting the complex requirements of multi-protocol, multi-load, and high-speed serial communication.

[0121] Another embodiment of the present invention provides a signal conditioning method for the transmitting end of an interface module, the signal conditioning method comprising: The signal input terminal receives the input signal.

[0122] An input signal is provided to the main drive unit so that the main drive unit generates a main output signal at the differential signal output terminal; specifically, the signal input terminal provides the received input signal to the main drive unit, and the main drive unit generates a main output signal at the differential signal output terminal after receiving the input signal.

[0123] The delay adjustment module performs delay processing on the input signal. Specifically, the signal input terminal provides the same received input signal to the delay adjustment module, which then performs delay processing on the input signal according to a configured delay amount. The delay adjustment module adjusts the delay time of the sub-output signal relative to the main output signal.

[0124] The delayed input signal is output to the sub-driver unit, so that the sub-driver unit generates a sub-output signal with a delay relative to the main output signal at the differential signal output terminal. Specifically, the delay adjustment module provides the delayed input signal to the sub-driver unit. After receiving the delayed input signal, the sub-driver unit generates a sub-output signal at the differential signal output terminal. This sub-output signal has a delay time t relative to the main output signal, and the delay time t is determined by the delay amount of the delay adjustment module.

[0125] The time-domain waveform parameters of the differential signal are adjusted by regulating the amplitude and / or timing relationship between the output signals of the main drive unit and the sub-drive unit. Adjusting the amplitude relationship includes adjusting the ratio of the number of drive unit chips 34 activated in each of the main and sub-drive units; adjusting the timing relationship includes adjusting the delay amount of the delay adjustment module to change the delay time of the sub-output signal relative to the main output signal. Through this adjustment method, flexible adjustment of the output swing and / or slew rate of the differential signal can be achieved.

[0126] The differential signal is generated by linearly superimposing the main output signal and the sub-output signal. It is worth noting that the execution order of the above steps is not limited to the described order. For example, the step of providing the input signal to the main drive unit and the step of the delay adjustment module performing delay processing on the input signal can be executed in parallel. After receiving the input signal, the signal input terminal simultaneously provides the same input signal to both the main drive unit and the delay adjustment module. The two signals are processed through the main drive unit path (without delay or with a basic delay) and the delay adjustment module path (with an adjustable delay), respectively, and then superimposed at the differential signal output terminal. Those skilled in the art should understand that the order of the above steps can be adjusted according to the actual circuit structure, and all such adjustments fall within the scope of protection of this application.

[0127] The signal conditioning method provided in this embodiment provides the input signal to the main drive unit and then to the sub-drive unit after delay processing by the delay adjustment module. This allows the main output signal and the sub-output signal to be linearly superimposed at the differential signal output terminal to generate a differential signal. By adjusting the amplitude and / or time relationship between the output signals of the main drive unit and the sub-drive unit, the time-domain waveform parameters of the differential signal are adjusted, achieving flexible adjustment of the differential signal output swing and / or slew rate. Each channel can execute the above adjustment method separately to make the slew rates of the clock signal and data signal tend to be consistent, thereby effectively reducing the timing offset introduced by edge differences and improving the reliability of data sampling in high-speed serial communication.

[0128] In an optional embodiment, the signal conditioning method further includes adjusting the output impedance. Specifically, the differential signal output terminal includes a positive differential output port and a negative differential output port, with an adjustable resistor module connected between the two ports. The adjustable resistor module includes multiple resistor branches connected in parallel, each branch including a resistor and a switching transistor connected in series, with the on / off state of each switching transistor independently controlled. By configuring the on / off state of each switching transistor, the equivalent resistance value of the adjustable resistor module is adjusted, thereby adjusting the output impedance of the interface module's transmitting end at the differential signal output terminal, matching the output impedance with the load impedance of the receiving end to suppress signal reflection.

[0129] In another optional embodiment, the signal conditioning method further includes adjusting the common-mode voltage. Specifically, the interface module transmitter further includes a common-mode feedback module connected to the differential signal output. The common-mode feedback module detects the common-mode voltage of the differential signal, compares the detection result with a reference voltage, and generates a feedback signal to the driver to control the driver to adjust the common-mode voltage of the differential signal to equal the reference voltage. The reference voltage is configured via a register; by configuring different reference voltage values, the common-mode voltage of the differential signal can be adjusted to different target values ​​to adapt to the common-mode voltage requirements of different transmission protocols.

[0130] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0131] In the embodiments provided in this disclosure, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0132] In the description of this disclosure, it should be understood that if the terms "upper", "lower", "front", "rear", "left" and "right" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the position or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0133] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0134] The above are merely embodiments of this disclosure and are not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of the claims of this disclosure.

Claims

1. An interface module transmitter, characterized in that, Includes a driver, the driver comprising: The signal input terminal is used to receive input signals. Differential signal output terminal, used to output differential signals; The main drive unit is connected between the signal input terminal and the differential signal output terminal, and is used to receive the input signal and generate the main output signal; A sub-driving unit is connected between the signal input terminal and the differential signal output terminal, and is used to receive the same input signal and generate a sub-output signal; A delay adjustment module is connected between the signal input terminal and the main drive unit and / or the sub-drive unit, and is used to adjust the delay time of the sub-output signal relative to the main output signal; The differential signal is a linear superposition of the main output signal and the sub-output signal; the time-domain waveform parameters of the differential signal are configured to be adjusted by adjusting the amplitude relationship and / or time relationship of the output signals of the main driving unit and the sub-driving unit.

2. The interface module sending end according to claim 1, characterized in that, Both the main drive unit and the sub-drive unit include multiple drive unit chips connected in parallel, and the enable states of the drive unit chips are independent of each other. The number of drive unit chips in the main drive unit that are in the enabled state is greater than the number of drive unit chips in the sub-drive unit that are in the enabled state.

3. The interface module sending end according to claim 2, characterized in that, When the time-domain waveform parameters of the differential signal are configured to be adjusted by regulating the amplitude relationship between the output signals of the main driving unit and the sub-driving unit, The greater the ratio of the number of drive unit chips turned on in the sub-drive unit relative to the number of drive unit chips turned on in the main drive unit, the greater the amplitude of the output signal of the sub-drive unit relative to the amplitude of the output signal of the main drive unit.

4. The interface module sending end according to claim 1, characterized in that, The delay adjustment module includes: The first adjustable delay unit is connected between the signal input terminal and the input terminal of the sub-driving unit. The second adjustable delay unit is connected between the signal input terminal and the input terminal of the main drive unit; The delay amount of the first adjustable delay unit and the delay amount of the second adjustable delay unit are configured independently.

5. The interface module sending end according to claim 4, characterized in that, When the time-domain waveform parameters of the differential signal are configured to be adjusted by regulating the time relationship between the output signals of the main driving unit and the sub-driving unit, wherein, When the first adjustable delay unit and the second adjustable delay unit are configured with different delay amounts, the sub-output signal has a delay time relative to the main output signal to adjust the slew rate of the differential signal; or When the first adjustable delay unit and the second adjustable delay unit are configured with the same delay amount, the sub-output signal is synchronously delayed relative to the main output signal, and the offset timing of the differential signal in the channel where the interface module's transmitting end is located is adjusted.

6. The interface module sending end according to claim 1, characterized in that, The interface module transmitter also includes a common-mode feedback module connected to the differential signal output terminal, used to detect the common-mode voltage of the differential signal and generate a feedback signal to the driver, so as to control the driver to adjust the common-mode voltage of the differential signal to be equal to the reference voltage.

7. The interface module sending end according to claim 1, characterized in that, The differential signal output terminal is used to connect to the receiving end, and the differential signal output terminal includes a positive differential output port and a negative differential output port. The interface module transmitter also includes an adjustable resistor module, which is connected between the positive differential output port and the negative differential output port, and is used to adjust the output impedance of the interface module transmitter according to the load impedance of the receiver.

8. The interface module sending end according to claim 1, characterized in that, The interface module transmitter includes an independently configured clock channel transmitter and a data channel transmitter. The clock channel transmitter includes the driver, and the signal input terminal of the clock channel transmitter is used to receive clock signals; The data channel transmitter includes the driver, and the signal input terminal of the data channel transmitter is used to receive data signals.

9. The interface module sending end according to claim 8, characterized in that, The time-domain waveform parameters include slew rate, which is adjusted by adjusting the relative delay time between the main driving unit and the sub-driving unit in the clock channel transmitter and / or the ratio of the number of driving unit chips that are turned on; and by adjusting the relative delay time between the main driving unit and the sub-driving unit in the data channel transmitter and / or the ratio of the number of driving unit chips that are turned on, so that the difference between the slew rate of the clock signal and the slew rate of the data signal is within a preset threshold range.

10. A signal conditioning method for the transmitting end of an interface module, characterized in that, include: The signal input terminal receives the input signal; An input signal is provided to the main drive unit so that the main drive unit generates a main output signal at the differential signal output terminal; The delay adjustment module performs delay processing on the input signal; the delay adjustment module outputs the delayed input signal to the sub-drive unit, so that the sub-drive unit generates a sub-output signal with a delay relative to the main output signal at the differential signal output terminal; Adjust the amplitude relationship and / or time relationship of the output signals of the main driving unit and the sub-driving unit to adjust the time-domain waveform parameters of the differential signal; The differential signal is generated by linearly superimposing the main output signal and the sub-output signal.

Images