A time-sharing scanning based display key multiplexing driving circuit and method

Abstract

The application provides a display key multiplexing driving circuit and method based on time-sharing scanning, and the display key multiplexing driving circuit comprises: a multiplexing driving chip, the multiplexing driving chip is provided with a communication pin electrically connected with a main controller, a plurality of anode driving pins and cathode bit selection pins; a detection unit, the detection unit adopts an OR gate logic device, two input channels of the OR gate logic device are connected with two cathode bit selection pins respectively, and one output channel is connected with a first input pin of the main controller; and an anti-reverse unit, the anti-reverse unit comprises: a controllable switch and a plurality of clamping diodes, the controllable switch is provided with a first end, a second end and a control end, the anodes of the clamping diodes are connected with the cathode bit selection pins respectively, the cathodes are connected with the first end after being connected in common, and the control end is connected with a second output pin of the main controller. The application solves the technical problem that the prior art cannot completely eliminate the periodic reverse voltage borne by the LED without sacrificing the key recognition accuracy and without significantly increasing the material cost.

Description

Technical Field

[0001] This invention relates to the field of LED digital tube driving and matrix key scanning circuit technology, and more specifically, to a display key multiplexing driving circuit based on time-division scanning and a display key multiplexing driving method based on time-division scanning. Background Technology

[0002] Time-division scanning multiplexed driver chips rely on the multiplexing of anode drive pins to realize LED segment code output and key row level acquisition, and the cathode digit selection pins to output high and low levels in a time-division manner to complete the digital tube digit selection and key column scanning. With the advantage of driving the display and human-machine buttons simultaneously with a single chip, they have been widely used in home appliance control panels.

[0003] The complete working cycle of this type of chip alternates between the display scan drive stage and the key scan drive stage. The output logic of the cathode bit selection pin is completely opposite in the two stages: In the display scan drive stage, the cathode bit selection pin outputs a low level in sequence to light up the corresponding LED; for LEDs that do not need to be lit, their anode drive pin outputs a low level. When the cathode bit selection pin corresponding to the LED switches to a high level, the cathode potential of the LED is higher than the anode potential, and the two ends of the LED continuously bear a periodic reverse voltage.

[0004] The relevant technologies have at least one of the following problems: the existing technologies cannot completely eliminate the periodic reverse voltage borne by the LED without sacrificing the accuracy of button recognition or significantly increasing the material cost. Summary of the Invention

[0005] This invention solves the technical problem that existing technologies cannot completely eliminate the periodic reverse voltage borne by LEDs without sacrificing button recognition accuracy or significantly increasing material costs.

[0006] To address the aforementioned problems, this invention provides a display button multiplexing drive circuit based on time-division scanning, comprising: a multiplexing drive chip integrating display scanning drive and button scanning drive functions, the multiplexing drive chip having a communication pin, multiple anode drive pins, and multiple cathode position selection pins, the communication pin being electrically connected to a main controller; a detection unit employing an OR gate logic device, the OR gate logic device having two input channels and one output channel, the two input channels being respectively connected to two cathode position selection pins, and the one output channel being connected to the first input pin of the main controller; and an anti-reverse unit comprising: a controllable switch and multiple clamping diodes, the controllable switch having a first terminal, a second terminal, and a control terminal, the anodes of the clamping diodes being respectively connected to the cathode position selection pins, the cathodes of the multiple clamping diodes being connected together and then connected to the first terminal, the second terminal being grounded, and the control terminal being connected to the second output pin of the main controller.

[0007] Compared with existing technologies, the technical effects achieved by this solution are as follows: The detection unit is used to acquire the real-time level waveforms of two cathode bit selection pins in the multiplexed driver chip, performs a logical OR operation on the two cathode levels, and identifies the current scanning stage based on the output level; by acquiring the two cathode waveforms through an OR gate logic device, the display and key scanning drive stages are distinguished at the hardware level, and the identification reliability is far higher than that of pure software timing judgment, and is not affected by program interruption or power ripple interference; The anti-reverse unit realizes dynamic switching, avoiding the need for internal architecture adjustments of the multiplexed driver chip: during the display scanning drive stage, the clamping diode is connected to the circuit to eliminate LED reverse voltage, and during the key scanning drive stage, it is disconnected to eliminate the diode conduction voltage drop, thus balancing LED protection and key recognition accuracy, overcoming the industry pain point that existing technologies cannot achieve both simultaneously.

[0008] In one embodiment of the present invention, the multiplexing driver chip is the TM1650 chip.

[0009] Compared with existing technologies, the technical effects achieved by adopting this technical solution are as follows: using the mainstream TM1650 chip as the implementation carrier, the solution can be directly adapted to a large number of existing home appliances and instrument products that use TM1650, and the transformation difficulty is low; the 8-anode and 4-cathode pin architecture of the TM1650 chip is clearly defined, providing a standardized hardware basis for the wiring of the display unit and button unit, which is convenient for those skilled in the art to replicate and implement.

[0010] In one embodiment of the present invention, the display button multiplexing driving circuit further includes: a display unit circuit, which includes multiple common cathode display lamp groups, each display lamp group being connected to a corresponding cathode position selection pin, and each display lamp group including multiple light-emitting LEDs, with the anodes of the light-emitting LEDs in the same segment being uniformly connected to the corresponding anode driving pin; and a button unit circuit, which includes multiple button matrix groups, each button matrix group being connected to a corresponding cathode position selection pin, and each button matrix group including multiple independent buttons, with the input terminals of the independent buttons in the same segment being uniformly connected to the corresponding anode driving pin.

[0011] Compared with existing technologies, the technical effects achieved by adopting this technical solution are as follows: It fully defines the hardware composition and wiring logic of the LED display array and the 4×8 matrix button array, fully matches the TM1650 standard multiplexing circuit architecture, and the technical solution is fully disclosed, requiring no additional creative work by those skilled in the art to build a complete circuit; it clearly distinguishes the multiplexing logic of "anode common row and cathode independent column", clarifies the common cathode arrangement of LEDs and the arrangement of the button matrix, eliminates wiring ambiguity, and avoids circuit construction errors during implementation.

[0012] In one embodiment of the present invention, the detection unit further includes: a first current-limiting resistor and a second current-limiting resistor, the first current-limiting resistor and the second current-limiting resistor being respectively connected between the input channel and the cathode bit selection pin; a first capacitor, one end of the first capacitor being connected to the output channel, and the other end of the first capacitor being grounded.

[0013] Compared with existing technologies, the technical effects achieved by this solution are as follows: the current-limiting resistor limits the cathode output current, protects the input ports of the OR gate logic devices, avoids burning out the OR gate logic devices due to the large current output of the multiplexed driver chip pins, and improves the long-term operational stability of the circuit; the filter capacitor filters out high-frequency pulse interference in the cathode waveform, smooths the output level of the OR gate, eliminates misidentification during the scanning stage caused by instantaneous noise, and further reduces the probability of erroneous switching of the controllable switch; it improves all the hardware components of the detection unit, forming a complete waveform recognition link of current-limiting acquisition - logic operation - filtering output, integrating hardware protection and signal processing.

[0014] In one embodiment of the present invention, the controllable switch is selected from any one of an NPN transistor, an NMOS transistor, and an electromagnetic relay. When the controllable switch is an NPN transistor, the base of the NPN transistor is connected to the second output pin, the emitter is grounded, and the collector is connected to the cathode of all clamping diodes. When the controllable switch is an NMOS transistor, the gate of the NMOS transistor is connected to the second output pin, the source is grounded, and the drain is connected to the cathode of all clamping diodes. When the controllable switch is an electromagnetic relay, one end of the coil of the electromagnetic relay is connected to the second output pin, and the other end of the coil is connected to the power supply through a current-limiting resistor. One end of the normally open contact of the electromagnetic relay is connected to the cathode of all clamping diodes, and the other end is grounded.

[0015] Compared with existing technologies, the technical effects achieved by adopting this solution are as follows: it provides three types of low-cost general-purpose controllable switching devices, which are compatible with different power supply panels of 3.3V and 5V. NPN transistors / NMOS transistors are used for small signal control, and electromagnetic relays are used for large current loads, making product selection flexible. The wiring relationship between each type of controllable switch and the second output pin of the main controller, the common cathode of the clamping diode, and ground is clearly defined. Different devices can be directly grounded, expanding the applicable scenarios of the solution.

[0016] In one embodiment of the present invention, the display button multiplexing drive circuit has multi-load adaptive control logic; when in a pure LED load scenario, the main controller continuously outputs a high level to the second output pin, and the controllable switch is permanently turned on; when in a pure button load scenario, the main controller continuously outputs a low level to the second output pin, and the controllable switch is permanently turned off; when in a mixed load scenario, the main controller dynamically switches the on / off state of the controllable switch according to the level of the first input pin; wherein, the pure LED load scenario is: only the display unit circuit is configured, and there is no button unit circuit; the pure button load scenario is: only the button unit circuit is configured, and there is no display unit circuit; the mixed load scenario is: both the display unit circuit and the button unit circuit are configured.

[0017] Compared with existing technologies, the technical effects achieved by adopting this technical solution are as follows: a single hardware circuit can adapt to three types of mainstream panel load scenarios without modifying the hardware; the control logic can be switched only through software program configuration, greatly improving hardware versatility; pure LED loads maintain reverse voltage protection throughout the process, completely eliminating LED reverse breakdown; pure button loads disconnect the clamping branch throughout the process, eliminating diode voltage drop interference with button recognition; and mixed loads can be dynamically switched in a time-sharing manner, taking into account both functions.

[0018] In one embodiment of the present invention, the main controller has a built-in timing module, a GPIO level acquisition module, a mode judgment module, and a switch control output module. The main controller acquires the level of the first input pin to identify the chip scanning mode, controls the on / off state of the controllable switch through the second output pin, and temporarily shuts down the real-time level acquisition of the first input pin to avoid waveform interference by setting the shielding duration through the timing module.

[0019] Compared with existing technologies, the technical effects achieved by this solution are as follows: A dual anti-misoperation mechanism is constructed, combining hardware waveform recognition and software timing shielding. Hardware recognition distinguishes the scanning phase, while software timing shielding prevents noise interference during the phase, thus eliminating the possibility of controllable switches being accidentally turned on or off. The main controller functions are modularly divided, resulting in clear logic, low software development difficulty, and ease of writing supporting control programs for engineers. The timing shielding mechanism prevents accidental disconnection of the protection during the display scanning drive phase and accidental activation of the diode branch during the button press phase, further improving LED reliability and button recognition stability.

[0020] On the other hand, embodiments of the present invention also provide a display button multiplexing driving method based on time-division scanning, applied to the display button multiplexing driving circuit as described in any embodiment of the present invention. The display button multiplexing driving method includes: after power-on initialization, the multiplexing driving chip starts cyclic scanning, and the main controller continuously acquires the level of the first input pin; based on the level of the first input pin, the scanning working stage is determined; based on the scanning working stage, the on / off state of the controllable switch is controlled, and the real-time level acquisition of the first input pin is temporarily turned off, and the timing module in the main controller is controlled to start timing; when the timing duration of the timing module reaches the duration threshold, the main controller clears the timing module and resumes the real-time level acquisition of the first input pin; wherein, the scanning working stage includes: a display scanning driving stage and a button scanning driving stage.

[0021] Compared with existing technologies, the technical effects achieved by adopting this technical solution are as follows: it provides a standardized closed-loop control method that matches the hardware circuit, with software and hardware working together to give full play to the innovative role of the hardware detection unit and the dynamic anti-reverse unit; the process runs in a loop, continuously and in real time identifying the scanning stage and dynamically switching the protection branch, without manual intervention throughout the process, and automatically adapting to the chip time-division scanning sequence.

[0022] In one embodiment of the present invention, according to the scanning operation stage, the controllable switch is turned on and off, and the real-time level acquisition of the first input pin is temporarily turned off. The timing module in the main controller is then controlled to start timing. This includes: when the scanning operation stage is the display scanning drive stage, the main controller turns on the controllable switch through the output control signal of the second output pin, multiple clamping diodes are connected to the cathode circuit, and the real-time level acquisition of the first input pin is temporarily turned off. The timing module starts timing according to the first timing threshold. When the scanning operation stage is the key scanning drive stage, the main controller turns off the controllable switch through the output control signal of the second output pin, multiple clamping diodes are disconnected from the cathode circuit, and the real-time level acquisition of the first input pin is temporarily turned off. The timing module starts timing according to the second timing threshold.

[0023] Compared with existing technologies, the technical effects achieved by adopting this technical solution are as follows: It clarifies the differentiated control logic for the two scanning stages, corresponding to the dynamic switching function of the hardware circuit. Program developers can directly write control code according to the steps, resulting in a low threshold for implementation. It distinguishes two sets of independent timing thresholds, which are matched with the display and button scanning cycle durations respectively. The shielding duration is consistent with the inherent timing of the chip, maximizing the shielding of interference without affecting the stage switching recognition.

[0024] In one embodiment of the present invention, determining the scanning operation stage based on the level of the first input pin includes: when the level of the first input pin is detected to be high, determining the scanning operation stage to be a display scanning drive stage; when the level of the first input pin is detected to be low, determining the scanning operation stage to be a key scanning drive stage.

[0025] Compared with existing technologies, the technical effects achieved by adopting this technical solution are as follows: It provides standardized level judgment logic, and the software mode judgment module can directly complete the stage identification through high and low levels. The logic is simple, the operation speed is fast, and it does not occupy the computing power of the main controller. The judgment rules are completely matched with the output logic of the OR gate, the software and hardware judgment standards are unified, there is no logical conflict, and the root cause of mode misjudgment is completely eliminated.

[0026] By adopting the technical solution of the present invention, the following technical effects can be achieved: (1) The anti-reverse unit achieves dynamic switching to avoid the need to reuse the internal architecture adjustment of the driver chip: the clamping diode is connected to the circuit during the display scanning drive stage to eliminate the LED reverse voltage, and disconnected during the button scanning drive stage to eliminate the diode conduction voltage drop. At the same time, it takes into account both LED protection and button recognition accuracy, overcoming the industry pain point that the two cannot be achieved simultaneously in the existing technology. (2) Two cathode waveforms are acquired through OR gate logic devices. The display and key scanning drive stages are distinguished at the hardware level. The recognition reliability is much higher than that of pure software timing judgment and is not affected by program interruption or power ripple interference. (3) Construct a dual anti-misoperation mechanism of hardware waveform recognition + software timed shielding. Hardware recognition distinguishes the scanning working stage, and software timed shielding prevents noise interference during the stage. The dual protection eliminates the accidental switching on and off of controllable switches. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Figure 1 This is a circuit diagram of a display key multiplexing driving circuit based on time-division scanning, provided in Embodiment 1 of the present invention. Figure 2 for Figure 1 A partially enlarged schematic diagram showing the pin connections of the shared driver chip for the display unit circuit and the button unit circuit. Figure 3 for Figure 1 A circuit diagram showing the connection between the multiplexed driver chip, display unit circuit, and key unit circuit; Figure 4 This is a circuit diagram of a display button multiplexing drive circuit in the prior art; Figure 5 To reuse the drive output waveform of the cathode bit select pin in the driver chip; Figure 6This is a detailed flowchart of a display button multiplexing driving method based on time-division scanning, provided in Embodiment 2 of the present invention.

[0028] Explanation of reference numerals in the attached figures: 2. Main controller; 10. Multiplexed driver chip; 20. Detection unit; 30. Anti-reverse unit; 40. Display unit circuit; 41. First channel display light group; 50. Key unit circuit; 51. First channel key matrix group. Detailed Implementation

[0029] To make the above-mentioned objectives, features, and advantages of the present invention more apparent and understandable, the technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Example 1 See Figure 1 This is a circuit diagram of a display button multiplexing driving circuit based on time-division scanning provided in the first embodiment of the present invention, combined with... Figures 2-5 The display button multiplexing drive circuit includes: a multiplexing drive chip 10, a detection unit 20, and an anti-reverse unit 30. The multiplexing drive chip 10 integrates display scanning drive and button scanning drive functions. The multiplexing drive chip 10 is provided with a communication pin, multiple anode drive pins, and multiple cathode position selection pins. The communication pin is electrically connected to the main controller 2. The detection unit 20 adopts an OR gate logic device. The OR gate logic device is provided with two input channels and one output channel. The two input channels are respectively connected to two cathode position selection pins, and the one output channel is connected to the first input pin of the main controller 2. The anti-reverse unit 30 includes: a controllable switch and multiple clamping diodes. The controllable switch is provided with a first terminal, a second terminal, and a control terminal. The anodes of the clamping diodes are respectively connected to the cathode position selection pins. The cathodes of the multiple clamping diodes are connected together and then connected to the first terminal. The second terminal is grounded. The control terminal is connected to the second output pin of the main controller 2.

[0031] Figure 3 In the existing display button driving circuit, the multiplexed driver chip 10 integrates display scanning driving and button scanning driving functions. The driving working principle of the multiplexed driver chip 10 is as follows: Figure 5 The diagram shows the drive output waveform of the cathode bit selection pin of the multiplexed driver chip 10, where pin DIG1 is represented by a blue line, pin DIG2 by a red line, pin DIG3 by a green line, and pin DIG4 by a yellow line. The cathode bit selection pin is a fixed scan drive output interface. Figure 4In a complete display and button scanning drive cycle, the back voltage pulse of the LED during the button scanning drive stage accounts for a very small percentage (1%), and the back voltage energy is extremely low and can be ignored.

[0032] During the display scan drive phase, the cathode bit selection pins DIG1 to DIG4 output low levels sequentially (i.e., scan output low levels), and the anode drive pins A to DP control the level according to display requirements (i.e., the anode drive interface is the control port, outputting high / low levels according to display requirements); specifically, according to the display control signal of the main controller 2, when a certain LED needs to be lit, its connected anode drive pin outputs a high level, and its connected cathode bit selection pin outputs a low level during scan, the LED is lit; Figure 5 In the process, the cathode position selection pins DIG1 to DIG4 continuously perform 3 display cycle scans.

[0033] During the key scanning drive phase, the cathode bit selection pins DIG1 to DIG4 output high levels (i.e., scan output high levels), and the anode drive pins A to DP serve as key detection terminals. Specifically, when an independent key S is pressed, when the cathode bit selection pin connected to it scans and outputs a high level, the anode drive pin connected to it detects a high level, and the system determines that the corresponding key has been pressed.

[0034] Based on the above-described working principle of the multiplexed driver chip 10, this driving method of the multiplexed driver chip 10 has an inherent defect in the display scanning driving stage: when any light-emitting LED (which can...) Figure 2 Taking LED-A2 as an example, when it is not needed to be lit, its connected anode drive pin A outputs a low level. When its connected cathode bit selection pin DIG2 scans and outputs a high level, the LED experiences reverse voltage (i.e., the cathode voltage of the LED is higher than its anode voltage). Long-term reverse voltage scanning poses a risk of LED burnout and affects normal display. In practical applications, this is particularly unfavorable for commonly used low-specification reverse voltage (5V) LEDs.

[0035] In one specific embodiment, X is an OR gate logic device, specifically a dual-channel input OR gate logic device; Y is a controllable switch, controlled by the second output pin GPIO2; D1~D4 are clamping diodes, with the anodes of diodes D1~D4 connected to four cathode bit selection pins respectively, and the cathodes of diodes D1~D4 connected to one end of the controllable switch Y, the other end of the controllable switch Y being grounded. The multiplexed driver chip 10 in this application integrates display scanning drive and key scanning drive functions. This multiplexed driver chip 10 can be externally connected to the display unit circuit 40 and the key unit circuit 50, accommodating both display drive control and key detection drive control; the communication pins of the multiplexed driver chip 10 are electrically connected to the communication interface of the main controller 2, completing the display segment code transmission and key scan data feedback.

[0036] A detection unit 20 and a controllable anti-reverse unit 30 are added outside the cathode position selection pin of the multiplexed driver chip 10. The OR gate logic device of the detection unit 20 collects the driving signals of the two cathode position selection pins to identify and distinguish between the display scan driving stage and the key scan driving stage. The output signal is connected to the main controller 2 through the first input pin GPIO1. The main controller 2 reads the cathode waveform data of the multiplexed driver chip 10 in real time through the detection unit 20 and determines the current scanning stage: when in display scan driving mode, the anti-reverse unit 30 is turned on to clamp the level of the cathode position selection pin to prevent reverse voltage from damaging the LED; when in key scan driving mode, the anti-reverse unit 30 is turned off to prevent the level of the cathode position selection pin from being pulled low, eliminating loop voltage drop and ensuring key detection accuracy. This solution has a simple circuit structure and low cost, does not require modification of the internal architecture of the multiplexed driver chip 10, and balances display effect and key sensitivity. It can be widely used in the driving circuit of the multiplexed driver chip 10 to improve the reliability of product design.

[0037] from Figure 5 It can be seen that the waveforms of DIG2 and DIG3 are clearly separated in the display scan drive stage and the key scan drive stage. Therefore, the levels of DIG2 and DIG3 are collected (1 represents high level and 0 represents low level in the figure). In the display scan drive stage, the output signal of the OR gate logic device X is high level. When entering the key scan drive stage, the OR gate logic device X outputs low level. By recognizing this information, it can be determined which scan drive stage is currently in. DIG2 and DIG3 are two cathode bit selection pins of the multiplexed driver chip 10.

[0038] Furthermore, the multiplexed driver chip 10 uses the TM1650 chip.

[0039] Specifically, the TM1650 chip is a dedicated IC for LED scanning driver control with integrated button scanning driver function. (See [link to relevant documentation]). Figure 3 The diagram shows the interface layout of the TM1650 chip: The TM1650 chip includes a power supply pin VCC, a ground pin GND, communication pins CLK and DAT, eight anode drive pins A, B, C, D, E, F, G and DP, and four cathode bit selection pins DIG1, ​​DIG2, DIG3 and DIG4; the communication pins CLK and DAT are used for electrical connection with the communication interface of the main controller 2; multiple anode drive pins are simultaneously multiplexed to connect the signal input terminals of the display unit circuit 40 and the key unit circuit 50; and multiple cathode bit selection pins are respectively connected to the scan column terminals of the display unit circuit 40 and the key unit circuit 50.

[0040] Further, see Figure 2The display button multiplexing drive circuit also includes: a display unit circuit 40 and a button unit circuit 50. The display unit circuit 40 includes multiple common cathode display lamp groups, each display lamp group is connected to a cathode position selection pin, and each display lamp group includes multiple light-emitting LEDs. The anodes of the light-emitting LEDs in the same segment are uniformly connected to the corresponding anode drive pin. The button unit circuit 50 includes multiple button matrix groups, each button matrix group is connected to a cathode position selection pin, and each button matrix group includes multiple independent buttons. The input terminals of the independent buttons in the same segment are uniformly connected to the corresponding anode drive pin.

[0041] Specifically, the display unit circuit 40 includes m common cathode LED groups, each consisting of n LEDs in the same column. Some of these LED groups can be used as n-segment digital displays. The cathodes of the LEDs in the same column are connected to a cathode selection pin of the multiplexed driver chip 10, and the anodes of the LEDs in the same row are connected to an anode drive pin of the multiplexed driver chip 10. Similarly, the button unit circuit 50 includes a button matrix groups, each consisting of b independent buttons in the same column. The right end of each independent button in the same column is connected to a cathode selection pin of the multiplexed driver chip 10, and the left end of each independent button in the same row is connected to an anode drive pin of the multiplexed driver chip 10.

[0042] Preferably, m is 4 and n is 8 to form a 4-digit 8-segment digital tube for displaying temperature and operating mode; a is 4 and b is 8 to form a 4×8 matrix keypad for inputting functions such as temperature adjustment, mode switching, fan speed, and timer; m and a are the same, and n and b are the same, so that the LEDs in the display unit circuit 40 correspond one-to-one with the independent keys in the keypad unit circuit 50.

[0043] like Figure 2 As shown, LED-A1 to LED-DP4 are light-emitting LEDs, and S11 to S84 are independent buttons. The display unit circuit 40 includes four common cathode LED groups, each of which includes eight light-emitting LEDs (i.e., four columns and eight rows of light-emitting LEDs). For example, the first LED group 41 includes eight light-emitting LEDs, LED-A1 to LED-DP1. The button unit circuit 50 includes four button matrix groups, each of which includes eight independent buttons (i.e., four columns and eight rows of independent buttons). For example, the first button matrix group 51 includes eight independent buttons, S11 to S81. Among them, the light-emitting LEDs and independent buttons in the same row and column share the same cathode position selection pin and anode drive pin. For example, LED-A1 and S11 share the cathode position selection pin DIG1 and the anode drive pin A; LED-C3 and S33 share the cathode position selection pin DIG3 and the anode drive pin C.

[0044] Furthermore, the detection unit 20 also includes: a first current-limiting resistor and a second current-limiting resistor and a first capacitor, the first current-limiting resistor and the second current-limiting resistor being connected between the input channel and the cathode position selection pin respectively; one end of the first capacitor is connected to the output channel, and the other end of the first capacitor is grounded.

[0045] Specifically, R1 is the first current-limiting resistor, R2 is the second current-limiting resistor, and C1 is the first capacitor. The two input channels of the OR gate logic device are connected to two different cathode bit selection pins of the multiplexed driver chip 10 through current-limiting resistors R1 and R2, respectively. In this embodiment, DIG2 and DIG3 are selected. The first and second current-limiting resistors limit the cathode output current, protect the input channels during the OR gate logic period, avoid the chip pins outputting large currents that burn out the OR gate logic device, and improve the long-term operating stability of the circuit. One output channel of the OR gate logic device is connected to the first input pin GPIO1 of the main controller 2, and is grounded through C1. The first capacitor filters out high-frequency pulse interference from the cathode waveform, smooths the OR gate output level, eliminates the misidentification during the scanning stage caused by instantaneous noise, and further reduces the probability of mis-switching of the controllable switch.

[0046] Preferably, the first current-limiting resistor R1 and the second current-limiting resistor R2 are carbon film current-limiting resistors; the first capacitor C1 is a ceramic filter capacitor; the OR gate logic device X is a dual-channel two-input OR gate integrated circuit, and the power supply voltage matches the TM1650 chip's 3.3V or 5V operating voltage.

[0047] Furthermore, the controllable switch can be any one of an NPN transistor, an NMOS transistor, or an electromagnetic relay. When an NPN transistor is used, the base of the NPN transistor is connected to the second output pin, the emitter is grounded, and the collector is connected to the cathode of all clamping diodes. When an NMOS transistor is used, the gate of the NMOS transistor is connected to the second output pin, the source is grounded, and the drain is connected to the cathode of all clamping diodes. When an electromagnetic relay is used, one end of the electromagnetic relay coil is connected to the second output pin, and the other end of the coil is connected to the power supply through a current-limiting resistor. One end of the normally open contact of the electromagnetic relay is connected to the cathode of all clamping diodes, and the other end is grounded.

[0048] Specifically, this embodiment provides three types of low-cost universal controllable switches, which are compatible with different power supply panels of 3.3V and 5V. NPN transistors / NMOS transistors are used for small signal control, and electromagnetic relays are used for large current loads, allowing for flexible product selection. The wiring relationship between each controllable switch device and the second output pin of the main controller 2, the common cathode of the clamping diode, and ground is clearly defined. Different devices can be directly grounded, expanding the applicable scenarios of the solution.

[0049] Preferably, when applied to an air conditioner control panel, the controllable switch is preferably an NPN transistor; when applied to a power supply smart meter, the controllable switch is preferably an NMOS transistor; and when applied to an induction cooker control panel, the controllable switch is preferably an electromagnetic relay.

[0050] Furthermore, the display button multiplexing drive circuit has multi-load adaptive control logic; when in a pure LED load scenario, the main controller 2 continuously outputs a high level to the second output pin, and the controllable switch is permanently turned on; when in a pure button load scenario, the main controller 2 continuously outputs a low level to the second output pin, and the controllable switch is permanently turned off; when in a mixed load scenario, the main controller 2 dynamically switches the on / off state of the controllable switch according to the level of the first input pin; wherein, the pure LED load scenario is: only the display unit circuit 40 is configured, and there is no button unit circuit 50; the pure button load scenario is: only the button unit circuit 50 is configured, and there is no display unit circuit 40; the mixed load scenario is: both the display unit circuit 40 and the button unit circuit 50 are configured.

[0051] Specifically, the system differentiates between three scenarios: pure LED load, pure button load, and mixed load. Control logic for the two pairs of controllable switches in the main controller is defined for each scenario: the switch for a pure LED load is permanently on, the switch for a pure button load is permanently off, and the switch for a mixed load is dynamically switched. A single hardware circuit adapts to all three mainstream panel load scenarios without requiring hardware modifications; the control logic can be switched solely through software configuration, significantly improving hardware versatility. Pure LED loads maintain reverse voltage protection throughout, completely eliminating LED reverse breakdown. Pure button loads have their clamping branches disconnected throughout, preventing interference from clamping diode voltage drops that could affect button recognition. Mixed loads feature time-sharing dynamic switching, balancing both functions.

[0052] Furthermore, the main controller 2 has a built-in timing module, GPIO level acquisition module, mode judgment module, and switch control output module. The main controller 2 acquires the level of the first input pin to identify the chip scanning mode, controls the on / off state of the controllable switch through the second output pin, and temporarily shuts down the real-time level acquisition of the first input pin to avoid waveform interference by setting the shielding duration through the timing module.

[0053] Specifically, the main controller 2 reads the GPIO1 level signal to identify the current TM1650 scanning working mode, and outputs a control level to GPIO2 to switch the controllable switch Y on and off according to the scanning working mode. At the same time, a fixed shielding duration is set through the timing module to temporarily disable the real-time level acquisition of GPIO1, shielding the instantaneous noise interference of the scanning waveform and avoiding accidental switching of the controllable switch.

[0054]

Example 2

[0055] Furthermore, S3 includes: S31: When the scanning operation stage is the display scanning drive stage, the main controller turns on the controllable switch through the output control signal of the second output pin, multiple clamping diodes are connected to the cathode circuit, and the real-time level acquisition of the first input pin is temporarily turned off. The timing module starts timing according to the first timing threshold. S32: When the scanning operation is in the key scanning drive stage, the main controller disconnects the controllable switch through the output control signal of the second output pin, the multiple clamping diodes are disconnected from the cathode circuit, and the real-time level acquisition of the first input pin is temporarily turned off. The timing module starts timing according to the second timing threshold.

[0056] Furthermore, S2 includes: When a high level is detected on the first input pin, the scanning operation phase is determined to be the display scanning drive phase; When the level of the first input pin is detected to be low, the scanning operation stage is determined to be the key scanning drive stage.

[0057] In one specific embodiment, the process of this application runs in a loop, continuously and in real time identifying the scanning work stage and dynamically switching the protection branch, without any manual intervention, and automatically adapting to the chip time-sharing scanning sequence.

[0058] The specific process includes: ①. Powering on and initializing the entire machine, the TM1650 chip starts its cyclic scanning operation and executes the display button scanning driver. The main controller continuously monitors the GPIO1 pin level in real time. When the main controller detects a high level input to GPIO1, it determines that it has entered the display scanning driver stage. The main controller drives the controllable switch Y to close and conduct through the high level output of GPIO2. The four clamping diodes D1~D4 are connected to the cathode circuit, clamping the potential of the DIG1~DIG4 pins and blocking the reverse voltage of the LED. The main controller temporarily disables the GPIO1 real-time level acquisition function and starts the timing module to start timing according to the first timing threshold t1. ②. The main controller continuously reads the timing value of the timing module. When the timing duration is equal to t1, the main controller resets the timing module to zero and restores the GPIO1 pin real-time level acquisition. ① The main controller continuously monitors the scan drive signal by acquiring the real-time level of the GPIO1 pin. When the main controller detects a low level input to GPIO1, it determines that it has entered the key scan drive stage. The main controller drives the controllable switch Y to turn off by outputting a low level through GPIO2. The four clamping diodes D1~D4 are disconnected from the cathode circuit, eliminating the forward voltage drop of the clamping diodes. The main controller temporarily disables the real-time level acquisition function of GPIO1 and starts the timing module to start timing according to the second timing threshold t2. ② The main controller continuously reads the timing value of the timing module. When the timing duration is equal to t2, the main controller resets the timing module to zero and restores the real-time level acquisition function of the GPIO1 pin. ③ The system loops back to ① and continuously executes the dynamic switching control logic between the display and key scan drive stages.

[0059] The purpose of temporarily disabling GPIO1 real-time acquisition in S31 is to shield the interference signals generated by the instantaneous level fluctuations of DIG2 and DIG3 during the display scan drive phase, prevent the OR gate logic device X from outputting an erroneous low level, causing the controllable switch Y to be mistakenly disconnected, and avoid the LED losing its reverse voltage protection. The software program reduces misjudgment and miscontrol. The purpose of temporarily disabling GPIO1 real-time acquisition in S32 is to shield the instantaneous low-level interference signals during the button scan drive phase, prevent the controllable switch Y from being mistakenly turned on, and avoid voltage drop distortion caused by button acquisition.

[0060] Preferably, the preferred value of t1 is 12ms. The duration of the display scan drive phase of the TM1650 chip is 12.6ms. t1 needs to be less than 12.6ms to ensure that the main controller can promptly resume GPIO1 monitoring for subsequent exit from the display scan drive phase and entry into the button scan drive phase. The preferred value of t2 can be 390us. The duration of one high-level signal in the button scan drive phase of the TM1650 chip is 130us. The total duration of three high-level pulses is 390us.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display key multiplexing driving circuit based on time-division scanning, characterized in that, The display button multiplexing drive circuit includes: The multiplexed driver chip (10) integrates display scanning driver and key scanning driver functions. The multiplexed driver chip (10) is provided with communication pins, multiple anode driving pins and multiple cathode position selection pins. The communication pins are electrically connected to the main controller (2). The detection unit (20) adopts an OR gate logic device. The OR gate logic device has two input channels and one output channel. The two input channels are respectively connected to the two cathode bit selection pins, and the one output channel is connected to the first input pin of the main controller (2). Anti-reverse unit (30), the anti-reverse unit (30) includes: a controllable switch and multiple clamping diodes, the controllable switch is provided with a first end, a second end and a control end, and the anodes of the clamping diodes are respectively connected to the cathode position selection pins, the cathodes of the multiple clamping diodes are connected together and then connected to the first end, the second end is grounded, and the control end is connected to the second output pin of the main controller (2).

2. The display button multiplexing drive circuit according to claim 1, characterized in that, The multiplexing driver chip (10) is a TM1650 chip.

3. The display button multiplexing drive circuit according to claim 1, characterized in that, The display button multiplexing drive circuit further includes: The display unit circuit (40) includes multiple common cathode display lamp groups. Each display lamp group is connected to one cathode position selection pin. Each display lamp group includes multiple light-emitting LEDs. The anodes of the light-emitting LEDs in the same segment are uniformly connected to the corresponding anode driving pin. The button unit circuit (50) includes multiple button matrix groups. Each button matrix group is connected to one cathode position selection pin. Each button matrix group includes multiple independent buttons. The input terminals of the independent buttons in the same segment are uniformly connected to the corresponding anode drive pin.

4. The display button multiplexing drive circuit according to any one of claims 1-3, characterized in that, The detection unit (20) further includes: A first current-limiting resistor and a second current-limiting resistor are respectively connected between the input channel and the cathode bit selection pin; A first capacitor, one end of which is connected to the output channel, and the other end of which is grounded.

5. The display button multiplexing drive circuit according to claim 1, characterized in that, The controllable switch can be any one of NPN transistor, NMOS transistor, or electromagnetic relay; When the controllable switch is an NPN transistor, the base of the NPN transistor is connected to the second output pin, the emitter is grounded, and the collector is connected to the cathode of all the clamping diodes. When the controllable switch is an NMOS transistor, the gate of the NMOS transistor is connected to the second output pin, the source is grounded, and the drain is connected to the cathode of all the clamping diodes. When the controllable switch is an electromagnetic relay, one end of the coil of the electromagnetic relay is connected to the second output pin, and the other end of the coil is connected to the power supply through a current-limiting resistor. One end of the normally open contact of the electromagnetic relay is connected to the cathode of all the clamping diodes, and the other end is grounded.

6. The display button multiplexing drive circuit according to claim 3, characterized in that, The display button multiplexing drive circuit has multi-load adaptive control logic; When in a pure LED load scenario, the main controller (2) continuously outputs a high level to the second output pin, and the controllable switch is permanently turned on; When in a pure button load scenario, the main controller (2) continuously outputs a low level to the second output pin, and the controllable switch is permanently turned off; When in a mixed load scenario, the main controller (2) dynamically switches the controllable switch on and off according to the level of the first input pin; The pure LED load scenario is: only the display unit circuit (40) is configured, and the button unit circuit (50) is not configured; the pure button load scenario is: only the button unit circuit (50) is configured, and the display unit circuit (40) is not configured; the mixed load scenario is: both the display unit circuit (40) and the button unit circuit (50) are configured.

7. The display button multiplexing drive circuit according to claim 1, characterized in that, The main controller (2) has a built-in timing module, GPIO level acquisition module, mode judgment module and switch control output module; The main controller (2) acquires the level of the first input pin to identify the chip scanning mode, controls the on / off state of the controllable switch through the second output pin, and temporarily shuts down the real-time level acquisition of the first input pin to avoid waveform interference by setting the shielding duration through the timing module.

8. A display button multiplexing driving method based on time-division scanning, characterized in that, The display button multiplexing driving method is applied to the display button multiplexing driving circuit as described in any one of claims 1-7, and the display button multiplexing driving method includes: After power-on initialization, the multiplexing driver chip starts a cyclic scan, and the main controller continuously acquires the level of the first input pin; The scanning operation stage is determined based on the level of the first input pin; According to the scanning operation stage, the on / off state of the controllable switch is controlled, and the real-time level acquisition of the first input pin is temporarily turned off, and the timing module in the main controller is controlled to start timing. When the timing duration of the timing module reaches the duration threshold, the main controller clears the timing module and resumes real-time level acquisition of the first input pin; The scanning process includes a display scanning drive stage and a key scanning drive stage.

9. The display button multiplexing driving method according to claim 8, characterized in that, The step of controlling the on / off state of the controllable switch according to the scanning working stage, temporarily disabling the real-time level acquisition of the first input pin, and controlling the timing module in the main controller to start timing includes: When the scanning operation phase is the display scanning drive phase, the main controller turns on the controllable switch through the output control signal of the second output pin, multiple clamping diodes are connected to the cathode circuit, and the real-time level acquisition of the first input pin is temporarily turned off. The timing module starts timing according to the first timing threshold. When the scanning operation phase is the key scanning drive phase, the main controller disconnects the controllable switch through the output control signal of the second output pin, the multiple clamping diodes are disengaged from the cathode circuit, and the real-time level acquisition of the first input pin is temporarily turned off. The timing module starts timing according to the second timing threshold.

10. The display button multiplexing driving method according to claim 8, characterized in that, Determining the scanning operation stage based on the level of the first input pin includes: When the level of the first input pin is detected to be high, the scanning operation phase is determined to be the display scanning drive phase; When the level of the first input pin is detected to be low, the scanning operation phase is determined to be the key scanning drive phase.

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