Capacitive sensing interface circuit, capacitive sensing chip and capacitive sampling method

Abstract

The embodiment of the application discloses a kind of capacitive sensing interface circuit, capacitive sensing chip and capacitive sampling method, by being arranged in first working phase, the first excitation voltage signal of target sensing capacitor and the second excitation voltage signal of compensation module remain unchanged;In the second working phase, the pulse frequency of second excitation voltage signal is greater than or equal to the pulse frequency of first excitation voltage signal, so that in the second working phase, the charging excitation frequency of compensation module is higher than or equal to the charging excitation frequency of target sensing capacitor, realize by increasing the pulse frequency of second excitation voltage signal in the second working phase, realize greater offset capacitor compensation range, in this way, the area of compensation module can be reduced, to realize the compensation of offset capacitor with smaller compensation capacitor, reduce chip size, improve the integration of capacitive sensing interface circuit, reduce the requirement to packaging manufacturing capacity.

Description

Technical Field

[0001] This invention relates to the field of capacitance sensing technology, and in particular to a capacitance sensing interface circuit, a capacitance sensing chip, and a capacitance sampling method. Background Technology

[0002] Capacitive sensing chips detect changes in physical quantities or chemical parameters by accurately measuring changes in capacitance values, and are widely used in fields such as industrial automation, consumer electronics, automotive electronics, medical devices, and environmental monitoring.

[0003] In practical applications, the sensing capacitance still has an inherent capacitance value when there is no target signal; this is called offset capacitance. To ensure accurate measurement of the target sensing capacitance and the capacitance measurement range, a compensation capacitor is needed to compensate for the offset capacitance.

[0004] However, excessively large compensation capacitors can lead to excessively large capacitive sensing chip sizes, increasing chip costs and potentially exceeding packaging and manufacturing capabilities. Summary of the Invention

[0005] This invention provides a capacitance sensing interface circuit, a capacitance sensing chip, and a capacitance sampling method, which compensates for offset capacitance with a smaller compensation capacitor, reduces chip size, and lowers the requirements for packaging manufacturing capabilities.

[0006] According to one aspect of the present invention, a capacitance sensing interface circuit is provided, comprising: an operational amplifier, a compensation module, a first excitation source, and a second excitation source; The first excitation source is electrically connected to the non-inverting input terminal of the operational amplifier and is used to provide the first excitation voltage signal to the non-inverting input terminal. The second excitation source is electrically connected to the first terminal of the compensation module and is used to provide a second excitation voltage signal to the first terminal of the compensation module; the second terminal of the compensation module is electrically connected to the inverting input terminal of the operational amplifier; the compensation module includes at least one compensation capacitor, and the inverting input terminal is also used to connect to the target sensing capacitor; In the first operating phase, the first excitation voltage signal and the second excitation voltage signal remain unchanged; in the second operating phase, the pulse frequency of the second excitation voltage signal is greater than or equal to the pulse frequency of the first excitation voltage signal.

[0007] Optionally, the second operating phase includes at least one first sub-phase and at least one second sub-phase, with the first and second sub-phases alternating; the second excitation voltage signal includes a pulse voltage sequence, in the first sub-phase, the pulse voltage sequence includes a first voltage sub-pulse; in the second sub-phase, the pulse voltage sequence includes a second voltage sub-pulse; the voltage value of the first voltage sub-pulse is higher than the voltage value of the second voltage sub-pulse; the voltage value of the second voltage sub-pulse is equal to the voltage value of the second excitation voltage signal in the first operating phase.

[0008] Optionally, the capacitive sensing interface circuit further includes a buffer branch and a first switching branch. The buffer branch and the first switching branch are connected in parallel between the second terminal of the compensation module and the inverting input terminal. The buffer branch is used to turn on in the second sub-stage and turn off in the first sub-stage and the first operating stage. The first switching branch is used to turn on in the first sub-stage and the first operating stage and turn off in the second sub-stage.

[0009] Optionally, the buffer branch includes a first switching element and a buffer, which are connected in series; the first switching branch includes a second switching element.

[0010] Optionally, the second excitation source includes a first voltage branch and a second voltage branch, which are electrically connected to the compensation module respectively. The first voltage branch is used to output a first voltage to the compensation module in a first sub-stage according to a first control signal; the second voltage branch is used to output a second voltage to the compensation module in a first working stage and a second sub-stage according to the first control signal. And / or, the first excitation source includes a third voltage branch and a fourth voltage branch, which are electrically connected to the non-inverting input terminal respectively. The third voltage branch is used to output a third voltage to the non-inverting input terminal in the first operating phase according to the second control signal; the fourth voltage branch is used to output a fourth voltage to the non-inverting input terminal in the second operating phase according to the second control signal.

[0011] Optionally, the capacitive sensing interface circuit also includes a second switching branch and a third switching branch. The second switching branch is connected in series with the non-inverting input terminal and the inverting input terminal, and is used to turn on in the first operating phase and turn off in the second operating phase. The third switch branch is connected to the output of the operational amplifier and is used to turn on during the first operating phase and turn off during the second operating phase.

[0012] Optionally, the compensation module includes a capacitor-to-analog converter, which is used to adjust the number of compensation capacitors connected according to the input third control signal.

[0013] Optionally, the capacitive sensing interface circuit also includes a feedback capacitor, one end of which is connected to the inverting input of the operational amplifier, and the other end is connected to the output of the operational amplifier.

[0014] According to another aspect of the present invention, a capacitive sensing chip is provided, including a capacitive sensing interface circuit according to any embodiment of the present invention.

[0015] According to another aspect of the present invention, a capacitance sampling method is provided, which applies a capacitance sensing interface circuit of any embodiment of the present invention. The capacitance sampling method includes: In the first working stage, a first excitation voltage signal of constant magnitude is provided to the non-inverting input terminal of the operational amplifier through the first excitation source, and a second excitation voltage signal of constant magnitude is provided to the first terminal of the compensation module through the second excitation source; In the second working stage, a first excitation voltage signal with a first pulse frequency is provided to the non-inverting input terminal through the first excitation source, and a second excitation voltage signal with a second pulse frequency is provided to the first terminal of the compensation module through the second excitation source; The second pulse frequency is higher than the first pulse frequency.

[0016] Optionally, the second working phase includes at least one first sub-phase and at least one second sub-phase, with the first and second sub-phases alternating. In the first operating phase, a first excitation voltage signal of constant magnitude is provided to the non-inverting input terminal of the operational amplifier through a first excitation source, and a second excitation voltage signal of constant magnitude is provided to the first terminal of the compensation module through a second excitation source, including: In the first working stage, a third voltage is input to the non-inverting input terminal through a first excitation source; a second voltage is provided to the first terminal of the compensation module through a second excitation source. In the second operating phase, a first excitation voltage signal with a first pulse frequency is provided to the non-inverting input terminal through a first excitation source, and a second excitation voltage signal with a second pulse frequency is provided to the first terminal of the compensation module through a second excitation source, including: In the second operating phase, a fourth voltage is provided to the non-inverting input terminal through the first excitation source; In the first sub-stage, a first voltage is provided to the first terminal of the compensation module through the second excitation source; in the second sub-stage, a second voltage is provided to the first terminal of the compensation module through the second excitation source. Among them, the first voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

[0017] Optionally, the number of the first and second sub-phases can be adjusted.

[0018] Optionally, the number of the first sub-stages is less than or equal to 5.

[0019] The capacitance sensing interface circuit, capacitance sensing chip, and capacitance sampling method of this invention, by setting the first excitation voltage signal of the target sensing capacitor and the second excitation voltage signal of the compensation module to remain unchanged in the first working stage; and by setting the pulse frequency of the second excitation voltage signal to be greater than or equal to the pulse frequency of the first excitation voltage signal in the second working stage, the number of charging excitations of the compensation module in the second working stage is higher than or equal to the number of charging excitations of the target sensing capacitor, thereby achieving a larger offset capacitance compensation range by increasing the pulse frequency of the second excitation voltage signal in the second working stage. In this way, the area of ​​the compensation module can be reduced, the offset capacitance can be compensated with a smaller compensation capacitor, the chip size can be reduced, the integration of the capacitance sensing interface circuit can be improved, and the requirements for packaging manufacturing capabilities can be reduced.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a capacitive sensing interface circuit provided in an embodiment of the present invention; Figure 2 This is a waveform diagram of the first excitation voltage signal and the second excitation voltage signal according to an embodiment of the present invention; Figure 3 This is a schematic diagram of another capacitive interface sensing circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention; Figure 5 This is a structural diagram of the compensation module; Figure 6 This is a flowchart of a capacitance sampling method provided in an embodiment of the present invention; Figure 7 This is the equivalent circuit diagram of the capacitive sensing interface circuit in the first working stage. Figure 8 This is the first sub-stage, the equivalent circuit diagram of the capacitive sensing interface circuit; Figure 9 This is the first second sub-stage, and the equivalent circuit diagram of the capacitive sensing interface circuit. Figure 10 This is the second first sub-stage, the equivalent circuit diagram of the capacitive sensing interface circuit; Figure 11 This is the second sub-stage, the equivalent circuit diagram of the capacitive sensing interface circuit; Figure 12 This is the third first sub-stage, the equivalent circuit diagram of the capacitive sensing interface circuit; Figure 13 This is a schematic diagram of the structure of a capacitive sensing interface chip provided in an embodiment of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] This invention provides a capacitance sensing interface circuit. Figure 1 This is a schematic diagram of a capacitive sensing interface circuit provided in an embodiment of the present invention. (Refer to...) Figure 1The capacitive sensing interface circuit includes an operational amplifier 100, a compensation module 200, a first excitation source 300, and a second excitation source 400. The first excitation source 300 is electrically connected to the non-inverting input of the operational amplifier 100 and is used to provide a first excitation voltage signal to the non-inverting input. The second excitation source 400 is electrically connected to the first end of the compensation module 200 and is used to provide a second excitation voltage signal to the first end of the compensation module 200. The second end of the compensation module 200 is electrically connected to the inverting input of the operational amplifier 100. The compensation module 200 includes at least one compensation capacitor, and the inverting input is also used to connect to the target sensing capacitor Cs. In the first operating phase, the first excitation voltage signal and the second excitation voltage signal remain unchanged. In the second operating phase, the pulse frequency of the second excitation voltage signal is greater than or equal to the pulse frequency of the first excitation voltage signal.

[0026] Specifically, the operational amplifier 100 includes a non-inverting input, an inverting input, and an output terminal OUT. The non-inverting input of the operational amplifier 100 is connected to a first excitation source 300, which provides a first excitation voltage signal to the non-inverting input. The inverting input of the operational amplifier 100 is connected to a compensation module 200. Specifically, a deflection capacitor Cb inevitably exists in the capacitive sensing chip. In this embodiment, a compensation module 200, including at least one compensation capacitor, is used to compensate for the deflection capacitor Cb, thereby improving the accuracy of the detected target sensing capacitor Cs. The first terminal of the compensation module 200 is connected to a second excitation source 400, which provides a second excitation voltage signal to the first terminal of the compensation module 200. The second terminal of the compensation module 200 is connected to the inverting input of the operational amplifier 100, which is also connected to the target sensing capacitor Cs, where the target sensing capacitor Cs is the capacitor being measured, i.e., the capacitor whose capacitance value needs to be detected.

[0027] In related technologies, a compensation module 200 with the same capacitance value as the offset capacitor Cb needs to be set in the capacitive sensing chip. When the offset capacitor Cb is large, the area of ​​the compensation module 200 needs to be made large, resulting in an excessively large size of the capacitive sensing chip. In this embodiment of the invention, the first excitation voltage signal and the second excitation voltage signal are a set of one-step excitation signals. By setting the pulse frequency of the second excitation voltage signal to be greater than or equal to the pulse frequency of the first excitation voltage signal in the second working stage, the compensation module 200 with a capacitance value less than or equal to the offset capacitor Cb can be used to compensate for the offset capacitor Cb. Specifically, in the first working stage, also known as the pre-charge phase, both the first excitation voltage signal and the second excitation voltage signal are constant voltage signals. The excitation from the first excitation source 300 to the target sensing capacitor Cs is the same as the excitation from the second excitation source 400 to the compensation module 200, establishing an initial reference for subsequent charge amplification. In the second operating phase, also known as the phase transition, the pulse frequency of the second excitation voltage signal is greater than or equal to the pulse frequency of the first excitation voltage signal. For example, the second excitation voltage signal may include m excitation pulses to achieve m charging excitations of the compensation capacitor, and the first excitation voltage signal includes n excitation pulses to achieve n charging excitations of the sensing capacitor, where m and n are both positive integers greater than or equal to 1, and m>n, thereby doubling the compensation range of the offset capacitor Cb. For example, n=1.

[0028] In this embodiment, the capacitive sensing interface circuit is configured such that, in the first operating phase, the first excitation voltage signal of the target sensing capacitor and the second excitation voltage signal of the compensation module remain unchanged; in the second operating phase, the pulse frequency of the second excitation voltage signal is greater than or equal to the pulse frequency of the first excitation voltage signal, so that the number of charging excitations of the compensation module in the second operating phase is higher than or equal to the number of charging excitations of the target sensing capacitor. This achieves a larger offset capacitor compensation range by increasing the pulse frequency of the second excitation voltage signal in the second operating phase. As a result, the area of ​​the compensation module can be reduced, and the offset capacitor can be compensated with a smaller compensation capacitor, thereby reducing the chip size, increasing the integration of the capacitive sensing interface circuit, and reducing the requirements for packaging manufacturing capabilities.

[0029] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0030] Figure 2 These are waveform diagrams of the first excitation voltage signal and the second excitation voltage signal according to an embodiment of the present invention. (Refer to...) Figure 2Optionally, the second operating phase φ2 includes at least one first sub-phase φ22 and at least one second sub-phase φ21, with the first sub-phase φ22 and the second sub-phase φ21 alternating; the second excitation voltage signal includes a pulse voltage sequence, in the first sub-phase φ22, the pulse voltage sequence includes a first voltage sub-pulse; in the second sub-phase φ21, the pulse voltage sequence includes a second voltage sub-pulse; the voltage value of the first voltage sub-pulse (i.e., the first voltage V1) is higher than the voltage value of the second voltage sub-pulse (i.e., the second voltage V2); the voltage value of the second voltage sub-pulse is equal to the voltage value of the second excitation voltage signal in the first operating phase φ1.

[0031] Specifically, in each first sub-stage φ22, the compensation module 200 can perform a charge injection; in each second sub-stage φ21, the compensation capacitor is pre-charged. Thus, compared to the second operating stage φ2, where the second excitation voltage signal remains unchanged, when the second operating stage φ2 includes k first sub-stages φ22, the compensation range for the offset capacitor Cb can be increased by a factor of k, where k is a positive integer greater than or equal to 1.

[0032] refer to Figure 2 Optionally, in the second operating phase φ2, the voltage of the first excitation voltage signal remains unchanged, but the voltage value of the first excitation voltage signal in the second operating phase φ2 (fourth voltage V4) is higher than the voltage value of the first excitation voltage signal in the first operating phase φ1 (third voltage V3). In the second operating phase φ2, the high-level pulse of the first excitation voltage signal is the excitation pulse of the sensing capacitor, and the first voltage sub-pulse of the second excitation voltage signal is the excitation pulse of the compensation module.

[0033] In the second operating phase φ2, the rising edge of the second excitation voltage signal corresponding to the first sub-phase is aligned with the rising edge of the first excitation voltage signal, and the falling edge of the second excitation voltage signal corresponding to the last first sub-phase φ22 is aligned with the falling edge of the first excitation voltage signal. The durations of different second sub-phases φ21 can be equal or unequal; the durations of different first sub-phases φ22 can also be equal or unequal.

[0034] Figure 3 This is a schematic diagram of another capacitive interface sensing circuit provided in an embodiment of the present invention, for reference. Figure 3Optionally, the capacitive sensing interface circuit also includes a buffer branch 500 and a first switch branch 600. The buffer branch 500 and the first switch branch 600 are connected in parallel between the second terminal and the inverting input terminal of the compensation module 200. The buffer branch 500 is used to turn on in the second sub-stage φ21 and turn off in the first sub-stage φ22 and the first working stage φ1. The first switch branch 600 is used to turn on in the first sub-stage φ22 and the first working stage φ1 and turn off in the second sub-stage φ21.

[0035] Specifically, during the second operating phase φ2, the voltage at the inverting input of the operational amplifier 100 is uncertain until it reaches the same voltage as the non-inverting input. By setting the buffer branch 500 to conduct during the second sub-phase φ21, the output of the buffer branch 500 drives the second terminal voltage of the compensation module 200, ensuring that the amount of compensation charge is independent of the voltage at the inverting input during the charge buildup process from the start to the end of the second operating phase φ2, thereby achieving compensation for the offset capacitor Cb.

[0036] Continue to refer to Figure 3 The buffer branch 500 includes a first switching element K1 and a buffer 510, which are connected in series; the first switching branch 600 includes a second switching element K2.

[0037] The input terminal of the buffer 510 is electrically connected to the inverting input terminal of the operational amplifier 100, the output terminal of the buffer 510 is electrically connected to the first terminal of the first switching element K1, and the second terminal of the first switching element K1 is electrically connected to the second terminal of the compensation module 200.

[0038] Optionally, the first switching element K1 and the second switching element K2 each include a transistor device.

[0039] Figure 4 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention, combined with... Figure 2 and Figure 4 In some embodiments, the second excitation source 400 includes a first voltage branch 410 and a second voltage branch 420. The first voltage branch 410 and the second voltage branch 420 are electrically connected to the compensation module 200, respectively. The first voltage branch 410 is used to output a first voltage V1 to the compensation module 200 in the first sub-stage φ22 according to the first control signal. The second voltage branch 420 is used to output a second voltage V2 to the compensation module 200 in the first working stage φ1 and the second sub-stage φ21 according to the first control signal.

[0040] Optionally, the first voltage branch 410 includes a third switching element K3, with its first terminal connected to a first voltage V1 and its second terminal electrically connected to the first terminal of the compensation module 200. The second voltage branch 420 includes a fourth switching element K4, with its first terminal connected to a second voltage V2 and its second terminal electrically connected to the first terminal of the compensation module 200. In some embodiments, the third switching element K3 and the fourth switching element K4 each include a transistor device, and their channel types may be the same or different. When their channel types are the same, the first control signal may include a first sub-control signal with opposite levels to the second sub-control signal, so that the third switching element K3 and the fourth switching element K4 are not simultaneously turned on. Specifically, by setting the timing of the first and second sub-control signals, the third switching element K3 is turned on in the first sub-stage φ22 and turned off in the first operating stage φ1 and the second sub-stage φ21; the fourth switching element K4 is turned on in the first operating stage φ1 and the second sub-stage φ21, and turned off in the first sub-stage φ22. When their channel types are opposite, the control terminals of the third switching element K3 and the fourth switching element K4 can be connected to the same signal.

[0041] Continue to refer to Figure 4 In some embodiments, the first excitation source 300 includes a third voltage branch 310 and a fourth voltage branch 320, which are electrically connected to the non-inverting input terminal respectively. The third voltage branch 310 is used to output a third voltage V3 to the non-inverting input terminal according to the second control signal φ1 in the first operating stage; the fourth voltage branch 320 is used to output a fourth voltage V4 to the non-inverting input terminal according to the second control signal φ2 in the second operating stage.

[0042] Optionally, the third voltage branch 310 includes a fifth switching element K5, the first terminal of which is connected to the third voltage V3, and the second terminal of which is electrically connected to the non-inverting input of the operational amplifier 100. The fourth voltage branch 320 includes a sixth switching element K6, the first terminal of which is connected to the fourth voltage V4, and the second terminal of which is electrically connected to the non-inverting input of the operational amplifier 100. Similarly, the fifth switching element K5 and the sixth switching element K6 may each include transistor devices. By setting the timing of the second control signal, the fifth switching element K5 is turned on in the first operating phase φ1 and turned off in the second operating phase φ2; the sixth switching element K6 is turned off in the first operating phase φ1 and turned on in the second operating phase φ2.

[0043] Continue to refer to Figure 4Optionally, the capacitor interface sensing circuit also includes a second switch branch 700 and a third switch branch 800. The second switch branch 700 is connected in series with the non-inverting input terminal and the inverting input terminal, and is used to turn on φ1 in the first operating stage and turn off φ2 in the second operating stage. The third switch branch 800 is connected to the output terminal of the operational amplifier 100, and is used to turn on φ1 in the first operating stage and turn off φ2 in the second operating stage.

[0044] The second switching branch 700 and the third switching branch 800 each include switching elements, such as transistors. For example, the second switching branch 700 includes a seventh switching element K7, and the third switching branch 800 includes an eighth switching element K8. During the first operating phase φ1, the second switching branch 700 is turned on, connecting the non-inverting and inverting input terminals of the operational amplifier 100. This ensures that the voltages at the inverting and non-inverting input terminals of the operational amplifier 100 are equal during the first operating phase φ1, establishing an initial reference for subsequent charge amplification. During the first operating phase φ1, the third switching branch 800 is turned on, resetting the output of the operational amplifier 100. Optionally, the fifth voltage V5 connected to the third switching branch 800 is equal to 0.

[0045] Continue to refer to Figure 4 The capacitive sensing interface circuit also includes a feedback capacitor Cfb, one end of which is connected to the inverting input terminal of the operational amplifier 100, and the other end is connected to the output terminal of the operational amplifier 100.

[0046] In some embodiments, the compensation module 200 includes a capacitor-to-analog converter 210, which is used to adjust the number of compensation capacitors connected according to the connected third control signal.

[0047] The capacitor-to-digital converter 210 can be connected to the control module of the capacitor sensing chip. The control module can output a third control signal to the capacitor-to-digital converter module. The capacitor-to-digital converter 210 adjusts the number of compensation capacitors connected according to the third control signal, thereby adjusting the capacitance value of the compensation module 200. Figure 5 This is a structural diagram of the compensation module, for reference. Figure 5 Optionally, the compensation module 200 includes multiple compensation branches, each including a compensation capacitor CF connected in series and a control switch K0. The third control signal can be a digital signal, and the number of compensation branches can be equal to the number of bits in the third control signal. In the third control signal, each bit controls the on / off state of one compensation branch, that is, the on / off state of one control switch K0, thereby controlling the number of parallel compensation capacitors CF, thus adjusting the overall capacitance value of the compensation module 200. For example, the third control signal is a digital signal, such as denoted as Dc. <p:0>That is, a p+1 bit digital signal, where p is a positive integer greater than or equal to 1.

[0048] This invention also provides a capacitance sampling method. Figure 6 This is a flowchart of a capacitance sampling method provided in an embodiment of the present invention, see reference. Figure 6 The capacitance sampling method includes: S210. In the first working stage, a first excitation voltage signal of constant magnitude is provided to the non-inverting input terminal of the operational amplifier through the first excitation source, and a second excitation voltage signal of constant magnitude is provided to the first terminal of the compensation module through the second excitation source.

[0049] S220. In the second working stage, a first excitation voltage signal with a first pulse frequency is provided to the non-inverting input terminal through the first excitation source, and a second excitation voltage signal with a second pulse frequency is provided to the first terminal of the compensation module through the second excitation source.

[0050] The second pulse frequency is higher than the first pulse frequency.

[0051] Wherein, the second pulse frequency is the excitation pulse frequency of the second excitation voltage signal, and the first pulse frequency is the excitation pulse frequency of the first excitation voltage signal.

[0052] After the second working stage, the size of the target sensing capacitance can be determined based on the formula for calculating the total charge at the inverting input terminal of the operational amplifier in the first working stage and the formula for calculating the total charge at the inverting input terminal of the operational amplifier in the second working stage.

[0053] The capacitance sampling method of this embodiment, when applied to the capacitance sensing interface circuit of any of the above embodiments of the present invention, possesses the beneficial effects of the capacitance sensing interface circuit of any of the above embodiments of the present invention.

[0054] In some embodiments, S210, in the first operating phase, a first excitation voltage signal of constant magnitude is provided to the non-inverting input terminal of the operational amplifier through a first excitation source, and a second excitation voltage signal of constant magnitude is provided to the first terminal of the compensation module through a second excitation source, including: in the first operating phase, a third voltage V3 is input to the non-inverting input terminal through the first excitation source; and a second voltage V2 is provided to the first terminal of the compensation module through the second excitation source.

[0055] Figure 7 This is the equivalent circuit diagram of the capacitive sensing interface circuit in the first operating stage. Combined with... Figure 2 , Figure 4 and Figure 7 In the first operating phase φ1, the third voltage branch 310 in the first excitation source is turned on, that is, the fifth switching element K5 is turned on, transmitting the third voltage V3 to the non-inverting input terminal. The second voltage branch 420 in the second excitation source is turned on, that is, the fourth switching element K4 is turned on, transmitting the second voltage V2 to the first terminal of the compensation module 200. Simultaneously, the second switching branch 700 is turned on, that is, the seventh switching element K7 is turned on, short-circuiting the non-inverting and inverting input terminals of the operational amplifier 100; the third switching branch 800 is turned on, that is, the eighth switching element K8 is turned on, resetting the output terminal of the operational amplifier 100 to 0 voltage. In the first operating phase φ1, the first switching branch 600 is turned on, electrically connecting the second terminal of the compensation module 200 to the inverting input terminal of the operational amplifier 100.

[0056] Taking the third voltage V3=Vr1 and the second voltage V2=0 as an example, the total charge Q0 at the inverting input terminal of the operational amplifier 100 can be expressed by the following formula (1): Q0=Vr1×(Cb+Cs+Cfb)+Vr1×Cc(1); In the second operating phase φ2, a fourth voltage V4 is provided to the non-inverting input terminal through the first excitation source. In some embodiments, the second operating phase φ2 includes at least one first sub-phase φ22 and at least one second sub-phase φ21, with the first sub-phase φ22 and the second sub-phase φ21 alternating.

[0057] by Figure 2 As shown, the second working stage φ2 includes three first sub-stages φ22 and two second sub-stages φ21, which will be used as an example for explanation. Figure 8 This is the equivalent circuit diagram of the first sub-stage, the capacitive sensing interface circuit. Combined with... Figure 2 , Figure 4 and Figure 8 In the first sub-stage φ22, a first voltage V1 is provided to the first terminal of the compensation module 200 through the second excitation source. Specifically, in the first sub-stage φ22, the first voltage branch 410 in the second excitation source is turned on, that is, the third switching element K3 is turned on, transmitting the first voltage V1 to the first terminal of the compensation module 200. The fourth voltage branch 320 in the first excitation source is turned on, that is, the sixth switching element K6 is turned on, transmitting the fourth voltage V4 to the non-inverting input terminal. At the same time, the second switching branch 700 and the third switching branch 800 are turned off. In the first sub-stage φ22, the first switching branch 600 is turned on, electrically connecting the second terminal of the compensation module 200 to the inverting input terminal of the operational amplifier 100.

[0058] Taking the first voltage V1=Vr2 and the fourth voltage V4=Vr2 as an example, the total charge Q221 at the inverting input terminal of the operational amplifier 100 in the first sub-stage φ22 can be expressed by the following formula (2): Q221=Vnx1×(Cb+Cs)+(Vnx1-Vr2)×Cc+(Vnx1-Vox1)×Cfb(2); Then, according to formulas (1) and (2), we can obtain the following formula (3). (Cb+Cs)×(Vnx1-Vr1)+Cc×(Vnx1-Vr2-Vr1)+Cfb×(Vnx1-Vox1-Vr1)=0(3); Wherein, Vnx1 represents the voltage at the inverting input terminal of operational amplifier 100 after the completion of the first sub-stage φ22; Vox1 represents the output voltage Vout at the output terminal of operational amplifier 100 after the completion of the first sub-stage φ22.

[0059] Figure 9 This is the equivalent circuit diagram of the capacitive sensing interface circuit in the first second sub-stage. (Reference) Figure 9 In the second sub-stage φ21, a second voltage V2 is provided to the first terminal of the compensation module 200 through the second excitation source. Specifically, in the second sub-stage φ21, the second voltage branch 420 in the second excitation source is turned on, that is, the fourth switching element K4 is turned on, transmitting the second voltage V2 to the first terminal of the compensation module 200. The fourth voltage branch 320 in the first excitation source is turned on, that is, the sixth switching element K6 is turned on, transmitting the fourth voltage V4 to the non-inverting input terminal. In the first operating stage φ1, the buffer branch 500 is turned on, that is, the first switching element K1 is turned on, and the output terminal of the buffer 510 is connected to the second terminal of the compensation module 200. At the same time, the second switching branch 700 and the third switching branch 800 are turned off. Among them, the first voltage V1 is higher than the second voltage V2, and the fourth voltage V4 is higher than the third voltage V3.

[0060] Then, in the first second sub-stage φ21, based on the voltage Vnx1 at the inverting input terminal of operational amplifier 100 and the voltage Vox1 at the output terminal of operational amplifier 100, the total charge Q211 at the inverting input terminal of operational amplifier 100 can be expressed by the following formula (4): Q211=Vnx1×(Cb+Cs)+Vnx1×Cc+(Vnx1-Vox1)×Cfb(4).

[0061] Figure 10 This is the equivalent circuit diagram of the capacitive sensing interface circuit in the second sub-stage. (Reference) Figure 10 In the second first sub-stage φ22, the conduction state of each switch is the same as in the first first sub-stage φ22. At this time, the total charge Q222 at the inverting input terminal of the operational amplifier 100 can be expressed by the following formula (5): Q222=Vnx2×(Cb+Cs)+(Vnx2-Vr2)×Cc+(Vnx2-Vox2)×Cfb(5); Wherein, Vnx2 represents the voltage at the inverting input terminal of operational amplifier 100 after the completion of the second first sub-stage φ22; Vox2 represents the output voltage Vout at the output terminal of operational amplifier 100 after the completion of the second first sub-stage φ22.

[0062] According to the principle of charge conservation, Q222=Q211, and according to formulas (4) and (5), the following formula (6) can be obtained: (Cb+Cs)×(Vnx2-Vnx1)+Cc×(Vnx2-Vr2-Vnx1)+Cfb(Vnx2-Vox2-Vnx1+Vox1)=0(6); Figure 11 This is the second sub-stage, the equivalent circuit diagram of the capacitive sensing interface circuit; Figure 12 This is the equivalent circuit diagram of the capacitive sensing interface circuit in the third sub-stage. (Reference) Figure 11 The second sub-stage φ21 has the same conduction state for each switch as the first sub-stage φ21. (Reference) Figure 12 In the third first sub-stage φ22, the conduction state of each switch is the same as in the first and second first sub-stages φ22. According to... Figure 11 , Figure 12 And formula (6) can be followed by formula (7): (Cb+Cs)×(Vr2-Vnx2)+Cc×(-Vnx2)+Cfb(Vr2-Vout-Vnx2+Vox2)=0(7); Adding formulas (7), (6), and (3) together yields formula (8). Cb×(Vr2-Vr1)-Cc×(2Vr2+Vr1)+Cs×(Vr2-Vr1)+Cfb(Vr2-Vr1-Vout)=0(8); In circuits where the first and second excitation voltage signals are always in phase, compensation and cancellation can be achieved when Vnx1 = Vr2, Vox1 = Vout, Vr2 = 2 × Vr1, and Cc = Cb. However, in this embodiment of the invention, when Vr2 = 2 × Vr1 is set, substituting Vr2 = 2 × Vr1 into formula (8) yields the following formula (9): (Cb+Cs)×Vr1+Cc×(-5Vr1)+Cfb(Vr1-Vout)=0(9); Simplifying, we get the following formula (10): (Cb-5×Cc)×Vr1+(Cs+Cfb)×Vr1-Cfb×Vout=0 (10); According to formula (10), selecting Cc=1 / 5Cb can achieve compensation for the offset capacitor Cb, that is, the maximum compensation range is expanded from the original Cc to 5×Cc.

[0063] The output voltage Vout at the output terminal of the compensated operational amplifier can be expressed as the following formula (11): Vout=Vr1+Vr1×Cs / Cfb (11).

[0064] The target sensing capacitor Cs is then calculated based on the output voltage Vout, the voltage Vr1, and the feedback capacitor Cfb.

[0065] The above analysis process, taking the example of injecting sufficient charge to compensate the offset capacitor Cb using three first sub-stages φ22 and two second sub-stages φ21, applies to a second operating stage comprising k first sub-stages φ22 and 0-(k-1) second sub-stages φ21, where k is a positive integer greater than or equal to 1. In some embodiments, due to limitations in speed and power consumption during use, the number of first sub-stages φ22 is less than or equal to 5.

[0066] It should be noted that the number of the first sub-stage φ22 and the second sub-stage φ21 is adjustable. Thus, when the offset capacitor Cb is too large, a larger compensation range for the offset capacitor Cb can be achieved by increasing the number of the first sub-stage φ22.

[0067] This invention also provides a capacitive sensing chip. Figure 13 This is a schematic diagram of the structure of a capacitive sensing interface chip provided in an embodiment of the present invention, for reference. Figure 13 The capacitive sensing chip includes the capacitive sensing interface circuit 10 of any embodiment of the present invention, and has the beneficial effects of the capacitive sensing interface circuit 10 of any embodiment of the present invention, which will not be described in detail here.

[0068] Continue to refer to Figure 12 Optionally, the capacitive sensing chip also includes a control module 20. The control module 20 is connected to the capacitive sensing interface circuit 10 through the analog-to-digital conversion module 30. In the capacitive sensing chip, the first stage is the capacitive sensing interface circuit 10. The capacitive sensing interface circuit 10 samples the offset capacitor Cb and the target sensing capacitor Cs and converts them into voltage signals. The second stage is the analog-to-digital converter module 30, which quantizes the analog voltage signal output by the capacitance sensing interface circuit 10 into a digital signal. The third stage is the control module 20, which can output the first control signal, the second control signal, and the third control signal in the above embodiment to the capacitance sensing interface circuit 10. The control module 20 may include a digital signal processing (DSP) unit. In the offset capacitance Cb compensation stage, the digital processing unit dynamically adjusts the first control signal and / or the third control signal in the above embodiment according to the digital signal from the analog-to-digital converter, thereby adjusting the pulse frequency and / or the capacitance value of the compensation module 200 in the second working stage, until the output signal of the analog-to-digital converter module 30 is 0, thus completing the offset capacitance Cb compensation and storing the first control signal and the third control signal for fixed offset compensation control in the subsequent target sensing capacitance Cs sampling process. In the sensing stage, the DSP receives the digital signal from the analog-to-digital converter, performs filtering processing, and stores the capacitance sensing result in the storage module 40 in real time.

[0069] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0070] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A capacitive sensing interface circuit, characterized in that, include: Operational amplifier, compensation module, first excitation source and second excitation source; The first excitation source is electrically connected to the non-inverting input terminal of the operational amplifier and is used to provide a first excitation voltage signal to the non-inverting input terminal; The second excitation source is electrically connected to the first terminal of the compensation module and is used to provide a second excitation voltage signal to the first terminal of the compensation module; the second terminal of the compensation module is electrically connected to the inverting input terminal of the operational amplifier; the compensation module includes at least one compensation capacitor, and the inverting input terminal is also used to connect to the target sensing capacitor; During the first working phase, the first excitation voltage signal and the second excitation voltage signal remain unchanged. In the second operating phase, the pulse frequency of the second excitation voltage signal is greater than or equal to the pulse frequency of the first excitation voltage signal.

2. The capacitive sensing interface circuit according to claim 1, characterized in that, The second operating phase includes at least one first sub-phase and at least one second sub-phase, which are performed alternately; the second excitation voltage signal includes a pulse voltage sequence, which includes a first voltage sub-pulse in the first sub-phase and a second voltage sub-pulse in the second sub-phase; the voltage value of the first voltage sub-pulse is higher than the voltage value of the second voltage sub-pulse. The voltage value of the second voltage sub-pulse is equal to the voltage value of the second excitation voltage signal during the first operating phase.

3. The capacitive sensing interface circuit according to claim 2, characterized in that, It also includes a buffer branch and a first switch branch, which are connected in parallel between the second end of the compensation module and the inverting input terminal. The buffer branch is used to be turned on in the second sub-stage and turned off in the first sub-stage and the first operating stage; the first switch branch is used to be turned on in the first sub-stage and the first operating stage and turned off in the second sub-stage.

4. The capacitive sensing interface circuit according to claim 3, characterized in that, The buffer branch includes a first switching element and a buffer, wherein the first switching element and the buffer are connected in series; the first switching branch includes a second switching element.

5. The capacitive sensing interface circuit according to claim 2, characterized in that, The second excitation source includes a first voltage branch and a second voltage branch. The first voltage branch and the second voltage branch are electrically connected to the compensation module. The first voltage branch is used to output a first voltage to the compensation module in the first sub-stage according to a first control signal. The second voltage branch is used to output a second voltage to the compensation module in the first working stage and the second sub-stage according to the first control signal. And / or, the first excitation source includes a third voltage branch and a fourth voltage branch, the third voltage branch and the fourth voltage branch being electrically connected to the non-inverting input terminal respectively, the third voltage branch being used to output a third voltage to the non-inverting input terminal in the first operating phase according to a second control signal; the fourth voltage branch being used to output a fourth voltage to the non-inverting input terminal in the second operating phase according to a second control signal.

6. The capacitive sensing interface circuit according to any one of claims 1-5, characterized in that, It also includes a second switch branch and a third switch branch, wherein the second switch branch is connected in series between the non-inverting input terminal and the inverting input terminal, and is used to turn on in the first operating phase and turn off in the second operating phase; The third switch branch is connected to the output of the operational amplifier and is used to turn on during the first operating phase and turn off during the second operating phase.

7. The capacitive sensing interface circuit according to claim 1, characterized in that, The compensation module includes a capacitor-to-analog converter, which is used to adjust the number of the compensation capacitors connected according to the input third control signal.

8. The capacitive sensing interface circuit according to claim 1, characterized in that, It also includes a feedback capacitor, one end of which is connected to the inverting input terminal of the operational amplifier, and the other end of which is connected to the output terminal of the operational amplifier.

9. A capacitive sensing chip, characterized in that, Includes the capacitive sensing interface circuit as described in any one of claims 1-8.

10. A capacitance sampling method, applied to the capacitance sensing interface circuit according to any one of claims 1-8, characterized in that, The capacitance sampling method includes: In the first working stage, a first excitation voltage signal of constant magnitude is provided to the non-inverting input terminal of the operational amplifier through the first excitation source, and a second excitation voltage signal of constant magnitude is provided to the first terminal of the compensation module through the second excitation source; In the second working stage, a first excitation voltage signal with a first pulse frequency is provided to the non-inverting input terminal through a first excitation source, and a second excitation voltage signal with a second pulse frequency is provided to the first terminal of the compensation module through a second excitation source; The second pulse frequency is higher than the first pulse frequency.

11. The capacitance sampling method according to claim 10, characterized in that, The second working phase includes at least one first sub-phase and at least one second sub-phase, with the first sub-phase and the second sub-phase being performed alternately; In the first operating phase, a first excitation voltage signal of constant magnitude is provided to the non-inverting input terminal of the operational amplifier through a first excitation source, and a second excitation voltage signal of constant magnitude is provided to the first terminal of the compensation module through a second excitation source, including: During the first operating phase, a third voltage is input to the non-inverting input terminal through the first excitation source; a second voltage is provided to the first terminal of the compensation module through the second excitation source. In the second operating phase, a first excitation voltage signal with a first pulse frequency is provided to the non-inverting input terminal through a first excitation source, and a second excitation voltage signal with a second pulse frequency is provided to the first terminal of the compensation module through a second excitation source, including: During the second operating phase, a fourth voltage is provided to the non-inverting input terminal through the first excitation source; In the first sub-stage, a first voltage is provided to the first terminal of the compensation module through the second excitation source; in the second sub-stage, a second voltage is provided to the first terminal of the compensation module through the second excitation source. Wherein, the first voltage is higher than the second voltage, and the fourth voltage is higher than the third voltage.

12. The capacitance sampling method according to claim 11, characterized in that, The number of the first sub-stage and the second sub-stage can be adjusted.

13. The capacitance sampling method according to claim 11, characterized in that, The number of the first sub-stages is less than or equal to 5.

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