Level shifter and nor flash memory

Abstract

The application provides a level converter and a NOR flash memory, comprising: an input module, working in a first voltage domain, generating a first control signal and a second control signal based on an input signal; a first conversion module, working in a second voltage domain, generating a first driving signal; a second conversion module, working in a third voltage domain, generating a second driving signal; a first transmission module, used for transmitting the first driving signal with a second high voltage and blocking the first driving signal with a first low voltage; a second transmission module, used for transmitting the second driving signal with a second low voltage and blocking the second driving signal with a first high voltage; and an output module, working in a fourth voltage domain, generating an output signal. The level converter can effectively reduce the large current consumed in the flip process, speed up the rise time and fall time of the output signal, and improve the conversion speed of the output signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a level converter and NOR flash memory. Background Technology

[0002] A level shifter is a voltage domain converter that translates logic signals from the low-voltage domain into levels recognizable by the high-voltage domain, or vice versa, while preventing high voltage from flooding low-voltage devices and causing breakdown. In NOR flash memory, level shifters are typically used to convert zero potential GND to a negative low voltage NVL and the power supply voltage VDD to a positive high voltage HVL, providing appropriate voltages for erase, program, and read operations.

[0003] Currently, level converters in NOR FLASH generally suffer from problems such as high current consumption and slow conversion speed during the switching process. Therefore, there is an urgent need to provide a high-speed, low-power level converter.

[0004] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a level converter and NOR flash memory to solve the problems of high current consumption and slow conversion speed during the level converter switching process in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a level converter, the level converter comprising at least:

[0007] The system comprises an input module, a first conversion module, a second conversion module, a first transmission module, a second transmission module, and an output module.

[0008] The input module operates in a first voltage domain and generates a first control signal and a second control signal located in the first voltage domain based on the input signal; wherein the logic of the first control signal and the second control signal is opposite, and the high voltage of the first voltage domain is the first high voltage and the low voltage is the first low voltage.

[0009] The first conversion module operates in the second voltage domain and generates a first drive signal based on the first control signal and the second control signal; wherein, the high voltage in the second voltage domain is the second high voltage and the low voltage is the first low voltage;

[0010] The second conversion module operates in the third voltage domain and generates a second drive signal based on the first control signal and the second control signal; wherein, the high voltage of the third voltage domain is the first high voltage and the low voltage is the second low voltage;

[0011] The first transmission module is connected to the output terminal of the first conversion module and is used to transmit the first drive signal with the second high voltage and block the first drive signal with the first low voltage.

[0012] The second transmission module is connected to the output of the second conversion module and is used to transmit the second drive signal with the second low voltage and block the second drive signal with the first high voltage.

[0013] The output module operates in a fourth voltage domain and generates an output signal based on the output signal of the first transmission module or the second transmission module; wherein, the high voltage of the fourth voltage domain is the second high voltage and the low voltage is the second low voltage;

[0014] The voltage values ​​of the second high voltage, the first high voltage, the first low voltage, and the second low voltage decrease sequentially.

[0015] Optionally, the input module includes a first inverter and a second inverter cascaded in sequence; the first inverter receives the input signal and outputs the first control signal; the input terminal of the second inverter receives the first control signal and generates the second control signal.

[0016] Optionally, the first conversion module is configured to: make the voltage of the first drive signal the first low voltage when the input signal is high level, and make the voltage of the first drive signal the second high voltage when the input signal is low level.

[0017] Alternatively, the first conversion module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0018] The sources of the first PMOS transistor and the second PMOS transistor are connected to the second high voltage; the drain of the first PMOS transistor is connected to the first low voltage via the third PMOS transistor and the first NMOS transistor in sequence; the gates of the third PMOS transistor and the first NMOS transistor are connected to the first control signal; the drains of the third PMOS transistor and the first NMOS transistor are connected to the gate of the second PMOS transistor; the drain of the second PMOS transistor is connected to the first low voltage via the fourth PMOS transistor and the second NMOS transistor in sequence; the gates of the fourth PMOS transistor and the second NMOS transistor are connected to the second control signal; the drains of the fourth PMOS transistor and the second NMOS transistor are connected to the gate of the first PMOS transistor and serve as the output terminal of the first conversion module.

[0019] Wherein, the first control signal is logically opposite to the input signal, and the second control signal is logically the same as the input signal.

[0020] Alternatively, the first transmission module includes a seventh PMOS transistor, the source of which is connected to the output of the first conversion module, the gate of which is connected to the second control signal, and the drain of which serves as the output of the first transmission module.

[0021] Alternatively, the substrate and source of the seventh PMOS transistor are connected together.

[0022] Optionally, the second conversion module is configured to: make the voltage of the second drive signal the second low voltage when the input signal is high level, and make the voltage of the second drive signal the first high voltage when the input signal is low level.

[0023] Alternatively, the second conversion module includes a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

[0024] The sources of the third and fourth NMOS transistors are connected to the second low voltage; the drain of the third NMOS transistor is connected to the first high voltage via the fifth NMOS transistor and the fifth PMOS transistor in sequence; the gates of the fifth NMOS transistor and the fifth PMOS transistor are connected to the first control signal; the drains of the fifth NMOS transistor and the fifth PMOS transistor are connected to the gate of the fourth NMOS transistor; the drain of the fourth NMOS transistor is connected to the first high voltage via the sixth NMOS transistor and the sixth PMOS transistor in sequence; the gates of the sixth NMOS transistor and the sixth PMOS transistor are connected to the second control signal; the drains of the sixth NMOS transistor and the sixth PMOS transistor are connected to the gate of the third NMOS transistor and serve as the output terminal of the second conversion module.

[0025] Wherein, the first control signal is logically opposite to the input signal, and the second control signal is logically the same as the input signal.

[0026] Alternatively, the second transmission module includes a seventh NMOS transistor, the source of which is connected to the output of the second conversion module, the gate of which is connected to the second control signal, and the drain of which serves as the output of the second transmission module.

[0027] Alternatively, the substrate and source of the seventh NMOS transistor are connected together.

[0028] Alternatively, the first conversion module includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor;

[0029] The sources of the eighth PMOS transistor and the ninth PMOS transistor are connected to the second high voltage; the drain of the eighth PMOS transistor is connected to the first low voltage via the tenth PMOS transistor and the eighth NMOS transistor in sequence; the gates of the tenth PMOS transistor and the eighth NMOS transistor are connected to the first control signal; the drains of the tenth PMOS transistor and the eighth NMOS transistor are connected to the gate of the ninth PMOS transistor; the drain of the ninth PMOS transistor is connected to the first low voltage via the eleventh PMOS transistor and the ninth NMOS transistor in sequence; the gate of the ninth NMOS transistor is connected to the second control signal; the drains of the eleventh PMOS transistor and the ninth NMOS transistor are connected to the gate of the eighth PMOS transistor and serve as the output terminal of the first conversion module.

[0030] The second conversion module includes a twelfth PMOS transistor, a thirteenth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor. The sources of the tenth and eleventh NMOS transistors are connected to the second low voltage. The drain of the tenth NMOS transistor is connected to the first high voltage via the twelfth NMOS transistor and the twelfth PMOS transistor. The gates of the twelfth and twelfth PMOS transistors are connected to the first control signal. The drains of the twelfth and twelfth PMOS transistors are connected to the gate of the eleventh NMOS transistor. The drain of the eleventh NMOS transistor is connected to the first high voltage via the thirteenth NMOS transistor and the thirteenth PMOS transistor. The gate of the thirteenth PMOS transistor is connected to the second control signal. The drains of the thirteenth and thirteenth PMOS transistors are connected to the gate of the tenth NMOS transistor and serve as the output terminal of the second conversion module.

[0031] The gate of the eleventh PMOS transistor is connected to the drain of the twelfth NMOS transistor and the twelfth PMOS transistor, and the gate of the thirteenth NMOS transistor is connected to the drain of the eighth NMOS transistor and the tenth PMOS transistor.

[0032] Alternatively, the first transmission module includes a fourteenth PMOS transistor, the source of which is connected to the output of the first conversion module, the gate of which is connected to the gate of the eleventh PMOS transistor, and the drain of which serves as the output of the first transmission module.

[0033] Alternatively, the substrate and source of the fourteenth PMOS transistor are connected together.

[0034] Alternatively, the second transmission module includes a fourteenth NMOS transistor, the source of which is connected to the output of the second conversion module, the gate of which is connected to the gate of the thirteenth NMOS transistor, and the drain of which serves as the output of the second transmission module.

[0035] Alternatively, the substrate and source of the fourteenth NMOS transistor are connected together.

[0036] Optionally, the output module includes a third inverter.

[0037] To achieve the above and other related objectives, the present invention also provides a NOR flash memory, the NOR flash memory comprising at least the above-described level converter.

[0038] As described above, the level converter and NOR flash memory of the present invention have the following beneficial effects:

[0039] The level converter of the present invention can effectively reduce the large current consumed during the switching process and speed up the setup time of the rising and falling edges of the output signal, thereby improving the conversion speed of the output signal. Attached Figure Description

[0040] Figure 1 The diagram shows a level conversion architecture.

[0041] Figure 2 This is a schematic diagram of another level conversion architecture.

[0042] Figure 3 The diagram shown is a schematic representation of a level converter according to the present invention.

[0043] Figure 4 This is a schematic diagram of another structure of the level converter of the present invention.

[0044] Figure 5 The diagram shown represents another structural embodiment of the level converter of the present invention.

[0045] Figure 6 Displayed as Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 A schematic diagram of the simulation data for the falling edge toggle time of the level converter.

[0046] Figure 7 Displayed as Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 A schematic diagram of the simulation data of the rising edge toggling time of the level converter.

[0047] Figure 8 Displayed as Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 A schematic diagram of simulation data showing the current consumption of HVL when the signal of the level converter circuit is flipped.

[0048] Figure 9 Displayed as Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 A simulation diagram showing the current consumption of NVL when the signal of the level converter circuit is flipped.

[0049] Component designation explanation

[0050] 1-Level converter; 11-Input module; 12-First conversion module; 13-Second conversion module; 14-First transmission module; 15-Second transmission module; 16-Output module. Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] Please see Figures 1-9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] like Figure 1 The diagram illustrates a level shifting architecture comprising two cascaded shifting modules. In the second-stage module, the high potential is the positive high voltage (HVL), and the low potential is the negative low voltage (NVL), with a significant voltage difference between them. During level switching, a large current is generated from the positive high voltage (HVL) to the negative low voltage (NVL). If multiple level shifting circuits switch simultaneously, the transient current becomes extremely large. Since the positive high voltage (HVL) and negative low voltage (NVL) are generated by a charge pump, if the transient current exceeds the maximum load capacity of the charge pump, it will cause severe jitter in the positive high voltage (HVL) and negative low voltage (NVL). In severe cases, the positive high voltage (HVL) and negative low voltage (NVL) will fail to meet design requirements, directly affecting the chip's normal read, write, and erase functions.

[0054] like Figure 2 The diagram shows another level-shifting architecture, comprising two parallel shifting modules. The high potential of the low-voltage side shifting module is the power supply voltage VDD, and the low potential is the negative low-voltage NVL. During the level shifting process, the current flows from the power supply voltage VDD to the negative low-voltage NVL. It is evident that the voltage difference in the circuit is reduced, resulting in a smaller shifting current. However, this correspondingly leads to a smaller gate-source voltage difference in the output stage MOSFET, thereby weakening the driving capability and slowing down the switching speed of the output signal OUTPUT.

[0055] To overcome the above problems, the present invention provides a level converter 1, which can reduce transient current and speed up conversion. The level converter 1 is described in detail below.

[0056] Example 1

[0057] like Figure 3 As shown, this embodiment provides a level converter 1, which includes an input module 11, a first conversion module 12, a second conversion module 13, a first transmission module 14, a second transmission module 15, and an output module 16.

[0058] like Figure 3 As shown, the input module 11 operates in the first voltage domain, generating a first control signal and a second control signal in the first voltage domain based on the input signal INPUT. The first control signal and the second control signal are logically opposite. The high voltage in the first voltage domain is the first high voltage VDD (the power supply voltage in this example), and the low voltage is the first low voltage GND (zero potential in this example).

[0059] Specifically, in this embodiment, the input module 11 includes a first inverter not1 and a second inverter not2 cascaded together. The first inverter not1 receives the input signal INPUT and outputs a first control signal; the logic of the first control signal is opposite to that of the input signal INPUT, with a logic high level representing the first high voltage VDD and a logic low level representing the first low voltage GND. The input terminal of the second inverter not2 receives the first control signal and generates a second control signal; the logic of the second control signal is opposite to that of the first control signal, with a logic high level representing the first high voltage VDD and a logic low level representing the first low voltage GND. Thus, through the two-stage inverter structure, a pair of logically complementary control signals can be generated based on the single-ended input signal INPUT, while ensuring that the signal driving capability meets the requirements of the subsequent circuits.

[0060] It should be noted that, in practical use, any circuit structure that can generate two logically complementary control signals located in the first voltage domain based on the input signal is applicable to the present invention, and is not limited to this embodiment.

[0061] like Figure 3 As shown, the first conversion module 12 operates in the second voltage domain and generates a first drive signal based on the first control signal and the second control signal. The high voltage in the second voltage domain is the second high voltage HVL (positive high voltage in this example), and the low voltage is the first low voltage GND (zero potential in this example).

[0062] Specifically, when the input signal INPUT is high, the first conversion module 12 generates a first drive signal with a first low voltage GND under the control of the first control signal and the second control signal; when the input signal INPUT is low, the first conversion module 12 generates a first drive signal with a second high voltage HVL under the control of the first control signal and the second control signal. Any circuit structure that can achieve the above functions is applicable to this invention, and will not be described in detail here.

[0063] More specifically, as an example, the first conversion module 12 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, and a second NMOS transistor N2. The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to a second high voltage HVL; the drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3; the drain of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1; the source of the first NMOS transistor N1 is connected to a first low voltage GND; the drain of the second PMOS transistor P2 is connected to the source of the fourth PMOS transistor P4; the drain of the fourth PMOS transistor P4 is connected to the drain of the second NMOS transistor N2; and the source of the second NMOS transistor N2 is connected to the first low voltage GND. The third PMOS transistor P3 and... The gate of the first NMOS transistor N1 is connected to a control signal (the first control signal in this embodiment) that is logically opposite to the input signal INPUT. The drain of the third PMOS transistor P3 and the first NMOS transistor N1 is connected to the gate of the second PMOS transistor P2. The gate of the fourth PMOS transistor P4 and the second NMOS transistor N2 is connected to a control signal (the second control signal in this embodiment) that is logically the same as the input signal INPUT. The drain of the fourth PMOS transistor P4 and the second NMOS transistor N2 is connected to the gate of the first PMOS transistor P1 and serves as the output terminal of the first conversion module 12. In one example, the substrate of each NMOS transistor in the first conversion module 12 is connected to the first low voltage GND, and the substrate of each PMOS transistor is connected to the second high voltage HVL. This example achieves signal regeneration amplification and state maintenance through the positive feedback mechanism of the cross-coupling structure, completing level switching and locking in a very short time, thereby improving voltage gain.

[0064] In this example, when the input signal INPUT is low, the first control signal is high and the second control signal is low; therefore, the first NMOS transistor N1 is turned on, the third PMOS transistor P3 is turned off, causing the gate of the second PMOS transistor P2 to be pulled towards the first low voltage GND, and the second PMOS transistor P2 is turned on; simultaneously, the second NMOS transistor N2 is turned off, and the fourth PMOS transistor P4 is turned on; therefore, the output terminal of the first conversion module 12 outputs the second high voltage HVL. When the input signal INPUT is high, the first control signal is low and the second control signal is high; therefore, the second NMOS transistor N2 is turned on, the fourth PMOS transistor P4 is turned off, the first NMOS transistor N1 is turned off, the third PMOS transistor P3 is turned on, the gate of the first PMOS transistor P1 is pulled towards the first low voltage GND, the first PMOS transistor P1 is turned on, the gate of the second PMOS transistor P2 is pulled towards the second high voltage HVL, and the second PMOS transistor P2 is turned off; therefore, the output terminal of the first conversion module 12 outputs the first low voltage GND.

[0065] like Figure 3As shown, the second conversion module 13 operates in the third voltage domain and generates a second drive signal based on the first control signal and the second control signal. The high voltage in the third voltage domain is the first high voltage VDD (the power supply voltage in this example), and the low voltage is the second low voltage NVL (the negative high voltage in this example).

[0066] Specifically, when the input signal INPUT is high, the second conversion module 13 generates a second drive signal with a second low voltage NVL under the control of the first control signal and the second control signal; when the input signal INPUT is low, the second conversion module 13 generates a second drive signal with a first high voltage VDD under the control of the first control signal and the second control signal. Any circuit structure that can achieve the above functions is applicable to this invention, and will not be described in detail here.

[0067] More specifically, as an example, the second conversion module 13 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6. The sources of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the second low-voltage NVL; the drain of the third NMOS transistor N3 is connected to the source of the fifth NMOS transistor N5; the drain of the fifth NMOS transistor N5 is connected to the drain of the fifth PMOS transistor P5; the source of the fifth PMOS transistor P5 is connected to the first high-voltage VDD; the drain of the fourth NMOS transistor N4 is connected to the source of the sixth NMOS transistor N6; the drain of the sixth NMOS transistor N6 is connected to the drain of the sixth PMOS transistor P6; and the source of the sixth PMOS transistor P6 is connected to the first high-voltage VDD. The fifth NMOS transistor N5 and... The gate of the fifth PMOS transistor P5 is connected to a control signal with the opposite logic to the input signal INPUT (the first control signal in this embodiment). The drains of the fifth NMOS transistor N5 and the fifth PMOS transistor P5 are connected to the gate of the fourth NMOS transistor N4. The gates of the sixth NMOS transistor N6 and the sixth PMOS transistor P6 are connected to a control signal with the same logic as the input signal INPUT (the second control signal in this embodiment). The drains of the sixth NMOS transistor N6 and the sixth PMOS transistor P6 are connected to the gate of the third NMOS transistor N3 and serve as the output terminal of the second conversion module 13. In one example, the substrates of each NMOS transistor in the second conversion module 13 are connected to the second low-voltage NVL, and the substrates of each PMOS transistor are connected to the first high-voltage VDD. Similarly, this example uses a positive feedback mechanism of a cross-coupling structure to achieve signal regeneration, amplification, and state maintenance, completing level switching and locking in a very short time, thereby improving voltage gain.

[0068] In this example, when the input signal INPUT is low, the first control signal is high and the second control signal is low; therefore, the fifth PMOS transistor P5 is off, the fifth NMOS transistor N5 is on, the sixth PMOS transistor P6 is on, and the sixth NMOS transistor N6 is off. This pulls the gate of the third NMOS transistor N3 towards the first high voltage VDD, turning the third NMOS transistor N3 on. The gate of the fourth NMOS transistor N4 is pulled towards the second low voltage NVL, turning the fourth NMOS transistor N4 off. Therefore, the output of the second conversion module 13 outputs the first high voltage VDD. When the input signal INPUT is high, the first control signal is low and the second control signal is high; therefore, the fifth PMOS transistor P5 is on, the fifth NMOS transistor N5 is off, the gate of the fourth NMOS transistor N4 is pulled towards the first high voltage VDD, and the fourth NMOS transistor N4 is on. Simultaneously, the sixth PMOS transistor P6 is off, and the sixth NMOS transistor N6 is on. Therefore, the output of the second conversion module 13 outputs the second low voltage NVL.

[0069] like Figure 3 As shown, the first transmission module 14 is connected to the output terminal of the first conversion module 12 and is used to transmit the first drive signal with the second high voltage HVL and block the first drive signal with the first low voltage GND.

[0070] Specifically, the first transmission module 14 is connected between the output terminal of the first conversion module 12 and the input terminal of the output module 16. When the first driving signal is the second high voltage HVL, the first transmission module 14 is turned on and outputs a voltage signal with the second high voltage HVL; when the first driving signal is the first low voltage GND, the first transmission module 14 is turned off and no signal is transmitted. Any circuit structure that can achieve the above functions is applicable to this invention, and will not be described in detail here.

[0071] More specifically, in this embodiment, the first transmission module 14 includes a seventh PMOS transistor P7. The source of the seventh PMOS transistor P7 is connected to the output terminal of the first conversion module 12, the gate is connected to the second control signal, and the drain serves as the output terminal of the first transmission module 14. In one example, the substrate of the seventh PMOS transistor P7 is connected to a second high voltage HVL.

[0072] like Figure 3 As shown, the second transmission module 15 is connected to the output terminal of the second conversion module 13 and is used to transmit the second drive signal with the second low voltage NVL and block the second drive signal with the first high voltage VDD.

[0073] Specifically, the second transmission module 15 is connected between the output terminal of the second conversion module 13 and the input terminal of the output module 16. When the second driving signal is the second low voltage NVL, the second transmission module 15 is turned on and outputs a voltage signal with the second low voltage NVL; when the second driving signal is the first high voltage VDD, the second transmission module 15 is turned off and no signal is transmitted. Any circuit structure that can achieve the above functions is applicable to this invention, and will not be described in detail here.

[0074] More specifically, in this embodiment, the second transmission module 15 includes a seventh NMOS transistor N7. The source of the seventh NMOS transistor N7 is connected to the output terminal of the second conversion module 13, the gate is connected to the second control signal, and the drain serves as the output terminal of the second transmission module 15. In one example, the substrate of the seventh NMOS transistor N7 is connected to a second low-voltage NVL.

[0075] like Figure 3 As shown, the output module 16 operates in the fourth voltage domain and generates the output signal OUTPUT based on the output signal of the first transmission module 14 or the second transmission module 15. The high voltage in the fourth voltage domain is the second high voltage HVL (positive high voltage in this example), and the low voltage is the second low voltage NVL (negative high voltage in this example).

[0076] Specifically, in this embodiment, the output module 16 includes a third inverter (composed of a fifteenth PMOS transistor P15 and a fifteenth NMOS transistor N15, with the substrate of the fifteenth PMOS transistor P15 connected to the second high voltage HVL and the substrate of the fifteenth NMOS transistor N15 connected to the second low voltage NVL), which shapes and generates the final output signal OUTPUT. The input terminal of the third inverter is connected to the output terminals of the first transmission module 14 and the second transmission module 15, and outputs the output signal OUTPUT of the level converter 1; the logic of the output signal OUTPUT is the same as that of the input signal INPUT, with a logic high level representing the second high voltage HVL and a logic low level representing the second low voltage NVL.

[0077] In this invention, the voltage values ​​of the second high voltage HVL, the first high voltage VDD, the first low voltage GND, and the second low voltage NVL decrease sequentially. This invention utilizes the first transmission module 14 and the second transmission module 15 to ensure that the voltage at the input terminal (point C) of the output module 16 has an output swing from the second high voltage HVL to the second low voltage NVL. In this embodiment, when the input signal INPUT changes from the first high voltage VDD to the first low voltage GND, the gate voltages of the seventh PMOS transistor P7 and the seventh NMOS transistor N7 are equal to the first low voltage GND, the voltage at point A is equal to the second high voltage HVL, and the voltage at point B is equal to the first high voltage VDD. Therefore, the seventh PMOS transistor P7 is turned on, and the seventh NMOS transistor N7 is turned off. The seventh PMOS transistor P7 transmits the second high voltage HVL to point C, where the voltage is equal to the second high voltage HVL. This drives the fifteenth NMOS transistor N15 in the output module 16 to turn on, pulling the output signal OUTPUT low to the second low voltage NVL. When the input signal INPUT changes from the first low voltage GND to the first high voltage VDD, the gate voltages of the seventh PMOS transistor P7 and the seventh NMOS transistor N7 are equal to the first high voltage VDD, the voltage at point A is equal to the first low voltage GND, and the voltage at point B is equal to the second low voltage NVL. Therefore, the seventh PMOS transistor P7 is turned off, the seventh NMOS transistor N7 is turned on, and the seventh NMOS transistor N7 transmits the second low voltage NVL to point C. The voltage at point C is equal to the second low voltage NVL, driving the fifteenth PMOS transistor P15 in the output module 16 to turn on, so as to pull the output signal OUTPUT high to the second high voltage HVL.

[0078] This invention achieves a wide-range level conversion from the first voltage domain to the fourth voltage domain through the cooperation of various modules. Since each module operates in a different voltage domain and selective signal blocking is performed by the transmission module, excessively high gate-source or drain-source voltages on the transistors can be effectively avoided, improving circuit reliability. Furthermore, the high and low levels of the second conversion module 13 are the first high voltage VDD and the second low voltage NVL, respectively. Since there is no voltage difference between the second high voltage HVL and the second low voltage NVL in the circuit itself, there is no large current during signal switching, greatly reducing power consumption during logic signal switching.

[0079] Example 2

[0080] In Example 1, assuming the first high voltage VDD = 1.6V, the first low voltage GND = 0V, the second high voltage HVL = 1.8V, and the second low voltage NVL = -5V; when the input signal INPUT is high, the seventh NMOS transistor N7 is turned on. At this time, the gate-source voltage difference V_gsn7 of the seventh NMOS transistor N7 is VDD - NVL = 6.6V, which is relatively large. Therefore, the seventh NMOS transistor N7 turns on quickly, resulting in a faster rising edge transition of the output signal OUTPUT. However, when the input signal INPUT is low, the seventh PMOS transistor P7 is turned on. At this time, the gate-source voltage difference V_gsp7 of the seventh PMOS transistor P7 is HVL = 1.8V, which is relatively small. Therefore, the seventh PMOS transistor P7 turns on slowly, resulting in a slower falling edge transition of the output signal OUTPUT.

[0081] To address this issue, this embodiment provides a level converter 1, which differs from Embodiment 1 in that the control signal connection relationships of each conversion module and transmission module are different.

[0082] like Figure 4 As shown, in this embodiment, the first conversion module 12 includes an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, an eighth NMOS transistor N8, and a ninth NMOS transistor N9. The sources of the eighth PMOS transistor P8 and the ninth PMOS transistor P9 are connected to a second high voltage HVL. The drain of the eighth PMOS transistor P8 is connected to a first low voltage GND via the tenth PMOS transistor P10 and the eighth NMOS transistor N8. The gates of the tenth PMOS transistor P10 and the eighth NMOS transistor N8 are connected to a first control signal (logically opposite to the input signal INPUT). The drains of the tenth PMOS transistor P10 and the eighth NMOS transistor N8 are connected to the gate of the ninth PMOS transistor P9. The drain of the ninth PMOS transistor P9 is connected to the first low voltage GND via the eleventh PMOS transistor P11 and the ninth NMOS transistor N9 in sequence. The gate of the ninth NMOS transistor N9 is connected to the second control signal (with the same logic as the input signal INPUT). The drains of the eleventh PMOS transistor P11 and the ninth NMOS transistor N9 are connected to the gate of the eighth PMOS transistor P8 and serve as the output terminal of the first conversion module 12.

[0083] like Figure 4As shown, in this embodiment, the second conversion module 13 includes a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, and a thirteenth NMOS transistor N13. The sources of the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 are connected to the second low voltage NVL. The drain of the tenth NMOS transistor N10 is connected to the first high voltage VDD via the twelfth NMOS transistor N12 and the twelfth PMOS transistor P12. The gates of the twelfth NMOS transistor N12 and the twelfth PMOS transistor P12 are connected to the first control signal. The drains of the twelfth NMOS transistor N12 and the twelfth PMOS transistor P12 are connected to the gate of the eleventh NMOS transistor N11. The drain of the eleventh NMOS transistor N11 is connected to the first high voltage VDD via the thirteenth NMOS transistor N13 and the thirteenth PMOS transistor P13. The gate of the thirteenth PMOS transistor P13 is connected to the second control signal. The drains of the thirteenth NMOS transistor N13 and the thirteenth PMOS transistor P13 are connected to the gate of the tenth NMOS transistor N10 and serve as the output terminal of the second conversion module 13.

[0084] It should be noted that in this embodiment, the gate of the eleventh PMOS transistor P11 is connected to the drain of the twelfth NMOS transistor N12; the gate of the thirteenth NMOS transistor N13 is connected to the drain of the eighth NMOS transistor N8 and the tenth PMOS transistor P10. The control signals (gate voltages) of the eleventh PMOS transistor P11 and the thirteenth NMOS transistor N13 are different from those in Embodiment 1, but the working principles of the first conversion module 12 and the second conversion module 13 are the same as in Embodiment 1, and will not be described in detail here.

[0085] In one example, in the first conversion module 12, the substrates of each NMOS transistor are connected to a first low voltage GND, and the substrates of each PMOS transistor are connected to a second high voltage HVL. In the second conversion module 13, the substrates of each NMOS transistor are connected to a second low voltage NVL, and the substrates of each PMOS transistor are connected to a first high voltage VDD.

[0086] like Figure 4 As shown, in this embodiment, the first transmission module 14 includes a fourteenth PMOS transistor P14. The source of the fourteenth PMOS transistor P14 is connected to the output terminal of the first conversion module 12, and the gate is connected to the gate of the eleventh PMOS transistor P11 (i.e., the drain of the twelfth NMOS transistor N12 and the drain of the twelfth PMOS transistor P12). The drain serves as the output terminal of the first transmission module 14. In one example, the substrate of the fourteenth PMOS transistor P14 is connected to a second high voltage HVL.

[0087] like Figure 4As shown, in this embodiment, the second transmission module 15 includes a fourteenth NMOS transistor N14. The source of the fourteenth NMOS transistor N14 is connected to the output terminal of the second conversion module 15, and the gate is connected to the gate of the thirteenth NMOS transistor N13 (i.e., the drain of the eighth NMOS transistor N8 and the tenth PMOS transistor P10). The drain serves as the output terminal of the second transmission module 15.

[0088] In this embodiment, the gate of the fourteenth PMOS transistor P14 is controlled by node E1 in the second conversion module 13, and the gate of the fourteenth NMOS transistor N14 is controlled by node D1 in the first conversion module 12, forming a cross-control mechanism. When the input signal INPUT is high, the voltage at point D1 is equal to the second high voltage HVL, the voltage at point D2 is equal to the first low voltage GND, the voltage at point E1 is equal to the first high voltage VDD, and the voltage at point E2 is equal to the second low voltage NVL. At this time, the fourteenth NMOS transistor N14 is turned on, and its gate-source voltage difference V_gsn14 is equal to HVL-NVL=6.6V, which is the same as the gate-source voltage difference V_gsn7 of the seventh NMOS transistor N7 in Embodiment 1. Therefore, the transmission speed of the fourteenth NMOS transistor N14 is the same as the transmission speed of the seventh NMOS transistor N7. When the input signal INPUT is low, the voltage at point D1 is equal to the first low voltage GND, the voltage at point D2 is equal to the second high voltage HVL, the voltage at point E1 is equal to the second low voltage NVL, and the voltage at point E2 is equal to the first high voltage VDD. At this time, the fourteenth PMOS transistor P14 is turned on, and its gate-source voltage V_gsp14 is equal to HVL-NVL=6.8V, which is greater than the gate-source voltage difference V_gsp7 of the seventh PMOS transistor P7 in Embodiment 1. Therefore, the transmission speed of the fourteenth PMOS transistor P14 is more than 3 times faster than that of the seventh PMOS transistor P7, and the falling edge switching speed of the output signal OUTPUT is greatly accelerated.

[0089] Therefore, the level converter in this embodiment has the advantages of low power consumption and fast rising edge switching in Embodiment 1, while overcoming the disadvantage of slow falling edge switching in Embodiment 1, so that the output signal OUTPUT switches quickly on the falling edge.

[0090] It should be noted that the other circuit structures and working principles are the same as in Embodiment 1, and will not be described in detail here.

[0091] Example 3

[0092] In Embodiment 1 and Embodiment 2, there is a voltage difference between the substrate and source of the transistor in the transmission module during operation, which will produce a substrate bias effect, leading to an increase in the threshold voltage, increasing the on-resistance of the transistor in the transmission module, and thus affecting the operating speed and stability of the circuit performance.

[0093] To address the substrate bias effect, this embodiment provides a level converter 1, which differs from embodiments one and two in that the substrate and source of the transistor in the transmission module are connected together, thereby keeping the threshold voltage stable.

[0094] Taking Example 1 as an example, such as Figure 5 As shown, the substrate and source of the seventh PMOS transistor P7 are both connected to the output terminal of the first conversion module 12, and the substrate and source of the seventh NMOS transistor N7 are both connected to the output terminal of the second conversion module 13.

[0095] In Example 2, the substrate and source of the fourteenth PMOS transistor P14 are connected together, and the substrate and source of the fourteenth NMOS transistor N14 are connected together, which will not be described in detail here.

[0096] It should be noted that the other circuit structures and working principles are the same as those in Examples 1 and 2, and will not be described in detail here.

[0097] Example 4

[0098] This embodiment provides a NOR flash memory, which includes at least a level converter 1 as described in any of the above embodiments. In NOR flash memory, a positive high voltage higher than the power supply voltage and a negative high voltage lower than ground voltage are typically required for programming, erasing, and reading operations on the memory cells.

[0099] Specifically, the level converter provided by this invention can convert low-voltage domain signals generated by logic control circuits into wide-voltage domain signals covering a range from positive high voltage to negative high voltage, thereby driving high-voltage switches or high-voltage decoding circuits. Because the level converter of this invention employs a voltage domain design and a blocking mechanism in the transmission module, it can effectively avoid excessive electric field stress on the transistor gate oxide layer during wide voltage conversion, improving the reliability and lifespan of NOR flash memory.

[0100] As an example, in a specific application of NOR flash memory, input module 11 receives logic signals from an address decoder or control logic unit, and the wide-range level signal output by output module 16 can be used to control word line selection switches or bit line high-voltage drive circuits. By setting the first high voltage to the normal power supply voltage of the NOR flash memory, the second high voltage to the high voltage required for programming, the first low voltage to the reference ground voltage, and the second low voltage to the negative high voltage required for erasure, flexible switching from normal logic levels to high-voltage programming levels and negative high-voltage erasure levels can be achieved.

[0101] It should be noted that this invention achieves a wide-range, highly reliable, low-power, and fast level conversion function by setting conversion and transmission modules operating in different voltage domains. This level converter can be widely used in integrated circuits that require wide voltage range signal driving, and is particularly suitable for memory devices such as NOR flash memory that require coordinated control of positive and negative high voltages.

[0102] The level converter 1 of this invention eliminates the voltage difference between the positive high voltage HVL and the negative high voltage NVL, reducing the switching current during circuit operation and increasing the switching speed of the output signal OUTPUT by adding a transmission transistor. Furthermore, the transmission transistor employs a self-biased method, keeping the threshold voltage constant, further improving the transmission speed and maintaining circuit stability.

[0103] like Figure 6 As shown Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 Simulation data of the falling edge transition time of the output signal of the level converter under the conditions of corner ssss, temperature equal to -40℃ and 105℃ (corresponding to OUT_fall_Prior#1). Figure 1 OUT_fall_Prior#2 corresponds to Figure 2 OUT_fall_PAT#1 corresponds to Figure 3 OUT_fall_PAT#2 corresponds to Figure 4 OUT_fall_PAT#3 corresponds to Figure 5 ),visible, Figure 2 The level shifter has the slowest switching speed, while the switching speed of the falling edge in the other circuit architectures can reach the fastest. Figure 2 Approximately 10 times that of a level converter. Figure 5 Level converter in Figure 3 , Figure 4 , Figure 5 The falling edge has the fastest flipping speed.

[0104] like Figure 7 As shown Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 Simulation data of the rise time of the output signal of the level converter under the conditions of corner ssss, temperature equal to -40℃ and 105℃ (corresponding to OUT_rise_Prior#1). Figure 1 OUT_rise_Prior#2 corresponds to Figure 2 OUT_rise_PAT#1 corresponds to Figure 3OUT_rise_PAT#2 corresponds to Figure 4 OUT_rise_PAT#3 corresponds to Figure 5 ),visible, Figure 2 The level shifter in this circuit has the slowest rising edge switching speed, while the rising edge switching speed of the other circuit architectures can reach the fastest. Figure 2 Approximately 6 times that of a level converter.

[0105] like Figure 8 As shown Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 Simulation data of HVL current consumption during signal switching of a level shifter under conditions of corner ssss and temperature equal to -40℃ and 105℃ (corresponding to IHVL_Prior#1). Figure 1 IHVL _Prior#2 corresponds to Figure 2 IHVL_PAT#1 corresponds to Figure 3 IHVL_PAT#2 corresponds to Figure 4 IHVL_PAT#3 corresponds to Figure 5 ),in, Figure 1 The level converter consumes the largest HVL current when it flips, which can be up to about 50 times that of the other circuits.

[0106] like Figure 9 As shown Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 Simulation data of NVL current consumption during signal switching of a level converter under conditions of corner ssss and temperatures of -40℃ and 105℃ (corresponding to INVL_Prior#1). Figure 1 INVL _Prior#2 corresponds to Figure 2 INVL_PAT#1 corresponds to Figure 3 INVL_PAT#2 corresponds to Figure 4 INVL_PAT#3 corresponds to Figure 5 ),in Figure 1 The level converter consumes the largest NVL current when it flips, which can be up to about 25 times that of the other circuits.

[0107] In summary, this invention provides a level converter and NOR flash memory, comprising: an input module, a first conversion module, a second conversion module, a first transmission module, a second transmission module, and an output module; the input module operates in a first voltage domain, generating a first control signal and a second control signal based on an input signal in the first voltage domain; wherein the first control signal and the second control signal are logically opposite, with the high voltage in the first voltage domain being the first high voltage and the low voltage being the first low voltage; the first conversion module operates in a second voltage domain, generating a first drive signal based on the first control signal and the second control signal; wherein the high voltage in the second voltage domain is the second high voltage and the low voltage is the first low voltage; the second conversion module operates in a third voltage domain, generating a first drive signal based on the first control signal and the second control signal. The second control signal generates the second drive signal; wherein, the high voltage of the third voltage domain is the first high voltage, and the low voltage is the second low voltage; the first transmission module is connected to the output terminal of the first conversion module and is used to transmit the first drive signal with the second high voltage and block the first drive signal with the first low voltage; the second transmission module is connected to the output terminal of the second conversion module and is used to transmit the second drive signal with the second low voltage and block the second drive signal with the first high voltage; the output module operates in the fourth voltage domain and generates an output signal based on the output signal of the first transmission module or the second transmission module; wherein, the high voltage of the fourth voltage domain is the second high voltage, and the low voltage is the second low voltage; wherein, the voltage values ​​of the second high voltage, the first high voltage, the first low voltage, and the second low voltage decrease sequentially. The level converter of the present invention can effectively reduce the large current consumed during the switching process and accelerate the establishment time of the rising and falling edges of the output signal, thereby improving the conversion speed of the output signal. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A level converter, characterized in that, The level converter includes at least: The system comprises an input module, a first conversion module, a second conversion module, a first transmission module, a second transmission module, and an output module. The input module operates in a first voltage domain and generates a first control signal and a second control signal located in the first voltage domain based on the input signal; wherein the logic of the first control signal and the second control signal is opposite, and the high voltage of the first voltage domain is the first high voltage and the low voltage is the first low voltage. The first conversion module operates in the second voltage domain and generates a first drive signal based on the first control signal and the second control signal; wherein, the high voltage in the second voltage domain is the second high voltage and the low voltage is the first low voltage; The second conversion module operates in the third voltage domain and generates a second drive signal based on the first control signal and the second control signal; wherein, the high voltage of the third voltage domain is the first high voltage and the low voltage is the second low voltage; The first transmission module is connected to the output terminal of the first conversion module and is used to transmit the first drive signal with the second high voltage and block the first drive signal with the first low voltage. The second transmission module is connected to the output of the second conversion module and is used to transmit the second drive signal with the second low voltage and block the second drive signal with the first high voltage. The output module operates in a fourth voltage domain and generates an output signal based on the output signal of the first transmission module or the second transmission module; wherein, the high voltage of the fourth voltage domain is the second high voltage and the low voltage is the second low voltage; The voltage values ​​of the second high voltage, the first high voltage, the first low voltage, and the second low voltage decrease sequentially.

2. The level converter according to claim 1, characterized in that: The input module includes a first inverter and a second inverter connected in series; the first inverter receives the input signal and outputs the first control signal; the input terminal of the second inverter receives the first control signal and generates the second control signal.

3. The level converter according to claim 1, characterized in that: The first conversion module is configured to: make the voltage of the first drive signal the first low voltage when the input signal is high, and make the voltage of the first drive signal the second high voltage when the input signal is low.

4. The level converter according to claim 3, characterized in that: The first conversion module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The sources of the first PMOS transistor and the second PMOS transistor are connected to the second high voltage; the drain of the first PMOS transistor is connected to the first low voltage via the third PMOS transistor and the first NMOS transistor in sequence; the gates of the third PMOS transistor and the first NMOS transistor are connected to the first control signal; the drains of the third PMOS transistor and the first NMOS transistor are connected to the gate of the second PMOS transistor; the drain of the second PMOS transistor is connected to the first low voltage via the fourth PMOS transistor and the second NMOS transistor in sequence; the gates of the fourth PMOS transistor and the second NMOS transistor are connected to the second control signal; the drains of the fourth PMOS transistor and the second NMOS transistor are connected to the gate of the first PMOS transistor and serve as the output terminal of the first conversion module. Wherein, the first control signal is logically opposite to the input signal, and the second control signal is logically the same as the input signal.

5. The level converter according to claim 4, characterized in that: The first transmission module includes a seventh PMOS transistor, the source of which is connected to the output terminal of the first conversion module, the gate of which is connected to the second control signal, and the drain of which serves as the output terminal of the first transmission module.

6. The level converter according to claim 5, characterized in that: The substrate and source of the seventh PMOS transistor are connected together.

7. The level converter according to claim 1, characterized in that: The second conversion module is configured to: make the voltage of the second drive signal the second low voltage when the input signal is high, and make the voltage of the second drive signal the first high voltage when the input signal is low.

8. The level converter according to claim 7, characterized in that: The second conversion module includes a fifth PMOS transistor, a sixth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The sources of the third and fourth NMOS transistors are connected to the second low voltage; the drain of the third NMOS transistor is connected to the first high voltage via the fifth NMOS transistor and the fifth PMOS transistor in sequence; the gates of the fifth NMOS transistor and the fifth PMOS transistor are connected to the first control signal; the drains of the fifth NMOS transistor and the fifth PMOS transistor are connected to the gate of the fourth NMOS transistor; the drain of the fourth NMOS transistor is connected to the first high voltage via the sixth NMOS transistor and the sixth PMOS transistor in sequence; the gates of the sixth NMOS transistor and the sixth PMOS transistor are connected to the second control signal; the drains of the sixth NMOS transistor and the sixth PMOS transistor are connected to the gate of the third NMOS transistor and serve as the output terminal of the second conversion module. Wherein, the first control signal is logically opposite to the input signal, and the second control signal is logically the same as the input signal.

9. The level converter according to claim 8, characterized in that: The second transmission module includes a seventh NMOS transistor, the source of which is connected to the output terminal of the second conversion module, the gate of which is connected to the second control signal, and the drain of which serves as the output terminal of the second transmission module.

10. The level converter according to claim 9, characterized in that: The substrate and source of the seventh NMOS transistor are connected together.

11. The level converter according to claim 3 or 7, characterized in that: The first conversion module includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The sources of the eighth PMOS transistor and the ninth PMOS transistor are connected to the second high voltage; the drain of the eighth PMOS transistor is connected to the first low voltage via the tenth PMOS transistor and the eighth NMOS transistor in sequence; the gates of the tenth PMOS transistor and the eighth NMOS transistor are connected to the first control signal; the drains of the tenth PMOS transistor and the eighth NMOS transistor are connected to the gate of the ninth PMOS transistor; the drain of the ninth PMOS transistor is connected to the first low voltage via the eleventh PMOS transistor and the ninth NMOS transistor in sequence; the gate of the ninth NMOS transistor is connected to the second control signal; the drains of the eleventh PMOS transistor and the ninth NMOS transistor are connected to the gate of the eighth PMOS transistor and serve as the output terminal of the first conversion module. The second conversion module includes a twelfth PMOS transistor, a thirteenth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor. The sources of the tenth and eleventh NMOS transistors are connected to the second low voltage. The drain of the tenth NMOS transistor is connected to the first high voltage via the twelfth NMOS transistor and the twelfth PMOS transistor. The gates of the twelfth and twelfth PMOS transistors are connected to the first control signal. The drains of the twelfth and twelfth PMOS transistors are connected to the gate of the eleventh NMOS transistor. The drain of the eleventh NMOS transistor is connected to the first high voltage via the thirteenth NMOS transistor and the thirteenth PMOS transistor. The gate of the thirteenth PMOS transistor is connected to the second control signal. The drains of the thirteenth and thirteenth PMOS transistors are connected to the gate of the tenth NMOS transistor and serve as the output terminal of the second conversion module. The gate of the eleventh PMOS transistor is connected to the drain of the twelfth NMOS transistor and the twelfth PMOS transistor, and the gate of the thirteenth NMOS transistor is connected to the drain of the eighth NMOS transistor and the tenth PMOS transistor.

12. The level converter according to claim 11, characterized in that: The first transmission module includes a fourteenth PMOS transistor, the source of which is connected to the output terminal of the first conversion module, the gate of which is connected to the gate of the eleventh PMOS transistor, and the drain of which serves as the output terminal of the first transmission module.

13. The level converter according to claim 12, characterized in that: The substrate and source of the fourteenth PMOS transistor are connected together.

14. The level converter according to claim 11, characterized in that: The second transmission module includes a fourteenth NMOS transistor, the source of which is connected to the output terminal of the second conversion module, the gate of which is connected to the gate of the thirteenth NMOS transistor, and the drain of which serves as the output terminal of the second transmission module.

15. The level converter according to claim 14, characterized in that: The substrate and source of the fourteenth NMOS transistor are connected together.

16. The level converter according to claim 1, characterized in that: The output module includes a third inverter.

17. A NOR flash memory, characterized in that, The NOR flash memory includes at least one level converter as described in any one of claims 1-16.

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