Sub-nanosecond level shift circuit with rise and fall time equalization

Abstract

The application discloses a sub-nanosecond level shift circuit with rising and falling edge delay balance, comprising a voltage domain conversion module, which is connected with a falling edge detection module and a dual-state common-mode transient disturbance self-correction module respectively; the voltage domain conversion module converts a circuit input signal into an internal node signal, the falling edge detection module identifies a falling edge jump of the internal node signal and outputs a control signal to make the internal node in the voltage domain conversion module complete charging, and the dual-state common-mode transient disturbance self-correction module obtains a circuit output signal after processing a noise signal and the internal node signal of the voltage domain conversion module. The sub-nanosecond level shift circuit with rising and falling edge delay balance combines sub-nanosecond symmetric delay transmission technology and high common-mode transient suppression technology; the symmetric delay transmission adopts the falling edge detection module, the internal node charging and discharging is completed in advance, the falling edge transmission time is greatly compressed, the rising and falling edge delays are stabilized in the sub-nanosecond interval, and the rising and falling edge delays are highly balanced.

Description

Technical Field

[0001] This invention belongs to the field of level shifting circuit technology, and relates to a sub-nanosecond level shifting circuit with equal rising and falling edge delays. Background Technology

[0002] With the popularization of 5G technology and the development of high-frequency and miniaturized electronic devices, the requirements for operating frequency, transmission speed, and operational stability of power conversion systems are constantly upgrading. Gate driver chips are the core carrier connecting low-voltage control modules and power switching devices, combining signal amplification, cross-domain level conversion, and device safety protection functions. Level shifting circuits, as the core key unit of the gate driver chip, undertake the task of signal transmission between different voltage domains. Their sub-nanosecond transmission speed, rise / fall delay matching accuracy, and common-mode transient immunity directly determine the high-frequency operating limit and long-term reliability of the power drive system.

[0003] In half-bridge power drive topologies, the high-frequency switching action of power devices generates extremely high-slope dV / dt (Derivative of Voltage with respect to Time) common-mode transient noise. This noise can easily couple into the level shifting circuit through device parasitic parameters, causing signal transmission distortion and, in severe cases, shoot-through of the upper and lower transistors and burnout of the power devices. Traditional solutions typically add a post-filter circuit to improve common-mode transient rejection capability, but the filter structure significantly increases signal transmission delay, compromising the circuit's sub-nanosecond high-speed performance. Simultaneously, to retain the narrow pulse effective signal, the input signal pulse width needs to be widened, leading to an increase in the conduction time of LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) and a rise in system power consumption. Therefore, traditional circuits always suffer from the core contradiction of incompatibility between sub-nanosecond high-speed transmission and high common-mode transient rejection, severely restricting the application of high-frequency power systems.

[0004] Conventional floating level shifter circuits possess inherent sub-nanosecond rise-time propagation speeds, meeting the high-speed requirements of high-frequency applications. However, they suffer from inherent drawbacks: the rise-and-fall-time propagation paths are asymmetrical. The rising edge path is simple with extremely low delay, maintaining a stable sub-nanosecond level; while the falling edge propagation path is lengthy with low charging and discharging efficiency, resulting in delays of over ten nanoseconds. This significant difference in rise-and-fall-time delays leads to severe delay mismatch. This waveform asymmetry not only causes switching timing deviations in power devices, dead-time control failures, and increased system losses, but also completely destroys the overall sub-nanosecond high-speed characteristics of the circuit, making it impossible to simultaneously meet the high-frequency design requirements of ultra-high-speed sub-nanosecond propagation across the entire domain and precise matching of rise-and-fall-time delays.

[0005] Currently, there are some improved solutions in the industry for delay optimization or common-mode transient suppression, but they generally have obvious performance trade-offs and it is difficult to achieve unified compatibility of the three core performance aspects: some solutions only optimize rise and fall delay matching and achieve waveform symmetry, but do not have strong common-mode transient suppression capabilities. They are prone to output false triggering under high dV / dt noise disturbances, resulting in insufficient reliability; other solutions focus on improving CMTI (Common Mode Transient Immunity) immunity performance, but require the addition of a large number of components and transmission paths, resulting in a significant increase in circuit delay and loss of the sub-nanosecond high-speed transmission advantage.

[0006] In summary, existing technologies cannot simultaneously achieve sub-nanosecond ultra-low speed transmission, high matching of rise and fall edge delays, and high common-mode transient immunity, and are therefore unsuitable for next-generation high-frequency, high-reliability power drive applications. Summary of the Invention

[0007] The purpose of this invention is to provide a sub-nanosecond level shift circuit with equal rise and fall edge delays, which solves the problem in the prior art that level shift circuits cannot simultaneously achieve sub-nanosecond high-speed transmission, rise and fall edge delay matching, and strong common-mode transient suppression capabilities.

[0008] The technical solution adopted in this invention is a sub-nanosecond level shift circuit with equalized rising and falling edge delays, including a voltage domain conversion module, which is connected to a falling edge detection module and a dual-state common-mode transient disturbance self-correction module. The voltage domain conversion module converts the circuit input signal into an internal node signal. The falling edge detection module identifies the falling edge transition of the internal node signal and outputs a control signal to enable the internal node in the voltage domain conversion module to complete charging. The dual-state common-mode transient disturbance self-correction module processes the noise signal and the internal node signal of the voltage domain conversion module to obtain the circuit output signal.

[0009] The invention is further characterized by: The voltage domain conversion module includes an NLDMOS (N-type Laterally Diffused Metal-Oxide-Semiconductor) transistor. N1 NLDMOS transistor L N2 And PLDMOS (P-type Laterally Diffused Metal-Oxide-Semiconductor) transistor L P1 PLDMOS transistor L P2 PLDMOS transistor L P4 PLDMOS transistor L P5and NMOS (N-type Metal-Oxide-Semiconductor) transistor M N1 NMOS transistor M N2 Inverter INV1, inverter INV2, inverter INV3, inverter INV4; NLDMOS transistor L N1 gate and input signal V IN and NLDMOS transistor L N2 The source connection of the NLDMOS transistor L N1 The source electrode and the low-pressure side of the ground V SSL Connection, NLDMOS transistor L N1 The drain of the PLDMOS transistor L P1 The drain and PLDMOS transistor L P4 Drain connection; NLDMOS transistor L N2 Gate and low-voltage side power supply V DDL Connection, NLDMOS transistor L N2 The drain of the PLDMOS transistor L P2 The drain and PLDMOS transistor L P5 The drain connection.

[0010] PLDMOS transistor L P1 The gate of the NMOS transistor M N1 The gate of the PLDMOS transistor is connected to the output of the inverter INV4. P1 The source and the high-voltage side power supply V DDH Connection; PLDMOS transistor L P2 The gate of the NMOS transistor M N2 The gate of the PLDMOS transistor is connected to the output of the inverter INV2 and one input of the OR gate OR1 in the dual-state common-mode transient disturbance self-correction module. P2 The source and the high-voltage side power supply V DDH connect.

[0011] PLDMOS transistor L P4 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P4 The source and NMOS transistor M N1 The drain, the input of inverter INV1, and the PMOS (P-type Metal-Oxide-Semiconductor) transistor M in the falling edge detection module.P1 The drain of the NOR gate NOR1 in the dual-state common-mode transient disturbance self-correction module is connected; PLDMOS transistor L P5 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P5 The source and NMOS transistor M N2 The drain of the NMOS transistor is connected to the input of inverter INV3 and the input of inverter INV5 in the falling edge detection module; NMOS transistor M N1 The source electrode and the high-voltage side ground V SSH Connection; NMOS transistor M N2 The source electrode and the high-voltage side ground V SSH connect.

[0012] The output terminal of inverter INV1 and the input terminal of inverter INV2, and the NMOS transistor M in the dual-state common-mode transient disturbance self-correction module. N4 The drain and PMOS transistor M P2 The drain of inverter INV3 is connected to the input of inverter INV4; inverters INV1, INV2, INV3, and INV4 are connected to the high-voltage side power supply respectively. V DDH High-voltage side of the ground V SSH connect.

[0013] The falling edge detection module includes inverters INV5, INV6, INV7, and INV8, a NAND gate NAND1, and a PMOS transistor M. P1 ; The output of inverter INV5 is connected to the input of inverter INV6 and one input of NAND gate NAND1; the output of inverter INV6 is connected to the input of inverter INV7; the output of inverter INV7 is connected to the input of inverter INV8; the output of inverter INV8 is connected to the other input of NAND gate NAND1; the output of NAND gate NAND1 is connected to PMOS transistor M. P1 Gate connection; PMOS transistor M P1 The source electrode and the high-voltage side ground V SSH connect.

[0014] The dual-state common-mode transient disturbance self-calibration module includes an NLDMOS transistor L N3 PLDMOS transistor L P3 PLDMOS transistor L P4 NMOS transistor M N3OR gate (OR1), NOR gate (NOR1), NMOS transistor (M) N4 PMOS transistor M P2 ; NLDMOS transistor L N3 The gate of the NLDMOS transistor L N3 The source electrode, the low-pressure side of the ground V SSL Connection, NLDMOS transistor L N3 The drain of the PLDMOS transistor L P3 drain of PLDMOS transistor L P6 Drain connection; PLDMOS transistor L P3 The gate of the NMOS transistor M N3 The gate connection of the PLDMOS transistor L P3 The source and the high-voltage side power supply V DDH connect.

[0015] PLDMOS transistor L P6 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P6 The source and NMOS transistor M N3 The drain of the NMOS transistor is connected to the other input of the OR gate (OR1) and the other input of the NOR gate (NOR1); NMOS transistor M N3 The source electrode and the high-voltage side ground V SSH connect.

[0016] The output of OR gate OR1 is connected to PMOS transistor M P2 The gate is connected; the output of the NOR gate NOR1 is connected to the NMOS transistor M. N4 Gate connection; PMOS transistor M P2 The source and the high-voltage side power supply V DDH Connection; NMOS transistor M N4 The source electrode and the high-voltage side ground V SSH connect.

[0017] The beneficial effects of this invention are: This invention uses a voltage domain conversion module containing dual NLDMOS and PLDMOS branches as the core transmission carrier, and transmits signals via low-voltage input signals. V IN Control NLDMOS transistor L N1 L N2The on / off state converts the logic signal in the low-voltage domain into the internal node level in the high-voltage floating domain. Relying on the high-voltage tolerance characteristics of the LDMOS device, it realizes electrical isolation between the high and low voltage domains and cross-domain signal transmission. It naturally has a sub-nanosecond rise edge transmission speed, providing a basic path for high-speed level conversion of the circuit. At the same time, the multiple output internal node signals can provide signal support for subsequent delay optimization and common-mode rejection modules. To address the inherent drawbacks of traditional floating level shift circuits, such as lengthy falling-edge transmission links and delays more than ten times greater than rising-edge delays, this invention employs a configuration consisting of a four-stage inverter delay chain, a NAND gate (NAND1), and a PMOS transistor (M). P1 The falling edge detection module can identify internal nodes in real time. V NM The falling edge of the signal triggers a short-time control signal, turning on the PMOS transistor M. P1 For internal nodes V N Provides an additional fast charging path, eliminating the need to wait for the original long-chain, step-by-step charging and discharging process to complete. V N The node potential rise effectively compresses the overall transmission time of the falling edge, keeping the transmission delay of both rising and falling edges in the sub-nanosecond range. This alleviates the problem of rising and falling edge delay mismatch in traditional circuits, helps reduce the risk of power device switching timing offset and dead-time control failure, and adapts to the timing accuracy requirements of high-frequency power drives. In terms of common-mode transient noise suppression, this invention employs a dual-state common-mode transient disturbance self-calibration module, through an NLDMOS transistor L... N3 PLDMOS transistor L P3 With L P6 NMOS transistor M N3 The reference branch replicates the common-mode noise signal under a constant low-level state, and then performs logical operations with the internal node signals through NOR1 and OR1 respectively to generate two targeted correction pulses, which drive the NMOS transistor M at the output terminal respectively. N4 With PMOS transistor M P2 For common-mode noise false triggering under both high and low input conditions, pull-down and pull-up potential clamping repairs are performed respectively, which can suppress output false flipping under high-speed common-mode voltage swing of 250V / ns and improve the common-mode transient immunity performance of the circuit. This invention abandons the common-mode rejection method of traditional RC (Resistance-Capacitance) post-filter circuits, fundamentally avoiding the additional transmission delay introduced by the filter structure. Simultaneously, the dual-state common-mode transient disturbance self-calibration module only outputs a correction signal during common-mode noise disturbances; under noise-free conditions, the correction branch remains off and does not interfere with the normal signal transmission path. This improves common-mode immunity without degrading the circuit's high-speed transmission performance and also helps reduce static power consumption. Through the coordinated operation of the three modules, the overall circuit achieves sub-nanosecond high-speed transmission while balancing rising and falling edge delay equalization and high common-mode transient immunity. This alleviates the contradiction between high speed, delay matching, and disturbance rejection that is difficult to achieve simultaneously in traditional level-shift circuits, making it suitable for power drive applications with higher frequency and higher reliability requirements. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the sub-nanosecond level shift circuit with rising and falling edge delay equalization of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the sub-nanosecond level shift circuit with rising and falling edge delay equalization of the present invention.

[0019] In the diagram, 1 is the voltage domain conversion module; 2 is the falling edge detection module; and 3 is the dual-state common-mode transient disturbance self-correction module. Detailed Implementation

[0020] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0021] Example 1 This embodiment proposes a sub-nanosecond level shift circuit with equalized rising and falling edge delays, such as... Figure 1 As shown, it includes a voltage domain conversion module 1, which is connected to a falling edge detection module 2 and a dual-state common-mode transient disturbance self-correction module 3. Voltage domain conversion module 1 converts the circuit input signal into an internal node signal. Falling edge detection module 2 identifies the falling edge transition of the internal node signal and outputs a control signal to enable the internal node in voltage domain conversion module 1 to complete charging. Dual-state common-mode transient disturbance self-correction module 3 processes the noise signal and the internal node signal of voltage domain conversion module 1 to obtain the circuit output signal.

[0022] Example 2 Based on Example 1, this example proposes, as follows: Figure 2 As shown, voltage domain conversion module 1 includes an NLDMOS transistor L N1 NLDMOS transistor L N2 and PLDMOS transistor L P1 PLDMOS transistor L P2 PLDMOS transistor LP4 PLDMOS transistor L P5 and NMOS transistor M N1 NMOS transistor M N2 Inverter INV1, inverter INV2, inverter INV3, inverter INV4; NLDMOS transistor L N1 gate and input signal V IN and NLDMOS transistor L N2 The source connection of the NLDMOS transistor L N1 The source electrode and the low-pressure side of the ground V SSL Connection, NLDMOS transistor L N1 The drain of the PLDMOS transistor L P1 The drain and PLDMOS transistor L P4 Drain connection; NLDMOS transistor L N2 Gate and low-voltage side power supply V DDL Connection, NLDMOS transistor L N2 The drain of the PLDMOS transistor L P2 The drain and PLDMOS transistor L P5 The drain connection.

[0023] Example 3 Based on Example 2, this example proposes a PLDMOS transistor L P1 The gate of the NMOS transistor M N1 The gate of the PLDMOS transistor is connected to the output of the inverter INV4. P1 The source and the high-voltage side power supply V DDH Connection; PLDMOS transistor L P2 The gate of the NMOS transistor M N2 The gate of the PLDMOS transistor L is connected to the output of the inverter INV2 and one input of the OR gate OR1 in the dual-state common-mode transient disturbance self-correction module 3. P2 The source and the high-voltage side power supply V DDH connect; PLDMOS transistor L P4 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P4 The source and NMOS transistor M N1 The drain of the inverter, the input of INV1, and the PMOS transistor M in the falling edge detection module 2. P1The drain of the NOR gate NOR1 in the dual-state common-mode transient disturbance self-correction module 3 is connected; PLDMOS transistor L P5 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P5 The source and NMOS transistor M N2 The drain of the inverter, the input of inverter INV3, and the input of inverter INV5 in falling edge detection module 2 are connected. NMOS transistor M N1 The source electrode and the high-voltage side ground V SSH Connection; NMOS transistor M N2 The source electrode and the high-voltage side ground V SSH connect; The output terminal of inverter INV1 and the input terminal of inverter INV2, and the NMOS transistor M in the dual-state common-mode transient disturbance self-correction module 3. N4 The drain and PMOS transistor M P2 The drain of inverter INV3 is connected to the input of inverter INV4; inverters INV1, INV2, INV3, and INV4 are connected to the high-voltage side power supply respectively. V DDH High-voltage side of the ground V SSH connect.

[0024] Example 4 Based on Example 3, this example proposes a falling edge detection module 2 including inverters INV5, INV6, INV7, and INV8, a NAND gate NAND1, and a PMOS transistor M. P1 ; The output of inverter INV5 is connected to the input of inverter INV6 and one input of NAND gate NAND1; the output of inverter INV6 is connected to the input of inverter INV7; the output of inverter INV7 is connected to the input of inverter INV8; the output of inverter INV8 is connected to the other input of NAND gate NAND1; the output of NAND gate NAND1 is connected to PMOS transistor M. P1 Gate connection; PMOS transistor M P1 The source electrode and the high-voltage side ground V SSH connect.

[0025] Example 5 Based on Example 4, this example proposes a dual-state common-mode transient disturbance self-correction module 3, including an NLDMOS transistor L. N3 PLDMOS transistor LP3 PLDMOS transistor L P4 NMOS transistor M N3 OR gate (OR1), NOR gate (NOR1), NMOS transistor (M) N4 PMOS transistor M P2 NLDMOS transistor L N3 The gate of the NLDMOS transistor L N3 The source electrode, the low-pressure side of the ground V SSL Connection, NLDMOS transistor L N3 The drain of the PLDMOS transistor L P3 drain of PLDMOS transistor L P6 The drain connection.

[0026] Example 6 Based on Example 5, this example proposes a PLDMOS transistor L P3 The gate of the NMOS transistor M N3 The gate connection of the PLDMOS transistor L P3 The source and the high-voltage side power supply V DDH connect; PLDMOS transistor L P6 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P6 The source and NMOS transistor M N3 The drain of the OR gate is connected to the other input of the OR gate and the other input of the NOR gate. NMOS transistor M N3 The source electrode and the high-voltage side ground V SSH connect; The output of OR gate OR1 is connected to PMOS transistor M P2 The gate is connected; the output of the NOR gate NOR1 is connected to the NMOS transistor M. N4 Gate connection; PMOS transistor M P2 The source and the high-voltage side power supply V DDH Connection; NMOS transistor M N4 The source electrode and the high-voltage side ground V SSH connect.

[0027] This invention achieves sub-nanosecond ultra-low transmission delay and balanced rise and fall edge delays while possessing extremely strong common-mode transient noise suppression capabilities, effectively improving the circuit's CMTI (Common Mode Transient Noise) performance. Voltage domain conversion module 1 receives low-voltage input signals. V INIt completes the cross-domain level conversion from the low-voltage domain to the high-voltage floating domain and outputs the internal node signal. V N , V NM This module employs a symmetrical structure. The logic signal circuits in the high-voltage region all utilize MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), while LDMOS is used to connect signals between the high-voltage and low-voltage regions. When the input signal changes from high to low, it passes through an NLDMOS transistor. N2 PLDMOS transistor L P5 Inverters INV3 and INV4, PLDMOS transistor L P1 PLDMOS transistor L P4 The output signal is only obtained from the inverter INV1. V OUT The fall delay is more than 10 times higher than the rise delay. A fall edge detection module 2 is added for real-time identification. V NM The signal transitions on the falling edge and immediately outputs a brief low-level control signal. V O Early drive of PMOS transistor M P1 For internal nodes V N After charging is completed, the falling edge transmission time is significantly reduced, ensuring that both rising and falling edge delays remain in the sub-nanosecond range, achieving high matching between rising and falling edge delays; the dual-state common-mode transient disturbance self-correction module 3 synchronously acquires the input constant low copy noise signal. V 1. Output of voltage domain conversion module V N , V N2 The node level is used to generate pull-down correction signals through NOR and OR logic operations. V S Pull-up correction signal V P The two correction signals pass through the NMOS transistor M. N4 and PMOS transistor M P2 Directly affects the output node V OUT The module performs potential clamping and repair for both high and low input conditions, and can withstand high-speed common-mode slewing of 250 V / ns without output false triggering. When the module is free from noise disturbance, there is no correction output, and it does not interfere with the normal signal transmission path, eliminating the need for traditional RC filter circuits to avoid additional delay and reducing static power consumption. The voltage domain conversion module output... V NThe signal is output as a final level signal after passing through inverter INV1. V OUT This completes the full cross-voltage domain drive transmission.

[0028] Voltage domain conversion module 1 is used to convert low-voltage input signals V IN Converted to the internal node level of the high-voltage floating domain V N , V NM Voltage domain conversion module 1 receives input signals. V IN With low-voltage power supply V DDL Control of high voltage NLDMOS transistor L N1 L N2 The switching on and off of the signal converts the low-voltage signal into a high-voltage branch current signal, and then sends both current signals to the high-voltage PLDMOS branch to complete potential restoration. When the input signal... V IN When it is high, L N1 On, L N2 Shutdown, node V N It was quickly pulled down to a low potential. V NM After passing through PLDMOS transistor L P2 Pull up to high potential; when input signal V IN When L is low N1 Shutdown, L N2 Conductivity, node V NM It was quickly pulled down to a low potential. V NM After passing through PLDMOS transistor L P1 Pull-up to high potential completes the cross-voltage domain signal transmission from the low-voltage control domain to the high-voltage floating domain; the high-voltage LDMOS inside the module can withstand the voltage difference between the high and low voltage domains to achieve isolation, and simultaneously outputs two internal nodes. V N , V NM These are respectively supplied to the falling edge detection branch and the dual-mode common-mode transient disturbance self-correction module, providing a basic path for the circuit to achieve sub-nanosecond transmission delay.

[0029] Falling edge detection module 2 is used to identify the output of voltage domain conversion module 1 in real time. V NM The signal transitions on the falling edge, outputting a brief low-level control signal. V O Early drive of PMOS transistor M P1For internal nodes V N Charge the device and accelerate the output of a low-level signal. V OUT This balances the rise and fall edge delay of the circuit; when the input signal... V IN When switching from high level to low level, V NM A falling edge is generated by a rapid pull-down, and the falling edge detection module 2 immediately generates a control signal. V O Turn on PMOS transistor M P1 ,for V N It provides a fast charging path, significantly compresses the falling edge transmission time of the circuit, and keeps the rising and falling edge delays in the sub-nanosecond range, achieving high matching of rising and falling edge delays and outputting a stable and symmetrical level signal.

[0030] The dual-state common-mode transient disturbance self-correction module 3 is used to suppress output false triggering caused by high-speed dV / dt common-mode slewing noise, improving the circuit's CMTI performance. Common-mode noise is transmitted via... V SSH When coupled to the internal circuit, the internal nodes are affected by the parasitic capacitance of the LDMOS device. V N , V NM The potential may experience abnormal jumps, which in turn will cause the output to... V OUT Incorrectly flipped. When input... V IN When =0, the high-voltage NLDMOS transistor L N1 Shutdown, L N2 On, steady state V N High level V NM It is low level; if V SSH With a rapid rise rate of +250 V / ns, the displacement current generated by noise will push the high potential... V N Simultaneous pull-down, ultimately causing V OUT The output was a short-term high level; V SSH When decreasing at a rate of -250V / ns, V N It can stably maintain a high potential, and negative dV / dt noise will not affect... V IN The operating conditions caused a false trigger. When input... V IN When =1, the high-voltage NLDMOS transistor LN1 On, L N2 Shutdown, steady state V N Low level V NM High level; if V SSH With a rapid rise of +250V / ns, the noise displacement current will be pulled down. V NM On the one hand, the high-voltage NLDPMOS transistor L is briefly turned on. P3 Raise V N ,on the other hand V NM The falling edge will be captured by the falling edge detection module 2, and the module will output a short-time low-level control signal. V O Further for V N Fast charging, with dual benefits V N Abnormal rise, causing V OUT The output is a short-term low level; and V SSH When the voltage drops at a rate of -250V / ns, the conducting L N1 Continue V N Clamped to a low potential, negative dV / dt noise will not affect V IN =1 The working condition was falsely triggered.

[0031] The dual-mode common-mode transient disturbance self-calibration module 3 copies one constant low-level reference noise signal. V 1. The bidirectional potential correction logic is completed in two paths: one path converts the reference signal into a bidirectional potential correction logic. V 1 and internal nodes of the circuit V N Perform NOR operations to generate only when V IN =0, a short-duration high-level correction pulse that is effective when common-mode noise occurs. V S , V S Drive pull-down NMOS transistor M N4 Output that falsely boosts noise V OUT Quickly clamp and pull low; another path will pull the reference signal. V 1 and internal nodes V N2 Perform OR or logical operations to generate only when V IN=1. A short-duration low-level correction pulse that is effectively present when common-mode noise occurs. V P , V 1. Drive pull-up PMOS transistor M P2 The output that was mistakenly pulled down by noise V OUT Rapid clamping and pull-up. Correction pulse when there is no common-mode noise disturbance. V S , V P Both are ineffective, the upper and lower correction transistors remain off, the branch will not interfere with normal signal transmission, and the output can be flipped without error under the 250 V / ns common mode slew condition without RC filtering, which greatly enhances the circuit's ability to resist common mode transient interference without introducing additional transmission delay.

Claims

1. A sub-nanosecond level shift circuit with equal rising and falling edge delays, characterized in that, It includes a voltage domain conversion module (1), which is connected to a falling edge detection module (2) and a dual-state common-mode transient disturbance self-correction module (3); The voltage domain conversion module (1) converts the circuit input signal into an internal node signal. The falling edge detection module (2) identifies the falling edge transition of the internal node signal and outputs a control signal to enable the internal node in the voltage domain conversion module (1) to complete charging. The dual-state common-mode transient disturbance self-correction module (3) processes the noise signal and the internal node signal of the voltage domain conversion module (1) to obtain the circuit output signal.

2. The sub-nanosecond level shift circuit with equalized rising and falling edge delays according to claim 1, characterized in that, The voltage domain conversion module (1) includes an NLDMOS transistor L N1 NLDMOS transistor L N2 and PLDMOS transistor L P1 PLDMOS transistor L P2 PLDMOS transistor L P4 PLDMOS transistor L P5 and NMOS transistor M N1 NMOS transistor M N2 Inverter INV1, inverter INV2, inverter INV3, inverter INV4; NLDMOS transistor L N1 gate and input signal V IN and NLDMOS transistor L N2 The source connection of the NLDMOS transistor L N1 The source electrode and the low-pressure side of the ground V SSL Connection, NLDMOS transistor L N1 The drain of the PLDMOS transistor L P1 The drain and PLDMOS transistor L P4 Drain connection; NLDMOS transistor L N2 Gate and low-voltage side power supply V DDL Connection, NLDMOS transistor L N2 The drain of the PLDMOS transistor L P2 The drain and PLDMOS transistor L P5 The drain connection.

3. The sub-nanosecond level shift circuit with equalized rising and falling edge delays according to claim 2, characterized in that, The PLDMOS transistor L P1 The gate of the NMOS transistor M N1 The gate of the PLDMOS transistor is connected to the output of the inverter INV4. P1 The source and the high-voltage side power supply V DDH Connection; PLDMOS transistor L P2 The gate of the NMOS transistor M N2 The gate of the PLDMOS transistor is connected to the output of the inverter INV2 and one input of the OR gate OR1 in the dual-state common-mode transient disturbance self-correction module (3). P2 The source and the high-voltage side power supply V DDH connect.

4. The sub-nanosecond level shift circuit with equalized rising and falling edge delays according to claim 3, characterized in that, The PLDMOS transistor L P4 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P4 The source and NMOS transistor M N1 The drain of the inverter INV1, the input of the inverter, and the PMOS transistor M in the falling edge detection module (2) P1 The drain of the two-state common-mode transient disturbance self-correction module (3) is connected to one input terminal of the NOR gate NOR1; PLDMOS transistor L P5 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P5 The source and NMOS transistor M N2 The drain of the NMOS transistor is connected to the input of inverter INV3 and the input of inverter INV5 in the falling edge detection module (2); NMOS transistor M N1 The source electrode and the high-voltage side ground V SSH Connection; NMOS transistor M N2 The source electrode and the high-voltage side ground V SSH connect.

5. The sub-nanosecond level shift circuit with equalized rising and falling edge delays according to claim 4, characterized in that, The output terminal of inverter INV1 and the input terminal of inverter INV2, and the NMOS transistor M in the dual-mode common-mode transient disturbance self-correction module (3) N4 The drain and PMOS transistor M P2 The drain of inverter INV3 is connected to the input of inverter INV4; inverters INV1, INV2, INV3, and INV4 are connected to the high-voltage side power supply respectively. V DDH High-voltage side of the ground V SSH connect.

6. The sub-nanosecond level shift circuit with equalized rising and falling edge delays according to claim 5, characterized in that, The falling edge detection module (2) includes inverters INV5, INV6, INV7, and INV8, a NAND gate NAND1, and a PMOS transistor M. P1 ; The output of inverter INV5 is connected to the input of inverter INV6 and one input of NAND gate NAND1; the output of inverter INV6 is connected to the input of inverter INV7; the output of inverter INV7 is connected to the input of inverter INV8; the output of inverter INV8 is connected to the other input of NAND gate NAND1; the output of NAND gate NAND1 is connected to PMOS transistor M. P1 Gate connection; PMOS transistor M P1 The source electrode and the high-voltage side ground V SSH connect.

7. The sub-nanosecond level shift circuit with equalized rising and falling edge delays according to claim 6, characterized in that, The dual-state common-mode transient disturbance self-correction module (3) includes an NLDMOS transistor L N3 PLDMOS transistor L P3 PLDMOS transistor L P4 NMOS transistor M N3 OR gate (OR1), NOR gate (NOR1), NMOS transistor (M) N4 PMOS transistor M P2 ; NLDMOS transistor L N3 The gate of the NLDMOS transistor L N3 The source electrode, the low-pressure side of the ground V SSL Connection, NLDMOS transistor L N3 The drain of the PLDMOS transistor L P3 drain of PLDMOS transistor L P6 Drain connection; PLDMOS transistor L P3 The gate of the NMOS transistor M N3 The gate connection of the PLDMOS transistor L P3 The source and the high-voltage side power supply V DDH connect.

8. The sub-nanosecond level shift circuit with equalized rising and falling edge delays according to claim 7, characterized in that, The PLDMOS transistor L P6 The gate and the ground on the high voltage side V SSH Connection, PLDMOS transistor L P6 The source and NMOS transistor M N3 The drain of the NMOS transistor is connected to the other input of the OR gate (OR1) and the other input of the NOR gate (NOR1); NMOS transistor M N3 The source electrode and the high-voltage side ground V SSH connect.

9. The sub-nanosecond level shift circuit with equalized rising and falling edge delays according to claim 8, characterized in that, The output of OR gate OR1 is connected to PMOS transistor M P2 The gate is connected; the output of the NOR gate NOR1 is connected to the NMOS transistor M. N4 Gate connection; PMOS transistor M P2 The source and the high-voltage side power supply V DDH Connection; NMOS transistor M N4 The source electrode and the high-voltage side ground V SSH connect.

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