A logic control circuit based on a comparator and a NAND gate

Abstract

The present application relates to the technical field of electronic circuit and power drive, and particularly relates to a logic control circuit based on a comparator and an NAND gate, which comprises a voltage comparison circuit and an NAND logic operation circuit; the voltage comparison circuit adopts a double-comparator double-threshold independent discrimination architecture, and performs real-time differential comparison between an analog working condition signal collected in a front end and a reference voltage, so as to realize over-limit discrimination of the working condition signal; the NAND logic operation circuit realizes multi-path signal interlocking judgment and level inversion based on a hardware NAND gate, and outputs a driving signal to control turn-on and turn-off of a subsequent MOS tube, and then realizes on-off control of a conversion circuit. The present application realizes control by pure hardware logic, does not need software participation, has fast response speed and strong anti-electromagnetic interference capability, can effectively avoid false triggering through multi-path signal and logic interlocking, and has strong load driving capability, and is suitable for reliable control of high-power devices in scenes such as low-altitude intelligent aerial vehicles.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits and power drive technology, specifically a logic control circuit based on comparators and NAND gates. Background Technology

[0002] Low-altitude intelligent aircraft will be widely used in key areas such as land surveying, meteorological observation, and power line inspection in the future. The reliability of its core high-power devices is a prerequisite for achieving long-endurance and high-precision operations. Currently, the switching control of high-power devices mainly falls into two categories of technical solutions: The first type is a MOSFET driver circuit based on a single comparator, which is a purely hardware control circuit for voltage comparison threshold judgment: when the monitored voltage is lower than the threshold voltage, a high level is output to drive the MOSFET to conduct; when the monitored voltage is higher than the threshold voltage, a low level is output and the MOSFET is turned off. This type of solution has a simple structure, but only supports single threshold monitoring, has a single logic form, and lacks hysteresis and anti-interference design. External electromagnetic interference can easily cause output level jitter, resulting in false flips, low judgment accuracy, inability to achieve interlocking protection for multiple operating conditions, and the signal is prone to coupling crosstalk.

[0003] The second type is a software control scheme based on programmable devices such as microcontrollers and DSPs. It can realize complex logic judgment and multi-parameter monitoring, but it relies on software program operation, has inherent delay in response speed, and is prone to program crashes and logic errors in strong electromagnetic interference environments. It has poor anti-electromagnetic interference capability and its reliability is difficult to meet the stringent working conditions of aviation. Summary of the Invention

[0004] To address the problems in the prior art, this invention provides a logic control circuit based on comparators and NAND gates, which solves the technical defects of existing comparator circuits, such as simple logic form, easy signal coupling and crosstalk, and only support for single threshold monitoring; at the same time, it overcomes the problems of traditional programmable control circuits, such as reliance on software, slow response, and poor electromagnetic interference resistance.

[0005] The technical solution adopted by the present invention to solve its technical problem is: a logic control circuit based on comparators and NAND gates, including a voltage comparison circuit and a NAND logic operation circuit; The voltage comparison circuit is used to perform real-time differential comparison between the analog operating condition signal acquired by the front end and the reference voltage, and output two independent level discrimination signals to realize dual threshold over-limit discrimination of the operating condition signal. The input terminal of the NAND logic operation circuit is connected to the two level discrimination signals, which are used to realize multi-channel signal interlocking judgment and level flipping through hardware NAND logic, and output drive signals to control the turn-on and turn-off of subsequent MOS transistors, thereby realizing the control of the switching circuit to turn on and off.

[0006] Specifically, the voltage comparison circuit includes a comparator U1, a Zener diode V1, resistors R2, R4, R5, R6, R7, R8, R9, R10, capacitor C2, and capacitor C3. The comparator U1 is an integrated dual-channel voltage comparator, comprising a first comparison unit and a second comparison unit; the first output pin of the comparator U1 is connected to resistors R2, R4, and R5; the first non-inverting input pin of the comparator U1 is connected to resistor R5, capacitor C2, and capacitor C3; the first inverting input pin of the comparator U1 is connected to resistor R2, capacitor C2, and resistor R6; and the second inverting input pin of the comparator U1 is connected to resistors R9 and R10. The cathode of the Zener diode V1 is connected to resistors R4, R7, and R9, and the anode is connected to ground GND. One end of resistor R2 is connected to resistors R4 and R5, and the other end is connected to resistor R6; one end of resistor R4 is connected to resistor R5, and the other end is connected to resistors R7 and R9; one end of resistor R5 is connected to capacitors C2 and C3, and the other end is the analog operating condition signal input terminal; One end of resistor R6 is connected to capacitor C2, and the other end is connected to capacitor C3, resistor R7, and resistor R8; one end of resistor R7 is connected to resistor R9, and the other end is connected to capacitor C3 and resistor R8; one end of resistor R8 is connected to capacitor C3, and the other end is connected to ground GND. One end of resistor R9 is connected to resistor R10, and the other end of resistor R10 is connected to ground (GND); capacitor C2 and capacitor C3 are connected in series and then grounded.

[0007] Specifically, the NAND logic circuit includes a NAND gate U2, a capacitor C1, a resistor R3, and a resistor R11; The NAND gate U2 is a digital logic chip integrating four sets of 2-input NAND gates; the first input pin of the NAND gate U2 is connected to the first discrimination signal of the voltage comparison circuit, the second input pin is connected to the capacitor C1 and the resistor R3 and connected to the second discrimination signal of the voltage comparison circuit; the first output pin of the NAND gate U2 is connected to the input pin of the second-stage NAND gate. The ground pin of NAND gate U2 is connected to ground GND, and the power supply pin is connected to power supply VCC; the final output pin of NAND gate U2 is connected to resistor R11, and the other end of resistor R11 is the drive signal output terminal, which is used to connect to the gate of an external MOSFET.

[0008] Specifically, it also includes resistor R1, one end of which is connected to power supply VCC, and the other end is connected to Zener diode V1, resistor R3, resistor R4, resistor R7, and resistor R9, which are used to provide current-limiting power supply for voltage comparison circuit and NAND logic operation circuit.

[0009] Specifically, it also includes a conversion circuit and a MOSFET Q1. One end of the conversion circuit is connected to the power supply VCC, and the other end is connected to the drain of the MOSFET Q1. The gate of the MOSFET Q1 is connected to the resistor R11, and the source is connected to the sampling resistor R12.

[0010] Specifically, one end of resistor R12 is connected to the source of MOSFET Q1, and the other end is connected to ground GND; resistor R12 is a current sampling resistor with a resistance range of 0.15Ω~0.22Ω.

[0011] Specifically, at least two sets of NAND gates in NAND gate U2 are short-circuited to form an inverter, and multiple sets of inverters are connected in parallel to output, which is used to improve the driving current capability.

[0012] Specifically, Zener diode V1, resistors R2, R4, R6, R7, and R8 together determine the threshold voltage and hysteresis range of the first comparator; Zener diode V1, resistors R9 and R10 together determine the threshold voltage of the second comparator.

[0013] The beneficial effects of this invention are: It is implemented with pure hardware logic, without the need for software programs. Compared with programmable control circuits, it has a faster response speed and stronger resistance to electromagnetic interference. At the same time, it saves on the cost of control devices and software development, resulting in a lower overall cost.

[0014] It completes the AND logic interlocking control of multiple signals. Only when all inputs meet the conditions can the output allow the MOSFET to be turned on or off, ensuring that subsequent execution actions are reliable and not triggered erroneously. It realizes the hardware logic closed-loop control of the equipment to ensure safety and stability, and is especially suitable for scenarios with extremely high reliability requirements such as aviation.

[0015] By using NOT logic to achieve level flipping and drive adaptation, the output level is made more suitable for driving MOSFETs; combined with a multi-gate parallel output structure, the circuit's load-carrying capacity and driving capability can be significantly improved; at the same time, with the hysteresis and filtering design at the comparator end, the problems of easy jitter and poor anti-interference in traditional comparator circuits are effectively solved. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] Figure 1 This is a schematic diagram illustrating the overall principle of the logic control circuit based on comparators and NAND gates described in this invention. Detailed Implementation

[0018] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0019] like Figure 1 As shown, the logic control circuit based on comparators and NAND gates of this invention includes a voltage comparison circuit and a NAND logic operation circuit. The voltage comparison circuit performs real-time differential comparison between the analog operating condition signal acquired from the front end and the reference voltage to realize the over-limit judgment of the operating condition signal; the NAND logic operation circuit is used to realize hardware logic judgment and level flipping, control the turn-on and turn-off of the subsequent MOSFETs, and thus realize the control of the switching circuit to turn on and off. The voltage comparison circuit adopts a dual comparator dual threshold independent judgment architecture, including two independent comparison channels, which can judge the upper and lower thresholds of two different operating condition signals or the same signal respectively, and output two level judgment signals. The voltage comparison circuit has a built-in hysteresis comparison structure and RC filter network, which has both channel anti-interference and signal shaping functions, and can effectively suppress level jitter and high-frequency coupling crosstalk. The NAND logic circuit is implemented based on an integrated NAND gate chip. Two discrimination signals are connected to the NAND gate inputs to achieve AND logic interlocking. The output is only allowed to turn on the MOSFET when all input signals meet the normal operating conditions; if any signal exceeds the limit, the output immediately flips to turn off the MOSFET, realizing a hardware safety closed loop. The NAND logic circuit improves the output current sinking and pulling capability through the parallel connection of gate circuits, adapting to the driving requirements of high-power MOSFETs and enhancing the circuit's load-carrying capacity.

[0020] Example 1:

[0021] It mainly consists of three parts: voltage comparison circuit, NAND logic operation circuit, power drive and sampling unit.

[0022] Voltage comparator circuit: The voltage comparison circuit includes comparator U1, Zener diode V1, resistors R2, R4, R5, R6, R7, R8, R9, R10, capacitor C2, and capacitor C3.

[0023] In this embodiment, comparator U1 is a dual-channel integrated open-drain output voltage comparator chip, including a first comparator unit U1A and a second comparator unit U1B, which features fast response speed and strong anti-interference capability. Zener diode V1 is a precision reference Zener diode used to provide a stable reference voltage source.

[0024] The specific connection relationships are as follows: The first output pin (U1A output terminal) of comparator U1 is connected to one end of resistor R2, one end of resistor R4, and one end of resistor R5. Resistor R2 is a positive feedback hysteresis resistor, and its other end is connected to the inverting input terminal of the first comparator unit, forming a hysteresis comparator structure, which can eliminate the output error caused by input signal jitter and improve anti-interference capability.

[0025] The first non-inverting input pin (U1A non-inverting terminal) of comparator U1 is connected to the other end of resistor R5, one end of capacitor C2, and one end of capacitor C3. Resistor R5 is the input current limiting resistor, and the external analog operating condition signal is connected to this pin through resistor R5. Capacitor C2 and capacitor C3 form a two-stage RC filter network to perform high-frequency filtering on the input signal, suppress coupling crosstalk, and realize signal shaping.

[0026] The first inverting input pin (U1A inverting terminal) of comparator U1 is connected to the other end of resistor R2, the other end of capacitor C2, and one end of resistor R6; this pin is connected to the first reference threshold voltage.

[0027] The second inverting input pin (U1B inverting terminal) of comparator U1 is connected to one end of resistor R9 and one end of resistor R10; this pin is connected to the second reference threshold voltage; the non-inverting input terminal of the second comparison unit is connected to the second analog operating condition signal, and the output terminal is connected to the second input terminal of the AND-NOT logic operation circuit.

[0028] The cathode of Zener diode V1 is connected to the other end of resistor R4, one end of resistor R7, and the other end of resistor R9, while the anode is connected to ground GND. Resistor R4 is the pull-up resistor for the open-drain output of the comparator and also provides the operating current for Zener diode V1.

[0029] The other end of resistor R6 is connected to the other end of capacitor C3, the other end of resistor R7, and one end of resistor R8. Resistors R7 and R8 are connected in series to form the first voltage divider branch, which divides the reference voltage of Zener diode V1 to obtain the first threshold voltage, which is then connected to the inverting input terminal of the first comparator unit via resistor R6.

[0030] The other end of resistor R8 is connected to ground (GND); the other end of resistor R10 is connected to ground (GND); resistors R9 and R10 are connected in series to form the second voltage divider branch, which divides the reference voltage to obtain the second threshold voltage, which is then connected to the inverting input of the second comparator unit.

[0031] With the above structure, the Zener diode V1, resistors R2, R4, R6, R7 and R8 together determine the threshold voltage and hysteresis range of the first comparison unit; the Zener diode V1, resistors R9 and R10 together determine the threshold voltage of the second comparison unit, realizing independent dual threshold discrimination.

[0032] NAND logic circuit: The NAND logic circuit includes NAND gate U2, capacitor C1, resistor R3, and resistor R11.

[0033] In this embodiment, NAND gate U2 is a CMOS process four-group 2-input NAND gate integrated chip, which has the characteristics of wide voltage operating range and strong driving capability.

[0034] The specific connection relationships are as follows: The first set of NAND gates in NAND gate U2 includes two input pins and one output pin: the first input pin is connected to the output signal of the first comparison unit of the voltage comparator circuit, and the second input pin is connected to one end of resistor R3 and one end of capacitor C1, and is connected to the output signal of the second comparison unit of the voltage comparator circuit; resistor R3 and capacitor C1 form an input RC debouncing network to further filter out interference glitches in the input signal.

[0035] The output pins of the first NAND gate are connected to the input pins of the second NAND gate; the two input pins of the second NAND gate are shorted to form an inverter structure, realizing the level flipping function, so that the output level can be adapted to the driving requirements of the subsequent MOSFET.

[0036] In this embodiment, the remaining two NAND gates in the chip are also connected as inverters and connected in parallel with the second-stage inverter for output, and connected together to one end of resistor R11; the parallel connection of multiple gates can significantly improve the output sinking and pulling current capability, enhance the load-carrying capability, and meet the gate driving requirements of high-power MOSFETs.

[0037] The ground pin of NAND gate U2 is connected to ground GND, and the power supply pin is connected to power supply VCC; the other end of resistor R11 is the drive signal output terminal, which is connected to the gate of MOSFET Q1 and serves as a gate current limiting resistor to prevent excessive drive current from damaging the MOSFET.

[0038] Power drive and sampling unit: The power drive and sampling unit includes resistor R1, conversion circuit, MOSFET Q1, and resistor R12.

[0039] One end of resistor R1 is connected to the power supply VCC, and the other end is connected to the cathode of Zener diode V1, the other end of resistor R3, the other end of resistor R4, one end of resistor R7, and one end of resistor R9, providing current-limiting power to the entire control circuit and biasing current to Zener diode V1.

[0040] One end of the conversion circuit is connected to the power supply VCC, and the other end is connected to the drain of the MOSFET Q1; the conversion circuit is a high-power load circuit, such as a DC-DC conversion circuit, a motor drive circuit, etc.

[0041] The source of MOSFET Q1 is connected to one end of resistor R12; the other end of resistor R12 is connected to ground GND and serves as a current sampling resistor with a resistance range of 0.15Ω to 0.22Ω. It is used to collect the operating current of the conversion circuit, and the sampled voltage can be fed back to the input of the voltage comparison circuit to realize the overcurrent protection function.

[0042] Circuit working principle: The operation of this circuit can be divided into two states: normal operating condition and over-limit operating condition. Normal operating condition: Both analog operating condition signals are within the normal range, the outputs of both comparison units are valid high level, the first stage inputs of the NAND gate are all high level, and the output is low level; after being flipped by the second stage inverter, the output is high level, which drives the MOS transistor Q1 to conduct through resistor R11, and the conversion circuit works normally.

[0043] Over-limit operation: If any analog operating condition signal exceeds the corresponding threshold range, the output of the comparison unit of that channel will flip to a low level. When the first stage input of the NAND gate is low, the output will immediately flip to a high level. After being flipped by the second stage inverter, the output will be low. The gate of MOS transistor Q1 will lose its driving voltage and turn off. The conversion circuit will stop working, realizing overvoltage, undervoltage or overcurrent protection.

[0044] Because the entire process uses pure hardware logic operation with no software delay, the response speed can reach the nanosecond level. Furthermore, the multi-channel signal interlocking ensures that the circuit only works when all operating conditions are normal, and immediately shuts down if any one channel malfunctions, greatly improving the system reliability.

[0045] Example of specific parameters: In this embodiment, the power supply VCC uses 12V DC; the Zener diode V1 is a 5.1V precision Zener diode; the comparator U1 is an LM393 dual-channel voltage comparator; the NAND gate U2 is a 74HC00 quad 2-input NAND gate; the MOSFET Q1 is an N-channel enhancement-mode power MOSFET with a withstand voltage of 60V and an on-resistance ≤20mΩ; resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are 10kΩ, R11, R12, and R12 are 0.2Ω; capacitors C1, C2, and C3 are 100nF. Those skilled in the art can adjust the component parameters according to actual operating conditions to achieve different threshold values ​​and drive capabilities.

[0046] Example 2:

[0047] As an alternative to the present invention, a single comparator and single threshold logic control circuit can be used, which is suitable for scenarios with low reliability requirements and only single-channel operating condition monitoring. The core architecture of this solution is consistent with the present invention, except that one comparison channel is removed, while retaining the basic logic structure of a single comparator and NAND gates, which can reduce circuit complexity and material costs.

[0048] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A logic control circuit based on comparators and NAND gates, characterized in that, This includes voltage comparison circuits and NAND logic operation circuits; The voltage comparison circuit is used to perform real-time differential comparison between the analog operating condition signal acquired by the front end and the reference voltage, and output two independent level discrimination signals to realize dual threshold over-limit discrimination of the operating condition signal. The input terminal of the NAND logic operation circuit is connected to the two level discrimination signals, which are used to realize multi-channel signal interlocking judgment and level flipping through hardware NAND logic, and output drive signals to control the turn-on and turn-off of subsequent MOS transistors, thereby realizing the control of the switching circuit to turn on and off.

2. The logic control circuit based on comparators and NAND gates according to claim 1, characterized in that: The voltage comparison circuit includes comparator U1, Zener diode V1, resistors R2, R4, R5, R6, R7, R8, R9, R10, capacitor C2, and capacitor C3. The comparator U1 is an integrated dual-channel voltage comparator, comprising a first comparison unit and a second comparison unit; the first output pin of the comparator U1 is connected to resistors R2, R4, and R5; the first non-inverting input pin of the comparator U1 is connected to resistor R5, capacitor C2, and capacitor C3; the first inverting input pin of the comparator U1 is connected to resistor R2, capacitor C2, and resistor R6; and the second inverting input pin of the comparator U1 is connected to resistors R9 and R10. The cathode of the Zener diode V1 is connected to resistors R4, R7, and R9, and the anode is connected to ground GND. One end of resistor R2 is connected to resistors R4 and R5, and the other end is connected to resistor R6; one end of resistor R4 is connected to resistor R5, and the other end is connected to resistors R7 and R9; one end of resistor R5 is connected to capacitors C2 and C3, and the other end is the analog operating condition signal input terminal. One end of resistor R6 is connected to capacitor C2, and the other end is connected to capacitor C3, resistor R7, and resistor R8; one end of resistor R7 is connected to resistor R9, and the other end is connected to capacitor C3 and resistor R8; one end of resistor R8 is connected to capacitor C3, and the other end is connected to ground GND. One end of resistor R9 is connected to resistor R10, and the other end of resistor R10 is connected to ground (GND); capacitor C2 and capacitor C3 are connected in series and then grounded.

3. A logic control circuit based on comparators and NAND gates according to claim 1, characterized in that: The NAND logic operation circuit includes NAND gate U2, capacitor C1, resistor R3, and resistor R11; The NAND gate U2 is a digital logic chip that integrates four sets of 2-input NAND gates; the first input pin of the NAND gate U2 is connected to the first discrimination signal of the voltage comparison circuit, and the second input pin is connected to the capacitor C1 and the resistor R3 and connected to the second discrimination signal of the voltage comparison circuit; the first output pin of the NAND gate U2 is connected to the input pin of the second-stage NAND gate. The ground pin of NAND gate U2 is connected to ground GND, and the power supply pin is connected to power supply VCC; the final output pin of NAND gate U2 is connected to resistor R11, and the other end of resistor R11 is the drive signal output terminal, which is used to connect to the gate of an external MOSFET.

4. A logic control circuit based on comparators and NAND gates according to claim 1, characterized in that: It also includes resistor R1, one end of which is connected to power supply VCC, and the other end is connected to Zener diode V1, resistor R3, resistor R4, resistor R7, and resistor R9, which are used to provide current-limiting power to voltage comparison circuit and NAND logic operation circuit.

5. A logic control circuit based on comparators and NAND gates according to claim 1, characterized in that: It also includes a conversion circuit and a MOSFET Q1. One end of the conversion circuit is connected to the power supply VCC, and the other end is connected to the drain of the MOSFET Q1. The gate of the MOSFET Q1 is connected to the resistor R11, and the source is connected to the sampling resistor R12.

6. A logic control circuit based on comparators and NAND gates according to claim 5, characterized in that: One end of resistor R12 is connected to the source of MOSFET Q1, and the other end is connected to ground GND; resistor R12 is a current sampling resistor with a resistance range of 0.15Ω~0.22Ω.

7. A logic control circuit based on comparators and NAND gates according to claim 3, characterized in that: In NAND gate U2, at least two sets of NAND gate input terminals are shorted to form an inverter, and multiple sets of inverters are connected in parallel to output, which is used to improve the drive current capability.

8. A logic control circuit based on comparators and NAND gates according to claim 2, characterized in that: Zener diode V1, resistors R2, R4, R6, R7, and R8 together determine the threshold voltage and hysteresis range of the first comparator; Zener diode V1, resistors R9 and R10 together determine the threshold voltage of the second comparator.

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