A multi-phase clock and data lane phase-shifted multiplexed pulse generation system and method

Abstract

The application discloses a multi-phase clock and data path phase shift multiplexing pulse generation system and method, and relates to the technical field of ultrasonic nondestructive testing, medical ultrasonic imaging and time-to-digital conversion, and comprises a clock generation network, a main clock domain pre-computation scheduling module, an instruction dispatching module, a multi-phase clock capture module and an exclusive OR synthesis module.The clock generation network is used for taking an external input clock as a reference, outputting multiple static clocks which are homologous, have the same frequency and have fixed phase differences through a phase-locked loop in parallel, and keeping the multiple static clocks fixed in physical connection.In the application, the bottom multiple clock connections are fixed and unchanged, and a MUX is not used for clock switching, and the subtle shift of pulse phase is realized by dispatching control instructions to different static clock domains and utilizing exclusive OR gate synthesis.The structural characteristics of 'clock not moving and data moving' reduce the glitch hidden danger generated by asynchronous clock switching from the physical mechanism.

Description

Technical Field

[0001] This invention relates to the fields of ultrasonic non-destructive testing, medical ultrasonic imaging, and time-to-digital conversion, and particularly to a pulse generation system and method for multiphase clock and data path phase shift multiplexing. Background Technology

[0002] In high-end industrial ultrasonic flaw detection and medical phased array ultrasonic imaging systems, extremely high time resolution, such as nanosecond or picosecond, is typically required to control the delay and pulse width of the transmitted pulses in order to achieve precise beam deflection and focusing. Limited by the internal physical clock frequency limit of FPGAs, existing technologies typically employ the following solutions to achieve a resolution of 2.5ns or even higher on conventional chips, but all of them have significant limitations: For example, document CN204578517U discloses an FPGA-based pulse selectable and adjustable generator, which describes that "the circuit units involved include a crystal oscillator circuit, a PLL frequency multiplier circuit, a frequency divider circuit, a frequency modulation circuit I, a frequency modulation circuit II, a single pulse width modulation circuit, a dual pulse width modulation circuit, a multiplexer, and a pulse signal conditioning circuit. The PLL frequency multiplier circuit receives a reference clock signal from the crystal oscillator circuit. The output of the PLL frequency multiplier circuit is connected to the input of the frequency divider circuit. The output of the frequency divider circuit is connected to both the frequency modulation circuit I and the frequency modulation circuit II. The single pulse width modulation circuit receives the output signal of the frequency modulation circuit I. The dual pulse width modulation circuit receives the output signal of the frequency modulation circuit II. The outputs of both the single and dual pulse width modulation circuits are connected to the input of the multiplexer. The output of the multiplexer is connected to the input of the pulse signal conditioning circuit." This device can simultaneously generate single and dual pulse signals with adjustable frequency and pulse width.

[0003] The above technical solution mainly uses an internal phase-locked loop (PLL) to multiply the system clock to an ultra-high frequency (e.g., 400MHz or even higher), and uses a high-speed counter to directly count the beats in the ultra-high frequency clock domain, thereby achieving sub-nanosecond or nanosecond level delay and pulse width control, while generating single or double pulses with adjustable frequency and pulse width.

[0004] The problems and drawbacks of this technical solution are as follows: This solution suffers from extremely difficult timing convergence and enormous dynamic power consumption. The main reason is that the ultra-high frequency global clock network is extremely sensitive to routing delays, making it very difficult to meet the setup and hold time timing requirements on conventional low-to-mid-range FPGAs; especially when expanded to multi-channel scaled arrays, such as 32 or 64 channels, the risk of system timing failure increases exponentially.

[0005] For example, document CN117437945A discloses a clock multiplexing circuit, a pulse generator, and a memory device, which states that "the clock multiplexing circuit includes a first transistor and a second transistor. The first transistor is located between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal, and operates based on the logic level of a second input terminal that receives a second input clock signal. The second transistor is located between an output terminal and a first voltage node, and operates based on the logic level of a second input terminal."

[0006] The above technical solution generates a master clock and multiple co-source phase-shifted clocks with fixed phase differences, such as 0°, 90°, 180°, and 270°. At the moment of pulse transmission, a multiplexer (MUX) dynamically switches the clock source connected to the current channel according to control parameters.

[0007] Problems and drawbacks of this technical solution: This solution has serious safety hazards and is prone to causing trigger malfunctions. The reason is that in the underlying structure of the FPGA, the asynchronous dynamic switching between clocks of different phases is very likely to generate clock "glitch". This glitch will cause severe metastability in subsequent triggers. When driving high-voltage (such as ±100V) ultrasonic transmitting chips, the data corruption caused by the glitch can cause catastrophic transmission errors, or even lead to a short circuit in the high-voltage power supply. Summary of the Invention

[0008] The purpose of this invention is to address the shortcomings of existing technologies by proposing a pulse generation system and method that utilizes phase shift multiplexing of multiphase clock and data paths.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: A pulse generation system for multiphase clock and data path phase shift multiplexing includes a clock generation network, a master clock domain pre-calculation scheduling module, an instruction dispatch module, a multiphase clock capture module, and an XOR synthesis module. The clock generation network is used to output multiple static clocks with the same source, frequency, and fixed phase difference in parallel through a phase-locked loop, based on an external input clock. The multiple static clocks are physically connected and no multiplexing switching of clock sources is performed during operation. The master clock domain pre-calculation scheduling module is used to receive externally configured delay parameters and pulse width parameters, and its clock terminal is connected to one of the multiple static clocks as the master control clock. The instruction dispatch module is connected to the output of the master clock domain pre-calculation scheduling module and is configured to receive the flip request signal generated by the master clock domain according to the calculated start fine phase and end fine phase, and route it to the data line corresponding to the fine phase. The multi-phase clock capture module includes multiple parallel flip-flops; the clock input of each flip-flop is connected to a static clock of a different phase output by the clock generation network, and the data input of each flip-flop is connected to the data line corresponding to the instruction dispatch module; each flip-flop is configured to capture the flip-flop request signal of the data input and execute the flip-flop of the output state when the edge of the static clock of its respective phase arrives. The XOR synthesis module has multiple input terminals connected to the output terminals of each flip-flop in the multi-phase clock capture module, and is configured to perform XOR logic operation on the output signals of all flip-flops to generate the final pulse output signal; wherein, when any flip-flop flips over, the level of the pulse output signal changes.

[0010] Preferably, the clock generation network uses the MMCM or PLL resources inside the FPGA to output four static clocks with phases of 0°, 90°, 180° and 270° respectively. The 0° phase clock serves as the main control clock and is connected to the clock terminals of the main clock domain pre-calculation scheduling module and the instruction dispatch module; the 0°, 90°, 180°, and 270° phase clocks are respectively fixedly connected to the corresponding trigger clock terminals in the multi-phase clock capture module.

[0011] Preferably, the master clock domain pre-calculation scheduling module is configured to, under the master control clock domain, parse the delay parameters and pulse width parameters to obtain the coarse period and fine phase of the pulse start point, and calculate the coarse period and fine phase of the pulse end point based on the pulse start point and end point; Both the delay parameter and the pulse width parameter are N-bit data, where the high-order bits are the coarse-adjustment period count value and the low-order bits are the fine-adjustment phase selection value. The master clock domain pre-computation scheduling module includes a parameter calculation unit and a counting scheduling unit; The parameter calculation unit is configured to execute the following logic: Extract the coarse period start_coarse and the fine phase start_phase of the starting point; Calculate the fine phase and sum_fine = start_phase + width_phase, where width_phase is the fine phase selection value in the pulse width parameter; Determine whether a carry flag (carry_fine) is generated based on the fine phase and sum_fine. Extract the low-order part of the end fine phase end_phase as sum_fine; The end coarse period is calculated as end_coarse = start_coarse + width_coarse + carry_fine, where width_coarse is the coarse period count value in the pulse width parameter.

[0012] Preferably, the counting and scheduling unit includes two decrementing counters: a start counter cnt_start and an end counter cnt_end; The counting and scheduling unit is configured to: upon receiving a global trigger signal, load start_coarse and end_coarse into cnt_start and cnt_end respectively, and start decrementing under the main control clock; When cnt_start is detected to decrease to 0, a start point reversal request signal fire_start is generated; when cnt_end is detected to decrease to 0, an end point reversal request signal fire_end is generated. If the initial value of start_coarse or end_coarse is 0, the counting scheduling unit is configured to generate the corresponding toggle request signal immediately in the next master control clock cycle after loading.

[0013] Preferably, the instruction dispatch module includes a multiplexer register, the number of which is the same as the number of triggers in the multiphase clock capture module; The instruction dispatch module is configured to: under the drive of the main control clock, write the logical value of the fire_start signal to the target register addressed by the value of start_phase, and write the logical value of the fire_end signal to the target register addressed by the value of end_phase; The outputs of the multiplexer are respectively connected to the data inputs of the corresponding flip-flops in the multiphase clock capture module.

[0014] Preferably, the flip-flops in the multiphase clock capture module are T-type flip-flops; The T-type flip-flop is configured such that when the clock input detects the rising edge of the corresponding phase of the static clock, if the data input receives a valid toggle request signal, the state of the output is toggled; otherwise, the state of the output remains unchanged.

[0015] Preferably, the multiphase clock capture module consists of four T-type flip-flops, namely a first flip-flop, a second flip-flop, a third flip-flop, and a fourth flip-flop; The clock input of the first flip-flop is connected to the 0° clock, the clock input of the second flip-flop is connected to the 90° clock, the clock input of the third flip-flop is connected to the 180° clock, and the clock input of the fourth flip-flop is connected to the 270° clock. The XOR synthesis module is a 4-input XOR gate, and its logical expression is: pulse_out=Q0^Q90^Q180^Q270, where Q0, Q90, Q180, and Q270 are the output signals of the four flip-flops, respectively.

[0016] A pulse generation method for multiphase clock and data path phase shift multiplexing includes the following steps: Step S1: Generate multiple static clocks with fixed phase shifts, and select one of them as the master control clock; Step S2: Under the main control clock domain, analyze the input delay parameters and pulse width parameters, calculate the coarse period and fine phase of the pulse start point, and calculate the coarse period and fine phase of the pulse end point based on the start point parameters and pulse width parameters through addition with carry. Step S3: Perform decrementing counting scheduling based on the calculated starting coarse period and ending coarse period. When the counter returns to zero, generate the corresponding starting flip request signal and ending flip request signal respectively. Step S4: Based on the fine phase parameter, route the start-point flip-up request signal and the end-point flip-up request signal to the data input terminal of the target trigger corresponding to the fine phase; Step S5: Each target flip-flop captures a signal at the static clock edge of its corresponding phase. If a valid toggle request signal is captured, the output state is toggled. Step S6: Perform XOR logic synthesis on the output states of all flip-flops, generate the rising and falling edges of the pulse according to the flip-flop flip-flop time, and output a high-precision pulse.

[0017] Preferably, the calculation of the coarse period and fine phase of the pulse endpoint in step S2 specifically includes: Calculate the fine phase and sum_fine: sum_fine = Delay_CH[1:0] + Width_CH[1:0]; Extract the carry flag carry_fine: retrieve the overflow bit of sum_fine; Extract the end fine phase (end_phase): Take the low-order part of sum_fine; Calculate the end coarse period end_coarse: end_coarse = Delay_CH[15:2] + Width_CH[15:2] + carry_fine; Where Delay_CH is the delay parameter and Width_CH is the pulse width parameter, the high-order part represents the coarse period and the low-order part represents the fine phase.

[0018] Preferably, the XOR logic synthesis in step S6 further includes a step of handling timing conflicts: If the start-of-pulse toggle request and the end-of-pulse toggle request are assigned to the same flip-flop, and the flip-flop captures two toggle requests consecutively within the same clock cycle, the output state of the flip-flop will toggle twice. Through XOR logic operation, the effects of the output change of the flip-flop on the final pulse output signal will cancel each other out, ensuring the accuracy of the pulse width.

[0019] The beneficial effects of this invention are as follows: 1. In this invention, the underlying multi-channel clock connection remains fixed and no MUX is used for clock switching. The slight offset of the pulse phase is achieved by dispatching control commands to different static clock domains and synthesizing them using XOR gates. This "clock remains stationary while data moves" structural feature reduces the risk of glitches caused by asynchronous clock switching from a physical mechanism perspective.

[0020] 2. This invention reduces the timing convergence difficulty of multi-channel expansion. This invention only requires a 100MHz global master clock to achieve a control accuracy of 2.5ns, avoiding the 400MHz ultra-high frequency clock required by the direct counting method. Due to the significant reduction in clock frequency, the setup time margin of the combinational logic inside the FPGA is sufficient. When performing large-scale array expansion, the system can achieve compilation and timing closure, and the development cycle and power consumption are greatly reduced.

[0021] 3. In this invention, thanks to the XOR synthesis mechanism at the end, the system can perfectly solve the timing collision problem of start and end events. Experimental data proves that in zero-cycle limit tests and cross-cycle carry tests, the system can automatically handle fine-phase carry, the measured total pulse timing is accurate, and no clock loss or jitter occurs when crossing clock boundaries. Attached Figure Description

[0022] Figure 1 This is a block diagram of the overall architecture of a pulse generation system that uses phase shift multiplexing of multiphase clock and data paths according to the present invention.

[0023] Figure 2 This is a flowchart illustrating the master clock domain pre-calculation scheduling module and instruction dispatch module of a pulse generation system for multiphase clock and data path phase shift multiplexing according to the present invention.

[0024] Figure 3 This is a schematic diagram of the underlying physical hardware connection structure of the multiphase clock capture module and the XOR synthesis module of a pulse generation system for multiphase clock and data path phase shift multiplexing according to the present invention.

[0025] Figure 4 This is a flowchart of a pulse generation method for multiphase clock and data path phase shift multiplexing according to the present invention. Detailed Implementation

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0027] Example 1, as shown in the attached document Figure 1 To be continued Figure 3 As shown: A pulse generation system for multiphase clock and data path phase shift multiplexing, including a clock generation network, a master clock domain pre-calculation scheduling module, an instruction dispatch module, a multiphase clock capture module, and an XOR synthesis module; The clock generation network is used to output multiple static clocks with the same source, frequency and fixed phase difference in parallel through a phase-locked loop, based on an external input clock. The multiple static clocks are kept physically fixed and no multiplexing switching of clock sources is performed during operation. Taking an external FPGA input of a 100MHz clock with a period of 10ns as an example, the clock generation network uses the MMCM or PLL resources inside the FPGA to output four static clocks with phases of 0°, 90°, 180° and 270° respectively. The 0° phase clock serves as the main control clock and is connected to the clock terminals of the main clock domain pre-calculation scheduling module and the instruction dispatch module; the 0°, 90°, 180° and 270° phase clocks are respectively fixedly connected to the corresponding trigger clock terminals in the multi-phase clock capture module.

[0028] The master clock domain pre-calculation scheduling module is used to receive externally configured delay parameters and pulse width parameters. Its clock terminal is connected to one of the multiple static clocks as the master control clock. The master clock domain pre-calculation scheduling module is configured to parse the delay parameters and pulse width parameters under the master control clock domain to obtain the coarse period and fine phase of the pulse start point, and calculate the coarse period and fine phase of the pulse end point based on the pulse start point and end point. Both the delay parameter and the pulse width parameter are N-bit data, where the high-order bits are the coarse-adjustment period count value and the low-order bits are the fine-adjustment phase selection value; The master clock domain pre-computation scheduling module includes a parameter calculation unit and a counting scheduling unit; The parameter calculation unit is configured to execute the following logic: Extract the coarse period start_coarse and the fine phase start_phase of the starting point; Calculate the fine phase and sum_fine = start_phase + width_phase, where width_phase is the fine phase selection value in the pulse width parameter; Determine whether a carry flag (carry_fine) is generated based on the fine phase and sum_fine. Extract the low-order part of the end fine phase end_phase as sum_fine; The end coarse period is calculated as end_coarse = start_coarse + width_coarse + carry_fine, where width_coarse is the coarse period count value in the pulse width parameter.

[0029] The counting and scheduling unit includes two decrementing counters: the start counter cnt_start and the end counter cnt_end; The counting scheduling unit is configured as follows: upon receiving a global trigger signal, start_coarse and end_coarse are loaded into cnt_start and cnt_end respectively, and the counting starts to decrease under the main control clock. When cnt_start is detected to decrease to 0, a start point reversal request signal fire_start is generated; when cnt_end is detected to decrease to 0, an end point reversal request signal fire_end is generated. If the initial value of start_coarse or end_coarse is 0, the counting scheduling unit is configured to generate the corresponding toggle request signal immediately in the next master control clock cycle after loading.

[0030] The instruction dispatch module is connected to the output of the master clock domain pre-calculation scheduling module. It is configured to receive the flip request signal generated by the master clock domain according to the calculated start fine phase and end fine phase, and route it to the data line corresponding to the fine phase. The instruction dispatch module includes multiplexers, and the number of multiplexers is the same as the number of flip-flops in the multiphase clock capture module; The instruction dispatch module is configured to: under the drive of the main control clock, write the logical value of the fire_start signal to the target register addressed by the value of start_phase, and write the logical value of the fire_end signal to the target register addressed by the value of end_phase; The outputs of the multiplexer are connected to the data inputs of the corresponding flip-flops in the multiphase clock capture module.

[0031] The multi-phase clock capture module includes multiple parallel flip-flops; the clock input of each flip-flop is connected to a static clock of a different phase output by the clock generation network, and the data input of each flip-flop is connected to the data line corresponding to the instruction dispatch module; each flip-flop is configured to capture the toggle request signal of the data input and execute the toggle of the output state when the static clock edge of its respective phase arrives. The flip-flops in the multiphase clock capture module are T-type flip-flops; The T-type flip-flop is configured such that when the clock input detects the rising edge of the corresponding phase of the static clock, if the data input receives a valid toggle request signal, the output state is toggled; otherwise, the output state remains unchanged. The XOR synthesis module has multiple input terminals connected to the output terminals of each flip-flop in the multiphase clock capture module. It is configured to perform XOR logic operation on the output signals of all flip-flops to generate the final pulse output signal. When any flip-flop flips over, the level of the pulse output signal changes.

[0032] The multiphase clock capture module consists of four T-type flip-flops, namely the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop; The clock input of the first flip-flop is connected to the 0° clock, the clock input of the second flip-flop is connected to the 90° clock, the clock input of the third flip-flop is connected to the 180° clock, and the clock input of the fourth flip-flop is connected to the 270° clock. The XOR synthesis module is a 4-input XOR gate, and its logical expression is: pulse_out=Q0^Q90^Q180^Q270, where Q0, Q90, Q180, and Q270 are the output signals of the four flip-flops, respectively.

[0033] Example 2, as shown in the attached document Figure 1 To be continued Figure 4 As shown: A pulse generation method for multiphase clock and data path phase shift multiplexing includes the following steps: Step S1: Generate multiple static clocks with fixed phase shifts, and select one of them as the master control clock; Step S2: Under the main control clock domain, analyze the input delay parameters and pulse width parameters, calculate the coarse period and fine phase of the pulse start point, and calculate the coarse period and fine phase of the pulse end point based on the start point parameters and pulse width parameters through addition with carry. The delay parameter Delay_CH and pulse width parameter Width_CH of the external configuration bus input are both 16-bit data. Among them, the high 14 bits [15:2] represent the coarse adjustment cycle count value, in units of 10ns, and the low 2 bits [1:0] represent the fine phase selection value, where 0 represents 0°, 1 represents 90°, 2 represents 180°, and 3 represents 270°. The master clock domain pre-computation scheduling module operates in the CLK0 (0° clock) domain and executes the following pre-computation logic: Extraction start point: start_coarse=Delay_CH[15:2], start_phase=Delay_CH[1:0].

[0034] Specifically, step S2, calculating the coarse period and fine phase at the pulse endpoint, includes: Calculate the fine phase and sum_fine: sum_fine = Delay_CH[1:0] + Width_CH[1:0]; Extract the carry flag carry_fine: retrieve the overflow bit of sum_fine; Extract the end fine phase (end_phase): Take the low-order part of sum_fine; Calculate the end coarse period end_coarse: end_coarse = Delay_CH[15:2] + Width_CH[15:2] + carry_fine; Where Delay_CH is the delay parameter and Width_CH is the pulse width parameter, the high-order part represents the coarse period and the low-order part represents the fine phase.

[0035] Step S3: Master clock domain state machine and event scheduling. Perform decrementing counting scheduling based on the calculated start coarse period and end coarse period. When the counter returns to zero, generate the corresponding start flip request signal and end flip request signal respectively. The system maintains two decrementing counters, cnt_start and cnt_end. Upon receiving a trigger signal, start_coarse and end_coarse are loaded respectively and decrementing begins. When cnt_start decrements to 0, the fire_start signal is generated; when cnt_end decrements to 0, the fire_end signal is generated; if the coarse period is 0, the corresponding signal is triggered immediately; all timing is performed within a single clock domain, completely preventing the state machine from running away.

[0036] Step S4: Cross-domain instruction dispatch. Based on the fine phase parameter, the start-point flip request signal and the end-point flip request signal are routed to the data input terminal of the target trigger corresponding to the fine phase. Use combinational logic to distribute signals based on fine phase parameters: For example, if start_phase=1, corresponding to 90°, then the register tog_req_90 will be set to 1 on the rising edge of CLK0; If end_phase=3, corresponding to 270°, then the register tog_req_270 will be set to 1 on the rising edge of CLK0; At this time, all request signals are in the 0° reference master clock domain, and there is no metastability.

[0037] Step S5: Four-phase clock capture and flip-flop toggling. Each target flip-flop captures the signal at the static clock edge of its corresponding phase. If a valid toggle request signal is captured, the output state is toggled. FF90 listens to CLK90. When its rising edge arrives (lagging CLK0 rising edge by 2.5ns), if tog_req_90 is high, FF90 output toggles. The FF270 listens to CLK270. When its rising edge arrives (lagging CLK0 rising edge by 7.5ns), if tog_req_270 is high, the FF270 output will toggle.

[0038] Step S6: Hardware XOR gate synthesis. Perform XOR logic synthesis on the output states of all flip-flops, generate the rising and falling edges of the pulse according to the flip-flop flip-flop flip-flop times, and output a high-precision pulse. Specifically, in step S6, the XOR logic synthesis also includes the step of handling timing conflicts: If the start-of-pulse toggle request and the end-of-pulse toggle request are assigned to the same flip-flop, and the flip-flop captures two toggle requests consecutively within the same clock cycle, the output state of the flip-flop will toggle twice. Through XOR logic operation, the effects of the output change of the flip-flop on the final pulse output signal cancel each other out, ensuring the accuracy of the pulse width. XOR gate logic equation: pulse_out = Q0^Q90^Q180^Q270; When FF90 flips for the first time, the output changes from 0 to 1, generating a rising edge; When the FF270 subsequently flips, the output changes from 1 to 0, generating a falling edge.

[0039] It is worth mentioning that if the start and end events happen to occur in the same period and the same phase, such as a delay of 10ns and a pulse width of 10ns, the two toggle instructions are naturally canceled out by XOR logic, ensuring mathematical completeness and physical consistency of timing.

[0040] Effect verification: Actual testing showed that when the delay was set to 0ns and the pulse width to 2.5ns, the oscilloscope successfully captured the extremely narrow spike; when the delay was set to 7.5ns and the pulse width to 7.5ns, the carry was automatically processed, and a stable pulse with a total timing of 15ns was output, without any clock loss or jitter across clock boundaries.

[0041] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A pulse generation system that uses phase shift multiplexing for multiphase clock and data paths, characterized in that, It includes a clock generation network, a master clock domain pre-computation scheduling module, an instruction dispatch module, a multi-phase clock capture module, and an XOR synthesis module; The clock generation network is used to output multiple static clocks with the same source, frequency, and fixed phase difference in parallel through a phase-locked loop, based on an external input clock. The multiple static clocks are physically connected and no multiplexing switching of clock sources is performed during operation. The master clock domain pre-calculation scheduling module is used to receive externally configured delay parameters and pulse width parameters, and its clock terminal is connected to one of the multiple static clocks as the master control clock. The instruction dispatch module is connected to the output of the master clock domain pre-calculation scheduling module and is configured to receive the flip request signal generated by the master clock domain according to the calculated start fine phase and end fine phase, and route it to the data line corresponding to the fine phase. The multi-phase clock capture module includes multiple parallel flip-flops; the clock input of each flip-flop is connected to a static clock of a different phase output by the clock generation network, and the data input of each flip-flop is connected to the data line corresponding to the instruction dispatch module; each flip-flop is configured to capture the flip-flop request signal of the data input and execute the flip-flop of the output state when the edge of the static clock of its respective phase arrives. The XOR synthesis module has multiple input terminals connected to the output terminals of each flip-flop in the multi-phase clock capture module, and is configured to perform XOR logic operation on the output signals of all flip-flops to generate the final pulse output signal; wherein, when any flip-flop flips over, the level of the pulse output signal changes.

2. The pulse generation system for multiphase clock and data path phase shift multiplexing according to claim 1, characterized in that, The clock generation network uses the MMCM or PLL resources inside the FPGA to output four static clocks with phases of 0°, 90°, 180° and 270° respectively. The 0° phase clock serves as the main control clock and is connected to the clock terminals of the main clock domain pre-calculation scheduling module and the instruction dispatch module; the 0°, 90°, 180°, and 270° phase clocks are respectively fixedly connected to the corresponding trigger clock terminals in the multi-phase clock capture module.

3. The pulse generation system for multiphase clock and data path phase shift multiplexing according to claim 1, characterized in that, The master clock domain pre-calculation scheduling module is configured to, under the master control clock domain, parse the delay parameters and pulse width parameters to obtain the coarse period and fine phase of the pulse start point, and calculate the coarse period and fine phase of the pulse end point based on the pulse start point and end point. Both the delay parameter and the pulse width parameter are N-bit data, where the high-order bits are the coarse-adjustment period count value and the low-order bits are the fine-adjustment phase selection value. The master clock domain pre-computation scheduling module includes a parameter calculation unit and a counting scheduling unit; The parameter calculation unit is configured to execute the following logic: Extract the coarse period start_coarse and the fine phase start_phase of the starting point; Calculate the fine phase and sum_fine = start_phase + width_phase, where width_phase is the fine phase selection value in the pulse width parameter; Determine whether a carry flag (carry_fine) is generated based on the fine phase and sum_fine. Extract the low-order part of the end fine phase end_phase as sum_fine; The end coarse period is calculated as end_coarse = start_coarse + width_coarse + carry_fine, where width_coarse is the coarse period count value in the pulse width parameter.

4. The pulse generation system for multiphase clock and data path phase shift multiplexing according to claim 3, characterized in that, The counting and scheduling unit includes two decrementing counters: a start counter cnt_start and an end counter cnt_end; The counting and scheduling unit is configured to: upon receiving a global trigger signal, load start_coarse and end_coarse into cnt_start and cnt_end respectively, and start decrementing under the main control clock; When cnt_start is detected to decrease to 0, a start point reversal request signal fire_start is generated; when cnt_end is detected to decrease to 0, an end point reversal request signal fire_end is generated. If the initial value of start_coarse or end_coarse is 0, the counting scheduling unit is configured to generate the corresponding toggle request signal immediately in the next master control clock cycle after loading.

5. A pulse generation system for multiphase clock and data path phase shift multiplexing according to claim 4, characterized in that, The instruction dispatch module includes a multi-channel register, and the number of the multi-channel registers is the same as the number of flip-flops in the multi-phase clock capture module. The instruction dispatch module is configured to: under the drive of the main control clock, write the logical value of the fire_start signal to the target register addressed by the value of start_phase, and write the logical value of the fire_end signal to the target register addressed by the value of end_phase; The outputs of the multiplexer are respectively connected to the data inputs of the corresponding flip-flops in the multiphase clock capture module.

6. The pulse generation system for multiphase clock and data path phase shift multiplexing according to claim 1, characterized in that, The flip-flop in the multiphase clock capture module is a T-type flip-flop; The T-type flip-flop is configured such that when the clock input detects the rising edge of the corresponding phase of the static clock, if the data input receives a valid toggle request signal, the state of the output is toggled; otherwise, the state of the output remains unchanged.

7. A pulse generation system for multiphase clock and data path phase shift multiplexing according to claim 2, characterized in that, The multiphase clock capture module consists of four T-type flip-flops, namely the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop; The clock input of the first flip-flop is connected to the 0° clock, the clock input of the second flip-flop is connected to the 90° clock, the clock input of the third flip-flop is connected to the 180° clock, and the clock input of the fourth flip-flop is connected to the 270° clock. The XOR synthesis module is a 4-input XOR gate, and its logical expression is: pulse_out=Q0^Q90^Q180^Q270, where Q0, Q90, Q180, and Q270 are the output signals of the four flip-flops, respectively.

8. A pulse generation method for multiphase clock and data path phase shift multiplexing, the method being implemented based on the pulse generation system for multiphase clock and data path phase shift multiplexing as described in claims 1-7, characterized in that, Includes the following steps: Step S1: Generate multiple static clocks with fixed phase shifts, and select one of them as the master control clock; Step S2: Under the main control clock domain, analyze the input delay parameters and pulse width parameters, calculate the coarse period and fine phase of the pulse start point, and calculate the coarse period and fine phase of the pulse end point based on the start point parameters and pulse width parameters through addition with carry. Step S3: Perform decrementing counting scheduling based on the calculated starting coarse period and ending coarse period. When the counter returns to zero, generate the corresponding starting flip request signal and ending flip request signal respectively. Step S4: Based on the fine phase parameter, route the start-point flip-up request signal and the end-point flip-up request signal to the data input terminal of the target trigger corresponding to the fine phase; Step S5: Each target flip-flop captures a signal at the static clock edge of its corresponding phase. If a valid toggle request signal is captured, the output state is toggled. Step S6: Perform XOR logic synthesis on the output states of all flip-flops, generate the rising and falling edges of the pulse according to the flip-flop flip-flop time, and output a high-precision pulse.

9. The pulse generation method for multiphase clock and data path phase shift multiplexing according to claim 8, characterized in that, Step S2, which involves calculating the coarse period and fine phase of the pulse endpoint, specifically includes: Calculate the fine phase and sum_fine: sum_fine = Delay_CH[1:0] + Width_CH[1:0]; Extract the carry flag carry_fine: retrieve the overflow bit of sum_fine; Extract the end fine phase (end_phase): Take the low-order part of sum_fine; Calculate the end coarse period end_coarse: end_coarse = Delay_CH[15:2] + Width_CH[15:2] + carry_fine; Where Delay_CH is the delay parameter and Width_CH is the pulse width parameter, the high-order part represents the coarse period and the low-order part represents the fine phase.

10. The pulse generation method for multiphase clock and data path phase shift multiplexing according to claim 8, characterized in that, Step S6, which describes performing XOR logic synthesis, also includes a step of handling timing conflicts: If the start-of-pulse toggle request and the end-of-pulse toggle request are assigned to the same flip-flop, and the flip-flop captures two toggle requests consecutively within the same clock cycle, the output state of the flip-flop will toggle twice. Through XOR logic operation, the effects of the output change of the flip-flop on the final pulse output signal will cancel each other out, ensuring the accuracy of the pulse width.

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