Bandwidth enhanced small area low jitter phase locked loop circuit

Abstract

The application provides a bandwidth-enhanced small-area low-jitter phase-locked loop circuit, comprising: an input reference multi-phase generator, a main loop, a frequency-locked loop and a calibration loop; the input reference multi-phase generator generates eight-phase sampling clocks, eight-phase holding clocks and eight-phase Gm enabling clocks, so that the loop works at eight times the input reference frequency; the main loop controls eight Gm input tubes through time division multiplexing of the eight-phase Gm enabling clocks, expands the loop bandwidth to 0.31 times the input reference frequency, and suppresses the out-of-band noise of the ring vibration; the calibration loop calibrates the phase error of the eight-phase clock by adjusting the load capacitance of the phase interpolator. The application generates eight-phase clocks through the input reference multi-phase generator, raises the loop working frequency to eight times the original reference frequency, expands the loop bandwidth to eight times the original loop bandwidth, significantly suppresses the out-of-band noise contribution of the loop oscillator, optimizes the in-band noise performance through time division multiplexing of the Gm module, and realizes the optimal noise performance balance.

Description

Technical Field

[0001] This invention relates to the technical field of integrated circuit design, and more specifically, to a small-area, low-jitter phase-locked loop circuit with enhanced bandwidth. Background Technology

[0002] In recent years, under-sampling phase-locked loops (SSPLLs) based on ring oscillators (ring oscillators) have attracted widespread attention due to their low noise and low power consumption characteristics. However, existing technologies still have significant limitations in practical applications. For example, reference 1 [SSNagam and PRKinget, "A 0.008mm² 2.4GHz type-I sub-samplingring-oscillator-based phase-locked loop with a -239.7dB FoM and -64dB creference spurs," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018, pp. 1-4.] proposes a Type-I structure under-sampling PLL that suppresses out-of-band noise of the ring oscillator by extending the loop bandwidth. However, the inherent defects of the Type-I structure lead to a static phase error between the sampled signal and the sampled signal, causing the sampling point to deviate from the zero-crossing point, reducing the sampling gain and deteriorating the in-band noise performance. Furthermore, its loop bandwidth is susceptible to temperature and voltage fluctuations, leading to insufficient system stability. Reference 2 [YCQian, YYChao and S.I.Liu, "A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol.69, no.2, pp.269-273, Feb.2022.] uses a cascaded delay-locked loop (DLL) to filter out loop oscillation noise, but the voltage-controlled delay chain needs to operate at the PLL output frequency, resulting in a significant increase in power consumption. Reference 3 [SSNagam and PRKinget, "A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector," in IEEE Journal of Solid-State Circuits, vol.53, no.3, pp.703-714, March 2018.] suppresses ring noise through feedforward noise cancellation technology, but requires precise matching of the feedforward path gain, making the calibration process complex, and the high-frequency operation of the noise cancellation module further exacerbates the power consumption problem.

[0003] The common problems of the aforementioned existing technologies can be summarized as follows: noise degradation caused by static phase error, high power consumption design, and complex calibration requirements. Specifically, the static phase error of the Type-I structure limits the optimization of noise performance; while cascaded DLLs and feedforward noise cancellation partially improve noise suppression capabilities, they come at the cost of power consumption and system complexity. In addition, existing undersampled phase-locked loops often require large integrating capacitors in the initial locking phase due to insufficient bandwidth, resulting in increased chip area and difficulty in meeting high integration requirements.

[0004] Therefore, a new technical solution is needed to improve the above-mentioned technical problems. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a bandwidth-enhanced, small-area, low-jitter phase-locked loop circuit.

[0006] According to the present invention, a bandwidth-enhanced small-area low-jitter phase-locked loop circuit includes: an input reference multi-phase generator, a main loop, a frequency-locked loop, and a calibration loop;

[0007] The input reference multiphase generator generates an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock, enabling the loop to operate at eight times the input reference frequency.

[0008] The main loop controls eight Gm input transistors by time-division multiplexing the eight-phase Gm enable clock, expanding the loop bandwidth to 0.31 times the input reference frequency and suppressing out-of-band noise of the loop oscillation.

[0009] The calibration loop calibrates the phase error of the eight-phase clock by adjusting the load capacitance of the phase interpolator.

[0010] Preferably, the input reference multiphase generator includes:

[0011] Passive PPF: Converts the input differential reference signal into a four-phase clock;

[0012] Phase interpolator: converts the four-phase clock into an eight-phase clock;

[0013] Combinational logic: Generates an eight-phase sampling clock with uniformly distributed edges, a hold clock, and an eight-phase Gm enable clock with evenly distributed duty cycles.

[0014] Preferably, the main loop includes:

[0015] Eight-channel sample-and-hold switch: each is controlled by an eight-phase sampling clock to sample the ring oscillator output;

[0016] AC coupler: Couples the sampling results from the second to the eighth channels to the corresponding Gm input transistor;

[0017] Gm module: In time-division multiplexing mode, it converts the sampled voltage into current and controls the charging and discharging of the filter to adjust the ring frequency.

[0018] Preferably, in undersampling mode: the Gm enable clock of the first sampling path is kept at a high level, while the Gm enable clocks of the other seven paths are at a low level; all Gm input transistors are connected to the first DC sampling voltage, and new zeros and poles are introduced on the basis of the loop zeros and poles to improve the low-frequency phase margin without increasing the filter integration capacitor.

[0019] Preferably, the frequency locking loop includes:

[0020] Frequency and phase detectors with dead zones: control the charging and discharging direction of the charge pump by the difference in duty cycle;

[0021] Frequency divider: Divides the ring oscillator output frequency to the reference clock range until the phase error enters the dead zone range, then switches to undersampling mode.

[0022] Preferably, the calibration loop compares the second to eighth sampling voltages with the first DC sampling voltage; and adjusts the load capacitance of the phase interpolator according to the comparison results to make the eight-phase clock edges evenly distributed.

[0023] Preferably, in oversampling mode: the duty cycle of the eight-phase Gm enable clock is 1 / 8, and the high voltage averages the reference clock period; by increasing the Gm gain to extend the loop bandwidth to the point where the in-band noise and out-of-band noise are equal, optimal noise suppression is achieved.

[0024] Preferably, the filter comprises:

[0025] Integrating capacitor: Its area is optimized by reusing the Gm input transistor and introducing new zeros and poles, maintaining a phase margin of more than 45 degrees in undersampling mode.

[0026] Preferably, the input reference multiphase generator is used to convert the input reference clock into an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock, wherein the edges of the eight-phase clock are evenly distributed within one reference clock cycle.

[0027] The main loop includes an eight-channel sample-and-hold switch, an AC coupler, a Gm unit, a filter, and a loop oscillator. The eight-channel sample-and-hold switch samples the output signal of the loop oscillator through the eight-phase sampling clock and the hold clock. The first sample signal is directly input to the Gm unit, and the other seven sample signals are input to the Gm unit through the AC coupler. The Gm unit operates in time-division multiplexing mode under the control of the eight-phase Gm enable clock and outputs a control voltage to adjust the frequency of the loop oscillator.

[0028] The frequency-locking loop is used to lock the loop oscillator frequency to near the reference clock frequency during the initial stage of loop locking;

[0029] The calibration loop is used to calibrate the phase error of the eight-phase sampling clock, so that the edges of each sampling clock are evenly distributed.

[0030] Preferably, the passive PPF converts the input differential reference sine signal into a four-phase clock;

[0031] The phase interpolator converts the four-phase clock into an eight-phase clock;

[0032] The combinational logic processes the eight-phase clock to generate an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock with evenly distributed duty cycles.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. This invention generates an eight-phase clock by using an input reference multi-phase generator, increasing the loop operating frequency to eight times the original reference frequency and expanding the loop bandwidth to eight times the original. This design significantly suppresses the out-of-band noise contribution of the loop oscillator, and further optimizes the in-band noise performance through the time-division multiplexing Gm module, achieving the optimal balance of noise performance.

[0035] 2. In undersampling mode, this invention solves the problem of increased area caused by the need for large integrating capacitors due to low bandwidth in traditional undersampling phase-locked loops by reusing the input transistor of the Gm module and introducing new zeros and poles. The new structure maintains loop stability by dynamically adjusting the distribution of zeros and poles without increasing the filter integrating capacitor, which significantly reduces chip area and manufacturing cost.

[0036] 3. The calibration loop of this invention calibrates the phase error of the multi-phase clock in real time through a comparator, ensuring that the sampling clock edges are evenly distributed and improving the accuracy of the sampling gain. In addition, the newly added zero-pole design introduces an extra phase margin in the low-frequency band, enabling the loop to maintain a phase margin of more than 45 degrees in undersampling mode, thereby enhancing the system's robustness to temperature and voltage changes.

[0037] 4. Compared with the existing technology that uses cascaded DLLs or feedforward noise cancellation, the present invention avoids the continuous operation of high-frequency modules (such as voltage-controlled delay chains) by using the time-division multiplexing mode of Gm controlled by multi-phase clock, thereby reducing the overall power consumption, simplifying the calibration process, and improving system efficiency.

[0038] 5. This invention can be widely applied to scenarios requiring high-precision clock synthesis, such as wired / wireless communication and multi-core processors. In particular, in system chips integrating multiple phase-locked loops, its low jitter, small area, and low power consumption characteristics can significantly improve the overall system performance. Attached Figure Description

[0039] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0040] Figure 1 Diagram of the bandwidth-enhanced undersampling phase-locked loop structure;

[0041] Figure 2 The Gm structure and loop phase diagram are shown in undersampling mode.

[0042] Figure 3 This is a schematic diagram of a multi-phase generator for a reference clock path. Detailed Implementation

[0043] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0044] Example 1:

[0045] Reference Figure 1 and Figure 2 According to the present invention, a bandwidth-enhanced small-area low-jitter phase-locked loop circuit includes: an input reference multi-phase generator, a main loop, a frequency-locked loop, and a calibration loop; the input reference multi-phase generator generates an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock, enabling the loop to operate at eight times the input reference frequency; the main loop controls eight Gm input transistors by time-division multiplexing the eight-phase Gm enable clock, extending the loop bandwidth to 0.31 times the input reference frequency and suppressing out-of-band noise of the loop oscillation; the calibration loop calibrates the phase error of the eight-phase clock by adjusting the load capacitance of the phase interpolator.

[0046] The input reference multiphase generator includes: a passive PPF that converts the input differential reference signal into a four-phase clock; a phase interpolator that converts the four-phase clock into an eight-phase clock; and combinational logic that generates an eight-phase sampling clock with uniformly distributed edges, a hold clock, and an eight-phase Gm enable clock with evenly distributed duty cycles.

[0047] The main loop includes: an eight-channel sample-and-hold switch, each controlled by an eight-phase sampling clock, to sample the ring oscillator output; an AC coupler, which couples the sampling results from the second to the eighth channels to the corresponding Gm input transistors; and a Gm module, which converts the sampled voltage into current in time-division multiplexing mode to control the charging and discharging of the filter to adjust the ring oscillator frequency.

[0048] In undersampling mode: the Gm enable clock of the first sampling path is kept high, while the Gm enable clocks of the other seven paths are low; all Gm input transistors are connected to the first DC sampling voltage, and new zeros and poles are introduced on the basis of the loop zeros and poles to improve the low-frequency phase margin without increasing the filter integration capacitor.

[0049] The frequency-locked loop includes: a frequency and phase detector with dead time: controlling the charging and discharging direction of the charge pump by the difference in duty cycle; and a frequency divider: dividing the output frequency of the ring oscillator to the reference clock range until the phase error enters the dead time range and then switching to undersampling mode.

[0050] The calibration loop compares the second to eighth sampling voltages with the first DC sampling voltage; based on the comparison results, it adjusts the load capacitance of the phase interpolator to ensure that the eight-phase clock edges are evenly distributed.

[0051] In oversampling mode: the duty cycle of the eight-phase Gm enable clock is 1 / 8, and the high voltage averages the reference clock period; by increasing the Gm gain to extend the loop bandwidth to the point where the in-band noise and out-of-band noise are equal, optimal noise suppression is achieved.

[0052] The filter includes an integrating capacitor whose area is optimized by reusing the Gm input transistor and introducing new zeros and poles, maintaining a phase margin of more than 45 degrees in undersampling mode.

[0053] An input reference multiphase generator is used to convert the input reference clock into an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock. The edges of the eight-phase clocks are evenly distributed within one reference clock cycle. The main loop includes eight sample-and-hold switches, an AC coupler, a Gm unit, a filter, and a loop oscillator. The eight sample-and-hold switches sample the output signal of the loop oscillator through the eight-phase sampling clock and the hold clock. The first sample signal is directly input to the Gm unit, and the other seven sample signals are input to the Gm unit through the AC coupler. The Gm unit operates in time-division multiplexing mode under the control of the eight-phase Gm enable clock, and outputs a control voltage to adjust the frequency of the loop oscillator. A frequency-locking loop is used to lock the frequency of the loop oscillator to near the reference clock frequency in the initial stage of loop locking. A calibration loop is used to calibrate the phase error of the eight-phase sampling clocks to ensure that the edges of each sampling clock are evenly distributed.

[0054] The passive PPF converts the input differential reference sine signal into a four-phase clock; the phase interpolator converts the four-phase clock into an eight-phase clock; the combinational logic processes the eight-phase clock to generate an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock with evenly distributed duty cycles.

[0055] Example 2:

[0056] This invention relates to a design method for extending the loop bandwidth of an undersampled phase-locked loop (PLL) with a Type-2 structure. A low-noise undersampled PLL structure based on a loop oscillator is proposed, with a loop bandwidth of 0.31 times the input reference frequency. An eight-phase clock is generated using a passive PPF and a phase interpolator. This eight-phase clock is then used by a multi-phase generator to produce eight sampling clocks, a hold clock, and a Gm enable clock, which control the eight sampling switches, hold switches, and Gm enable, respectively. Gm operates in time-division multiplexing mode, enabling the loop to operate at eight times the input reference frequency. This extends the maximum achievable bandwidth of the loop to eight times its original value, effectively suppressing the out-of-band noise contribution of the loop oscillator and achieving low-noise performance for the PLL. In addition, in order to reduce the initial stage of loop lock-in, i.e. the area of ​​the integrating capacitor of the filter operating in undersampling mode, and at the same time enable the eight Gm input transistors, all eight Gm input transistors are connected to the sampling voltage of the first DC sampling path, thereby introducing new zeros and poles on the basis of the original loop zeros and poles, so that the loop can achieve stable lock-in over a wider bandwidth without increasing the size of the integrating capacitor in the filter.

[0057] The low-noise, loop oscillator-based undersampled phase-locked loop (PLL) circuit consists of four parts: an input reference multiphase generator, a main loop, a frequency-locking loop, and a calibration loop. The input reference multiphase generator produces a multiphase sampling clock, a multiphase hold clock, and a multiphase Gm enable clock, extending the loop's operating frequency by eight times. The main loop samples the loop oscillator output using the clock generated by the multiphase generator and ultimately converts it into a voltage-controlled loop frequency. The frequency-locking loop is used for initial locking of the loop, bringing it into the undersampled PLL's locking range. The calibration loop calibrates the phase error of the eight-phase output generated by the multiphase generator, improving the sampling gain of multi-path sampling, reducing variations in sampling gain, loop bandwidth, and phase margin caused by changes in sampling position during multi-path sampling, lowering loop noise, and improving loop stability.

[0058] The input reference multiphase generator comprises the following components: a passive PPF, a phase interpolator, and combinational logic. The passive PPF converts the input differential reference sine wave signal into a four-phase clock. The phase interpolator converts the four-phase clock into an eight-phase clock. The combinational logic processes the eight-phase clock to generate an eight-phase sampling clock with evenly distributed edges within one clock cycle, an eight-phase hold clock, and an eight-phase Gm enable clock with a duty cycle evenly divided within one clock cycle.

[0059] The main loop consists of the following components: a sample-and-hold switch, an AC coupler, a filter, a loop oscillator, and an edge generator. The sample-and-hold switch samples the loop oscillator output, which has been linearized by the edge generator. The first sample result is directly fed to the input transistor of the Gm, while the sample results from other paths are fed to their respective Gm input transistors via the AC coupler. The Gm converts the sampled voltage into current to charge and discharge the filter and generates voltage to control the frequency of the loop oscillator.

[0060] The frequency-locked loop consists of the following components: a frequency divider, a frequency and phase detector with dead time, and a charge pump. The frequency divider divides the ring oscillator output frequency by a ratio equal to the ring oscillator frequency and the input reference frequency. The frequency and phase detector with dead time processes the division ratio and the input reference clock to obtain the phase difference information of the input clock. The charge pump converts the phase difference into current to charge and discharge the filter, thereby controlling the ring oscillator frequency.

[0061] The calibration loop consists of the following components: a differential sample-and-hold circuit and a comparator. Before the loop locks, the comparator sequentially compares the sampled voltages of the multi-path sampling circuit and the differential sampling circuit. Based on the comparison result (GND or VDD), it adjusts the load capacitance of the phase interpolator in the multi-path generator, thereby adjusting the phase of the multi-path phase interpolator to ensure its edges are evenly distributed within a reference clock cycle.

[0062] This ring-based low-noise multi-path sampling undersampling phase-locked loop (PLL) can be widely used in system-on-a-chip (SoC) applications requiring the integration of multiple PLL circuits, such as wired or wireless communications. In these applications, the input signals are an input reference clock and a division ratio control value. Based on the input reference clock and the division ratio, the PLL can output a clock signal that is multiplied by the input reference clock.

[0063] This embodiment operates through the following steps:

[0064] 1) In the initial stage of loop locking, the frequency-locked loop begins operation. The frequency divider in the loop divides the ring oscillator output to a frequency near the reference clock range. Then, a phase detector with dead time converts the phase error between the divider's output and the reference clock into the duty cycle information of the differential output clock, controlling the charge pump to charge and discharge the filter. When the divider's output clock phase leads the reference clock phase, the duty cycle of the differential output signal P terminal of the phase detector is higher than that of the N terminal. Conversely, when the divider's output clock lags the reference clock phase, the duty cycle of the differential output signal P terminal of the phase detector is lower than that of the N terminal. The P and N terminals of the phase detector control the charging and discharging paths of the charge pump, respectively. When the duty cycle of the phase detector's output signal P terminal is higher than that of the N terminal, the enable time of the charging path is longer than that of the discharging path. Therefore, the filter output voltage increases, and the ring oscillator frequency becomes higher. Conversely, when the duty cycle of the output signal P terminal of the frequency and phase detector is lower than that of the N terminal, the enable time of the charging path is lower than that of the discharging path. Therefore, the filter output voltage decreases, and the ring oscillation frequency decreases. The frequency-locked loop controls the change of the ring oscillation frequency until the phase difference between the frequency divider output signal and the input reference clock signal is small and enters the dead zone range of the frequency and phase detector. At this time, the frequency-locked loop generates a flag signal, the charge pump is no longer enabled, and the ring oscillation frequency remains constant.

[0065] 2) After the frequency-locked loop finishes its operation and generates a flag signal, the loop enters undersampling loop-locked mode. The reference clock multi-phase generator produces 8 sampling clocks, 8 hold clocks, and 8 Gm enable clocks. The edges of the sampling and hold clocks are evenly distributed within one reference clock cycle. The Gm enable clock of the first sampling path, i.e., the DC sampling path, is always high, while the Gm enable clocks of the remaining 7 AC sampling paths are all low. At this time, although all 8 sample-and-hold circuits are sampling normally, only the sampling voltage of the first path, i.e., the DC sampling path, will be applied to Gm (corresponding to the Gm input transistor being enabled). The sampling voltages of the other sampling paths will not affect the loop. Therefore, the loop is operating in undersampling mode at this time.

[0066] In the undersampling mode, the maximum achievable bandwidth of the loop is limited by the frequency of the input reference clock, and is usually limited to less than 1 / 10 of the input reference clock frequency, that is, fBW<fREF / 10. In the case of such a small bandwidth, in order to maintain sufficient phase margin, the integrating capacitor CLF in the filter needs to be set large enough, thus occupying a large area. To solve this problem, the output voltage of the first sampling and holding switch in this mode is simultaneously connected to the Gm input differential transistors of other paths. At this time, new poles and zeros are introduced on the basis of the original poles and zeros of the phase-locked loop, and the zero frequency is 1 / 8 of the pole frequency. The newly introduced poles and zeros increase the phase of the loop at low frequencies, so that without increasing the integrating capacitor in the filter, when the loop bandwidth is low in the undersampling mode, the loop phase margin still meets the stability requirement of being higher than 45 degrees.

[0067] 3) After the loop is locked in the undersampling mode, the phase generated by the phase interpolator of each path can be calibrated respectively according to the sampling voltages of the multi-path sampling and holding switches, and the phase calibration is realized by adjusting the load capacitance of the phase interpolator. The sampling voltage of the DC sampling path is used for loop locking and will eventually be locked near the zero crossing point, which does not need to be calibrated, while the sampling voltages of other AC sampling paths will not be used for loop locking, and their voltages are mainly determined by the relative positions of the edges of the multi-phase sampling clocks generated by the multi-phase generator, so calibration is required. The multi-phase generator first selects the output voltage of the second sampling and holding switch to compare with the output voltage of the sampling and holding switch at the differential input end of the comparator. When the comparison result is GND, it indicates that the sampling voltage is too large, and the load capacitance of the second phase interpolator needs to be increased. When the comparison result is VDD, it indicates that the sampling voltage is too small, and the load capacitance of the second phase interpolator needs to be reduced. By analogy, the clock phases generated by the multi-phase generator from the third path to the eighth path can be calibrated respectively.

[0068] 4) After the calibration is completed, the loop starts to work in the oversampling mode. At this time, the multi-phase generator not only generates eight-phase sampling and holding clocks, but also generates eight-phase Gm enable clocks each with a duty cycle of 1 / 8. The high levels of the eight-phase Gm enable clocks evenly divide one reference clock period, and at this time the Gm works in the time division multiplexing mode. At this time, the loop bandwidth can be increased by increasing the Gm gain to suppress the out-of-band noise contributed by the ring oscillator, so that the position of the loop bandwidth is at the position where the in-band noise and the out-of-band noise are equal, thereby achieving optimal noise performance.

[0069] This invention generates an eight-phase sample-and-hold clock and a Gm enable clock through a multi-phase generator in the input reference clock path, extending the loop operating frequency to eight times the original. This, in turn, extends the maximum achievable bandwidth of the loop to eight times the original, effectively reducing the out-of-band noise contributed by the ring oscillation and solving the problem of excessive ring oscillation noise contribution in ring-oscillation-based Type-2 undersampling phase-locked loops. To ensure that the edges of the eight-phase sampling clock generated by the multi-phase generator are more evenly distributed within a reference clock cycle, a front-end calibration method is employed. The sample-and-hold voltage of each path is compared with the reference voltage, and the load capacitance of the phase interpolator is calibrated based on the comparison results. This reduces the phase error of the eight-phase sampling clock, ensuring that the sampling voltage of each sampling path is near the zero-crossing position, thereby guaranteeing high sampling gain and low in-band noise. Furthermore, the noise of each module in the multi-phase generator is independent, thus further improving in-band noise performance compared to the single-path sampling undersampling structure. Therefore, this ring-based phase-locked loop structure reduces the out-of-band noise contribution of the ring vibration while maintaining low in-band noise, achieving optimal loop noise performance.

[0070] In the initial stage of loop-locked circuits, under the undersampling mode, by multiplexing Gm, the input transistors of the second to eighth paths Gm are connected to the DC sampling path, introducing new zeros and poles at the low frequency of the loop. Without increasing the filter integration capacitor or the chip area, the phase of the loop at the low frequency is increased, thus solving the problem of insufficient loop phase margin due to the low loop bandwidth in the initial stage of loop-locked circuits under the undersampling mode.

[0071] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.

[0072] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0073] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A bandwidth-enhanced small-area low-jitter phase-locked loop circuit, characterized in that, include: Input reference multiphase generator, main loop, frequency-locked loop, and calibration loop; The input reference multiphase generator generates an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock, enabling the loop to operate at eight times the input reference frequency. The main loop controls eight Gm input transistors by time-division multiplexing the eight-phase Gm enable clock, expanding the loop bandwidth to 0.31 times the input reference frequency and suppressing out-of-band noise of the loop oscillation. The calibration loop calibrates the phase error of the eight-phase clock by adjusting the load capacitance of the phase interpolator.

2. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 1, characterized in that, The input reference multiphase generator includes: Passive PPF: Converts the input differential reference signal into a four-phase clock; Phase interpolator: converts the four-phase clock into an eight-phase clock; Combinational logic: Generates an eight-phase sampling clock with uniformly distributed edges, a hold clock, and an eight-phase Gm enable clock with evenly distributed duty cycles.

3. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 1, characterized in that, The main loop includes: Eight-channel sample-and-hold switch: each is controlled by an eight-phase sampling clock to sample the ring oscillator output; AC coupler: Couples the sampling results from the second to the eighth channels to the corresponding Gm input transistor; Gm module: In time-division multiplexing mode, it converts the sampled voltage into current and controls the charging and discharging of the filter to adjust the ring frequency.

4. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 1, characterized in that, In undersampling mode: the Gm enable clock of the first sampling path is kept at a high level, while the Gm enable clocks of the other seven paths are at a low level; all Gm input transistors are connected to the first DC sampling voltage, and new zeros and poles are introduced on the basis of the loop zeros and poles to improve the low-frequency phase margin without increasing the filter integration capacitor.

5. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 1, characterized in that, The frequency locking loop includes: Frequency and phase detectors with dead zones: control the charging and discharging direction of the charge pump by the difference in duty cycle; Frequency divider: Divides the ring oscillator output frequency to the reference clock range until the phase error enters the dead zone range, then switches to undersampling mode.

6. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 1, characterized in that, The calibration loop compares the second to eighth sampling voltages with the first DC sampling voltage; based on the comparison results, it adjusts the load capacitance of the phase interpolator to ensure that the eight-phase clock edges are evenly distributed.

7. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 1, characterized in that, In oversampling mode: the duty cycle of the eight-phase Gm enable clock is 1 / 8, and the high voltage averages the reference clock period; by increasing the Gm gain to extend the loop bandwidth to the point where the in-band noise and out-of-band noise are equal, optimal noise suppression is achieved.

8. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 1, characterized in that, The filter includes: Integrating capacitor: Its area is optimized by reusing the Gm input transistor and introducing new zeros and poles, maintaining a phase margin of more than 45 degrees in undersampling mode.

9. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 1, characterized in that, The input reference multiphase generator is used to convert the input reference clock into an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock, wherein the edges of the eight-phase clock are evenly distributed within one reference clock cycle. The main loop includes an eight-channel sample-and-hold switch, an AC coupler, a Gm unit, a filter, and a loop oscillator. The eight-channel sample-and-hold switch samples the output signal of the loop oscillator through the eight-phase sampling clock and the hold clock. The first sample signal is directly input to the Gm unit, and the other seven sample signals are input to the Gm unit through the AC coupler. The Gm unit operates in time-division multiplexing mode under the control of the eight-phase Gm enable clock and outputs a control voltage to adjust the frequency of the loop oscillator. The frequency-locking loop is used to lock the loop oscillator frequency to near the reference clock frequency during the initial stage of loop locking; The calibration loop is used to calibrate the phase error of the eight-phase sampling clock, so that the edges of each sampling clock are evenly distributed.

10. The bandwidth-enhanced small-area low-jitter phase-locked loop circuit according to claim 2, characterized in that, The passive PPF converts the input differential reference sine signal into a four-phase clock. The phase interpolator converts the four-phase clock into an eight-phase clock; The combinational logic processes the eight-phase clock to generate an eight-phase sampling clock, an eight-phase hold clock, and an eight-phase Gm enable clock with evenly distributed duty cycles.

Images