Time-based off-site synchronous signal reconstruction output method and system

Abstract

The application discloses a time mark-based off-site synchronous signal reconstruction output method and system, relates to the field of signal reconstruction, and comprises the following steps: acquiring a test waveform data packet with a time mark sent by an off-site sending end and a local second pulse signal; performing waveform phase reconstruction based on the time mark of the test waveform data packet and the local second pulse signal to obtain reconstruction data; acquiring the queue depth of a cache area where the reconstruction data is located, and determining the phase gradient of the reconstruction data when the queue depth deviates from a preset hub; determining a correction coefficient according to the queue depth and the phase gradient; determining the frequency control word of a digital control oscillator based on the correction coefficient, and controlling the digital control oscillator to output a hardware sampling clock based on the frequency control word; and converting the reconstruction data into an analog test signal by driving a digital-to-analog converter through the hardware sampling clock to perform output. The application can effectively guarantee the accuracy and reliability of new energy station testing.

Description

Technical Field

[0001] This application relates to the field of signal reconstruction, and in particular to a time-scaled method and system for reconstructing and outputting remotely synchronized signals. Background Technology

[0002] With the rapid development of new energy power generation technologies, the scale of new energy power plants such as wind farms and photovoltaic power stations is constantly expanding, and the stability and reliability of their grid-connected operation have become a key focus of the power system. To ensure the safe and stable operation of new energy power plants, comprehensive performance testing and verification are necessary. In actual testing scenarios, since new energy power plants are often located in geographically remote areas, there is a significant physical distance between the testing equipment and the control center. Therefore, it is necessary to transmit test signals and data via network to achieve remote testing capabilities.

[0003] In traditional testing methods for new energy power plants, test signals are typically generated and output directly by a local testing instrument. However, when remote collaborative testing is required, test waveform data needs to be transmitted from a remote location to a local testing instrument via a network, where it is then reconstructed and output as an analog signal. Due to uncertain delays and jitter in network transmission, the arrival time of data packets received at the receiving end is random, making it difficult to guarantee the continuity of the data stream. Furthermore, the clock sources between the remote transmitting and receiving ends are usually independent, with slight differences in clock frequencies between the two locations, leading to accumulated clock drift over long periods. These factors combined make it difficult for the receiving end to accurately reconstruct a test signal synchronized with the transmitting end, thus affecting the accuracy and reliability of new energy power plant testing. Summary of the Invention

[0004] This application provides a time-stamped method and system for reconstructing and outputting remotely synchronized signals, which enables the receiving end to accurately reconstruct test signals synchronized with the transmitting end, thereby ensuring the accuracy and reliability of new energy power station testing.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: Firstly, a time-scaled method for reconstructing and outputting remote synchronization signals is provided, applied to a new energy power station test instrument. The test instrument includes a numerically controlled oscillator and a digital-to-analog converter. The method includes: Acquire the test waveform data packets with timestamps sent by the remote sender and the local second pulse signal; Based on the timestamp of the test waveform data packet and the local second pulse signal, waveform phase reconstruction is performed to obtain reconstructed data; Obtain the queue depth of the cache containing the reconstructed data, and determine the phase gradient of the reconstructed data when the queue depth deviates from the preset center. The correction coefficient is determined based on the queue depth and phase gradient; The frequency control word of the numerically controlled oscillator is determined based on the correction coefficient, and the hardware sampling clock of the numerically controlled oscillator is controlled based on the frequency control word. The reconstructed data is converted into an analog test signal for output by a digital-to-analog converter driven by a hardware sampling clock.

[0006] In one possible implementation of the first aspect, after determining the correction coefficients based on the queue depth and phase gradient, the following is included: The dynamic pointer offset step size is determined based on the correction factor; The index position is determined based on the dynamic pointer offset step size; Linear phase interpolation is performed between adjacent data points on both sides of the index position to obtain virtual sampling points; When the queue depth is lower than the preset center, insert virtual sampling points into the data queue; When the queue depth is higher than the preset central value, the data queue is subjected to phase-preserving extraction and filtering.

[0007] In another possible implementation of the first aspect, waveform phase reconstruction is performed based on the timestamp of the test waveform data packet and the local second pulse signal to obtain reconstructed data, including: Obtain the sender timestamp and local arrival timestamp of the test waveform data packet; The transmission time difference is determined based on the sender's timestamp and the local arrival timestamp, and a high-frequency local counter value aligned with the local second pulse signal is latched. The phase offset angle relative to the local second pulse signal is determined based on the transmission time difference and the high-frequency local counter value; The discrete waveform sequence is obtained by indexing and mapping the preset sine waveform lookup table according to the phase offset angle, and then output as the reconstructed data.

[0008] In another possible implementation of the first aspect, before indexing and mapping a preset sine wave lookup table according to the phase offset angle, the following is included: Obtain the time difference change of continuous test waveform data packets within the arrival window; Perform recursive sliding window mid-range filtering on the time difference variation to separate out systematic transmission delay; The linear phase drift slope is determined based on the systematic transmission delay; The predicted phase advance for the next frame period is determined based on the linear phase drift slope. The initial phase of the preset sine wave lookup table is compensated based on the predicted phase advance.

[0009] In another possible implementation of the first aspect, the correction coefficients are determined based on the queue depth and phase gradient, including: Obtain the difference between the read and write addresses in the buffer to determine the current queue depth; Determine the rate of change of the current queue depth over time to obtain the speed of change of the queue depth; The error coupling term is determined by cross-multiplying the queue depth change rate with the phase gradient; The correction coefficient is determined based on the deviation of the current queue depth from the preset center and the error coupling term.

[0010] In another possible implementation of the first aspect, the numerically controlled oscillator is a dual-loop numerically controlled oscillator. The main loop of the dual-loop numerically controlled oscillator is used to lock the local second pulse signal, and the secondary loop is used to receive the phase adjustment residual determined according to the correction coefficient. The frequency control word of the numerically controlled oscillator is determined based on the correction coefficient, including: The correction coefficient is decomposed into coarse frequency control quantity and fine phase residual quantity; The coarse adjustment frequency control value is input to the main loop accumulator of the main loop to track the clock drift relative to the local second pulse signal; The residual fine-tuning phase is input into the secondary loop phase shifter of the secondary loop to perform cycle-by-cycle phase correction; The output of the main loop accumulator and the output of the secondary loop phase shifter are combined by phase step size synthesis to obtain the digital phase step size; The frequency control word for driving the hardware sampling clock is determined based on the digital phase step size.

[0011] In another possible implementation of the first aspect, after determining the frequency control word driving the hardware sampling clock based on the digital phase step, the method further includes: The locking state of the main loop is determined based on the phase difference between the local second pulse signal and the main loop. When the locked state is the unlocked state, increase the loop gain of the secondary loop; When the lock state is locked, the fine-tuning phase residual input of the sub-loop is frozen; Reduce the loop bandwidth of the secondary loop to suppress phase noise; Smoothly transition the frequency control word during the adjustment of the loop bandwidth.

[0012] In another possible implementation of the first aspect, the reconstructed data is converted into an analog test signal for output by driving a digital-to-analog converter via a hardware sampling clock, including: The reconstructed data is converted into an initial analog signal by a hardware sampling clock-driven digital-to-analog converter. The initial analog signal is filtered for out-of-band noise by using a low-pass filter circuit to obtain the filtered analog signal. The filtered analog signal is amplified by a power amplifier circuit to obtain an analog test signal, which is then output.

[0013] Secondly, this application provides a new energy power station testing instrument, comprising: The memory is configured to store instructions; and The processor is configured to retrieve the instructions from the memory and, when executing the instructions, to implement the aforementioned time-stamp-based remote synchronization signal reconstruction output method.

[0014] Thirdly, this application provides a remote collaborative testing system, comprising: Remote sending end; Multiple new energy power station testing instruments; The remote transmitter is wirelessly connected to each new energy power station tester. The remote transmitter is used to send test waveform data packets to each new energy power station tester, and each new energy power station tester is used to receive the test waveform data packets and reconstruct and output the corresponding analog test signal.

[0015] By acquiring test waveform data packets with timestamps and local second pulse signals, a precise correspondence between the remote transmission time and the local time reference is established, providing a reliable time reference for waveform phase reconstruction. Waveform phase reconstruction based on timestamps and local second pulse signals maps received discrete data points to accurate phase positions, eliminating the impact of network transmission delays on waveform phase and ensuring phase consistency between the reconstructed waveform and the original waveform. By real-time monitoring of the buffer queue depth and combining it with phase gradient information to determine correction coefficients, adaptive control of data stream continuity is achieved, effectively addressing the challenges posed by network transmission rate fluctuations and the randomness of data packet arrival times. A dual-loop numerically controlled oscillator architecture is employed. The main loop locks onto the local second pulse signal to ensure long-term frequency stability, while the secondary loop rapidly responds to correction coefficients for phase fine-tuning. Their collaborative operation enables the hardware sampling clock to accurately track the transmitting clock, compensating for clock frequency differences and accumulated drift between the transmitting and receiving ends. The hardware sampling clock drives the digital-to-analog converter to output an analog signal, which, after filtering and power amplification, ensures that the final output test signal maintains a high degree of consistency with the original signal from the remote transmitting end in terms of frequency, phase, and amplitude. This technical solution not only meets the remote testing needs of individual renewable energy power plants but also supports collaborative testing scenarios for multiple plants. Through a unified time base and standardized signal processing procedures, it achieves time synchronization and signal consistency across geographically dispersed testing systems. This effectively improves the accuracy and reliability of renewable energy power plant performance testing, provides technical support for the safe and stable operation of renewable energy grid connection, and promotes the development of renewable energy power generation technology and the intelligent upgrading of the power system.

[0016] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] Figure 1 A flowchart illustrating a time-stamped remote synchronization signal reconstruction output method provided in this application embodiment; Figure 2 A schematic diagram of the structure of a new energy power station testing instrument provided in this application embodiment; Figure 3 This is a schematic diagram of a remote collaborative testing system provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0020] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0021] Figure 1 The illustration schematically shows a flowchart of a time-stamped remote synchronization signal reconstruction output method according to an embodiment of this application. Figure 1As shown in the figure, this application provides a time-scaled method for reconstructing and outputting remote synchronization signals, which is applied to a new energy power station test instrument. The new energy power station test instrument includes a numerically controlled oscillator and a digital-to-analog converter. The method may include the following steps.

[0022] S110. Obtain the test waveform data packet with timestamp sent by the remote transmitter and the local second pulse signal; S120. Based on the timestamp of the test waveform data packet and the local second pulse signal, the waveform phase is reconstructed to obtain the reconstructed data; S130. Obtain the queue depth of the buffer where the reconstructed data is located, and determine the phase gradient of the reconstructed data when the queue depth deviates from the preset center. S140. Determine the correction coefficient based on the queue depth and phase gradient; S150. Determine the frequency control word of the numerically controlled oscillator based on the correction coefficient, and control the output hardware sampling clock of the numerically controlled oscillator based on the frequency control word; S160 uses a hardware sampling clock to drive a digital-to-analog converter to convert the reconstructed data into an analog test signal for output.

[0023] In this embodiment, after acquiring the timestamped test waveform data packets sent by the remote transmitter and the local second pulse signal, the process may include: real-time monitoring of the arrival time interval of the test waveform data packets; triggering a packet loss compensation state when the arrival time interval exceeds a preset expected frame period; extracting the fundamental period, amplitude, and phase change slope of the signal based on historically received reconstructed data; generating smooth extrapolated waveform sampling points based on historical parameters using a polynomial curve fitting algorithm; and filling the smooth extrapolated waveform sampling points into the buffer queue to ensure the phase continuity of the digital-to-analog converter output waveform.

[0024] In another embodiment of this invention, the new energy power station tester includes a multi-channel digital-to-analog converter. The method may include the following steps: acquiring multi-channel test waveform data packets with timestamps sent by a remote transmitter; writing the reconstructed data of each channel into the corresponding channel buffer; determining the relative phase difference between channels based on the read pointer of each channel buffer; determining the delay compensation coefficient of each channel based on the relative phase difference; adjusting the read timing of each channel buffer based on the delay compensation coefficient, and then synchronously driving the multi-channel digital-to-analog converter to perform parallel output based on the hardware sampling clock.

[0025] Reference Figure 2The new energy power station tester in this embodiment includes a data receiving module, a clock synchronization module, a waveform reconstruction module, a buffer management module, a numerically controlled oscillator, and a digital-to-analog converter. The data receiving module is used to receive test waveform data packets transmitted by a remote transmitter over a network. The clock synchronization module is used to process the synchronization of the local second pulse signal and the timestamp. The waveform reconstruction module is used to execute step S120. The buffer management module is used to process steps S130 and S140. The numerically controlled oscillator and the digital-to-analog converter are used to execute steps S150 and S160.

[0026] In practice, the new energy power station test instrument first receives test waveform data packets from a remote transmitter via a network interface. The remote transmitter, located in a remote control center, is responsible for generating standard test waveforms and sending them to the field test instrument via the network. Each test waveform data packet is precisely timestamped before transmission, recording the exact moment the data packet leaves the transmitter.

[0027] Specifically, the structure of the test waveform data packet includes a header, a timestamp field, a waveform data payload, and a checksum field. The header identifies the sequence number and channel information of the data packet; the timestamp field records the second and sub-second values ​​of the transmission time; the waveform data payload contains the amplitude values ​​of discrete sampling points; and the checksum field is used to verify data integrity. Simultaneously, the new energy power station tester is equipped with a local second pulse signal source, which typically comes from a GPS or BeiDou timing module, providing a pulse signal synchronized with Coordinated Universal Time (UTC) once per second. The local second pulse signal serves as a time reference, with its rising edge precisely corresponding to the integer second of each second. By simultaneously acquiring the timestamped test waveform data packet and the local second pulse signal, the tester establishes a correspondence between the remote transmission time and the local time reference, laying the foundation for subsequent waveform phase reconstruction.

[0028] After acquiring the test waveform data packet and the local second pulse signal, the tester performs waveform phase reconstruction processing. First, it extracts the sender timestamp from the test waveform data packet, which records the precise moment the waveform data was generated and transmitted at the sender. Simultaneously, it records the local arrival timestamp of the data packet at the local receiver, which is latched by a local high-precision counter at the instant the data packet arrives. By calculating the difference between the sender timestamp and the local arrival timestamp, the network transmission time difference can be determined.

[0029] Because network transmission involves uncertain delays, this transmission time difference includes both fixed transmission delays and random jitter. To establish an accurate phase reference, the test instrument latches a local counter value driven by a high-frequency crystal oscillator when the rising edge of the local second pulse signal arrives. This high-frequency local counter operates at a frequency much higher than the waveform sampling rate, such as 100 MHz, thus providing sub-microsecond time resolution.

[0030] By combining the transmission time difference with the high-frequency local counter value, the phase offset angle of the test waveform data relative to the local second pulse signal can be calculated. The specific calculation method is as follows: the phase offset angle equals the transmission time difference plus the time offset corresponding to the local counter value, multiplied by the angular frequency of the test signal. For example, if the test signal is a 50Hz power frequency signal, the angular frequency is... If the time offset is 3 milliseconds per second (radians per second), then the phase offset angle is... radian.

[0031] After obtaining the phase offset angle, the tester uses a pre-stored sine wave lookup table in memory for index mapping. This lookup table stores sine wave sample values ​​within a complete cycle at a certain phase resolution. By using the phase offset angle as an index, the corresponding waveform amplitude value can be quickly found. For cases where the phase offset angle lies between two lookup table indices, a linear interpolation method is used to calculate the precise amplitude value. By performing the above phase mapping and interpolation operations on each sample point in the test waveform data packet, a series of discrete waveform sequences are generated. This sequence is the reconstructed data, and its phase has been accurately correlated with the local second pulse signal.

[0032] After obtaining the reconstructed data, the tester writes the reconstructed data into the buffer queue and monitors the queue depth of the buffer in real time. The queue depth is defined as the amount of valid data in the buffer that has not yet been read by the digital-to-analog converter, usually expressed as the number of sampling points or bytes. The tester tracks the queue depth by maintaining write pointers and read pointers in the buffer. The write pointer indicates the write position of the next reconstructed data, and the read pointer indicates the read position of the next data to be converted. The queue depth is equal to the address difference between the write pointer and the read pointer.

[0033] The preset center is an ideal target value for queue depth, typically set to the middle position of the buffer capacity. For example, when the buffer capacity is 1024 sampling points, the preset center can be set to 512 sampling points. When the queue depth is maintained near the preset center, it indicates that the data write rate and read rate are basically balanced, and the system is operating in a stable state.

[0034] However, due to fluctuations in network transmission latency and slight differences in clock frequencies between the sending and receiving ends, the queue depth may deviate from the preset threshold. When the queue depth is below the preset threshold, it indicates that data consumption is faster than data arrival, posing a risk of buffer underflow; when the queue depth is above the preset threshold, it indicates that data arrival is faster than data consumption, posing a risk of buffer overflow. When a queue depth deviation from the preset threshold is detected, the tester needs to determine the phase gradient of the reconstructed data. The phase gradient describes the rate of change of the waveform phase over time and can be obtained by calculating the phase difference between adjacent sampling points divided by the sampling time interval. For a standard sine wave, the phase gradient is equal to the angular frequency. By analyzing the phase changes of multiple consecutive sampling points, the current phase gradient can be estimated more accurately. This parameter reflects the instantaneous frequency characteristics of the waveform, providing a basis for subsequent frequency correction.

[0035] After obtaining the queue depth and phase gradient, the tester calculates a correction factor to adjust the output frequency of the numerically controlled oscillator. The determination of the correction factor takes into account both the queue depth deviation and the phase gradient information.

[0036] First, calculate the deviation of the current queue depth from the preset center value. The deviation is the current queue depth minus the preset center value. A positive deviation indicates queue backlog, while a negative deviation indicates queue shortage. Simultaneously, calculate the rate of change of queue depth, i.e., the first derivative of queue depth with time. This rate of change reflects the trend of queue depth deviation. Cross-multiply the rate of change of queue depth with the phase gradient to obtain an error coupling term, which describes the influence of the phase change rate on queue depth change. The formula for calculating the correction coefficient can be expressed as: ,in For correction factor, This represents the deviation in queue depth. , , These are the proportional, differential, and integral gain coefficients. For phase gradient, This represents the coupling gain coefficient. This formula essentially constitutes an enhanced PID controller: the proportional term provides a fast response to deviation, the derivative term predicts the deviation trend, the integral term eliminates steady-state error, and the coupling term compensates for the effects of phase changes. By appropriately setting each gain coefficient, precise control of the queue depth can be achieved, stabilizing it near a preset center, thereby ensuring the continuity of the data stream and the synchronization of the waveform output.

[0037] After determining the correction coefficient, the tester uses this coefficient to adjust the frequency control word of the numerically controlled oscillator, thereby controlling the output frequency of the hardware sampling clock. The numerically controlled oscillator is a digital circuit that generates a periodic digital phase signal by accumulating the frequency control word. This phase signal is then converted from phase to amplitude to output clock pulses. The frequency control word determines the step size of the phase accumulation, thus controlling the frequency of the output clock.

[0038] In this embodiment, the numerically controlled oscillator adopts a dual-loop architecture, including a main loop and a secondary loop. The main loop is used to lock the local second pulse signal to ensure long-term frequency stability. The main loop includes a main loop accumulator and a main loop phase comparator. The main loop accumulator accumulates data using a fixed reference frequency control word. The main loop phase comparator compares the accumulator output with the local second pulse signal to generate a phase error signal. This phase error signal is then filtered by a loop filter and fed back to adjust the frequency control word of the main loop accumulator, forming a phase-locked loop.

[0039] The secondary loop receives the phase adjustment residual determined by the correction coefficients and performs rapid phase fine-tuning. The correction coefficients are decomposed into a coarse-tuning frequency control and a fine-tuning phase residual. The coarse-tuning frequency control acts on the main loop accumulator to track clock drift between the transmitter and receiver, which is typically a slow-changing phenomenon. The fine-tuning phase residual is input to the secondary loop phase shifter, which makes small phase adjustments each clock cycle to compensate for rapid phase changes caused by network latency jitter and queue depth fluctuations.

[0040] The output of the main loop accumulator and the output of the secondary loop phase shifter are combined to obtain a digital phase step. This digital phase step is then converted into a frequency control word, driving a numerically controlled oscillator to output a hardware sampling clock. The frequency of the hardware sampling clock is dynamically adjusted according to a correction coefficient. When the queue depth is higher than a preset threshold, the sampling clock frequency is reduced to slow down data consumption; when the queue depth is lower than the preset threshold, the sampling clock frequency is increased to accelerate data consumption, thus achieving adaptive balance of queue depth.

[0041] Finally, the tester drives a digital-to-analog converter (DAC) via a hardware sampling clock to convert the reconstructed data into an analog test signal and output it. The DAC reads a reconstructed data sample from the buffer queue on each rising edge of the hardware sampling clock and converts the digital value into the corresponding analog voltage or current signal. The conversion accuracy of the DAC is typically 12 to 16 bits, providing sufficient amplitude resolution to accurately reproduce the test waveform.

[0042] The converted initial analog signal contains high-frequency quantization noise and image frequency components, requiring out-of-band noise filtering via a low-pass filter circuit. The low-pass filter circuit employs a multi-order active filter or an LC passive filter, with the cutoff frequency set at 1.5 to 2 times the highest frequency component of the test signal to maintain signal integrity while filtering out noise. The filtered analog signal has a relatively small amplitude and requires power amplification to drive the device under test (DUT) at the renewable energy power station. The power amplification circuit provides the appropriate voltage and current output capabilities according to the test requirements. The amplified analog test signal is connected to the DUT through the output port, completing the remote synchronous reconstruction output of the test signal. Throughout the process, due to the use of time-scaled phase reconstruction, queue depth adaptive control, and dual-loop CNC oscillator frequency adjustment, the output analog test signal maintains precise phase synchronization and frequency consistency with the original test signal at the remote transmitter, ensuring the accuracy and reliability of the test signal even in the presence of network latency fluctuations and clock drift.

[0043] This embodiment integrates a numerically controlled oscillator and a digital-to-analog converter into the new energy power station tester, achieving high-precision synchronous output of remote test signals and effectively overcoming the signal distortion problems caused by network delay uncertainty and clock drift in traditional remote testing methods. By acquiring test waveform data packets with timestamps and local second pulse signals, a precise correspondence between the remote transmission time and the local time reference is established, providing a reliable time reference for waveform phase reconstruction. Based on the timestamps and local second pulse signals, waveform phase reconstruction maps the received discrete data points to accurate phase positions, eliminating the impact of network transmission delay on waveform phase and ensuring phase consistency between the reconstructed waveform and the original waveform. By real-time monitoring of the buffer queue depth and combining it with phase gradient information to determine the correction coefficient, adaptive control of data stream continuity is achieved, effectively addressing the challenges posed by network transmission rate fluctuations and the randomness of data packet arrival times. A dual-loop numerically controlled oscillator architecture is adopted, with the main loop locking the local second pulse signal to ensure long-term frequency stability, and the secondary loop quickly responding to the correction coefficient to achieve phase fine-tuning. The collaborative work of both enables the hardware sampling clock to accurately track the transmitting clock, compensating for clock frequency differences and accumulated drift between the transmitting and receiving ends. The analog signal is driven by a hardware sampling clock to output a digital-to-analog converter. After filtering and power amplification, the final output test signal maintains a high degree of consistency with the original signal at the remote transmitting end in terms of frequency, phase, and amplitude. This technical solution not only meets the remote testing needs of a single renewable energy power station but also supports collaborative testing scenarios for multiple stations. Through a unified time base and standardized signal processing procedures, it achieves time synchronization and signal consistency across geographically dispersed testing systems. This effectively improves the accuracy and reliability of performance testing at renewable energy power stations, provides technical support for the safe and stable grid-connected operation of renewable energy, and promotes the development of renewable energy power generation technology and the intelligent upgrading of the power system.

[0044] In one embodiment of this example, after determining the correction coefficient based on the queue depth and phase gradient, the following steps are included: S210. Determine the dynamic pointer offset step size based on the correction coefficient; S220. Determine the index position based on the dynamic pointer offset step size; S230. Perform linear phase interpolation between adjacent data points on both sides of the index position to obtain virtual sampling points; S240. When the queue depth is lower than the preset center, insert the virtual sampling point into the data queue; S250. When the queue depth is higher than the preset center, perform phase-preserving extraction filtering on the data queue.

[0045] This implementation addresses the issue of waveform phase discontinuity that may occur when the queue depth deviates from the preset center. By processing at the data level and adjusting the frequency control word, it can effectively ensure the phase continuity and frequency accuracy of the output waveform. It effectively solves the problem of uneven data flow caused by network transmission rate fluctuations and avoids phase abrupt changes caused by simple data loss or duplication.

[0046] Specifically, after determining the correction coefficient, the tester calculates the dynamic pointer offset step size based on the correction coefficient. This step size guides the adjustment of the buffer read pointer's movement speed. The calculation of the dynamic pointer offset step size takes into account both the magnitude and direction of the correction coefficient. The correction coefficient reflects the degree to which the current queue depth deviates from the preset center and the influence of the phase gradient; its value typically ranges from -1 to 1.

[0047] A positive correction coefficient indicates a need to accelerate data consumption to reduce queue depth; a negative correction coefficient indicates a need to slow down data consumption to increase queue depth. The formula for calculating the dynamic pointer offset step size is: ,in This is the dynamic pointer offset step size. The standard pointer offset step size. For correction factor, The sensitivity coefficient is adjusted by the step size. The standard pointer offset step size is typically set to 1, meaning the read pointer advances one data point per sampling clock cycle. The sensitivity coefficient for step size adjustment is set according to the system's response speed requirements. The dynamic adjustment mechanism in this embodiment allows the data read rate to change in real time according to the queue depth, enabling fine control of the data flow and providing a precise positioning basis for subsequent phase interpolation and data adjustment.

[0048] Based on the dynamic pointer offset step, the tester determines the index position in the cache. The index position is a real value representing the precise position of the read pointer in the cache, which may fall between two integer indices. The index position is calculated by adding the dynamic pointer offset step to the current integer read pointer position.

[0049] Because the dynamic pointer offset step may not be an integer, the accumulated index position contains both an integer and a fractional part. The integer part indicates the index of the nearest data point, and the fractional part represents the relative position between two adjacent data points. For example, if the current read pointer is at index 100 and the dynamic pointer offset step is 1.04, then the next index position is 101.04. This means that the required data point is located between index 101 and index 102, occupying a 4% distance from index 101.

[0050] In practical implementation, the tester uses fixed-point or floating-point numbers to store the index positions to ensure calculation accuracy. Determining the index positions provides accurate parameters for subsequent linear phase interpolation, enabling the generation of virtual sampling points to precisely correspond to the required phase positions, thereby ensuring the continuity of the waveform phase.

[0051] After determining the index position, the tester performs linear phase interpolation between adjacent data points on both sides of the index position to generate virtual sampling points.

[0052] Linear phase interpolation is an interpolation method that preserves phase continuity. Its principle is to calculate the value of a sampling point at an intermediate position based on the amplitude and phase information of two adjacent known sampling points. Let the index position be... ,in For the integer part, The decimal part and The two adjacent data points are respectively and Their corresponding phases are respectively and .

[0053] The phase of the virtual sampling points is calculated using linear interpolation: Then, based on the interpolated phase, the amplitude value of the virtual sampling point is obtained either through a sine waveform lookup table or by direct calculation. ,in This represents the signal amplitude.

[0054] For complex waveforms, amplitude linear interpolation can be used: The linear phase interpolation method is computationally simple and effectively maintains a smooth phase transition, avoiding waveform distortion caused by abrupt phase changes. The generated virtual sampling points are numerically located between adjacent data points and precisely correspond to the phase angle indicated by the index position, providing high-quality supplementary data for the dynamic adjustment of the data queue.

[0055] When the queue depth is below the preset threshold, it indicates that data consumption is faster than data arrival, and the buffer faces the risk of insufficient data. In this case, the tester inserts generated virtual sampling points into the data queue to increase the amount of effective data in the queue and prevent buffer underflow. The insertion position of the virtual sampling point is determined based on the index position, usually after the current read pointer position. The insertion operation needs to maintain the temporal continuity of the data queue, that is, the inserted virtual sampling point should be located at the correct position between the preceding and following data points on the timeline.

[0056] In practice, the tester writes virtual sampling points into the empty region between the write and read pointers and adjusts the write pointer position accordingly. Since the virtual sampling points are generated through linear phase interpolation, their phase remains continuous with adjacent data points, so the insertion operation does not cause a phase jump in the output waveform. After inserting virtual sampling points, the queue depth increases, gradually moving closer to the preset center. This mechanism effectively compensates for data shortages caused by increased network transmission latency or packet loss, ensuring that the digital-to-analog converter always has sufficient data to read, maintaining the continuity and stability of the output signal.

[0057] When the queue depth exceeds the preset threshold, it indicates that the data arrival rate is faster than the data consumption rate, and the buffer faces the risk of data backlog. In this situation, the tester performs phase-preserving extraction filtering on the data queue to reduce the amount of data in the queue and prevent buffer overflow.

[0058] In this embodiment, phase-preserving decimation filtering differs from simple data discarding. Its core lies in ensuring that the decimated data sequence retains its original phase continuity and frequency characteristics. The decimation filtering is implemented as follows: based on the dynamic pointer offset step size, when the step size is greater than 1, the read pointer advances a distance exceeding one data point each time, thus skipping some data points. The skipped data points are not sent to the digital-to-analog converter, reducing the amount of data. To maintain phase continuity, the skipping operation is precisely controlled based on the fractional part of the index position. For example, when the dynamic pointer offset step size is 1.3, the read pointer advances 6.5 data point positions within 5 sampling periods, equivalent to decimating 1.5 data points every 5 periods.

[0059] By accumulating the decimal part of the index position, a data point skipping operation is performed when the accumulated value exceeds 1. This accumulation-based decimation method ensures a uniform distribution of skipped data points, avoiding phase abrupt changes caused by concentrated skipping. Simultaneously, combined with linear phase interpolation, phase smoothing is performed before and after skipping data points to ensure the phase gradient of the output waveform remains constant. Through phase-preserving decimation filtering, the queue depth gradually decreases, returning to the preset center, while the frequency and phase characteristics of the output signal are well preserved, effectively avoiding increased delay and waveform distortion caused by data backlog.

[0060] In this embodiment, the calculation of the dynamic pointer offset step size transforms the correction coefficient into a specific data read rate adjustment, enabling the data consumption rate to change in real time according to the queue depth, thus achieving adaptive balance of the data flow. Virtual sampling points are generated based on linear phase interpolation of the index position, providing high-quality supplementary data for the dynamic adjustment of the data queue and ensuring phase continuity. Inserting virtual sampling points when the queue depth is below the preset threshold effectively compensates for data shortages caused by network latency fluctuations, preventing buffer underflow and output signal interruption. Furthermore, when the queue depth is above the preset threshold, phase-preserving decimation filtering is employed, reducing data backlog while maintaining waveform phase continuity and avoiding phase abrupt changes and frequency shifts caused by simple data discarding. In summary, this significantly improves the system's adaptability to network transmission uncertainties, ensures high precision and stability of the output test signal, and provides reliable technical support for remote collaborative testing of new energy power plants.

[0061] In one embodiment of this invention, waveform phase reconstruction is performed based on the timestamp of the test waveform data packet and the local second pulse signal to obtain reconstructed data, including the following steps: S310. Obtain the sender timestamp and local arrival timestamp of the test waveform data packet; S320. Determine the transmission time difference based on the sender's timestamp and the local arrival timestamp, and latch the high-frequency local counter value aligned with the local second pulse signal; S330. Determine the phase offset angle relative to the local second pulse signal based on the transmission time difference and the high-frequency local counter value; S340. The preset sine waveform lookup table is indexed and mapped according to the phase offset angle to obtain a discrete waveform sequence, and the discrete waveform sequence is output as reconstructed data.

[0062] This implementation addresses the waveform phase mismatch problem caused by network transmission delay between remote transmitters and receivers. By establishing a precise mapping relationship between the transmitter's time reference and the local time reference, the waveform phase can be accurately restored, ensuring the consistency of the reconstructed waveform with the original waveform in phase, thus laying the foundation for subsequent synchronization signal output.

[0063] Specifically, after receiving the test waveform data packet, the tester first extracts the sender's timestamp and the local arrival timestamp of the data packet carried in the data packet.

[0064] The sender timestamp is added by the remote sender when generating the test waveform data and encapsulating it into a data packet, recording the moment the data packet leaves the sender's network interface. The sender timestamp typically uses a universal time format that includes both second and sub-second values. The sub-second values ​​can achieve a high level of precision and are generated using a high-precision clock source.

[0065] The local arrival timestamp is generated by the receiver tester immediately upon the arrival of the data packet at the network interface. It is recorded by reading the current value of the local high-precision time counter at the instant the data packet reception interruption is triggered. The local time counter is synchronized with the sender using the same time base.

[0066] By simultaneously acquiring the sender's timestamp and the local arrival timestamp, the tester establishes a complete time link for the data packet from sending to receiving. The difference between these two timestamps directly reflects the data packet's transmission time in the network, including network routing delay, switch processing delay, and physical link propagation delay. Accurate acquisition of both timestamps provides a reliable time data foundation for subsequent accurate calculation of transmission time difference and phase offset.

[0067] After acquiring the dual timestamps, the tester calculates the transmission time difference and latches the high-frequency local counter value when the local second pulse signal arrives.

[0068] The formula for calculating transmission time difference is: ,in For transmission time difference, Local arrival timestamp This is the sender's timestamp. Since the clocks of the sender and receiver are synchronized, the calculated transmission time difference has practical physical meaning.

[0069] To establish an accurate phase reference, this embodiment is equipped with a high-frequency local counter. The high-frequency local counter begins counting from the rising edge of each second pulse and resets to start counting again when the next second pulse arrives, thus providing high-precision time resolution within seconds. When the rising edge of the local second pulse signal arrives, the tester captures and saves the current value of the high-frequency local counter through a hardware latching circuit.

[0070] The latched counter value is converted into a time quantity, representing the time offset from the most recent rising edge of the second pulse to the current moment. By combining the transmission time difference and the latched high-frequency counter value, the tester can accurately determine the time position of the test waveform data relative to the local second pulse signal.

[0071] After obtaining the transmission time difference and the high-frequency local counter value, the tester calculates the phase offset angle of the test waveform data relative to the local second pulse signal.

[0072] First, determine the absolute time position of the test waveform data on the local time axis. This position is equal to the most recent local second pulse moment plus the time offset corresponding to the high-frequency counter value, and then subtract the transmission time difference. This gives the mapping position of the sending end time corresponding to the waveform sampling point in the data packet on the local time axis.

[0073] For a standard sine wave test signal, the formula for calculating the phase offset angle is: ,in This is the phase offset angle. To test the signal frequency, The value of the high-frequency counter that is latched. This refers to the operating frequency of the high-frequency counter. The period of the test signal.

[0074] For example, for a 50Hz power frequency test signal with a period of 20 milliseconds, if the high-frequency counter value corresponds to 5 milliseconds and the transmission time difference is 23 milliseconds, then the transmission time difference modulo the period is 3 milliseconds, the relative time offset is 2 milliseconds, and the phase offset angle is calculated as follows: Radius. Using this calculation method, the tester can accurately determine the phase position of the received waveform data under the local time reference.

[0075] After determining the phase offset angle, the tester uses a preset sine waveform lookup table for index mapping to generate a discrete waveform sequence as reconstructed data.

[0076] The sine wave lookup table is pre-stored in memory, containing amplitude values ​​for a complete sine wave cycle. The index mapping process converts the phase offset angle into an index value for the lookup table. The formula for calculating the index value is: ,in For index value, This is the phase offset angle. This represents the number of sampling points in the lookup table.

[0077] For cases where the phase offset angle lies between two lookup table indices, linear interpolation can be used to improve accuracy. Let the precise index corresponding to the phase offset angle be... The integer part is The decimal part is The interpolated amplitude value is: ,in and Indexes in the lookup table and The amplitude value at that point.

[0078] A discrete waveform sequence is generated by performing phase offset angle calculations and lookup table mapping operations on the sampling points in the test waveform data packet. This sequence is then written to a buffer queue as reconstructed data for subsequent digital-to-analog conversion processing.

[0079] In this embodiment, a complete time link is established by acquiring the sender's timestamp and the local arrival timestamp, enabling accurate calculation of the data packet's transmission time difference in the network. A high-precision local time reference is established by latching a high-frequency local counter value aligned with the local second pulse signal. The phase offset angle is calculated by combining the transmission time difference and the high-frequency counter value, precisely quantifying the phase position of the waveform data relative to the local time reference. Furthermore, indexing and interpolating the sine waveform lookup table based on the phase offset angle allows for the rapid generation of a phase-corrected discrete waveform sequence. In summary, this embodiment effectively eliminates the impact of network transmission delay on waveform phase, ensuring the consistency of the reconstructed waveform with the original waveform in phase, and significantly improving the accuracy and stability of signal reconstruction in remote collaborative testing.

[0080] In one embodiment of this invention, before indexing and mapping a preset sine wave lookup table according to the phase offset angle, the following steps are included: S410. Obtain the time difference change of continuous test waveform data packets within the arrival window; S420. Perform recursive sliding window mid-range filtering on the time difference change to separate out the systematic transmission delay; S430. Determine the linear phase drift slope based on the systematic transmission delay; S440. Determine the predicted phase advance of the next frame period based on the linear phase drift slope. S450. Compensate the initial phase of the preset sine wave lookup table according to the predicted phase advance.

[0081] This implementation addresses the problem of accumulated phase error caused by systematic drift in network transmission delay. By using a method based on time difference variation analysis and predictive phase compensation, it statistically analyzes the transmission time difference of continuous data packets, separates the systematic transmission delay component, and predicts future phase drift trends, thus achieving feedforward phase compensation. This can effectively avoid waveform distortion caused by accumulated phase error during long-term operation and improve the long-term stability and accuracy of remote synchronization signal reconstruction.

[0082] Specifically, during the process of receiving continuous test waveform data packets, the tester monitors and records the transmission time difference of each data packet in real time, and calculates the change in time difference of continuous data packets within the arrival window.

[0083] The arrival window is a time observation interval, which can be set to include the period of the 10 to 50 most recently received data packets. For each newly arrived data packet, the tester calculates its transit time difference and compares it with the transit time difference of the previous data packet to obtain the change in time difference.

[0084] The formula for calculating the change in time zone is: ,in For the first The time difference change of each data packet For the first The time difference of transmission of each data packet. For the first The time difference of transmission of each data packet.

[0085] The time difference variation reflects the fluctuating characteristics of network transmission delay, and its value contains two components: one is random jitter caused by factors such as network congestion and routing changes; the other is systematic drift caused by small differences in clock frequencies between the sender and receiver. By collecting the time difference variation of multiple data packets within the arrival window, a time difference variation sequence is formed, which provides the data basis for subsequent separation analysis.

[0086] After obtaining the time difference change sequence, the tester performs recursive sliding window mid-range filtering on the sequence to separate the systematic transmission delay component.

[0087] The implementation process of recursive sliding window mid-value filtering is as follows: Set the sliding window length. (For example, taking 5 to 15 data points), the window slides over the time difference change series. For the data points within the window... The time difference change values ​​are sorted and the median is taken as the filtered output.

[0088] The selection of the median makes the filtering result insensitive to extreme outliers, effectively filtering out time difference spikes caused by sudden network congestion. The filtered output sequence retains the slow trend of time difference variation, which reflects the systematic transmission delay.

[0089] The physical source of systematic transmission delay is primarily a slight difference in clock frequencies between the transmitting and receiving ends, which causes a linearly cumulative offset between the two time bases. By separating this trend component through median filtering, the tester can accurately identify the presence and magnitude of systematic transmission delay.

[0090] After separating the systematic transmission delay, the tester determines the linear phase drift slope based on the variation characteristics of the delay.

[0091] The linear phase drift slope is calculated using a least-squares fit. Let the filtered systematic propagation delay sequence be... The corresponding time series is ,in , The sequence length is given. A straight line is fitted using the least squares method. Solve for the slope .

[0092] slope The calculation formula is: The slope This reflects the relative deviation of the clock frequency.

[0093] To convert the slope in the time domain to the slope in the phase domain, it needs to be multiplied by the angular frequency of the test signal. The formula for calculating the linear phase drift slope is: ,in The linear phase drift slope is expressed in radians per second. To test the signal frequency.

[0094] For example, if the slope of the time domain is If the test signal frequency is 50Hz, then the phase drift slope is calculated as follows: Radius per second. This slope represents the rate of cumulative phase drift of the waveform per second and is a key parameter for predicting future phase shifts.

[0095] Based on the linear phase drift slope, the tester predicts the phase advance of the next frame period, thus achieving feedforward phase compensation.

[0096] Let the data packet sending period be The linear phase drift slope is Then the formula for calculating the prediction phase advance of the next frame period is: .

[0097] This formula represents the additional waveform phase shift caused by the accumulation of clock frequency deviation when the next data packet arrives. By predicting the phase advance, the tester can anticipate the phase shift trend and compensate in advance before the data packet arrives, avoiding the lag of traditional feedback correction and realizing feedforward phase control.

[0098] After determining the predicted phase advance, the tester compensates for the initial phase of the preset sine wave lookup table based on this advance.

[0099] Phase compensation is implemented by subtracting the predicted phase advance from the uncompensated initial phase to obtain the compensated initial phase. The compensation formula is: ,in The initial phase after compensation. The initial phase is uncompensated. To predict phase advance.

[0100] This compensation operation is performed before the lookup table index mapping. The compensated initial phase serves as a new phase reference for subsequent index mapping calculations based on the phase offset angle. This feedforward compensation mechanism, combined with the system's feedback control mechanism, forms a composite control strategy of feedforward plus feedback.

[0101] In this embodiment, a time-series dataset of transmission delay fluctuations is established by acquiring the time difference change of continuous test waveform data packets within the arrival window. By performing recursive sliding window mid-range filtering on the time difference change, the systematic transmission delay component is effectively separated and random jitter interference is filtered out. The rate of influence of clock frequency deviation on the phase is accurately quantified by determining the linear phase drift slope based on the systematic transmission delay. Active prediction of future phase shifts is achieved by predicting the phase advance of the next frame period based on the linear phase drift slope. Furthermore, the initial phase of the sine wave lookup table is compensated based on the predicted phase advance, realizing feedforward phase correction. In summary, this embodiment effectively offsets the phase accumulation drift caused by clock frequency deviation, improves the system's adaptability to clock frequency deviation and phase control accuracy, and ensures the stability and reliability of remote synchronization signal reconstruction during long-term continuous operation.

[0102] In one embodiment of this invention, determining the correction coefficient based on the queue depth and phase gradient includes the following steps: S510. Obtain the difference between the read and write addresses of the buffer to determine the current queue depth; S520. Determine the rate of change of the current queue depth over time to obtain the speed of queue depth change. S530. Cross-multiply the queue depth change rate with the phase gradient to determine the error coupling term; S540. Determine the correction coefficient based on the deviation of the current queue depth from the preset center and the error coupling term.

[0103] This implementation addresses the problem of insufficient control accuracy caused by the coupling relationship between queue depth fluctuations and phase changes. By introducing a correction coefficient calculation method based on error coupling terms, it incorporates cross-coupling analysis of queue depth change rate and phase gradient. This method can accurately quantify the dynamic characteristics of the data flow and effectively overcome the problems of response lag and oscillation when controlling solely based on queue depth deviation. It also improves the accuracy of correction coefficient calculation and the stability of the control system.

[0104] Specifically, when monitoring the status of the buffer in real time, the tester determines the current queue depth by obtaining the difference between the read and write addresses of the buffer.

[0105] The buffer is implemented using a circular buffer structure, containing two address indicators: a write pointer and a read pointer. The write pointer points to the memory location where the next reconstructed data will be written. Whenever new reconstructed data arrives, the data is written to the location pointed to by the write pointer, and then the write pointer increments. The read pointer points to the location where the next data to be sent to the digital-to-analog converter (DAC) will be sent. Whenever the hardware sampling clock triggers the DAC, the data pointed to by the read pointer is read, and then the read pointer increments. When the pointer reaches the end of the buffer, it automatically wraps back to the beginning of the buffer.

[0106] The formula for calculating the current queue depth is: ,in This represents the current queue depth. To write the pointer address, To read the pointer address, This represents the total capacity of the cache.

[0107] This formula handles pointer wraparound using modular arithmetic, ensuring the accuracy of queue depth calculation. For example, if the buffer capacity is 1024 sample points, the write pointer is at address 100, and the read pointer is at address 50, then the queue depth is 50 sample points; if the write pointer is at address 50 and the read pointer is at address 900, then the queue depth is... Each sampling point. By acquiring the read / write address difference in real time, the tester can accurately determine the amount of data to be processed in the buffer, which reflects the balance between the data write rate and the read rate.

[0108] After obtaining the current queue depth, the tester determines the rate of change of queue depth by calculating the rate of change of queue depth over time.

[0109] The rate of change is calculated using the finite difference method, and the formula is: ,in For the rate of change of queue depth, The current queue depth. This represents the queue depth at the previous time step. This represents the sampling time interval.

[0110] The unit for the rate of change of queue depth is sampling points per second. A positive value indicates that the queue depth is increasing, while a negative value indicates that the queue depth is decreasing. To improve the stability of the rate of change calculation, a moving average method can be used to smooth the rate of change over multiple consecutive sampling periods.

[0111] By introducing the rate of change parameter, the tester can not only sense the current state of the queue depth, but also predict its development trend, providing a basis for implementing predictive control and avoiding the lag problem when controlling based solely on the current deviation.

[0112] After determining the rate of change of queue depth, the tester cross-multiplies this rate with the phase gradient to determine the error coupling term.

[0113] The phase gradient describes the rate of change of the waveform phase over time, and its value is equal to the angular frequency of the test signal. The formula for calculating the error coupling term is: ,in For error coupling terms, The coupling coefficient is... For the rate of change of queue depth, This represents the phase gradient.

[0114] The coupling coefficient is a parameter calibrated according to system characteristics, used to adjust the weight of the coupling term on the correction coefficient. The error coupling term is used to quantify the degree of influence of dynamic changes in queue depth on the waveform phase.

[0115] By cross-multiplying the queue depth change rate with the phase gradient, the error coupling term comprehensively reflects the strength of the impact of dynamic imbalance in the data stream on the phase. For example, if the queue depth change rate is 100 samples per second, and the phase gradient is... In radians per second, with a coupling coefficient set to 0.05, the error coupling term is calculated as follows: This coupling term enables the control system to respond simultaneously to both the current deviation and the trend of change in queue depth.

[0116] After determining the error coupling term, the tester calculates the correction coefficient based on the deviation of the current queue depth from the preset center and the error coupling term.

[0117] The formula for calculating the deviation is: ,in This is the deviation amount. This represents the current queue depth. This is the preset central value.

[0118] The correction coefficient is calculated using an enhanced proportional-derivative control strategy, and the formula is as follows: ,in For correction factor, For proportional gain, For differential gain, This represents the coupling term gain.

[0119] For example, if the proportional gain is set to 0.5, the differential gain to 0.2, and the coupling term gain to 0.0001, when the deviation is 50 sampling points, the queue depth changes at a rate of 100 sampling points per second, and the error coupling term is 1570, the correction coefficient is calculated as follows: .

[0120] This correction factor was then used to adjust the frequency control word of the numerically controlled oscillator, thereby changing the frequency of the hardware sampling clock and enabling fine control over the data consumption rate.

[0121] In this embodiment, the current queue depth is determined by obtaining the difference between the read and write addresses of the buffer, establishing real-time monitoring of the data flow status. The rate of change of queue depth over time is calculated to obtain the speed of queue depth change, introducing the ability to perceive the dynamic trend of the data flow. An error coupling term is determined by cross-multiplying the speed of queue depth change with the phase gradient, establishing a quantitative relationship between queue dynamic changes and phase influence. Furthermore, a correction coefficient is determined based on the deviation and the error coupling term, achieving a comprehensive consideration of static deviation, dynamic trends, and phase characteristics. In summary, this embodiment significantly improves the accuracy of correction coefficient calculation and the stability of the control system, effectively suppressing control oscillations and phase errors, ensuring high precision and high reliability of remote synchronization signal reconstruction.

[0122] In one embodiment of this invention, the numerically controlled oscillator is a dual-loop numerically controlled oscillator. The main loop of the dual-loop numerically controlled oscillator is used to lock the local second pulse signal, and the secondary loop is used to receive the phase adjustment residual amount determined according to the correction coefficient. The frequency control word of the numerically controlled oscillator is determined based on the correction coefficient, including the following steps: S610. Decompose the correction coefficient into coarse adjustment frequency control quantity and fine adjustment phase residual quantity; S620: Input the coarse adjustment frequency control value into the main loop accumulator of the main loop to track the clock drift relative to the local second pulse signal; S630: Input the fine-tuning phase residual into the secondary loop phase shifter of the secondary loop to perform cycle-by-cycle phase correction; S640. The output of the main loop accumulator and the output of the secondary loop phase shifter are combined to obtain a digital phase step. S650 determines the frequency control word for driving the hardware sampling clock based on the digital phase step size.

[0123] This implementation addresses the trade-off between response speed and control accuracy in single-loop numerically controlled oscillators when handling wide-range frequency adjustments and fine phase corrections. It employs a dual-loop architecture-based control method for the numerically controlled oscillator, decomposing the correction coefficient into coarse and fine adjustment components, processed by the main loop and secondary loop respectively. This effectively balances frequency stability and phase flexibility, resolving the control conflict between wide-range clock frequency drift compensation and rapid phase jitter suppression, thereby improving the dynamic performance of the numerically controlled oscillator and the quality of the output clock.

[0124] Specifically, after obtaining the correction coefficient, the tester first decomposes the correction coefficient into two components: coarse frequency control quantity and fine phase residual quantity, in order to adapt to the control architecture of the dual-loop numerically controlled oscillator.

[0125] The correction factor reflects the total amount of adjustment to the sampling clock frequency, and includes two types of components: one is the long-term stable offset caused by the difference between the clock frequencies of the transmitting and receiving ends; the other is the short-term phase disturbance caused by network transmission delay jitter and rapid fluctuations in queue depth.

[0126] The decomposition is achieved by performing low-pass and high-pass filtering on the correction coefficients. For example, a low-pass filter with an appropriate cutoff frequency is used to extract low-frequency components as coarse-tuning frequency control, while a high-pass filter is used to extract high-frequency components as fine-tuning phase residuals.

[0127] The decomposition formula can be expressed as: ,in For correction factor, For coarse adjustment of frequency control quantity, This is for fine-tuning the phase residual. Coarse-tuning the frequency control quantity reflects the systematic deviation of the clock frequency, while fine-tuning the phase residual reflects rapidly changing phase disturbances. Through classification and decomposition, different processing strategies can be adopted for different control requirements.

[0128] After completing the correction coefficient decomposition, the tester inputs the coarse adjustment frequency control value into the main loop accumulator of the main loop to track the clock drift relative to the local second pulse signal.

[0129] The main loop accumulator performs phase accumulation using a specific frequency control word. The coarse adjustment frequency control value is added to the reference frequency control word as an adjustment value. The formula for the adjusted frequency control word is: ,in The adjusted main loop frequency control word. For reference frequency control word, This is the frequency adjustment proportional coefficient. This is the coarse adjustment frequency control value.

[0130] The frequency adjustment ratio is set according to the system's frequency resolution and control sensitivity. By adjusting the frequency control word of the main loop accumulator, the output frequency of the main loop changes accordingly, thereby stably compensating for systematic deviations in the clock frequency and ensuring the long-term stability of the output clock.

[0131] While the main loop processes the coarse adjustment frequency control quantity, the tester inputs the fine adjustment phase residual quantity into the secondary loop phase shifter of the secondary loop to perform cycle-by-cycle phase correction.

[0132] The secondary loop phase shifter performs fine-tuning of the phase within each clock cycle. The fine-tuning phase residual serves as the control input to the phase shifter, indicating the amount of phase adjustment required each cycle.

[0133] The phase adjustment formula is: ,in This is the phase adjustment amount per cycle. This is the phase adjustment ratio. This is for fine-tuning the phase residual.

[0134] The secondary loop effectively suppresses phase disturbances caused by network transmission delay jitter and rapid queue depth fluctuations, ensuring short-term phase stability of the output clock. Cycle-by-cycle phase correction via the secondary loop avoids the generation of phase accumulation errors.

[0135] After the main loop and the secondary loop have completed their control tasks, the tester synthesizes the output of the main loop accumulator and the output of the secondary loop phase shifter to obtain the final digital phase step.

[0136] The synthesis method is a phase addition operation, and the formula is: ,in This represents the total phase step size after synthesis. The phase step size output by the main loop accumulator. This is the phase adjustment amount output by the secondary loop phase shifter.

[0137] The synthesized total phase step combines the advantages of frequency stability and phase flexibility, enabling it to track long-term clock drift while suppressing short-term phase jitter.

[0138] After obtaining the digital phase step size, the tester determines the frequency control word that drives the hardware sampling clock based on this step size.

[0139] The formula for calculating the frequency control word is: ,in For frequency control word, For digital phase step size, This represents the bit width of the phase accumulator.

[0140] For example, if the digital phase step size is 0.01 radians and the phase accumulator bit width is 32 bits, then the frequency control word is calculated as follows: .

[0141] The frequency control word is fed into the phase accumulator of the numerically controlled oscillator. The formula for calculating the frequency of the hardware sampling clock is: ,in The hardware sampling clock frequency, This refers to the system clock frequency. By dynamically adjusting the frequency control word, the frequency of the hardware sampling clock can precisely follow the data flow requirements, enabling accurate control of the digital-to-analog converter's read rate.

[0142] In this embodiment, a classification processing mechanism for control requirements at different time scales is established by decomposing the correction coefficient into coarse-tuning frequency control and fine-tuning phase residual. Stable compensation for long-term systematic frequency deviations is achieved by inputting the coarse-tuning frequency control into the main loop accumulator to track clock drift. Effective suppression of short-term rapid phase disturbances is achieved by inputting the fine-tuning phase residual into the secondary loop phase shifter to perform cycle-by-cycle phase correction. Phase step size synthesis of the main and secondary loop outputs balances frequency stability and phase flexibility. Furthermore, the frequency control word driving the hardware sampling clock is determined based on the digital phase step size, enabling fine control of data read rate and waveform output characteristics. In summary, this embodiment significantly improves the dynamic performance of the numerically controlled oscillator and the overall quality of the output clock, ensuring high accuracy and long-term stability for remote synchronization signal reconstruction.

[0143] In one embodiment of this invention, after determining the frequency control word for driving the hardware sampling clock based on the digital phase step size, the following steps are further included: S710. Determine the locking state of the main loop based on the phase difference between the local second pulse signal and the main loop. S720. When the locked state is the unlocked state, increase the loop gain of the secondary loop; S730. When the locked state is locked, freeze the fine-tuning phase residual input of the sub-loop; S740, reduce the loop bandwidth of the secondary loop to suppress phase noise; S750: Smoothly transition the frequency control word during the adjustment of loop bandwidth.

[0144] In this embodiment, when the locked state is locked, the following steps can be performed: obtain the pulse width and period stability of the local second pulse signal; determine to enter the hold operation mode when the local second pulse signal is abnormal; freeze the historical average frequency control word of the main loop accumulator in the locked state; switch the phase reference input of the secondary loop to the frequency division output of the local crystal oscillator; adjust the fine-tuning phase residual amount through the secondary loop according to the timestamp difference of the test waveform data packet to maintain synchronous output.

[0145] This implementation addresses the performance optimization issues caused by fixed control parameters in dual-loop numerically controlled oscillators under different operating states. By using a control method that adaptively adjusts loop parameters based on the locked state, the locking state of the main loop is monitored in real time, and the gain and bandwidth parameters of the secondary loop are dynamically adjusted. Combined with a smooth transition strategy during parameter switching, this effectively solves the performance trade-off between locking speed, phase noise suppression, and dynamic response when loop parameters are fixed, thereby improving the overall performance and output clock quality of the numerically controlled oscillator in different operating stages.

[0146] Specifically, during the operation of the numerically controlled oscillator, the tester continuously monitors the locking status of the main loop to determine whether the main loop has successfully locked onto the local second pulse signal.

[0147] The lockout state is determined based on the phase difference between the main loop output phase and the local second pulse signal phase. The main loop phase comparator compares the phase signal generated by the main loop accumulator with the local second pulse signal and outputs a phase error signal. The tester collects phase error values ​​for multiple consecutive cycles and calculates their root mean square value or peak-to-peak value.

[0148] The formula for determining the locked state is: If If the condition is met, the state is considered locked; otherwise, it is considered unlocked. For the first Phase error at each sampling point The number of sampling points. This is a threshold for locking.

[0149] The lockout threshold is set based on the system's phase accuracy requirements. For example, if the root mean square value of the phase error over 100 consecutive sampling points is 0.008 radians and the lockout threshold is 0.01 radians, then the main loop is determined to be in a locked state. Accurate determination of the lockout state allows the system to optimize its control strategy based on the current operating state.

[0150] When the main loop is in an unlocked state, it indicates that the main loop is in the initial locking process or has been disturbed, causing it to lose lock. At this time, the tester increases the loop gain of the secondary loop to improve the secondary loop's response speed to phase errors.

[0151] The increase in the secondary loop gain is achieved by adjusting the control coefficient of the secondary loop phase shifter. The gain adjustment formula is: ,in The adjusted secondary loop gain, This is the nominal secondary loop gain. This is the gain boost factor.

[0152] For example, if the nominal gain is 0.05 and the gain boost factor is set to 1, the adjusted gain will be 0.1. Increasing the secondary loop gain makes the secondary loop more sensitive to the fine-tuning phase residual, enabling it to quickly adjust the phase of the output clock, assisting the main loop in accelerating convergence to the locked state and shortening the lock-in time. Once the main loop reaches the locked state, the secondary loop gain returns to its normal level.

[0153] Once the main loop reaches the locked state, the system enters the steady-state operation phase. The tester freezes the residual phase adjustment input of the secondary loop, that is, it stops inputting new phase adjustment commands to the secondary loop phase shifter.

[0154] The freeze operation is implemented by setting a data gating circuit between the lock state detection module and the secondary loop phase shifter. When the lock state is locked, the gating circuit is closed, blocking the transmission of the fine-tuning phase residual. The secondary loop remains in the state of the last adjustment, avoiding unnecessary phase jitter caused by the introduction of measurement noise into the secondary loop.

[0155] Simultaneously, the tester reduces the loop bandwidth of the secondary loop to further suppress phase noise. The bandwidth adjustment formula is: ,in The adjusted secondary loop bandwidth, The nominal secondary loop bandwidth, This is the bandwidth reduction factor.

[0156] For example, if the nominal bandwidth is 10Hz and the bandwidth reduction factor is set to 0.2, the adjusted bandwidth is 2Hz. After reducing the loop bandwidth, the response of the sub-loop to high-frequency noise is suppressed, the phase noise power spectral density of the output clock is significantly reduced, and the short-term stability is improved.

[0157] During the adjustment of the sub-loop gain and bandwidth, the tester implements a smooth transition strategy.

[0158] A smooth transition is achieved by using a gradual adjustment algorithm, which distributes parameter changes over multiple clock cycles. The gradual adjustment formula is: ,in For the first Parameter values ​​for each period, These are the initial parameter values. For the target parameter value, This represents the number of transition cycles.

[0159] For example, if the sub-loop gain needs to be adjusted from 0.1 to 0.05, and the number of transition cycles is set to 50, then the gain decreases by 0.001 in each cycle, and smoothly transitions to the target value over 50 cycles.

[0160] Meanwhile, a low-pass filter is applied to the digital phase step to achieve a smooth transition of the frequency control word. The filter time constant is matched with the parameter transition period, which effectively avoids transient impacts during parameter switching and ensures the continuity and smoothness of the output clock phase.

[0161] In another embodiment of this invention, after the main loop reaches the locked state, the tester will also monitor the quality of the local second pulse signal. The tester acquires the pulse width and period stability parameters of the local second pulse signal. If the period stability exceeds a preset threshold or the pulse width is abnormal, the local second pulse signal is determined to be abnormal, and the tester controls the system to enter a hold operation mode.

[0162] In the operation mode, the tester first freezes the historical average frequency control word of the main loop accumulator in the locked state. The main loop accumulator continues to operate with this fixed frequency control word to maintain a stable base output frequency.

[0163] At the same time, the tester switches the phase reference input of the secondary loop to the frequency division output of the local crystal oscillator, providing a short-term stable phase reference.

[0164] Furthermore, the tester infers the relative frequency of the transmitting end's clock based on the changes in the timestamp difference of the test waveform data packets, and adjusts the fine-tuning phase residual through the secondary loop to maintain synchronization with the transmitting end. This persistent operation mode ensures continuous synchronous output capability even in cases of abnormal timing signals.

[0165] In this embodiment, an accurate mechanism for judging the system's operating state is established by determining the locking state based on the phase difference between the local second pulse signal and the main loop. Increasing the gain of the secondary loop in the unlocked state improves the phase-locked loop response speed and shortens the system startup and recovery time. Freezing the secondary loop input and reducing the loop bandwidth in the locked state effectively suppresses phase noise and improves the purity and short-term stability of the output clock. Implementing a smooth transition during loop parameter adjustment avoids transient disturbances during parameter switching, ensuring the continuity of waveform output. Furthermore, entering a hold-on operation mode when the local second pulse signal is abnormal ensures continuous operation capability in the event of a timing signal failure. In summary, this embodiment achieves performance optimization of the dual-loop numerically controlled oscillator at different operating stages, ensuring high precision, high stability, and high reliability for remote synchronization signal reconstruction.

[0166] In one embodiment of this invention, the reconstructed data is converted into an analog test signal for output by driving a digital-to-analog converter with a hardware sampling clock, including the following steps: S810 uses a hardware sampling clock-driven digital-to-analog converter to convert reconstructed data into an initial analog signal; S820 performs out-of-band noise filtering on the initial analog signal based on a low-pass filter circuit to obtain a filtered analog signal; S830 performs power amplification on the filtered analog signal based on the power amplifier circuit to obtain the analog test signal and output it.

[0167] In this embodiment, the process of performing out-of-band noise filtering on the initial analog signal based on a low-pass filter circuit to obtain a filtered analog signal may include: extracting the current clock frequency from the hardware sampling clock in real time; calculating a cutoff frequency adjustment code that matches the current clock frequency; sending the cutoff frequency adjustment code to the programmable filtering network of the low-pass filter circuit; synchronously changing the pole positions of the low-pass filter circuit as the hardware sampling clock updates; and filtering out out-of-band switching harmonics generated by the dynamic adjustment of the sampling frequency in the initial analog signal in real time while maintaining the consistency of the passband amplitude-frequency characteristics, thereby obtaining the filtered analog signal.

[0168] This implementation addresses the issues of quantization noise, image frequency, and out-of-band harmonic interference that exist during the conversion of digital reconstructed data into analog test signals. By employing a hardware sampling clock-driven digital-to-analog conversion and multi-stage signal conditioning method, through three cascaded processing stages of digital-to-analog conversion, low-pass filtering, and power amplification, it can effectively solve the problems of signal distortion and noise pollution during the digital-to-analog conversion process, improve the purity, amplitude accuracy, and driving capability of the output analog test signal, and provide a reliable excitation signal for the testing of new energy power station equipment.

[0169] Specifically, after completing the buffering and clock control of the reconstructed data, the tester drives the digital-to-analog converter through hardware sampling clock to convert the reconstructed data into an initial analog signal.

[0170] The digital-to-analog converter (DAC) employs a high-precision parallel input architecture. Its operation involves reading reconstructed data sampling points from a buffer queue when triggered by a hardware sampling clock. The DAC then generates the corresponding analog output based on the weights of each bit of the input digital code.

[0171] The converted initial analog signal presents a stepped waveform, with each step corresponding to the amplitude value of a sampling point. This stepped waveform contains the fundamental component of the original test signal, as well as high-frequency components introduced due to the sampling and quantization processes (such as image frequencies, quantization noise, and switching harmonics). The initial analog signal is then fed into subsequent filtering circuits for conditioning.

[0172] After obtaining the initial analog signal, the tester performs out-of-band noise filtering on the signal through a low-pass filter circuit to obtain a filtered analog signal.

[0173] The low-pass filter circuit uses an active or passive filter structure to filter out out-of-band components such as image frequencies, quantization noise, and switching harmonics in the initial analog signal, while retaining the fundamental frequency and necessary harmonic components of the test signal.

[0174] In this embodiment, the low-pass filter circuit uses a programmable filter network, which can dynamically adjust the cutoff frequency according to the frequency of the hardware sampling clock.

[0175] The tester extracts the current clock frequency from the hardware sampling clock in real time and measures the clock period to calculate the current sampling frequency. Then, it calculates the corresponding cutoff frequency adjustment code based on the sampling frequency, using the following formula: ,in For cutoff frequency adjustment code, The cutoff frequency coefficient, This is the current sampling frequency.

[0176] The adjustment code is sent to the programmable filter network of the low-pass filter circuit, changing the filter's pole positions and cutoff frequency by adjusting the filter's resistor or capacitor values. As the hardware sampling clock updates, the cutoff frequency changes synchronously, ensuring the filter always operates at an appropriate level, filtering out out-of-band switching harmonics in real time, and avoiding the under- or over-filtering problems that may occur with fixed-cutoff-frequency filters when the sampling frequency changes.

[0177] After obtaining the filtered analog signal, the tester amplifies the signal through a power amplifier circuit to obtain an analog test signal with the required driving capability and outputs it.

[0178] The power amplifier circuit employs a structure consisting of a cascaded voltage amplification stage and a current amplification stage. The voltage amplification stage is responsible for amplifying the amplitude of the filtered analog signal to a preset voltage range, and its input is designed with high impedance to avoid causing a load effect on the low-pass filter circuit.

[0179] The current amplification stage is responsible for providing sufficient output current, employing a push-pull output structure or a power amplification structure, to drive the input impedance of the device under test. The power amplifier circuit also includes overcurrent protection and overheat protection circuits to prevent output short circuits or overloads.

[0180] The amplified analog test signal is connected to the device under test through the output port, which can meet the requirements of power frequency signal and its harmonic testing, and ensure the amplitude accuracy and low distortion of the output signal.

[0181] In this embodiment, a basic conversion from the digital domain to the analog domain is achieved by converting the reconstructed data into an initial analog signal using a digital-to-analog converter driven by a hardware sampling clock. Out-of-band noise filtering is performed using a low-pass filter circuit, effectively filtering out image frequencies, quantization noise, and switching harmonics. Specifically, by calculating the cutoff frequency adjustment code in real time based on the hardware sampling clock frequency and dynamically adjusting the programmable filter network, synchronous optimization of the filter poles and sampling frequency is achieved, ensuring consistent filtering performance under dynamic changes in the sampling frequency. Furthermore, voltage and current amplification is performed using a power amplifier circuit, improving the signal's driving capability and anti-interference performance. In summary, this embodiment ensures high quality in terms of amplitude accuracy, spectral purity, and driving capability of the output analog test signal, providing a reliable excitation signal for performance testing of new energy power plants.

[0182] This application embodiment also provides a new energy power station testing instrument, including: The memory is configured to store instructions; and The processor is configured to retrieve the instructions from the memory and, when executing the instructions, to implement the aforementioned time-stamp-based remote synchronization signal reconstruction output method.

[0183] Reference Figure 3 This application also provides a remote collaborative testing system, including: Remote sending end; Multiple new energy power station testing instruments; The remote transmitter is wirelessly connected to each new energy power station tester. The remote transmitter is used to send test waveform data packets to each new energy power station tester, and each new energy power station tester is used to receive the test waveform data packets and reconstruct and output the corresponding analog test signal.

[0184] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0185] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0186] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0187] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0188] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0189] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0190] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0191] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0192] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A time-scaled method for reconstructing and outputting a remotely synchronized signal, characterized in that, Applied to a new energy power station testing instrument, which includes a numerically controlled oscillator and a digital-to-analog converter, the method includes: Acquire the test waveform data packets with timestamps sent by the remote sender and the local second pulse signal; Based on the timestamp of the test waveform data packet and the local second pulse signal, waveform phase reconstruction is performed to obtain reconstructed data; Obtain the queue depth of the cache containing the reconstructed data, and determine the phase gradient of the reconstructed data when the queue depth deviates from the preset center. The correction coefficient is determined based on the queue depth and phase gradient; The frequency control word of the numerically controlled oscillator is determined based on the correction coefficient, and the hardware sampling clock of the numerically controlled oscillator is controlled based on the frequency control word. The reconstructed data is converted into an analog test signal for output by a digital-to-analog converter driven by a hardware sampling clock.

2. The method according to claim 1, characterized in that, After determining the correction coefficients based on the queue depth and phase gradient, the following is included: The dynamic pointer offset step size is determined based on the correction factor; The index position is determined based on the dynamic pointer offset step size; Linear phase interpolation is performed between adjacent data points on both sides of the index position to obtain virtual sampling points; When the queue depth is lower than the preset center, insert virtual sampling points into the data queue; When the queue depth is higher than the preset central value, the data queue is subjected to phase-preserving extraction and filtering.

3. The method according to claim 1, characterized in that, Based on the timestamp of the test waveform data packet and the local second pulse signal, waveform phase reconstruction is performed to obtain reconstructed data, including: Obtain the sender timestamp and local arrival timestamp of the test waveform data packet; The transmission time difference is determined based on the sender's timestamp and the local arrival timestamp, and a high-frequency local counter value aligned with the local second pulse signal is latched. The phase offset angle relative to the local second pulse signal is determined based on the transmission time difference and the high-frequency local counter value; The discrete waveform sequence is obtained by indexing and mapping the preset sine waveform lookup table according to the phase offset angle, and then output as the reconstructed data.

4. The method according to claim 3, characterized in that, Before indexing and mapping the preset sine waveform lookup table according to the phase offset angle, the following steps are included: Obtain the time difference change of continuous test waveform data packets within the arrival window; Perform recursive sliding window mid-range filtering on the time difference variation to separate out systematic transmission delay; The linear phase drift slope is determined based on the systematic transmission delay; The predicted phase advance for the next frame period is determined based on the linear phase drift slope. The initial phase of the preset sine wave lookup table is compensated based on the predicted phase advance.

5. The method according to claim 1, characterized in that, The correction coefficients are determined based on the queue depth and phase gradient, including: Obtain the difference between the read and write addresses in the buffer to determine the current queue depth; Determine the rate of change of the current queue depth over time to obtain the speed of change of the queue depth; The error coupling term is determined by cross-multiplying the queue depth change rate with the phase gradient; The correction coefficient is determined based on the deviation of the current queue depth from the preset center and the error coupling term.

6. The method according to claim 1, characterized in that, The numerically controlled oscillator is a dual-loop numerically controlled oscillator. The main loop of the dual-loop numerically controlled oscillator is used to lock the local second pulse signal, and the secondary loop is used to receive the phase adjustment residual determined according to the correction coefficient. Based on the correction coefficient, the frequency control word of the numerically controlled oscillator is determined, including: The correction coefficient is decomposed into coarse frequency control quantity and fine phase residual quantity; The coarse adjustment frequency control value is input to the main loop accumulator of the main loop to track the clock drift relative to the local second pulse signal; The residual fine-tuning phase is input into the secondary loop phase shifter of the secondary loop to perform cycle-by-cycle phase correction; The output of the main loop accumulator and the output of the secondary loop phase shifter are combined by phase step size synthesis to obtain the digital phase step size; The frequency control word for driving the hardware sampling clock is determined based on the digital phase step size.

7. The method according to claim 6, characterized in that, After determining the frequency control word that drives the hardware sampling clock based on the digital phase step size, the following is also included: The locking state of the main loop is determined based on the phase difference between the local second pulse signal and the main loop. When the locked state is the unlocked state, increase the loop gain of the secondary loop; When the lock state is locked, the fine-tuning phase residual input of the sub-loop is frozen; Reduce the loop bandwidth of the secondary loop to suppress phase noise; Smoothly transition the frequency control word during the adjustment of the loop bandwidth.

8. The method according to claim 1, characterized in that, The reconstructed data is converted into an analog test signal for output by a hardware sampling clock-driven digital-to-analog converter, including: The reconstructed data is converted into an initial analog signal by a hardware sampling clock-driven digital-to-analog converter. The initial analog signal is filtered for out-of-band noise by using a low-pass filter circuit to obtain the filtered analog signal. The filtered analog signal is amplified by a power amplifier circuit to obtain an analog test signal, which is then output.

9. A new energy power station testing instrument, characterized in that, include: The memory is configured to store instructions; as well as A processor is configured to retrieve the instructions from the memory and, when executing the instructions, to implement the time-stamp-based remote synchronization signal reconstruction output method according to any one of claims 1 to 8.

10. A remote collaborative testing system, characterized in that, include: Remote sending end; Multiple new energy power station testing instruments as described in claim 6; The remote transmitter is wirelessly connected to each new energy power station tester. The remote transmitter is used to send test waveform data packets to each new energy power station tester, and each new energy power station tester is used to receive the test waveform data packets and reconstruct and output the corresponding analog test signal.

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