A small step low phase noise wideband direct synthesis frequency source

Abstract

The application provides a small-step low-phase-noise wideband direct synthesis frequency source, and relates to the technical field of a synthesis frequency source.The target frequency is input into a preset discrete model for decomposition, the frequency deviation distance between the third-order intermodulation spurious frequency and the cutoff frequency of a filter amplification circuit is calculated, and the optimal parameter combination is obtained by optimizing the frequency deviation distance maximization principle, so that the small-step signal output is ensured, and the risk of spurious falling into the passband is reduced;the overall timing is dispatched by adopting a three-section control method through a timing control module, so that smooth transition during frequency switching is ensured, and the risk of out-of-band power overshoot and spurious pollution is reduced;finally, the frequency synthesis module performs multi-stage frequency division and multi-stage frequency mixing under the condition of no phase-locked loop, so that the low phase noise in the frequency hopping process is reduced, the dependence on complex filter devices is reduced, and the anti-interference ability of the synthesis frequency source in the wideband environment is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of synthesized frequency source technology, specifically to a small-step, low-phase-noise, broadband direct synthesized frequency source. Background Technology

[0002] In modern electronic warfare, frequency-hopping radar, and high-speed wireless communication systems, the frequency synthesis source, as a core component, directly determines the anti-jamming capability and target detection accuracy of the entire system through its frequency hopping speed, spectral purity, and phase noise performance. With the increasing complexity of microwave warfare environments, systems require frequency sources to cover ultra-wideband frequencies while possessing microsecond-level ultra-fast frequency hopping capabilities and extremely low phase noise. Existing frequency synthesis schemes are mainly divided into phase-locked loop (PLL) frequency synthesis and direct frequency synthesis. While PLL-based frequency sources can achieve good spurious suppression capabilities, their frequency switching response is typically on the order of milliseconds due to limitations in PLL bandwidth and narrowband integral filter settling time. This cannot meet the microsecond-level ultra-fast and agile frequency hopping requirements of modern microwave systems. Furthermore, during multi-stage frequency multiplication, division, and mixing in the ultra-wideband range, the nonlinear characteristics of semiconductor devices inevitably introduce a large amount of high-order intermodulation spurious signals, especially those near the passband edge, which are difficult to filter out. This necessitates the use of more complex filtering components, significantly increasing both system size and manufacturing costs.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a small-step, low-phase-noise, broadband direct-synthesized frequency source to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A small-step, low-phase-noise, broadband direct-synthesizing frequency source, specifically comprising: The frequency decomposition module is used to decompose the received target frequency input into a preset discrete model to obtain several sets of candidate solutions composed of the frequency division coefficients of the frequency division circuit and the signal frequency of the DDS circuit. A spurious optimization module is used to sequentially calculate the frequency offset distance corresponding to each candidate solution in the candidate solution set, and to optimize according to the principle of maximizing the frequency offset distance to obtain the optimal parameter combination. The frequency synthesis module includes a crystal oscillator unit, a comb frequency multiplier circuit, a mixer group, a frequency divider circuit group, a DDS circuit, and a filter amplifier circuit group. It is used to perform multi-stage frequency division and multi-stage frequency mixing with the optimal parameter combination as a reference under the condition of no phase-locked loop, so as to generate an output signal that meets the target frequency.

[0006] Preferably, the mixer group includes a first mixer, a second mixer, and a third mixer; the frequency divider circuit group includes a first frequency divider circuit, a second frequency divider circuit, and a third frequency divider circuit; and the filter amplifier circuit group includes a first filter amplifier circuit, a second filter amplifier circuit, and a third filter amplifier circuit.

[0007] Preferably, the operating logic of the frequency synthesis module is as follows: The crystal oscillator unit generates a low-frequency reference signal. After the reference signal is amplified by the comb frequency multiplier circuit, a high-frequency point frequency signal is obtained. The point frequency signal is then divided into four paths and labeled as the first to fourth point frequency signals in sequence. The first frequency signal is divided by the first frequency divider circuit to obtain the reference radio frequency standard signal for the DDS circuit. The DDS circuit generates a small step frequency hopping intermediate frequency signal based on the reference radio frequency standard signal. The second frequency signal is divided by the second frequency divider circuit to obtain the large step frequency hopping frequency mark signal. The large step frequency hopping frequency mark signal and the fourth frequency signal are then combined by the first mixer and the first filter amplifier circuit to generate the large step radio frequency mark signal. The third frequency signal is divided by the third frequency divider circuit to obtain a large step frequency hopping intermediate frequency signal. The large step frequency hopping intermediate frequency signal and the small step frequency hopping intermediate frequency signal are then combined by the second mixer and the second filter amplifier circuit to generate a wideband intermediate frequency signal. The large-step RF frequency standard signal and the broadband intermediate frequency signal are combined through a third mixer and a third filter amplifier circuit to generate the final output signal.

[0008] Preferably, the division coefficient of the first frequency divider circuit is a preset fixed value, and the division coefficients of the second frequency divider circuit and the third frequency divider circuit are selected from a preset set of coefficients, and the set of coefficients consists of several sets of fixed values. The large-step radio frequency standard signal is the difference frequency signal between the fourth point frequency signal and the large-step frequency hopping frequency standard signal; the wideband intermediate frequency signal is the sum frequency signal between the large-step frequency hopping intermediate frequency signal and the small-step frequency hopping intermediate frequency signal; and the output signal is the sum frequency signal between the large-step radio frequency standard signal and the wideband intermediate frequency signal. The discrete model is obtained by reverse modeling the working logic of the frequency synthesis module, and each candidate solution in the candidate solution set includes a combination composed of the frequency division coefficients of the second frequency division circuit and the third frequency division circuit, as well as the signal frequency of the small step frequency hopping intermediate frequency signal.

[0009] Preferably, the working principle of the stray optimization module is as follows: For each candidate solution, calculate the large-step RF frequency standard signal and the broadband intermediate frequency signal under that candidate solution to obtain the third-order intermodulation spurious frequency when the output signal is output. Calculate the absolute difference between the third-order intermodulation spurious frequency and the cutoff frequency of the third filter amplifier circuit to obtain the frequency offset distance corresponding to the candidate solution; Iterate through each candidate solution in the candidate solution set, and define the candidate solution with the largest frequency offset distance as the optimal parameter combination.

[0010] Preferably, the third-order intermodulation spurious frequency is the absolute difference between the signal frequency of twice the large-step radio frequency standard signal and the signal frequency of the broadband intermediate frequency signal.

[0011] Preferably, the frequency synthesis module further includes a timing control module, which is used to perform timing control on the synthesized frequency source as a whole.

[0012] Preferably, the timing control module adopts a three-stage control method, and its specific working logic is as follows: In the first timing stage, gating control signals are sent to the first filter amplifier circuit, the second filter amplifier circuit, and the third filter amplifier circuit to establish filter channels; In the second timing stage, the two frequency division coefficients in the optimal parameters are converted into corresponding coefficient control signals and then sent to the second frequency division circuit and the third frequency division circuit respectively. In the third timing stage, the signal frequency of the small-step frequency hopping intermediate frequency signal in the optimal parameters is converted into a frequency control signal and then sent to the DDS circuit.

[0013] Preferably, the frequency synthesis module further includes a first power divider circuit and a second power divider circuit. The first power divider circuit is used to divide the reference signal generated by the crystal oscillator unit into two paths, one of which enters the comb frequency multiplier circuit for amplification, and the other of which enters the timing control module as a clock reference. The second power divider circuit is used to divide the point frequency signal into four paths.

[0014] Compared with the prior art, the beneficial effects of the present invention are: This invention decomposes the target frequency into a preset discrete model to obtain a candidate solution set composed of frequency division coefficients and signal frequencies. It then calculates the frequency offset distance between the third-order intermodulation spurious frequency and the cutoff frequency of the filter amplifier circuit. Finally, it optimizes the parameter combination by maximizing the frequency offset distance. This ensures small-step signal output while reducing the risk of spurious signals falling into the passband, thus significantly improving the spectral purity of the full-band output signal. Furthermore, the timing control module employs a three-stage control method to schedule the overall timing, following the steps of establishing the filter channel and converting the frequency division coefficients. The sequence of transmitted frequency control signals is controlled sequentially to ensure a smooth transition during frequency switching, reducing the risk of out-of-band power overshoot and dynamic spurious pollution. Finally, through the synergistic effect of the crystal oscillator unit, comb frequency multiplier circuit, mixer group, frequency divider circuit group, DDS circuit and filter amplifier circuit group, the optimal parameter combination is used for multi-stage frequency division and multi-stage mixing under phase-locked loop conditions. This not only maintains low phase noise during high-speed frequency hopping, but also reduces the dependence on complex filtering devices, thereby greatly improving the anti-interference capability and engineering reliability of the synthesized frequency source in a broadband environment. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall modular structure of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the frequency synthesis module in this invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0017] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0018] Example: Please see Figures 1-2 The present invention provides a technical solution: A small-step, low-phase-noise, broadband direct-synthesizing frequency source specifically includes: a frequency decomposition module, a spurious optimization module, and a frequency synthesis module.

[0019] The frequency decomposition module is used to decompose the received target frequency input into a preset discrete model to obtain several sets of candidate solutions composed of the frequency division coefficients of the frequency division circuit and the signal frequency of the DDS circuit.

[0020] The spurious optimization module is used to calculate the frequency offset distance corresponding to each candidate solution in the candidate solution set in turn, and to optimize the optimal parameter combination by maximizing the frequency offset distance. The frequency synthesis module includes a crystal oscillator unit, a comb frequency multiplier circuit, a mixer group, a frequency divider circuit group, a DDS circuit, and a filter amplifier circuit group. It is used to perform multi-stage frequency division and multi-stage frequency mixing with the optimal parameter combination as a reference under the condition of no phase-locked loop, so as to generate an output signal that meets the target frequency.

[0021] The mixer group includes a first mixer, a second mixer, and a third mixer; the frequency divider circuit group includes a first frequency divider circuit, a second frequency divider circuit, and a third frequency divider circuit; and the filter amplifier circuit group includes a first filter amplifier circuit, a second filter amplifier circuit, and a third filter amplifier circuit.

[0022] The frequency synthesis module also includes a first power divider circuit and a second power divider circuit. The first power divider circuit is used to divide the reference signal generated by the crystal oscillator unit into two paths. One path enters the comb frequency multiplier circuit for amplification, and the other path enters the timing control module as a clock reference. The second power divider circuit is used to divide the point frequency signal into four paths.

[0023] The working logic of the frequency synthesis module is as follows: The crystal oscillator unit generates a low-frequency reference signal. Reference signal The high-frequency point frequency signal is obtained after amplification by the spectrum multiplier circuit. and the point frequency signal Divided into four channels, sequentially labeled as the first to fourth frequency signals, denoted as... ; First frequency signal After frequency division by the first frequency divider circuit, the reference RF frequency standard signal used by the DDS circuit is obtained. The DDS circuit is based on the reference radio frequency standard signal. Generate small-step frequency hopping intermediate frequency signal ; Second frequency signal After frequency division by the second frequency divider circuit, a large-step frequency hopping frequency standard signal is obtained. and the large step frequency hopping frequency standard signal With the fourth point frequency signal After being processed by the first mixer and the first filter amplifier circuit, a large-step radio frequency standard signal is generated. And large step radio frequency standard signal The fourth frequency signal With large step frequency hopping frequency standard signal The difference frequency signal between them, that is: Among them, the large step frequency hopping frequency mark signal It can also be expressed in the following form: In the formula These represent the division coefficients of the second frequency divider circuit, and these signal identifiers (e.g., ...) are used during formula calculations. , (e.g., ) indicates the signal frequency of the corresponding signal; Therefore, large step radio frequency standard signals Ultimately, it can be expressed as: Third frequency signal After frequency division by the third frequency divider circuit, a large-step frequency-hopping intermediate frequency signal is obtained. and the large step frequency hopping intermediate frequency signal With small step frequency hopping intermediate frequency signal After being processed by the second mixer and the second filter amplifier circuit, a wideband intermediate frequency signal is generated. Broadband intermediate frequency signal For large step frequency hopping intermediate frequency signals With small step frequency hopping intermediate frequency signal The sum-frequency signal between them, that is: Among them, the large step frequency hopping intermediate frequency signal It can also be expressed in the following form: In the formula This represents the frequency division coefficient of the second frequency divider circuit; Large step radio frequency standard signal With broadband intermediate frequency signal The final output signal is generated after the third mixer and the third filter amplifier circuit work together. and output signal Large step radio frequency standard signal With broadband intermediate frequency signal The sum-frequency signal between them, that is: The division coefficient of the first frequency divider circuit is a preset fixed value. The division coefficients of the second and third frequency divider circuits are selected from a preset set of coefficients, and the set of coefficients consists of several sets of fixed values.

[0024] As can be seen from the above description, unlike existing frequency synthesizers, the frequency synthesis module in this scheme adopts a phase-locked loop (PLL)-free design. This is because PLLs require time to lock during frequent switching, and high harmonics degrade phase noise. This scheme uses a crystal oscillator to generate the signal for direct spectrum combing, and then employs a hardware circuit structure for frequency division combined with DDS circuit conditioning. The switching frequency is then only affected by the digital logic of the signal and the switching speed of the switching filter, thus greatly improving the frequency hopping switching speed. The first frequency divider circuit provides a reference signal for the DDS circuit as a sampling clock; therefore, the division coefficient is usually set to a fixed value. The second and third frequency divider circuits are mainly for achieving wideband frequency hopping at multiple frequency points in the frequency domain, equivalent to "coarse adjustment" and "fine adjustment," respectively. Therefore, the corresponding division coefficients are usually set to several sets of discrete integer values. In this embodiment, assuming the final output signal frequency is between 10.85 GHz and 13.1 GHz, the reference signal generated by the crystal oscillator... It can be set to 100MHz, and after passing through a 108-fold frequency multiplier circuit, a 10.8GHz point frequency signal is obtained. The division factor of the first frequency divider circuit is set to 3, resulting in a 3.6 GHz reference radio frequency standard signal. To avoid spurious superposition and aliasing in the DDS circuit, the output frequency of the DDS is limited to between 15% and 22%, i.e., 0.5 GHz to 0.8 GHz. The division factor of the second frequency divider circuit is set to... One of them can output one of 9.0GHz, 9.257GHz, 9.45GHz, and 9.6GHz respectively. The division factor of the third frequency divider circuit is set to It can output one of 2.7GHz, 1.8GHz, and 1.35GHz respectively. By combining the coarse adjustment of the second frequency divider circuit with the fine adjustment of the third frequency divider circuit and the DDS circuit, the entire frequency band of 10.85GHz to 13.1GHz can be fully covered.

[0025] The discrete model is obtained by reverse-engineering the operating logic of the frequency synthesis module. Each candidate solution in the candidate solution set includes a combination of the division coefficients of the second and third frequency divider circuits and the signal frequency of the small-step frequency hopping intermediate frequency signal. The discrete model essentially involves reverse-engineering the operating logic of the frequency synthesis module; that is, first determining the frequency of the output signal, and then reverse-engineering the division coefficients of the second and third frequency divider circuits and the signal frequency of the DDS circuit. It can be expressed in the following form: Due to the third frequency signal and the fourth frequency signal Compared with the initial point frequency signal Since they are the same, the formula can be simplified to: Understandably, even for the same There may be different , , Since the combination of these can be achieved, there are naturally several different candidate solutions. By classifying these candidate solutions together, we can obtain the candidate solution set.

[0026] The working principle of the stray optimization module is as follows: For each candidate solution, calculate the large-step RF frequency standard signal and the broadband intermediate frequency signal under that candidate solution, that is, through... , The two parameters were calculated to obtain The third-order intermodulation spurious frequency of the output signal is obtained by using a formula based on the nonlinear theory of microwave radio frequency circuits. Since this is existing technology, the specific derivation process will not be elaborated here. The final calculation formula is as follows: In the formula Indicates the third-order intermodulation spurious frequency; Next, the absolute difference between the third-order intermodulation spurious frequency and the cutoff frequency of the third filter amplifier circuit is calculated to obtain the frequency offset distance corresponding to the candidate solution. The third-order intermodulation spurious frequency is the absolute difference between the signal frequency of twice the large-step RF frequency standard signal and the signal frequency of the broadband intermediate frequency signal. The calculation formula is expressed as: In the formula Indicates frequency offset distance. This indicates the cutoff frequency of the third filter amplifier circuit; Iterate through each candidate solution in the candidate solution set, and define the candidate solution with the largest frequency offset distance as the optimal parameter combination.

[0027] Understandably, as a nonlinear device, a mixer will inevitably produce high-order combination products when mixing large-step RF standard signals and broadband IF signals, the strongest of which is third-order intermodulation spurious. In practical terms, this reflects the frequency offset between the third-order intermodulation spurious signal and the cutoff frequency of the last stage switching filter in the third-stage filtering amplifier circuit. If the frequency of the third-order intermodulation spurious signal is far from the cutoff frequency, the filtering circuit can easily filter it out. Conversely, if the frequency of the third-order intermodulation spurious signal falls near the cutoff frequency, it will be extremely difficult to filter out and easily pollute the spectrum of the output signal. This is why it is necessary to... As a quantitative indicator for judging the quality of candidate solutions, and with Maximizing is the optimization objective, and by maximizing... This ensures that spurious signals entering the third filter amplifier circuit are located far from the stopband. Therefore, the third filter amplifier circuit can employ a smaller, simpler switching filter, further reducing the overall size of the frequency source. The entire optimization process involves only simple algebraic operations, excluding complex algorithms and solving high-order equations. The response speed is extremely fast, and this "calculation-first" approach obtains the most suitable set of parameters before the signal is even output. This effectively transforms the passive filtering process in traditional frequency hopping into active avoidance, further improving the overall performance of the frequency source.

[0028] The frequency synthesis module also includes a timing control module, which is used to perform timing control on the entire synthesized frequency source. The timing control module employs a three-stage control method, and its specific working logic is as follows: In the first timing stage, gating control signals are sent to the first filter amplifier circuit, the second filter amplifier circuit, and the third filter amplifier circuit to establish filter channels; In the second timing stage, the two frequency division coefficients in the optimal parameters are converted into corresponding coefficient control signals and then sent to the second frequency division circuit and the third frequency division circuit respectively. In the third timing stage, the signal frequency of the small-step frequency hopping intermediate frequency signal in the optimal parameters is converted into a frequency control signal and then sent to the DDS circuit.

[0029] In traditional PLL frequency hopping control, control signals for the switching filters and frequency dividers in the filtering and amplification circuit, as well as the DDS frequency control word, are typically issued simultaneously within the same clock cycle. This approach can easily lead to out-of-band power overshoot or out-of-band spurious signals in the output signal. In this solution, the phase-locked loop (PLL) is omitted to achieve a faster response speed. Therefore, it is even more crucial to ensure signal purity through timing control. By employing time-division multiplexing timing, it is ensured that the selected switching filters are all in a stable closed state before signal output, and the frequency divider is also in a defined division state. This not only makes the signal after frequency hopping purer but also reduces high VSWR reflections caused by floating or unclosed switching filters, thus protecting the components in each filtering and amplification circuit.

[0030] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0031] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented in software, the above embodiments can be implemented, in whole or in part, as a computer program product. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution.

[0032] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0033] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A small-step, low-phase-noise, broadband direct-synthesizing frequency source, characterized in that, Specifically, it includes: The frequency decomposition module is used to decompose the received target frequency input into a preset discrete model to obtain several sets of candidate solutions composed of the frequency division coefficients of the frequency division circuit and the signal frequency of the DDS circuit. A spurious optimization module is used to sequentially calculate the frequency offset distance corresponding to each candidate solution in the candidate solution set, and to optimize according to the principle of maximizing the frequency offset distance to obtain the optimal parameter combination. The frequency synthesis module includes a crystal oscillator unit, a comb frequency multiplier circuit, a mixer group, a frequency divider circuit group, a DDS circuit, and a filter amplifier circuit group. It is used to perform multi-stage frequency division and multi-stage frequency mixing with the optimal parameter combination as a reference under the condition of no phase-locked loop, so as to generate an output signal that conforms to the target frequency.

2. The small-step, low-phase-noise, broadband direct-synthesizing frequency source according to claim 1, characterized in that: The mixer group includes a first mixer, a second mixer, and a third mixer; the frequency divider circuit group includes a first frequency divider circuit, a second frequency divider circuit, and a third frequency divider circuit; and the filter amplifier circuit group includes a first filter amplifier circuit, a second filter amplifier circuit, and a third filter amplifier circuit.

3. The small-step, low-phase-noise, broadband direct-synthesizing frequency source according to claim 2, characterized in that: The operating logic of the frequency synthesis module is as follows: The crystal oscillator unit generates a low-frequency reference signal. After the reference signal is amplified by the comb frequency multiplier circuit, a high-frequency point frequency signal is obtained. The point frequency signal is then divided into four paths and labeled as the first to fourth point frequency signals in sequence. The first frequency signal is divided by the first frequency divider circuit to obtain the reference radio frequency standard signal for the DDS circuit. The DDS circuit generates a small step frequency hopping intermediate frequency signal based on the reference radio frequency standard signal. The second frequency signal is divided by the second frequency divider circuit to obtain a large step frequency hopping frequency mark signal. The large step frequency hopping frequency mark signal and the fourth frequency signal are then combined by the first mixer and the first filter amplifier circuit to generate a large step radio frequency mark signal. The third frequency signal is divided by the third frequency divider circuit to obtain a large step frequency hopping intermediate frequency signal. The large step frequency hopping intermediate frequency signal and the small step frequency hopping intermediate frequency signal are then combined by the second mixer and the second filter amplifier circuit to generate a wideband intermediate frequency signal. The large-step RF frequency standard signal and the broadband intermediate frequency signal are combined through a third mixer and a third filter amplifier circuit to generate the final output signal.

4. The small-step, low-phase-noise, broadband direct-synthesizing frequency source according to claim 3, characterized in that: The division coefficient of the first frequency divider circuit is a preset fixed value, and the division coefficients of the second and third frequency divider circuits are selected from a preset set of coefficients, and the set of coefficients consists of several sets of fixed values. The large-step radio frequency standard signal is the difference frequency signal between the fourth point frequency signal and the large-step frequency hopping standard signal; the broadband intermediate frequency signal is the sum frequency signal between the large-step frequency hopping intermediate frequency signal and the small-step frequency hopping intermediate frequency signal; and the output signal is the sum frequency signal between the large-step radio frequency standard signal and the broadband intermediate frequency signal. The discrete model is obtained by reverse modeling the working logic of the frequency synthesis module, and each candidate solution in the candidate solution set includes a combination composed of the frequency division coefficients of the second frequency division circuit and the third frequency division circuit, as well as the signal frequency of the small step frequency hopping intermediate frequency signal.

5. A small-step, low-phase-noise, broadband direct-synthesizing frequency source according to claim 4, characterized in that: The working principle of the stray optimization module is as follows: For each candidate solution, calculate the large-step RF frequency standard signal and the broadband intermediate frequency signal under that candidate solution to obtain the third-order intermodulation spurious frequency when the output signal is output. Calculate the absolute difference between the third-order intermodulation spurious frequency and the cutoff frequency of the third filter amplifier circuit to obtain the frequency offset distance corresponding to the candidate solution; Iterate through each candidate solution in the candidate solution set, and define the candidate solution with the largest frequency offset distance as the optimal parameter combination.

6. The small-step, low-phase-noise, broadband direct-synthesizing frequency source according to claim 5, characterized in that: The third-order intermodulation spurious frequency is the absolute difference between the signal frequency of twice the large-step radio frequency standard signal and the signal frequency of the broadband intermediate frequency signal.

7. A small-step, low-phase-noise, broadband direct-synthesizing frequency source according to claim 5, characterized in that: The frequency synthesis module also includes a timing control module, which is used to perform timing control on the synthesized frequency source as a whole.

8. A small-step, low-phase-noise, broadband direct-synthesizing frequency source according to claim 7, characterized in that: The timing control module adopts a three-stage control method, and its specific working logic is as follows: In the first timing stage, gating control signals are sent to the first filter amplifier circuit, the second filter amplifier circuit, and the third filter amplifier circuit to establish filter channels; In the second timing stage, the two frequency division coefficients in the optimal parameters are converted into corresponding coefficient control signals and then sent to the second frequency division circuit and the third frequency division circuit respectively. In the third timing stage, the signal frequency of the small-step frequency hopping intermediate frequency signal in the optimal parameters is converted into a frequency control signal and then sent to the DDS circuit.

9. A small-step, low-phase-noise, broadband direct-synthesizing frequency source according to claim 7, characterized in that: The frequency synthesis module also includes a first power divider circuit and a second power divider circuit. The first power divider circuit is used to divide the reference signal generated by the crystal oscillator unit into two paths, one of which enters the comb frequency multiplier circuit for amplification, and the other of which enters the timing control module as a clock reference. The second power divider circuit is used to divide the point frequency signal into four paths.

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