Reducing harmonic distortion in high-speed precision digital-to-analog converters
Patent Information
- Application Number
- CN202610468949.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-11-28
- Filing Date
- 2026-04-10
- Publication Date
- 2026-10-27
Smart Images
Figure CN122993706A_ABST
Abstract
Description
Cross-references to related applications
[0001] This application claims the benefit of Indian Patent Application No. IN 202541039833, filed on April 25, 2025, which is hereby incorporated herein by reference.
[0002] This application relates to and is associated with U.S. Patent Application No. 19 / 403,446, filed on the same day, entitled “Reducing Harmonic Distortion in High-Speed Precision Digital-to-Analog Converters,” and with Attorney’s Case No. T107218, which is hereby incorporated herein by reference. Technical Field
[0003] This disclosure generally relates to electronic systems and methods, and in certain embodiments, to reducing harmonic distortion in high-speed precision digital-to-analog converters (DACs). Background Technology
[0004] Many applications in modern electronic circuits require the conversion of digital data into analog signals. A circuit called a digital-to-analog converter (DAC) typically receives digital input words or codes from a data stream and generates a corresponding analog output signal that reflects the code values in the input data stream. The bit width of the input code, and therefore the precision of the DAC output signal, can vary depending on the system application.
[0005] Precision digital-to-analog converter (DAC) circuits are commonly used in applications such as instrumentation and control, signal generation or synthesis, biasing circuits, and calibration. Some applications may have very stringent performance requirements. For example, a precision DAC may be required to convert up to 20 bits of digital data into high-frequency (e.g., 100 kHz) analog signals. Harmonic distortion of the synthesized analog output signal is a significant problem, especially in test and measurement applications. Summary of the Invention
[0006] According to an embodiment, a digital-to-analog converter circuit includes: a thermometer segment corresponding to a number of T input bits and having a first output terminal and a second output terminal, the thermometer segment comprising: a first plurality of resistors, the number of which is M, where M is at least 2T, each of the first plurality of resistors being coupled to a first reference voltage terminal, the first plurality of resistors having substantially equal resistance to each other; and a first plurality of switches, the number of which is at least 2T, each of the first plurality of switches being associated with and coupled on one side to a corresponding one of the first plurality of resistors, each of the first plurality of switches being configured to, in response to a control signal of the switch, couple its associated resistor to the first output terminal or the second output terminal; and an output amplifier having an input coupled to the first output terminal.
[0007] According to an embodiment, a digital-to-analog converter circuit includes: a binary segment having a first output terminal and a second output terminal, the binary segment comprising one or more slices, each slice corresponding to one of the number B input bits of the input code, each slice comprising: a first plurality of resistors, each coupled to a first reference voltage terminal, the first plurality of resistors having substantially equal resistances to each other; a first plurality of switches, each associated with and coupled to a corresponding one of the first plurality of resistors, each of the first plurality of switches being configured to, in response to a control signal of the switch, select either the first output terminal or the second output terminal to couple to its associated resistor; a second plurality of resistors, each coupled to a second reference voltage terminal, the second plurality of resistors having substantially equal resistances to each other and substantially equal to the resistances of the first plurality of resistors associated with their respective positions; and a second plurality of switches, each associated with and coupled to a corresponding one of the second plurality of resistors on one side, each of the second plurality of switches being configured to, in response to a control signal of the switch, select either the first output terminal or the second output terminal to couple to its associated resistor; a second plurality of resistors, each associated with and coupled to a corresponding one of the second plurality of resistors on one side, each of the second plurality of switches being configured to, in response to a control signal of the switch, select either the first output terminal or the second output terminal to couple to its associated resistor; a second plurality of resistors, each having substantially equal resistances to each other and substantially equal to the resistances of the first plurality of resistors associated with its position; and a second plurality of switches ... An associated resistor is coupled to either the first output terminal or the second output terminal; an output amplifier having an input coupled to the first output terminal; and switching logic having an input configured to receive B input bits of the input code and configured to provide control signals to the first plurality of switches and the second plurality of switches of each slice of the binary segment, in response to the input bit corresponding to the slice having a first logic state, coupling a single resistor of the first plurality of resistors to the first output terminal and coupling the other resistors of the first plurality of resistors and each of the second plurality of resistors to the second output terminal, and in response to the input bit corresponding to the slice having a second logic state, coupling a single resistor of the second plurality of resistors to the first output terminal and coupling the other resistors of the second plurality of resistors and each of the first plurality of resistors to the second output terminal; wherein the resistance of each of the first plurality of resistors and the second plurality of resistors of each slice is twice the resistance of the resistor of the slice corresponding to the next most significant input bit of the input code.
[0008] According to an embodiment, a digital-to-analog converter circuit includes: a thermometer segment having a first output terminal and a second output terminal, and further including: a plurality of slices, numbered T, wherein each slice includes a plurality of elements of number M, each element being coupled to a first reference voltage terminal and having substantially equal resistance to each other; an output amplifier having a first input coupled to the first output terminal; and switching logic coupled to the plurality of slices and configured to: receive T input code bits representing a first digital value VT[n]; in response to the first digital value VT[n], provide control signals to the plurality of slices to couple M × VT[n] elements between the first reference voltage terminal and the first output terminal; receive T input code bits representing a second digital value VT[n+1]; and in response to the second digital value VT[n+1], change a selected number C of the control signals to couple M × VT[n+1] elements between the first reference voltage terminal and the first output terminal, wherein the number C is a constant regardless of whether the second digital value VT[n+1] is greater than, less than, or equal to the first digital value VT[n].
[0009] According to an embodiment, a digital-to-analog converter system includes: a digital-to-analog converter (DAC) having a digital input, having an analog output, and including a number of N+E slices arranged in one or more segments; and a signal generator circuit having an output coupled to the digital input of the DAC, the signal generator circuit being configured to generate a digital multitone signal in response to an N-bit first frequency tuning word (FTW) corresponding to a first tone and an N-bit second FTW corresponding to a second tone by: providing a first code value of the multitone signal to the DAC at an output pipeline stage; and simultaneously, performing a calculation of a second code value of the multitone signal at the preceding pipeline stage.
[0010] According to an embodiment, a digital-to-analog converter circuit includes: a signal generator circuit comprising: a plurality of registers, each for storing an N-bit frequency tuning word (FTW) associated with a tone; a plurality of phase accumulators, each associated with one of the plurality of registers; a multiplexer having inputs coupled to the outputs of the plurality of phase accumulators and having a selection input; a first mapping circuit having inputs coupled to the outputs of the multiplexer and configured to output a sine value; a summing circuit having inputs coupled to the outputs of the first mapping circuit; a buffer having inputs coupled to the outputs of the summing circuit; pipelined control logic configured to pipeline the multiplexer, the first mapping circuit, the summing circuit, and the buffer; and a DAC array having inputs coupled to the outputs of the buffers and configured to output an analog signal in response to an input bitstream received at its input.
[0011] According to an embodiment, a digital-to-analog converter system includes: a digital-to-analog converter (DAC) having a digital input, having an analog output, and including a number of N+E slices arranged in one or more segments; a signal generator circuit having an output coupled to the digital input of the DAC, the signal generator circuit being configured to generate a digital multitone signal in response to an N-bit first frequency tuning word (FTW) corresponding to a fundamental frequency and an N-bit second FTW corresponding to a harmonic frequency of the fundamental frequency by: providing a first code value of the multitone signal to the DAC at an output pipeline stage; and simultaneously, at the previous pipeline stage, performing calculation of a second code value of the multitone signal; and a harmonic distortion measurement circuit having an input coupled to the analog output of the DAC, configured to iteratively calculate the second FTW, the second FTW having an amplitude and phase responsive to the output analog signal from the DAC. Attached Figure Description
[0013] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:
[0014] Figure 1 This is an electrical block diagram of an electronic system incorporating a digital-to-analog converter (DAC) integrated circuit according to some embodiments of this disclosure;
[0015] Figure 2A and 2B It is an electrical block diagram of a DAC circuit based on existing technology;
[0016] Figure 3 This is an electrical block diagram of a segmented DAC according to some embodiments of the present disclosure;
[0017] Figure 4A This is an electrical schematic diagram of a pseudo-differential thermometer segment according to some embodiments of this disclosure;
[0018] Figure 4B This is an electrical schematic diagram of a slice of the DAC segment of a thermometer based on existing technology;
[0019] Figure 4C This is an electrical schematic diagram of the elements of a slice of a thermometer segment according to some embodiments of the present disclosure;
[0020] Figure 4D This is an electrical schematic diagram of a thermometer segment according to some embodiments of the present disclosure;
[0021] Figure 5A This illustrates an embodiment of the present disclosure for use in... Figure 3 A flowchart of the switching logic operation of the thermometer segment of the DAC;
[0022] Figure 5B This illustrates an embodiment according to the present disclosure. Figure 5A The flowchart is a table of examples of the switching logic operations;
[0023] Figure 5C Based on embodiments of this disclosure Figure 5A The flowchart shows the electrical schematic diagram of the switching logic of the operation.
[0024] Figure 6 According to embodiments of this disclosure Figure 3 Electrical schematic diagram of the binary segments of a segmented DAC;
[0025] Figure 7 According to embodiments of this disclosure Figure 6 Electrical schematic diagram of a slice in a binary segment;
[0026] Figure 8 This illustrates an embodiment of the present disclosure. Figure 7 The state diagram of the operation of instances of switching logic related to binary segment slices;
[0027] Figure 9A and 9B It is an electrical block diagram of a multi-tone correction signal generation circuit based on existing technology;
[0028] Figure 10 This is an electrical block diagram of a DAC including a pipelined multi-tone signal generation circuit according to some embodiments of the present disclosure;
[0029] Figure 11 This is an electrical schematic diagram of a thermometer slice, a binary slice, and an R-2R slice in a DAC according to some embodiments of this disclosure;
[0030] Figure 12A This is a functional diagram of direct digital frequency synthesis in a pipelined multi-tone signal generation circuit incorporated into some embodiments of this disclosure;
[0031] Figure 12B The document includes waveform diagrams illustrating examples of multi-tone signal generation according to some embodiments of the present disclosure.
[0032] Figure 13 This is an electrical block diagram of a pipelined multi-tone signal generation circuit according to some embodiments of the present disclosure;
[0033] Figure 14 This is a table illustrating examples of the operation of a pipelined multi-tone signal generation circuit according to some embodiments of the present disclosure;
[0034] Figure 15 This is a flowchart illustrating the operation of a harmonic distortion measurement circuit for a DAC according to some embodiments of the present disclosure; and
[0035] Figure 16 These are a set of graphs illustrating examples of the operation of a harmonic distortion measurement circuit according to some embodiments of the present disclosure.
[0036] Unless otherwise stated, corresponding reference numerals and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments, and the figures are not necessarily drawn to scale. Detailed Implementation
[0037] The manufacture and use of the disclosed embodiments are discussed in detail below. However, it should be understood that this disclosure provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using this disclosure and do not limit the scope of this disclosure.
[0038] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments based on the description. These embodiments may be obtained without one or more of these specific details, or may be obtained using other methods, components, materials, etc. In some cases, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" or "example" in this specification indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" or "in one example," which may appear in different places in this specification, do not necessarily refer entirely to the same embodiment. Furthermore, specific forms, structures, or features may be combined in any suitable manner in one or more embodiments.
[0039] The following description uses illustrative examples to describe several aspects of this disclosure. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of this disclosure. This disclosure is not limited to the described order of actions or events, as some actions may occur in a different order and / or simultaneously with other actions or events.
[0040] Some embodiments relate to circuits and methods for converting digital data into analog signals.
[0041] In some applications, mismatch between nominally identical circuit elements (e.g., those used to implement multi-bit resistive or capacitive DACs) can cause nonlinear distortion of the analog output signal. In these and other applications, dynamic errors arising from asymmetrical switching of DAC elements, virtual ground sampling, etc., can also cause distortion of the analog output signal. For some system applications of high-speed (e.g., up to 100 kHz) and high-precision (e.g., 18-bit digital input codes) DAC circuits, such as in instrumentation and control systems, stringent distortion limits (e.g., total harmonic distortion or THD <-130 dBc) are required. Some embodiments described in this specification relate to the reduction of dynamic errors and the mitigation of static mismatches in high-frequency, high-precision DAC integrated circuits.
[0042] Figure 1 A system 100 incorporating a digital-to-analog converter (DAC) is illustrated according to some embodiments. In this example, DAC integrated circuit 120, in response to a digital data stream SDIN generated by processor 110, generates an analog output signal at its output terminal VOUT to be applied to the input of circuit 130. The nature of circuit 130 depends on the specific system application. For example, in a high-precision control loop application, circuit 130 may represent one or more integrated circuits that receive analog signals from DAC integrated circuit 120 for use as control signals. In a test equipment application, circuit 130 represents a device under test (DUT), where DAC integrated circuit 120 generates an analog signal at terminal VOUT to be used as a reference AC waveform for a specific test.
[0043] Figure 1 In system 100, processor 110 corresponds to a logic circuit system that generates a digital data stream, which corresponds to a sequence of DAC input code values that define a desired analog signal to be generated. In some embodiments, processor 110 may be implemented as a general-purpose or custom (e.g., application-specific) microprocessor or microcontroller coupled to or incorporated with memory and configured to execute program instructions stored in such memory. In some embodiments, processor 110 may be implemented as a field-programmable gate array (FPGA) or other semi-custom or custom logic circuit system. Other embodiments are also possible.
[0044] In some embodiments, for example, such as Figure 1 As shown, the DAC integrated circuit 120 includes an input interface 122 coupled to the processor 110 to receive a serial data stream at the input terminal SDIN. In this example, the input interface 122 is a Serial Peripheral Interface (SPI), and therefore, the digital data stream received at the terminal SDIN is physically a serial data stream, synchronized with a serial clock signal SCLK generated by the clock circuit system 115. In some embodiments, the clock circuit system 115 may be a separate integrated circuit in the system 100, or it may be implemented within the processor 110. In other embodiments, the processor 100 may transmit the DAC input code as parallel digital data (e.g., having a bit width corresponding to the desired DAC accuracy), in which case the input interface 122 of the DAC integrated circuit 120 will be a parallel interface.
[0045] In some embodiments, the DAC integrated circuit 120 has other timing and control terminals, including the SPI bus chip select input terminal SYNC, the serial data output terminal SDO, and other terminals (not shown) for various control signals. Figure 1 The DAC integrated circuit 120 in the example also has one or more power supply terminals, one or more ground terminals, and one or more reference voltage terminals, such as Figure 1 As shown.
[0046] In some embodiments, the DAC integrated circuit 120 includes a buffer register 124 having an input coupled to an SPI interface 122. The buffer register 124 buffers and stores digital data received by the input interface 122, for example, to parallelize incoming serial input data into DAC input codewords (e.g., 18-bit wide words). A DAC register 126 is downstream of the buffer register 124 in the DAC integrated circuit 120 and stores one or more DAC input codewords from the buffer register 124 to provide to the DAC 150, thereby allowing the buffer register 124 to receive and parallelize the serial input data received at the input interface.
[0047] In some embodiments, additional auxiliary circuitry and functions may also be provided in the DAC integrated circuit 120. Figure 1 In this example, the DAC integrated circuit 120 provides a power-on reset circuit 127 and a power-off logic 129. Other circuit functions, including clock circuits, voltage reference generators, control logic, etc. (not shown), may also be provided as needed for specific applications.
[0048] According to some embodiments, DAC 150 is a segmented resistive DAC circuit comprising a thermometer segment, a binary segment, and an R-2R segment. In some embodiments, DAC 150 is configured as a pseudo-differential resistive DAC, such as that described in co-pending U.S. Patent Application SN 18 / 814,694, filed August 26, 2024, entitled “A Multiplying Digital-to-Analog Converter,” which is jointly assigned herein and incorporated by reference. According to these embodiments, DAC 150 receives both a positive reference voltage and a negative reference voltage from terminals +VREF and -VREF, as... Figure 1 As shown. In other embodiments, DAC 150 is a resistive segmented DAC coupled from one of terminals +VREF and -VREF to a positive or negative reference voltage. In some embodiments, DAC 150 is a non-multiplicative DAC that generates a time-varying analog signal from a digital input code stream having time-varying values based on a substantially constant reference voltage. In other embodiments, DAC 150 is a multiplicative DAC that generates a time-varying analog signal from a time-varying reference voltage based on a scaling factor conveyed as a digital input code. The construction and operation of DAC 150 according to some embodiments are described in detail below.
[0049] Ideally, the analog signal output from a DAC corresponds faithfully to the time-varying sequence of the input code applied to the DAC. However, in reality, the output signal from a DAC contains distortion in the form of nonlinearity and harmonic distortion to some extent. Causes of this distortion include static mismatches between identical circuit elements (e.g., transistor variations), dynamic mismatches between corresponding electrical signals (e.g., rise and fall time differences of complementary signals), poor switching noise, and quantization noise in the digital domain. The specifications of precision DAC integrated circuits typically specify the maximum total harmonic distortion (THD) of the output signal over the operating conditions.
[0050] Figure 2AA prior art DAC system is illustrated in which, during manufacturing, a "fine-tuning" DAC 202 is used to fine-tune the nonlinearity of the output of the "master" DAC 200. In this prior art method, a nonlinearity (e.g., integral nonlinearity or INL, differential nonlinearity or DNL) of the analog output signal of the master DAC 200 is observed within the DAC input range. Parameters corresponding to the observed INL or DNL are programmed into a one-time programmable (OTP) memory 204. During normal operation, the master DAC 200 and the fine-tuning DAC 202 receive the same sequence of DAC input codes V[n], and in response, the master DAC 200 and the fine-tuning DAC 202 generate analog output currents I_out and I_trim, respectively, which are summed at the negative input of amplifier 205. The fine-tuning DAC 202 is controlled according to parameters stored in the OTP memory 204 such that the fine-tuning current I_trim compensates for (e.g., cancels) the distortion from the output current I_out of the master DAC 200. Figure 2A In the arrangement, amplifier 206 is implemented (e.g., where feedback resistor 206 is coupled between amplifier output and its negative input, and where positive input is grounded) to generate voltage V_out corresponding to output current I_out compensated by trimming current I_trim.
[0051] Figure 2B A prior art DAC system is illustrated, in which distortion caused by switching errors in DAC 210 is reduced by an output "deglitcher". The segmented resistive DAC 210 includes, for example, a thermometer segment 214 and an R-2R segment 216. Switches 212 in segments 214 and 216 are used to selectively couple corresponding resistors to the input (negative input) of amplifier 220, for example, according to the DAC input code. The noise generated by the switching of switch 212 in response to changes in the DAC input code value may introduce switching errors at the output of amplifier 220, regardless of the effects of resistors 222 and capacitor 224 coupled between the input and output of amplifier 220. The deglitcher of this prior art system includes a clock switch 226 coupled between the output of amplifier 220 and a ground bias capacitor 228, which is used to periodically sample and hold the DAC output.
[0052] In conjunction with the embodiments described below, it has been observed that, through Figure 2A and 2B The improvements achieved by existing technological methods cannot meet the extremely low distortion requirements of precision DACs in modern instrumentation, testing, and control applications. For example, Figure 2AMethods may leave some residual static mismatch, as well as uncorrected errors due to variations in manufacturing processes, power supply voltage, and temperature (PVT). Existing dynamic calibration methods, such as Dynamic Component Matching (DEM) and Data Weighted Average (DWA), can address these error causes, but they typically increase switching activity in the DAC, leading to higher switching noise levels that exceed the capabilities of existing de-glitching techniques. Figure 2B As shown.
[0053] Some embodiments overcome some or all of the problems of the prior art.
[0054] Figure 3 A DAC 150 according to various embodiments is shown. In some embodiments, Figure 3 The DAC 150 can be integrated into a DAC integrated circuit, for example... Figure 1 The system 100 contains a DAC integrated circuit 120. In these embodiments, the DAC 150 has a segmented architecture, comprising multiple segments of different types, each segment responding to a sampling clock signal ( Figure 3 A sample stream of N-bit DAC input code V[n] (not shown in the image) is synchronized to facilitate the generation of the analog output signal V. out (For example, as voltage).
[0055] exist Figure 3 In this example, the DAC 150 includes a thermometer segment 300, a binary segment 302, and an R-2R segment 304. The thermometer segment 300 is arranged into T "slices" 3011 to 3012. T The slices collectively correspond to the T most significant bits (MSBs) of the N-bit DAC input code V[n]. Binary segment 302 is arranged into B "slices" 3031 to 301. B Each slice corresponds to one of the B least significant bits (ULSB) of the DAC input code V[n]. The R-2R segment 304 is arranged into L+E “slices” 3051 to 305. L+E The L most significant slices of segment R-2R 304 each correspond to one of the L least significant bits (LSBs) of the DAC input code V[n]. According to some embodiments, the E least significant slices of 304 are associated with additional LSBs beyond the N bits of the received DAC input code V[n] to further reduce output distortion, as described below.
[0056] exist Figure 3 In this embodiment, DAC 150 is a resistive DAC implemented according to a pseudo-differential architecture, generally following the method described in the above-incorporated U.S. patent application SN 18 / 814,694. Therefore, each of segments 300, 302, and 304 receives voltage from the positive reference voltage +V. refand negative polarity reference voltage -V ref Both are biased. Each slice 301, 303, 305 in each of segments 300, 302, 304 is coupled to output nodes OUT1 and OUT2.
[0057] The construction of each segment 300, 302, and 304 is described in further detail below. In some embodiments, segments 300, 302, and 304 are resistive DAC segments. In DAC 150, the DAC input code V[n] is applied to a digital processor 310, which in turn provides a switch control signal SCW to a switch in each of slices 301, 303, and 305 of segments 300, 302, and 304, respectively. Figure 3 As shown, the digital processor 310 includes the circuitry or functions of switching logic 312 and signal conditioning circuitry 314. Examples of the construction and operation of these functions in the digital processor 310 are described in detail below.
[0058] Output node OUT1 is coupled to the negative input of amplifier 320. Output node OUT2 is coupled to the output of ground buffer 330, which has a feedback input at the positive input of amplifier 320 coupled to output node OUT2 and another input coupled to a common potential (e.g., circuit ground). Alternatively, output node OUT2 from segments 300, 302, and 304 may be directly coupled to the common potential without ground buffer 330. In this embodiment, amplifier 320 is configured as a current-voltage buffer, wherein feedback resistor 322 and feedback capacitor 324 are coupled in parallel between the output and negative input of amplifier 320.
[0059] In the operation of DAC 150 according to some embodiments, each of slices 301, 303, 305, in response to the switch control signal SCW, will reduce the voltage from the reference voltage +V. ref and -V ref The bias resistor is switched to one of the output nodes OUT1 and OUT2, thereby establishing a current at output nodes OUT1 and OUT2 corresponding to the value of the DAC input code V[n]. Amplifier 320 responds to the current at output node OUT1 by providing a voltage V in the form of an analog signal. out The voltage reflects the input signal represented by the sample stream of the DAC input code V[n].
[0060] In some embodiments, DAC 150 may alternatively be implemented according to an architecture other than a pseudo-differential arrangement. For example, one or more of segments 300, 302, 304 may be derived from a unipolar reference voltage (e.g., voltage +V). ref ) bias, instead of like in Figure 3The thermometer segment 300 is biased from both positive and negative reference voltages, as in the pseudo-differential architecture. Other arrangements such as DAC slices and segments, output amplifiers, and bias schemes are also considered.
[0061] Figure 4A The construction of a thermometer segment 300 according to some embodiments is shown. As described above, the thermometer segment 300 includes T slices 3011 to 301... T The slices collectively correspond to T MSBs of the N-bit DAC input code V[n]. However, in these embodiments, thermometer slices 3011 to 301... T Individual thermometer slices (collectively or generally referred to as slice 301) are not associated with specific bits of the DAC input code V[n].
[0062] In the pseudo-differential architecture of the DAC 150 according to some embodiments, the thermometer segment 300 includes a voltage source from a positive reference voltage +V. ref The biased portion is 400P and from the negative reference voltage -V ref The bias portion is 400M. In this embodiment, each slice 301 is biased from the reference voltage +V. ref and -V ref Both are biased, and therefore include components in each of the 400P and 400M.
[0063] According to these embodiments, the segments 301 of the thermometer segment 300 are "sub-segmented," with each segment 301 containing multiple resistive elements connected in parallel to establish the total resistance R of the segment. In this embodiment, each segment 301 includes two resistors 402 and 403 in portion 400P, which are coupled to a reference voltage +V on one side, respectively. ref And on the other side, they are coupled to switches 404 and 405 respectively. Each slice 301 also includes two resistors 412 and 413 in part 400M, which are coupled to a reference voltage -V on one side respectively. ref And on the other side, they are coupled to switches 414 and 415 respectively. For example... Figure 4A As shown in the representative slice 3013, resistors 402, 412 and switches 404 and 414 constitute the resistive element 4013 in slice 3013 [0], and resistors 403, 413 and switches 405 and 415 constitute the second resistive element 4013 in slice 3013 [1].
[0064] Switches 404, 405, 414, and 415 each have terminals coupled to output nodes TOUT1 and TOUT2. According to some embodiments (e.g., in...), Figure 3In the segmented architecture of the DAC 150 (in the middle), the output nodes TOUT1 and TOUT2 of the thermometer segment 300 are coupled to the output nodes OUT1 and OUT2. Output node TOUT1 is coupled to the negative input of amplifier 320, and output node TOUT2 is coupled to the positive input of amplifier 320 at the circuit ground (e.g., via ground buffer 330, such as...). Figure 3 (As shown). Each switch 404, 405, 414, 415 is used to respond to the input from switch logic 312 ( Figure 3 The switch control signal SCW of the DAC input code V[n] couples the corresponding resistors 402, 403, 412, and 413 to the output node TOUT1 or the output node TOUT2 according to the value of the DAC input code V[n].
[0065] In some embodiments, according to Figure 3 In the pseudo-differential architecture, switches 404 and 414 operate complementaryly to each other, such that for each sample of the DAC input code V[n], one of resistors 402 and 412 is coupled to output node TOUT1, and the other is coupled to output node TOUT2. Therefore, output node TOUT1 is connected either through resistor 402 to the reference voltage +V. ref To receive positive current, either through resistor 412 from the reference voltage -V ref Receives negative current. Similarly, switches 405 and 415 in the same slice operate complementaryly, coupling one of resistors 403 and 413 to output node TOUT1 and the other to output node TOUT2, thereby establishing either a positive or negative current at the negative input of amplifier 320. Given slice 301 k Component 401 k [0] and 401 k [1] They are controlled independently of each other. For example, reference Figure 4A In the slice 3013 shown, complementary switches 404 and 414 in element 4013[0] are separate from and independently controlled by complementary switches 405 and 415 in element 4013[1].
[0066] In this embodiment where slice 301 is subdivided into two resistive elements, each of resistors 402, 403, 412, and 413 has a resistance (2R) twice the total resistance R of the slice. Alternatively, slice 301 may be subdivided into four resistive elements (each with a resistance of 4R), eight resistive elements (each with a resistance of 8R), and so on.
[0067] Figure 4B A slice (or a portion thereof) according to an implementation scheme in the prior art is shown. 460 j 460 slices jIt includes two resistors 462 and 463, each of which is coupled to a reference voltage +V on one side. ref And it is coupled to switch 464 on the other side. This slices 460. j The resistor R is divided into two resistors, 462 and 463 (each with a resistance of 2R), which is considered to improve the static differential nonlinear (DNL) performance. Figure 4B In this prior art arrangement, switch 464 is controlled by switch control signal SCW[k] to connect both resistors 462 and 463 to output node TOUT1 (e.g., at amplifier input) or to circuit ground at output node TOUT2.
[0068] In contrast, as described above, each resistor 402, 403, 412, 413 in each slice 301 of the thermometer segment 300 according to some embodiments is individually associated with a corresponding switch 404, 405, 414, 415, respectively. Figure 4A As shown. Figure 4C It shows Figure 4A The construction of switches 404 and 414 in a representative resistive element 4013[0] of slice 3013 in thermometer segment 300. In this example, switch 404 includes n-channel metal-oxide-semiconductor (NMOS) transistors 420 and 422, which have drains coupled to resistor 402, which in turn is coupled to a reference voltage +V. ref The source of transistor 420 is coupled to output node TOUT1, and the source of transistor 422 is coupled to output node TOUT2. Switch 414 similarly includes NMOS transistors 424 and 426, which have drains coupled to resistor 412, which in turn is coupled to a reference voltage -V. ref The source of transistor 424 is coupled to output node TOUT1, and the source of transistor 426 is coupled to output node TOUT2. One or more of transistors 420, 422, 424, and 426 may alternatively be implemented as p-channel MOS transistors, bipolar junction transistors, etc. Complementary switching control signals SCW[k] and SCW[k] / from switching logic 312 in digital processor 310 are transmitted to switches 404 and 414. The gates of NMOS transistors 420 and 426 receive signal SCW[k], and the gates of NMOS transistors 422 and 424 receive complementary signal SCW[k] / .
[0069] During operation, the high logic level at signal SCW[k] and therefore the low logic level at signal SCW[k] / turns on NMOS transistors 420 and 426, and turns off NMOS transistors 422 and 424. In this case, switch 404 is used to turn off resistor 402 (and therefore from the reference voltage +V). ref The positive current) is coupled to the output node TOUT1 at the negative input of amplifier 320, while switch 414 is used to couple resistor 412 (and therefore from the reference voltage -V) to the output node TOUT1 at the negative input of amplifier 320, and switch 414 is used to couple resistor 412 (and therefore from the reference voltage -V) to the output node TOUT1 at the negative input of amplifier 320. ref The negative current is coupled to the output node TOUT2 at the circuit ground. The opposite logic levels of signals SCW[k] and SCW[k] / (low and high respectively) cause switch 404 to couple the positive current to the output node TOUT2 through resistor 402, and switch 414 to couple the negative current to the output node TOUT1 through resistor 412.
[0070] According to some of these embodiments, multiple elements within each slice 301 are controlled independently of each other. For example, Figure 4A The switches 405 and 415 of element 4013[1] in slice 3013 are controlled by separate switch control signal pairs (e.g., SCW[k+1] and SCW[k+1] / ), and are independent of the switches 404 and 414 of element 4013[0] in the same slice 3013.
[0071] Return to reference Figure 4A The thermometer segment 300 conducts current to the negative input of the amplifier 320 according to the thermometer code. Each of the T slices 301 is sub-segmented in multiples of two. Figure 4A In one example, the thermometer code that determines the output current contains 2T bits, each of which independently controls one of the two elements 401[0] and 401[1] of each slice 301. At a reference voltage +V ref and -V ref Having the same amplitude (|V ref In the pseudo-differential architecture of thermometer segment 300 with opposite polarity, the net current IOUT flowing from thermometer segment 300 into amplifier 320 is... T It can be represented as:
[0072] (1)
[0074] Each resistor 402, 403, 412, 413 has a resistance of 2R, and k is the number of switches 404, 405, which couple their respective resistors 402, 403 to output node TOUT1 based on the switch control signal SCW from the switch logic and signal conditioning circuit 130. As the input signal changes from one DAC input code V[n] to the next V[n+1], the number of switches 404, 405, 414, 415 in slice 301 changes, and these switches couple their associated resistors 402, 403, 412, 413 to output nodes OUT1 and OUT2. In this specification, the number of switches 404, 405, 414, 415 that change the position from one DAC input code V[n] to the next V[n+1] is referred to as the thermometer transition vector K[n].
[0075] Figure 4D A thermometer segment 300' according to another embodiment is shown. In this example, the thermometer segment 300' is connected to a unipolar reference voltage +V. ref Bias, rather than like Figure 4A In the pseudo-differential architecture of the thermometer segment 300, bias is applied from both a positive and a negative reference voltage. Therefore, Figure 4D The 300' thermometer segment effectively corresponds to, for example Figure 4A The thermometer segment 300 shown has an upper portion 400P, but no lower portion 400M.
[0076] Figure 4D Thermometer segment 300' contains T slices 3011' to 301 T The T slices 301' are not individually associated with specific points in the T MSBs of the DAC input code V[n]. In this example, each of the slices 301' is segmented to contain elements respectively coupled to the reference voltage +V. ref Two resistors 432 and 433 are connected between corresponding switches 434 and 435. For example, as shown in slice 3013', a combination of resistor 432 and switch 434 in a given slice 301' constitutes a resistive element 4013'[0], and a combination of resistor 433 and switch 435 constitutes a second resistive element 4013'[1]. Alternatively, each slice 301' may be subdivided to contain four, eight, or other numbers of resistive elements. Figure 4CIn this example, the two resistors 432 and 433 have the same resistance as each other and are identical to the two resistors 432 and 433 in all other slices 301' of the thermometer segment 300'. Each switch 434 and 435 of each segment 301' responds to a corresponding switch control signal SCW (not shown) to selectively couple its corresponding resistor 432 or 433 to either output node TOUT1 or output node TOUT2. As in the thermometer segment 300 described above, output node TOUT1 is coupled to the negative input of amplifier 320, and output node TOUT2 is coupled to circuit ground together with the positive input of amplifier 320 (e.g., directly or via ground buffer 330).
[0077] exist Figure 4D During the operation of thermometer segment 300', the switching logic and signal conditioning circuit 130 generates a switching control signal SCW, causing switches 434 and 435 to switch on a selected number of resistive elements 401. k Coupled to output node TOUT1, this provides current to amplifier 320 with an amplitude corresponding to T MSBs of the DAC input code V[n] (e.g., according to thermometer code). As in Figure 4A Similar to thermometer segment 300, the number of switches 434 and 435 in slice 301' will change with the successive DAC input codes V[n], and the switches couple their associated resistors 432 and 433 to the output node TOUT1. The number of switches 434 and 435 that change position as the input sample value changes from one DAC input code V[n] to the next DAC input code V[n+1] is the thermometer transition vector K[n].
[0078] According to some embodiments, the thermometer slice is subsegmented by providing an independent switch for each resistor within each of two or more resistive elements in each slice. This allows the value of the thermometer transition vector K[n] to be independent of the input signal and to remain constant from one DAC input code value to the next, regardless of the DAC input code value. This separation of the thermometer transition vector K[n] from the input signal reduces spurious harmonics in the output signal, which are contributing factors to THD. Maintaining a constant value for the thermometer transition vector K[n] also has the effect of shifting inter-symbol interference (ISI) errors to DC (f=0). According to some embodiments, the subsegmentation of the thermometer slice further allows the "on" switch to rotate within the subsegments, thereby reducing residual static mismatch errors.
[0079] Figures 5A to 5CAn embodiment of switching logic 312 according to some embodiments is shown, and its operation in controlling the thermometer segment 300 of DAC 150 to maintain a constant transition vector K[n] value over the sequence of DAC input codes V[n]. Additionally, Figures 5A to 5C The example further enables the current to be cyclical on slice 301 of thermometer segment 300. Figures 5A to 5C The implementation and operation of the switch logic 312 shown in the example can be applied to thermometer segments of various architectures, including, for example... Figure 4A The pseudo-differential architecture shown and, for example Figure 4D The unipolar reference voltage architecture is shown.
[0080] Figure 5A This is a flowchart of the operation of the switching logic 312 in conjunction with these embodiments. Figure 5B This is a table that indicates the sixteen segments 3011 to 301 of the thermometer segment 300. 16 Each of the two resistive elements 401 k [0] and 401 k The states of switches 404 and 405 in [1], the slice is associated with T=16 MSBs of the N-bit DAC input code V[n]. Figure 5C It shows the method for execution Figure 5A The flowchart shows the switching logic of the operation of the example architecture 312.
[0081] For reference Figure 5B To understand using the examples shown Figure 5A The algorithm. Figure 5B Each element 401 with an entry of "1" k [0]、401 k [1] Indicates that its corresponding switch 404 or 405 (as the case may be) is controlled by switch logic 312 to couple its associated resistor 402 or 403 to output node TOUT1 (e.g., to the input of amplifier 320), respectively. Figure 4A In the pseudo-differential architecture of thermometer segment 300, component 401 k [0]、401 k The “1” entry in [1] further indicates that its corresponding switch 414 or 415 (as the case may be) is controlled to couple its resistor 412 or 413 to the output node TOUT2 (e.g., at circuit ground). Figure 5BThe "0" entry for the element in slice 301 indicates the opposite state, in which switch 404 or 405 (whichever is appropriate) couples its resistor 402 or 403 to output node OUT2, and the corresponding switch 414 or 415 (whichever is appropriate) couples its resistor 412 or 413 to output node TOUT1, respectively. In other words, the "1" entry for the element in slice 301 indicates that a positive current (from the reference voltage +V) is supplied from said element to the negative input of amplifier 320. ref The "0" entry indicates that a negative current (from the reference voltage -V) is supplied from the component to the negative input of amplifier 320. ref ).
[0082] exist Figure 5B In the example, at time n=0, the value of the T MSBs of the DAC input code V[0] is V. T [0] is 7. In slices 3011 to 301... 16 In this example, where each resistor has a resistance of 2R, switching logic 312 generates an appropriate switching control signal SCW to set the state of the fourteen elements to "1". Figure 5B In this example, at time n=0, the fourteen elements with "1" entries are two elements in each of the consecutive slices 3011 to 3017. In this embodiment, element 4011[0] is the first element with a "1" entry and is identified by the "start" pointer value Start[n]=1. The other elements with "1" values are... Figure 5B The table follows the element 4011[0] in a left-to-right sequence, indicated by the start pointer value Start[n]=1. In some embodiments, this start pointer value Start[n] is used around T slices 3011 to 301 T Rotate the "1" item.
[0083] According to some embodiments, the transition vector value K[n] remains a constant value C over the DAC input code sample sequence. Figure 5A In this example, the value C = 2. Other values of the constant C can be used. For example... Figures 5A to 5C In some embodiments, it is assumed that the sampling rate of the DAC input code is oversampled relative to the frequency of the analog output signal, such that the T MSBs of consecutive DAC input codes are V T [n-1] and V T The difference of [n] does not exceed one thermometer code level. In other words, the DAC input code V T The values of the T MSBs of [n] are related to the previous code V. T The values of [n-1] differ only by -1, 0, or +1.
[0084] Figure 5AThe example process begins in process 502, where switch logic 312 receives the DAC input code V[n]. In process 504, T MSBs V are calculated. T [n] relative to the T MSBs V from the previous sample T The difference ΔV between [n-1] T [n]. Then decisions 505 and 507 are executed to adjust the difference ΔV. T [n] is evaluated as -1, 0, or +1, based on which the quantity Jump[n] can be determined. In these embodiments, based on the current value V T The computational amount of values for [n] and C is Jump[n] so that the switch position rotates in slice 301 while maintaining a constant transition vector value K[n].
[0085] exist Figure 5A In the example, Decision 505 first determines whether there is a difference ΔV. T [n] = 0. If so (decision 505 returns "yes"), then in process 506, the quantity Jump[n] is set to a random value r[n], which is either +1 or -1 from the value in process 509. For example, the switching logic 312 or other circuitry in the DAC 150 may execute a pseudo-random number generator (PRNG) in process 509 based on white noise or shaped noise characteristics. If the difference ΔV T If [n]≠0 (Decision 505 returns "No"), then switch logic 312 executes decision 507 to determine whether the difference ΔV is true. T [n] = +1. If yes (Decision 507 returns "yes"), then in process 508, the quantity Jump[n] is set to the random value r[n] from process 509 minus 1 (e.g., r[n] - 1). If the difference ΔV T [n]≠+1 (Decision 507 returns "No"), then the difference ΔV T [n] = -1. In this case, in process 510, switch logic 312 sets the quantity Jump[n] to the random value r[n] from process 509 plus 1 (e.g., r[n] + 1). After calculating the quantity Jump[n] of the current DAC input code V[n] in one of processes 506, 508, or 510, in process 512, switch logic 312 increments, decrements, or maintains the start pointer value Start[n] according to the quantity Jump[n].
[0086] Meanwhile, in process 511, based on the T MSBs of the current DAC input code V[n] T [n] Encodes the thermometer code value. In this embodiment, refer to... Figure 5B The thermometer code is arranged to match the value V. T[n] is a sequence of consecutive "1" entries corresponding to all other entries, where all other entries have a "0" value. In process 514, switch logic 312 applies switch control signals to switches 404, 405, 414, and 415 in thermometer slice 301 according to the thermometer code value encoded in process 511. Consecutive "1" entries of the thermometer code are assigned to elements 401 in slice 301 starting from the position indicated by the start pointer value Start[n].
[0087] Figure 5B An example is shown where each slice 301 contains two elements 401. Figure 5A An example of the process. As mentioned above, at time n=0, the value of the T MSBs of the DAC input code V[0] is V. T [0] is 7, and therefore, slices 3011 to 301 16 Fourteen (2×7) of the elements are set to the "1" state, starting from element 4011[0] of slice 3011 (indicated by the start pointer value Start[n]=1). More generally, in the case where each slice 301 contains M elements 401, the number of elements set to the "1" state is the value V of the T MSBs of the input code. T [n] times M.
[0088] At time n=1, Figure 5A In process 502, the next input code V[1] is received, and the value V in its T MSBs is... T [1] is 8. In process 504, the difference ΔV is determined. T [1] = +1, causing decision 505 to return "No" and decision 507 to return "Yes". In process 508, the amount of the current DAC input code V[1] is calculated (Jump[1]). Figure 5B In the example, the random value is r[1]=-1, making the quantity Jump[1]=(-1)-1=-2. In process 512, the start pointer value Start[0] is decremented by Jump[1]=-2, becoming the value Start[1]=31 (the element wrapping around slice 301), pointing to slice 301. 16 Component 401 16 [0]. Because the current value V T [1]=8, so the sixteen elements of slice 301 are set to "1" starting from the position indicated by the start pointer value Start[1]. As a result, the number of entries that change at time n=1 relative to time n=0 is two, that is, slice 301 16 The two entries. Therefore, the value of the transformation vector K[1]=2.
[0089] At time n=2, the next received value VT [2] is 7, making the difference ΔV T [2] = -1. Decisions 505 and 507 both return "No". In procedure 510, in this instance, the random value r[1] = +1 is used to calculate the quantity Jump[2], such that the quantity Jump[2] = (+1) + 1 = +2. In procedure 512, the start pointer value Start[1] is incremented by Jump[2] = +2, becoming the value Start[2] = 1 (again wrapping around the element of slice 301), pointing to element 4011[0] of slice 3011. For the current value V T [2]=7, the fourteen elements of slice 301 are set to "1" starting from the position indicated by the start pointer value Start[2]. Similarly, the number of entries that change at time n=2 relative to time n=1 is two, that is, slice 301 16 The two entries (from “1” to “0”). The value of the transformation vector remains constant at K[2]=2.
[0090] In this example, at time n=3, the next received value V T [3] Keep the value 7, so that the difference ΔV T [3]=0, and decision 505 returns "yes". In procedure 510, in this instance, the random value r[3]=+1 is used to calculate the quantity Jump[3], such that the quantity Jump[3]=+1. In procedure 512, the start pointer value Start[2] is incremented by Jump[3]=+1, becoming the value Start[3]=2, pointing to element 4011[1] of slice 3011. Current value V T [3]=7 maintains the fourteen elements of slice 301 as set to “1” starting from the position indicated by the new start pointer value Start[3]. At time n=3, the transition vector value K[3]=2, corresponding to the change at the first entry of slice 3011 (from “1” to “0”) and the change at the first entry of slice 3018 (from “0” to “1”).
[0091] At time n=4, the received value V T [4]=6. According to... Figure 5A The process, process 504, calculates the difference ΔV. T [4] = -1, and decisions 505 and 507 both return "No". In process 508, in this case, the quantity Jump[4] is calculated with a random value r[4] = +1, resulting in the quantity Jump[4] = (+1) + 1 = +2. In process 512, the start pointer value Start[3] is incremented by Jump[4] = +2, becoming the value Start[4] = 4, pointing to element 4012[0] of slice 3012. Current value V T[4]=6 corresponds to the twelve elements of slice 301 that are set to “1” starting from the position indicated by the new start pointer value Start[4]. Similarly, at time n=4, the value of the transition vector K[4]=2 corresponds to the change at the second entry of slice 3011 and the first entry of slice 3012 (both from “1” to “0”).
[0092] Figure 5A The process continues in this manner for use in later sample DAC input codes V[n]. This is achieved by basing the input code value V on the current input code value. T [n] relative to the previous input code value V T The difference ΔV between [n-1] T [n] The computational amount Jump[n] (which is randomized based on the constant C of the transition vector K[n]) is used to rotate the switching positions of the elements in slice 301 on thermometer segment 300 while maintaining a constant transition vector K[n]=C.
[0093] Figure 5C The following are examples of implementations. Figure 5A The architecture of the switching logic 520 used for the operation of the thermometer segment 300. For example, according to Figure 5C The switching logic 520 of the architecture can be functionally arranged as combinational or sequential logic or a combination of both, and physically implemented in the form of a custom or semi-custom logic circuit system, programmable logic (e.g., a microprocessor or microcontroller combined with a program memory), or a combination thereof.
[0094] In these embodiments, the switching logic 520 includes a delay buffer 521 and an adder 522, both having T MSBs V that receive the DAC input code V[n] of the current (nth) input code. T The input is [n]. The delay buffer 521 is clocked by the sampling clock of the sample stream of the DAC input code V[n], and will store T MSBs of the previous input code V. T [n-1] is the output to the input of adder 522. Adder 522 calculates the value V. T [n] and V T The difference ΔV between [n-1] T [n] ( Figure 5A The process 504), and the difference ΔV T [n] Output to differential encoder 524.
[0095] Differential encoder 524 executes switching logic 520. Figure 5A The decision-making processes involved, such as 505 and 507. Figure 5C As shown, the differential encoder 524 responds to the difference ΔV determined by the adder 522. T[n], outputs a 2-bit binary code. Figures 5A to 5C In one embodiment, the sampling rate of the DAC input code is oversampled, causing the difference ΔV T [n] The difference ΔV from adder 522, not exceeding one thermometer code level. T The set of possible values for [n] is {-1, 0, +1}. The difference encoder 524 responds to the difference ΔV. T The value of [n] and the output 2-bit binary code are applied to the selection input of the multiplexer 528.
[0096] exist Figure 5C In this example, multiplexer 528 has four inputs, three of which are coupled to the outputs of multiplexers 526a, 526b, and 526c, while the fourth receives a value of 0 (e.g., an error or other null event). Multiplexer 526a has one input that receives a value of +1 and a second input that receives a value of -1; multiplexer 526b has one input that receives a value of 0 and a second input that receives a value of -2; and multiplexer 526c has one input that receives a value of 0 and a second input that receives a value of +2. Each of multiplexers 526a, 526b, and 526c has the ability to receive a random bit value r. b The selection input [n] takes a random bit value of 0 or 1, and thus controls the selection of multiplexers 526a, 526b, and 526c.
[0097] In this example, the operation of multiplexer 526a corresponds to Figure 5A In process 506, for the difference ΔV T When [n] = 0, the quantity Jump[n] is randomly determined to be +1 or -1. For the difference ΔV T When [n]=0, the difference encoder 524 outputs a binary value of 00 for diff_code[1:0], so that the multiplexer 528 selects the output of the multiplexer 526a as the quantity Jump[n].
[0098] Similarly, the operation of multiplexer 526b corresponds to Figure 5A In process 508, for the difference ΔV T In the case where [n] = +1, the quantity Jump[n] is randomly determined to be 0 or -2. For the difference ΔV... T When [n]=+1, the difference encoder 524 outputs binary values 01 for diff_code[1:0], so that the multiplexer 528 selects the output of the multiplexer 526b as the quantity Jump[n].
[0099] The 526c multiplexer corresponds to Figure 5A Process 510, targeting the difference ΔV T[n]=-1, randomly determining the quantity Jump[n] as 0 or +2. In this case, the differential encoder 524 outputs diff_code[1:0]=11, causing the multiplexer 528 to select the output of the multiplexer 526c as the quantity Jump[n].
[0100] According to some embodiments, Figure 5C The shift logic 520 includes an adder 530, a fetch module 532, and a delay buffer 533, used to determine the start pointer value Start[n] of the current input code V[n], for example, regarding... Figure 5A The process described in step 512. In these embodiments, the start pointer value Start[n] of the current input code is determined based on the quantity Jump[n] of the output of multiplexer 528 and the start pointer value Start[n-1] of the previous sample. The adder 530 in shift logic 520 has one input that receives the quantity Jump[n] from the output of multiplexer 528 and a second input that receives the previous start buffer value Start[n-1] from the output of delay buffer 533. Adder 530 adds the quantity Jump[n] to the previous start buffer value Start[n-1] and outputs the sum as the value sum_out to fetch module 532. Fetch module 532 outputs the current start pointer value Start[n] as the remainder of the modulo operation performed on the value sum_out, where the divisor is the number of elements in thermometer segment 300 (e.g., for Figure 5B An example of 32 is provided, where T = 16 and each slice 301 has two elements 401. A start pointer value Start[n] is applied to the input of a delay buffer 533, which is clocked by a sampling clock, and is also applied to the shift input of a circular shifter 540. The circular shifter 540 can be configured as a shift register, where the stored data can be shifted according to the value received at the shift input, or it can be configured as a register storing data that can be read sequentially starting from the index value applied at the shift input (e.g., data stored in a non-shift register). In either case, the circular shifter 540 is circular because its contents wrap around during shifting.
[0101] According to some embodiments, the thermometer encoder 530 in the shift logic 520 has T MSBs that receive the DAC input code V[n]. T The input is [n]. The thermometer encoder 530 is based on the input code value V. T [n] Encodes the thermometer code value therm_code[n], as described above. Figure 5AThe process described in step 511 is as follows. The encoding applied by the thermometer encoder 530 is derived based on the architecture of the thermometer segment 300 and the number of elements 401. In this example, the thermometer code generated by the encoder 530 is loaded into the cyclic shifter 540. The cyclic shifter 540 assigns "1" entries to elements 401 by shifting the thermometer code value therm_code[n] according to the start pointer value Start[n] from the fetch module 532. The output of the cyclic shifter 540 will switch the control signal SCW. T [n] Slices 3011 to 301 provided to thermometer segment 300 T The switch in the middle responds to T MSBs of the current DAC input code V[n]. T [n] to generate an appropriate current.
[0102] In some embodiments, implementation may be carried out according to Figures 5A to 5C The shift logic 520 process and certain modifications to the circuit system. In some embodiments, the size of the shifter can be reduced to half the number of elements 401 in slice 301 to save chip area and execution time. In this arrangement, the shift of the “1” entry of element 401 can be performed in two operations, wherein the first half of the shifted content is stored in a buffer and the shift is repeated for the second half; the multiplexer can append a “0” or “1” value according to the final LSB of the start pointer. In another arrangement, according to some embodiments, by adding 1 to the digital offset and the DAC input code value V T The [n] are added together, and the addition is canceled out by a normally open element in the analog circuit system of thermometer segment 300, thus avoiding the extreme value V of the DAC input code. T Ambiguity arises when [n] = 0 or full-code (e.g., all T bits are "1"). In some embodiments, slices 3011 to 301 may be included. T Two or more additional elements besides the associated elements are used to ensure seamless rotation of the start pointer value. Furthermore, although the embodiment described above references a transition vector K[n] value C=2, Figure 5A The process and Figure 5C The architecture of the switching logic shown can be easily modified for other transition vector values and four, eight or other numbers of elements in each slice 301.
[0103] According to the above text about Figures 4A to 4DSome embodiments described in 5A to 5C can significantly reduce dynamic errors in the form of harmonic distortion, at least in part by maintaining a constant value for the transition vector, independent of the input bitstream. According to some embodiments, since this reduction in dynamic error only requires changing the switching configuration and control circuitry of the DAC, the required additional chip area is extremely small compared to conventional resistive DACs. Errors due to residual static mismatch are also improved due to the inherent rotation of the conductive branches on the thermometer array.
[0104] Figure 6 The binary segment 302 in a DAC 150 according to some embodiments is schematically shown. Binary segment 302 in... Figure 6 The image shows the T-th slice 301 of the thermometer segment 300 of the DAC 150. T Adjacent. As mentioned above... Figure 1 As described, binary segment 302 is arranged into B slices, each slice corresponding to one of the B least significant bits (ULSB) of the DAC input code V[n]. In this example, B=3, and therefore, according to these embodiments... Figure 6 The binary segment 302 comprises three slices 3031 to 3013, each slice corresponding to one of the three ULSBs of the DAC input code V[n]. According to these embodiments, the binary segment 302 may contain more or fewer binary slices 303.
[0105] Thermometer Slice 301 T exist Figure 6 The diagram is schematically shown to nominally include series coupling to a positive reference voltage +V. ref The resistor 602 and switch 604, and the series coupling to the negative polarity reference voltage -V ref Resistor 612 and switch 614. For the purposes of this description of binary segment 302, thermometer slice 301 T The resistors 602 and 612 (and all other thermometer slices) each have a nominal value R. In some embodiments, as described above, thermometer slice 301 T It can be subdivided into multiple elements that contain resistors and associated switches, thereby achieving a nominal resistance R (e.g., two elements with resistance 2R, four elements with resistance 4R, etc.).
[0106] Therefore, given thermometer slice 301 T The nominal resistor R, binary slice 3011 contains a switch 6241 coupled in series to the positive reference voltage +V. ref A resistor 6221 with a nominal value of 2R, and a switch 6341 coupled in series to a negative polarity reference voltage -V. refThe resistor 6321 has a nominal value of 2R. The binary slice 3012 contains a switch 6242 coupled in series to a positive reference voltage +V. ref The nominal value 2 2 The resistor R is 6222, and it is coupled in series with switch 6342 to the negative reference voltage -V. ref The nominal value of the resistor 6322 is 22R. Similarly, the binary slice 3013 is contained in series with the switch 6243 and coupled to the reference voltage +V. ref The nominal value 2 3 The resistor R is 6223, and it is coupled in series with the switch 6343 to the reference voltage -V. ref The nominal value 2 3 The resistance of R is 6323. The nominal resistance of any additional binary slice 301 in binary segment 302 increases to a power of two in a similar manner.
[0107] Switches 624 and 634 are controlled by corresponding switch control signals SCW from switch logic 312 to couple their corresponding resistors 622 and 632 to binary output nodes BOUT1 and BOUT2, respectively. Binary output node BOUT1 is coupled to the negative input of amplifier 320, and binary output node BOUT2 is coupled to circuit ground (e.g., via ground buffer 330) or to the positive input of amplifier 320. In the segmented architecture of DAC 150, binary output nodes BOUT1 and BOUT2 are coupled to thermometer output nodes TOUT1 and TOUT2, respectively.
[0108] For binary segment 302, the encoding of the B ULSBs of the DAC input code V[n] is binary, which differs from the thermometer code encoding used for thermometer segment 300. Therefore, as Figure 6 As shown, because the values of resistors 622 and 632 are from a binary slice 303 k To the next least significant binary slice 303 k+1 The current is increased to twice the normal value, so the current conducted to the binary output node BOUT1 is reduced by half from slice to slice.
[0109] Even in the embodiment for reducing harmonic distortion, such as that described above for thermometer segment 300, some residual nonlinearity may still exist due to signal harmonics in the transition vector of the ULSB bits implemented as binary segment 302. The B ULSB bits of a given DAC input code V[n] can be... B The effective transition vector K of the 3-bit binary segment 302 of [n] is... B [n] is represented as:
[0110] (2)
[0112] Where K B1 [n]、K B2 [n]、K B3 [n] are the transformation vectors of binary slices 3031, 3032, and 3033, respectively. Because the transformation vector K of equation (2) for binary segment 302... B The component values of [n] are weighted bitwise, so the binary transformation vector K B The value of [n] is related to the input signal, resulting in harmonic distortion due to dynamic mismatch in binary slice 303.
[0113] According to some embodiments, the binary slice 303 is divided into multiple redundant elements so that it can be rotated among these elements, thereby transforming the transformation vector K. B [n] remains at a constant value K B [n]=J, which is independent of the value of the DAC input code V[n], and thus reduces harmonic distortion sources. Figure 7 The construction of binary slice 3031 according to some embodiments is shown. Other binary slices 3032, 3033, etc., are similar. Figure 7 The slice 3031 is constructed similarly, but has a different resistance value than the resistance value described above.
[0114] exist Figure 7 In this example, the binary slice 3031 includes four resistors 622A, 622B, 622C, and 622D (collectively or generally referred to as resistor 622), each of which is coupled to a positive reference voltage +V. ref Switches 624A, 624B, 624C, and 624D (collectively or generally referred to as switch 624) are coupled on one side to corresponding resistors 622A, 622B, 622C, and 622D, respectively. Switch 624 can be used in conjunction with the resistors described above. Figure 4C The switch 404 is constructed in a similar manner. Each switch 624 is independently controlled by a switch control signal from switch logic 312 to couple its associated resistor 622 to one of the output nodes BOUT1, BOUT2. Similarly, binary slice 3031 also includes four resistors 632A, 632B, 632C, and 632D (collectively or generally referred to as resistor 632), each of which is coupled to a negative reference voltage -V. ref This is related to one of switches 634A, 634B, 634C, and 634D (collectively or generally referred to as switch 632). Switch 634 can be used with the switch described above. Figure 4CSwitch 414 is constructed in a similar manner. Each switch 634 is also independently controlled by a switch control signal from switch logic 312 to couple its associated resistor 632 to one of the output nodes BOUT1, BOUT2. As mentioned above, switch 624 is controlled independently of switch 634 (e.g., not necessarily in a complementary manner).
[0115] According to some embodiments, resistors 622 and 632 each have a nominal resistance 2R of slice 3031. Similarly, resistors in slices 3032 and 3033 constructed in a similar manner each have a nominal resistance 2R of those slices. 2 R and 2 3 R. As a result, for any given input code value, only one of the resistors 622 and 632 in slice 3031 is coupled to the output node BOUT1, where resistor 622 or 632 provides a voltage corresponding to the reference voltage |V. ref The current is | / 2R.
[0116] exist Figure 7 In the example shown, corresponding to the "1" at the bit position corresponding to binary slice 3031 in the DAC input code V[n], one of the switches 624 (e.g., switch 624A) receives a switch control signal from switch logic 312, causing the switch to couple resistor 622A to output node BOUT1. All other switches 624 and 634 receive switch control signals, causing the switches to couple their corresponding resistors 622 and 632 to output node BOUT2. Therefore, in this example, the positive current +V ref / 2R is conducted to output node BOUT1. Conversely, in response to a “0” at the bit position corresponding to binary slice 3031 in the DAC input code V[n], one of the switches 634 (e.g., switch 634A) is controlled by the corresponding switch control signal to couple its resistor 632A to output node BOUT1; all other switches 624 and 634 receive switch control signals such that the switches couple their corresponding resistors 622 and 632 to output node BOUT2.
[0117] According to some embodiments, switch logic 312 is configured to control switches 624 and 634 in each binary slice 303 according to a mode that causes their resistors 622 and 632 to alternate between switches 624 and 634 of output node BOUT1 in each DAC input code V[n]. Figure 8This is an example state diagram of such a rotation according to some embodiments, wherein the switching logic 312 is implemented as sequential logic of a representative slice 3031 of binary segment 302. In an alternative to sequential logic, the switching logic 312 of binary segment 302 may be implemented as combinational logic, programmable logic that executes program instructions stored in memory, or a combination thereof.
[0118] exist Figure 8 In the example, the transition vector K is maintained for slice 3031 on the sequence of DAC input codes V[n]. B1 The constant value of [n] is J=2. Figure 8 In this example, the value J=2. For the purposes of this description, the “on” state of switches 624 and 634 indicates that output node OUT1 is selected to couple to its corresponding resistors 622 and 632; conversely, the “off” state of switches 624 and 634 indicates that output node OUT2 is selected to couple to its corresponding resistors 622 and 632. Furthermore, for the purposes of this example description, a “1” state (referred to as bit “B1”) in the bit position corresponding to slice 3031 in the DAC input code V[n] indicates that one of switches 624A, 624B, 624C, and 624D is on, while the other switches and all switches 634A, 634B, 634C, and 634D are off. Conversely, the "0" state in the bit position corresponding to slice 3031 in the DAC input code V[n] indicates that one of the switches 634A, 634B, 634C, and 634D is turned on, while the other switches and all switches 624A, 624B, 624C, and 624D are turned off.
[0119] Figure 8 An example sequence is shown, in which an "on" state position responds to a sample sequence of DAC input codes V[n] while... Figure 7 The switches 624 and 634 of slice 3031 alternate. For example, starting in state 802, switch 624A is turned on in response to a "1" at bit B1 of the DAC input code V[n]. All other switches 624 and 634 are in the "off" state. This is based on the constant value K of the transition vector. B1 In this example where [n]=2, switches 624 and 634 will change their states in response to the next DAC input code V[n+1], regardless of whether bit B1 is "0" or "1". In this example, bit B1 is "1" in response to the DAC input code V[n+1], and switch logic 312 executes a transition from state 802 to state 804, thereby turning off switch 624A and turning on switch 624B, and causing the value of the transition vector K to change. B1[n+1]=2. By selecting a different switch in switch 624 to remain on in response to bit B1 not changing from one input code to the next, a constant transition vector value is maintained, and the "on" switch position is also rotated among redundant switches 624. Figure 8 As shown, for the additional DAC input code, consecutive "1" values at bit B1 cause the "on" switch to cycle through the sequence from switch 624A to switch 624B (state 804) to switch 624C (state 806) to switch 624D (state 808) and back to switch 624A (state 802). The constant value K of the transition vector is always maintained. B1 [n]=2. In this case, the specific sequence of the switching 624 may differ. Figure 8 The sequence shown (e.g., from switch 624A to switch 624C to switch 624B to switch 624D, etc.) maintains a constant transition vector value and is rotated in switch 624.
[0120] Conversely, starting again from state 802, bit B1 in response to the DAC input code V[n+1] is "0". In this instance, switch logic 312 performs the transition from state 802 to state 814, thereby turning off switch 624A and turning on switch 634B. In fact, any change in bit B1 from "1" to "0" will necessarily change the transition vector value K. B1 [n+1]=2 because one switch 624 must be off and one switch 634 must be on. Similarly, any change in bit B1 from "0" to "1" (e.g., from...) Figure 8 The transition from state 814 to state 806 in the equation makes the transition vector value K... B1 [n+1]=2, because one switch 634 must be off and one switch 624 must be on. (Based on the included...) Figure 8 In some embodiments of the example, switch logic 312 is configured to enforce a cycle pattern of state transitions of bit B1 from "0" to "1" or from "1" to "0", for example... Figure 8 As shown. Similarly, the specific sequences in which switches 624 and 634 turn on and off in response to changes in the value of bit B1 may differ from those shown. Figure 8 The sequence shown maintains a constant transition vector value and alternates between switches 624 and 634. For example, bit B1 can change from "1" to "0" in state 802 by turning off switch 624A and turning on switch 634A (state 812), provided that one of switches 624B, 624C, or 624C is turned on in response to bit B1 changing from "0" to "1" starting from state 812 (instead of turning on switch 624A again).
[0121] Similarly, the continuous sequence of "0" values at bit B1 of the additional DAC input code causes the "on" switch to cycle through the switches in the following sequence: from switch 634A to switch 634B (state 814) to switch 634C (state 816) to switch 634D (state 818) and back to switch 634A (state 812). Throughout this sequence, the transition vector maintains a constant value K. B1 [n]=2, and the "on" state alternates between switches 634.
[0122] According to these embodiments, the redundancy provided by the multiple resistors 622 and 632 and the multiple corresponding switches 624 and 634 enables the switching logic 312 to target each slice 303 of the binary segment 302. k Maintain a constant transformation vector value K Bk [n], and is independent of the value of the DAC input code V[n]. As a result, the transition vector K of binary segment 302 B The value of [n] remains constant overall, independent of the input signal, which reduces harmonic distortion of the analog output signal from the DAC 150. Furthermore, this redundancy allows resistor selection to rotate among the components of each slice 303, thereby reducing the effects of residual static mismatch.
[0123] In some DAC systems, predistortion is applied to the DAC input signal to correct for nonlinearity and harmonics in the analog output signal. The predistortion of the input signal in these systems is based on the observed error in the output signal relative to the applied DAC input code.
[0124] Figure 9A An example of prior art for generating a predistorted signal and applying it to an input signal is shown, such as in conjunction with a DAC system for generating an analog sine wave. In this method, signal generator 900 generates a digital bitstream for generating the desired sine wave at the fundamental frequency f0. Multiple signal generators 9012 to 901... m A digital bitstream is generated to add predistortion signals at frequencies from 2f0 to mf0, corresponding to the second to m harmonics of the fundamental frequency f0. The amplitudes and phases of these predistortion signals are selected to cancel or compensate for the distortion in the analog output signal V. out_fin Harmonic distortion observed in [the signal generators]. (Sources: Signal generators 900 and 9012 to 901) m The sampling rate of the digital stream is at least twice the highest harmonic frequency mf0. In this prior art example, DACs 902 and 9032 to 903... m From signal generators 900 and 9012 to 901 m The digital stream is received as the DAC input code, and each input code generates a corresponding analog output signal. This applies to input signals from DACs 902 and 9032 to 903. mThe analog output signal is summed (e.g., by applying current to the input of a current-voltage buffer, or by summing the output voltage at a summing amplifier) to generate an analog voltage signal V. out1 Analog voltage signal V out1 It can consist of one or more analog circuit blocks (e.g., filters, buffers, or amplifiers), 9042 to 904. i Processing to generate an analog output signal V out_fin .
[0125] Figure 9B Another prior art example of generating a predistorted signal and applying it to an input signal is shown. In this example, signal generator 910 generates a digital code stream to generate a desired sine wave at its fundamental frequency f0. Multiple signal generators 9112 to 911 are also shown. m Digital code streams corresponding to harmonic frequencies from 2f0 to mf0 are generated, and their amplitudes and phases are selected to cancel or compensate in the analog output signal V. out_fin Harmonic distortion observed in [the data]. In this prior art example, [the signal] is generated from signal generators 910 and 9112 to 911. m The digital signal is applied to the input of the summing function 912, which digitally adds the streams to form a stream of DAC input code V[n], which is then applied to DAC 914. As in Figure 9A As in the example, the analog output from the DAC 914 can be supplied by one or more analog circuit blocks (e.g., filters, buffers, or amplifiers) from 9162 to 916. i Processing to generate an analog output signal V out_fin .
[0126] It has been observed Figure 9A and 9B The limitations of each of these existing technological methods. Figure 9A In the method shown, the signals from multiple DACs 902 and 9032 to 903 are... m This method involves adding the analog output signals, which requires a large chip area and strict constraints on device matching between multiple DACs. Figure 9B In the method, the signals from signal generators 910 and 9112 to 911 are... m The outputs are digitally summed to be applied to the DAC 914. This method has proven ineffective in achieving the desired harmonic distortion reduction within the range of input bit depth (e.g., 18 to 20 bits) and the resolution range of the DAC 914. Multiple digital signal generators 910 and 9112 to 911... m It also requires a significant increase in chip area.
[0127] Some embodiments overcome some or all of the problems of the prior art.
[0128] Figure 10 A DAC 1000 according to some embodiments is shown. The DAC 1000 includes registers 10020 to 10020. m The register stores a frequency tuning word (FTW) for each of a plurality of frequencies. Each FTW contains an indication of the desired analog output signal V. out The information pertains to the amplitude and phase of the frequency components. In this example, register 10020 stores the frequency tuning word FTW0 for the fundamental frequency f0. For the desired analog output signal V... out In the case of a sinusoidal waveform, FTW0 indicates the amplitude and phase at the fundamental frequency. Register 10022 stores the frequency tuning word FTW2, which indicates the amplitude and phase of the correction signal at the second harmonic 2f0 of the fundamental frequency. Additional register 1002 is provided for higher-order harmonics, up to a maximum of register 1002. m It is used to store the correction signal of the highest order (mth) harmonic mf0 to be corrected.
[0129] In these embodiments, register 1002 is coupled to the input of time-division multiplexed multi-tone signal generator 1010. Signal generator 1010 may be powered by digital processor 310. Figure 3 The signal generator 1010 performs the operation, for example, by its signal conditioning logic 314. As described in detail below, in these embodiments, the signal generator 1010 generates a switch control signal corresponding to a DAC input code V[n], the number of bits (e.g., N+E bits) of which is greater than the nominal N-bit width of the DAC 100. The switch control signal of the N+E-bit DAC input code V[n] is forwarded to the DAC array 1020, which includes, for example... Figure 3 The thermometer segment 300, binary segment 302, and R-2R segment 304 are arranged as shown. As described above, segments 300, 302, and 304 are coupled to output nodes OUT1 and OUT2. Output node OUT1 is coupled to the negative input of the current-voltage buffer amplifier 320, while output node OUT2 is coupled to circuit ground (e.g., via a ground buffer in some embodiments) and the positive input of amplifier 320. Feedback resistor 322 and capacitor 324 are coupled in parallel between the output and negative input of amplifier 320. The output of amplifier 320 at terminal VOUT will simulate the output signal V. out Provided to downstream circuits (e.g., Figure 1 The inputs of the circuit 130 and the harmonic distortion measurement circuit 1030.
[0130] In some embodiments, the harmonic distortion measurement circuit 1030 monitors the analog output signal V from the amplifier 320. outTo identify distortion at harmonic frequencies 2f0, 3f0…mf0, and based on the identified output distortion, to load the frequency tuning words FTW2 to FTWm into registers 10022 to 1000. m In these tuning words, the amplitude and phase of the correction signal components at these frequencies are indicated. In some instances, the harmonic distortion measurement circuit 1030 may also include a circuit system for identifying static corrections, which may be applied to the DAC 1000, for example, by fine-tuning the DAC (e.g., as shown in Figure 2).
[0131] Figure 11 An arrangement of a DAC array 1020 according to some embodiments is shown. In this arrangement, the thermometer segment 300 of the DAC array 1020 includes T slices 3011 to 301 T (Corresponding to T MSBs of the N-bit DAC input code V[n]. In this example, binary segment 302 contains slices 3031 and 3032 of binary segment 302 (corresponding to B=2 ULSBs of the N-bit DAC input code V[n]); binary segment 302 may alternatively contain more (or fewer) binary slices 303. The R-2R segment 304 of DAC array 1020 contains L slices 3051, 3052, 3053, etc. (corresponding to L LSBs of the N-bit DAC input code V[n], where the numbers T+B+L=N). In addition, the R-2R segment 304 contains E additional slices 305', containing Figure 11 The example shown is slice 305 E-1 'and 305 E The number of these additional slices 305' can vary depending on the implementation. In one example, the DAC array 1020 contains E=6 additional slices 305'. As described above, these additional slices 305' exceeding the bit width N of the DAC 1000 are controlled by a time-division multiplexed multi-tone signal generator 1010 to further correct harmonic distortion at the output.
[0132] For simplicity, Figure 11 The schematic diagram shows that each slice 301, 303 is shown as a single resistor element with a single switch, which selectively couples its resistor to output node OUT1 or output node OUT2. In some embodiments, thermometer slice 301 is configured to include redundant elements, as described above. Figures 3 to 5C As described above. In some embodiments, the binary slice 303 is configured to include redundant elements, as described above. Figures 6 to 8 As described.
[0133] For simplicity as well, the DAC array 1020 is... Figure 11 The diagram shows the voltage from a single reference voltage (in this example, a positive reference voltage +V). refBias. In some embodiments, the DAC array 1020, comprising thermometer slice 301, binary slice 303, and R-2R segments 305, 305', is arranged in a pseudo-differential architecture as described above and in U.S. application SN 18 / 814,694, which is incorporated above.
[0134] refer to Figure 11 Thermometer slices 3011 to 301 T Each of the binary slices has a nominal resistance R, whether as a single resistor with resistance R, or as two redundant parallel resistors each with resistance 2R, or as four parallel resistors each with resistance 4R, etc. Therefore, the first binary slice 3031 has a nominal resistance 2R (e.g., twice the nominal resistance R of thermometer slice 301), and the second binary slice 3032 has a nominal resistance 4R, twice that of its next most significant binary slice 3031. Any additional low-order significant binary slice 303... k The resistor will be its next most significant binary slice 303 k-1 Twice the nominal resistance.
[0135] The R-2R slice 3051 includes resistors 1101 and 1103. Resistor 1101 is coupled to a reference voltage +V on one side. ref And on the other side, it is coupled to resistor 1101 in resistor 1103 and the next R-2R slice 3052. The resistance of resistor 1101 is half the nominal resistance of the lowest-order binary slice 3032. Figure 11 In the example where slice 3032 has a nominal resistance of 4R, resistor 1101 has a resistance of 2R. Resistor 1103 has a resistance of 4R, twice the resistance of resistor 1101 in slice 3011, in this case, the latter has a resistance of 4R. Resistor 1103 is coupled to switch 1104, which selectively couples slice 3051 to output node OUT1 or output node OUT2.
[0136] R-2R sections 3052, 3053, etc., and section 305 E-1 '、305 E Each includes a resistor 1101 with a resistance of 2R, a resistor 1103 with a resistance of 4R, and a switch 1104, arranged in a manner similar to that of slice 3051. In this example, slice 3052 is coupled to slice 3051 in sequence, slice 3053 is coupled to slice 3052, and so on, up to slice 305. E A terminating resistor 1105 with a resistance of 4R is coupled to the last slice 305. E 'Between circuit ground. In this arrangement of R-2R segment 304, the reference voltage +V is obtained from the given slice 305.'ref The conducted current is half the current of the next most active slice 305 (or slice 3032 in the case of slice 3051). In response to the state of the bits of the DAC input code V[n] associated with slice 305, the current from said slice 305 is conducted to output node OUT1 or output node OUT2. On the other hand, in response to the frequency tuning word FTW2 to FTW generated by the time-division multiplexed multi-tone signal generator 1010... m The state of one of the generated E extended bits corresponds to the current from one of the E slices 305', which is conducted to output node OUT1 or output node OUT2. As described above, according to these embodiments, harmonic distortion can be further reduced by providing and controlling the current from an additional E slices 305' exceeding the N-bit width of the DAC 1000.
[0137] Figure 12A Functionally, this illustrates the generation of the tone k of a correction signal based on a frequency tuning word FTWk of a tone k in a time-division multiplexed multi-tone signal generator 1010, according to some embodiments. The arrangement in Figure 12 corresponds to a direct digital frequency synthesis (DDFS) architecture. Register 1002 k The FTWk of pitch k is stored and applied to one input of adder 1201 in phase accumulator 1202. Adder 1201 adds the value of FTWk to the accumulated phase value stored as an N-bit value in phase buffer 1203. In this example, any overflow beyond the value 2π in the accumulated phase value is simply wrapped around. Therefore, the output of phase accumulator 1202 has a linear sawtooth characteristic as shown in Figure 12, at 2 N Within each interval of / FTWk cycles, progress from 0 to 2π.
[0138] The output of phase accumulator 1202 is applied to quadrant mapping logic 1206. Quadrant mapping logic 1206 maps the accumulated phase value from the phase accumulator to 2. N The range from 0 to π / 2 within each of the four quadrants of / FTWk loops is applied using the symmetry of a sinusoidal waveform. Therefore, the output of quadrant mapping logic 1206 corresponds to a triangular waveform with a frequency twice that of the sawtooth waveform from phase accumulator 1202.
[0139] The output of quadrant mapping logic 1206 is applied to phase-sine lookup table (LUT) memory 1208. LUT memory 1208 is arranged as a memory resource where each value output by quadrant mapping logic 1206 addresses a value in LUT memory 1208 representing a point along a rectified sine wave with the same frequency as the triangular waveform from quadrant mapping logic 1206, as shown in Figure 12. LUT memory 1208 can output this sine wave as an M-bit sample stream, where M represents a number of bits larger than N bits for FTWk. For example, M can be equal to N+E, where E is the number of extended slices 305' in DAC array 1020.
[0140] The sign correction and offset addition logic 1210 generates a digital value that follows a complete sine wave based on the rectified sine wave output from the LUT memory 1208, and adds an offset according to the required DC level of the sine wave. The sine wave presented by the DAC input code stream output by the sign correction and offset addition logic 1210 has a similar characteristic to 2... N / FTWk cycles correspond to the period of the interval.
[0141] Figure 12B This is an illustrative example of multi-tone signal generation according to some embodiments, such as that implemented by a pipelined time-division multiplexed multi-tone signal generator 1010. Figure 12B In this example, a multi-tone signal can be generated as a weighted sum of three signals 1251, 1252, and 1253 with different frequencies, amplitudes, and phases. In this example, for instance, by combining... Figure 12A The described DDFS method generates signal 1251 with frequency f1, gain G1, and phase φ1. Signals 1252 and 1253 are similarly generated by DDFS, where signal 1252 is at frequency f2, gain G2, and phase φ2, and signal 1253 is at frequency f3, gain G3, and phase φ3. In this example, frequency f2 is higher than frequency f1 (e.g., at the second harmonic), and frequency f3 is higher than frequency f2 (e.g., at the mth harmonic, where m>2). The three signals 1251, 1252, and 1253 are summed at arithmetic unit 1255 to produce a multi-tone signal 1254. For signals with... Figure 12B The waveform shown is an example of signal 1254, with gain G1 of 0.5 and gains G2 and G3 both of 0.25.
[0142] As mentioned above, this is combined with existing technologies. Figure 9B The aforementioned uses multiple digital signal generators 910 and 9112 to 911. m Generating multi-tone signals significantly increases the additional chip area. According to some embodiments, Figure 10The pipelined time-division multiplexed multi-tone signal generator 1010 of the DAC 1000 shown avoids this additional cost by digitally generating multi-tone signals in a time-division multiplexed and pipelined manner to be applied to the DAC array 1020.
[0143] Figure 13 Illustrations are shown according to some embodiments Figure 3 The architecture of the signal conditioning circuit 314 incorporates a pipelined time-division multiplexed multi-tone signal generator 1010. In this architecture, the signal generator 1010 has connections to registers 10020 to 1002... m The input. With Figure 9B Compared to multiple digital signal generators, the signal generator 1010 according to some embodiments includes phase accumulators 12020 to 1202... m The phase accumulators each have registers 10020 to 1002... m Receive frequency tuning words FTW0 to FTW m Phase accumulators 12020 to 1202 m The output has a corresponding input coupled to the multiplexer 1314. The multiplexer 1314 has a control input coupled to the output of the tone selection circuit 1312 and an output coupled to the input of the quadrant mapping logic 1316. The quadrant mapping logic 1316 may be implemented as a logic circuit system or as, for example, a read-only memory (ROM) (e.g., implemented as a lookup table).
[0144] According to some embodiments, the pipeline control unit 1310 controls the timing of various circuits and functions in the signal generator 1010. The pipeline control unit 1310 can be implemented as a logic circuit system, such as a combined, sequential, or programmable logic circuit system operating synchronously with a clock signal CLK from a clock circuit system (not shown) in the DAC 1000. Figure 13 As shown, the pipeline control unit 1310 clocks the tone selection circuit 1312 to control the phase selection circuit 1312 via the phase accumulator 12020 to 12022. m Initiate the phase accumulation cycle and control the multiplexer 1314 to select phase accumulators 12020 to 1202 in the same sequential order. m The output is forwarded to quadrant mapping logic 1316.
[0145] Quadrant mapping logic 1316 maps the accumulated phase at its input from a sawtooth waveform shape to a triangular waveform, such as... Figure 12AAs described in the DDFS method. The output of quadrant mapping logic 1316 is applied to the input of sine calculation circuit 1318, which performs the functions of sine LUT 1208 (converting a triangular waveform into a rectified sine wave) and sign correction and offset addition 1210, both as described above. Figure 12A As described. The output of the sine calculation circuit 1318 is coupled to the input of the adder 1320. In some embodiments, the output of the sine calculation logic 1318 is in the form of an N+E bit digital word, extending the bit width of the sine sample value by E bits, beyond the N-bit specified resolution of the DAC 1000 (e.g., as from the frequency tuning word FTW0 to FTW). m The N-bit width indicates this. These E bits correspond to the DAC array 1020 (…). Figure 11 ) of the E slices of segment 304 of R-2R segment 305'.
[0146] From frequency tuning word FTW0 to FTW m The time-division multiplexing of the indicated pitch is achieved by sequentially applying phase accumulators 12020 to 1202 using multiplexer 1314. m And that's how it's achieved. Because it comes from phase accumulators 12020 to 1202. m The accumulated phases are applied sequentially, so the sine calculation circuit 1318 is processing the sine value of one tone, while the quadrant mapping logic 1316 is processing the accumulated phase of the next tone in the sequence.
[0147] Adder 1320 has an output coupled to the input of buffer 1322, and the output of buffer 1322 is coupled to a second input of adder 1320. Therefore, under the control of pipeline control unit 1310, adder 1320 and buffer 1322 accumulate values corresponding to the frequency tuning words FTW0 to FTW. m An instance of the calculated sine value for each tone. Additional calculations can be performed in conjunction with buffer 1322 when appropriate, such as as needed to generate a correct sine wave. Thus, this accumulation of the calculated sine values for each tone generates a digital multi-tone signal (e.g., Figure 12B A sample of the multi-tone signal 1254. The output of buffer 1322 is coupled to switching logic 312 and fine-tuning function 1330.
[0148] In some embodiments, the signal generator 1010 is clocked at a rate at least m times higher than the sampling frequency of the DAC input code V[n] to enable time-division multiplexing and pipelined generation of digital multitone signals. For an example of an octave multitone signal, the signal generator 1010 must be clocked at a rate at least 8 times (e.g., 10 times) the sampling frequency of the DAC input code.
[0149] exist Figure 13 In the example architecture, switch logic 312 generates appropriate switch control signals SCW for the switches in thermometer segment 300 and binary segment 302, for example, based on the above combined with Figure 6 and 8 The described embodiments. In some embodiments, the fine-tuning circuit 1330 may apply the output of the fine-tuning DAC (not shown) to the least significant bit of the multi-tone sample corresponding to the R-2R segment 304, for example, to correct inter-symbol interference (ISI). Additional fine-tuning stages 1332, 1334 may follow the switching logic 312 and the fine-tuning stage 1330, for example, to apply corrections from the fine-tuning DAC (not shown) to correct static mismatch and other fine-tuning correctable errors (e.g., similar to...). Figure 2B The output of the final fine-tuning stage 1334 is applied to the output buffer 1336, which stores the corrected multi-tone signal samples for application to the DAC array 1020, for example, synchronized with the clock signal DACsync at the sampling frequency of the DAC input code V[n].
[0150] Figure 14 Illustrations are shown according to some embodiments Figure 13 An example of the operation of the signal conditioning circuit 314, which includes a pipelined time-division multiplexed multi-tone signal generator 1010. According to this example, the signal generator 1010 generates four tones, such as the fundamental tone at frequency f0 and the second to fourth harmonics of said tone at frequencies 2f0, 3f0, and 4f0. Therefore, the signal generator 1010 operates at a clock rate at at least four times the sampling rate of the DAC input code V[n] (e.g., ...). Figure 13 The operation is performed using the clock rate of the clock CLK in the system. Figure 14 In this example, the oversampling at signal generator 1010 is seven times the sampling rate of the DAC input code V[n] to allow sufficient setup time at the input of DAC array 1020 and to provide a transition interval between consecutive codes. More specifically, as Figure 14 As shown, the clock period CLK of signal generator 1010 is 11 nanoseconds, while the sampling clock period of DAC input code V[n] at DAC array 1020 is 77 nanoseconds.
[0151] In example Figure 14 In some embodiments shown, the signal generator 1010 operates in six pipeline stages to time-division multiplex the digital values of four tones in this example. (See combined references) Figure 13 and 14 The six pipeline stages in this example are:
[0152] Tone: Tone selection circuit 1312 pairs phase accumulators 12020 to 1202 mOne of the output selections
[0153] Quadrant Mapping ROM: Maps the sawtooth waveform from phase accumulator 1202 to the triangular waveform at quadrant mapping ROM 1316.
[0154] Sine calculation: The output of quadrant-mapped ROM 1316 is applied to the sine calculation circuit (LUT) 1318.
[0155] Summation: The sine values of the four tones are accumulated at adder 1320 and buffer 1322.
[0156] ISI: Operation of switch logic 312 and fine-tuning function 1330 for ISI correction.
[0157] Fine-tuning: Operations at fine-tuning levels 1332 and 1334
[0158] Each sample of the multi-tone signal (e.g., DAC input code V[n]) output from the fine-tuning stages 1332 and 1334 is stored in buffer 1336 for a number of cycles of clock CLK corresponding to the sampling clock (clock DACsync) period at DAC array 1020.
[0159] For example, according to an embodiment, Figure 13 The process of signal generator 1010 generating DAC input code V[0] representing a multi-tone signal in a pipelined time-division multiplexing manner begins at phase accumulators 12020 to 12020. m Phase accumulation is performed on the frequency tuning words FTW0 to FTWm. This phase accumulation is clock-controlled, for example, by the pipeline control unit 1310, and is synchronized with the DAC input code (e.g., the sampling clock DACsync). Figure 14In the first CLK cycle (0 ns), multiplexer 1314 selects the output of phase accumulator 12020 as the fundamental tone (tone 0). In the next CLK cycle (11 ns), quadrant mapping ROM 1316 outputs the mapped value R0 as tone 0, while in the same CLK cycle, multiplexer 1314 selects the output of phase accumulator 12021 as tone 1 (e.g., second harmonic). In the CLK cycle at 22 ns, the mapped value R0 of tone 0 is applied to sine wave calculation circuit 1318, outputting value S0. Also in the CLK cycle at 22 ns, quadrant mapping ROM 1316 outputs the mapped value R1 as tone 1, and multiplexer 1314 selects the output of phase accumulator 12022 as tone 2 (e.g., third harmonic). In the CLK loop at 33 ns, the value S0 output by the sine calculation circuit 1318 is stored (=S0) in buffer 1322 (buffer 1322 has been cleared of any previous DAC input codes). Also in this CLK loop at 33 ns, the mapped value R1 of tone 1 is applied to the sine calculation circuit 1318, which outputs the value S1. The quadrant mapping ROM 1316 outputs the mapped value R2 of tone 2, and the multiplexer 1314 selects the output of the phase accumulator 12023 as tone 3 (e.g., the fourth harmonic).
[0160] In the CLK loop at 44 ns, adder 1320 adds the value S1 of tone 1 from sine calculation circuit 1318 to the contents S0 of buffer 1322, thereby accumulating the sine values of tone 0 and 1. Also in this CLK loop at 44 ns, the mapped value R2 of tone 2 is applied to sine calculation circuit 1318, which outputs value S2, and quadrant mapping ROM 1316 outputs the mapped value R3 of tone 3. Processing of the next DAC input code value also begins in the CLK loop at 44 ns, where multiplexer 1314 selects the output of phase accumulator 12020 as the fundamental tone (tone 0) of the next DAC input code V[1].
[0161] This pipelined operation of the signal generator 1010 continues in the same manner within successive CLK cycles. In the CLK cycles at 55 ns and 66 ns, adder 1320 adds the values S2 and S3 to the accumulated sine values in buffer 1322, respectively, thereby generating the sum Σ0 of the DAC input codes V[0] at the output of buffer 1322 in CLK cycle 66. In these cycles, the earlier pipeline stages (sine calculation, quadrant mapping ROM, tone) are processed to obtain the tone of the next DAC input code V[1]. In the CLK cycles at 77 and 88 ns, the sum Σ0 of the DAC input codes V[0] is processed by switching logic 312 for the thermometer segment and binary segment, and by fine-tuning stage 1330 for the R-2R segment (value D0). In this example, during a CLK cycle starting at 99 ns and continuing for six CLK cycles, buffer 1336 retains and outputs (to DAC array 1020) the value T0 of the DAC input code V[0] from trimmer stages 1332 and 1334. The first two CLK cycles (77 and 88 ns) during which buffer 1336 retains and outputs the value T0 of the DAC input code V[0] provide sufficient setup time for DAC array 1020, which begins accepting the value T0 from the CLK cycle at 121 ns. During the CLK cycle at 154 ns, DAC array 1020 is clocked by clock DACsync.
[0162] It is evident from these embodiments that multi-tone correction signals can be generated in a pipelined and time-division multiplexed manner, extending beyond the data path bit width at the input of the DAC system to an additional LSB, without requiring multiple signal generator circuits. For high-precision DACs, excellent total harmonic distortion compensation is achieved.
[0163] like Figure 10 As shown, the DAC 1000 according to some embodiments includes a harmonic distortion measurement circuit 1030. In these embodiments, the harmonic distortion measurement circuit 1030 includes, for example, a precision analog-to-digital converter (ADC) for periodically monitoring the signal at the output terminal VOUT, thereby measuring distortion at various harmonic frequencies from 2f0 to mf0. Based on these measurements, the harmonic distortion measurement circuit can determine and adjust the frequency tuning words FTW2 to FTWm to be stored in registers 10022 to 1002 respectively. m Based on these frequency tuning words FTW2 to FTWm, a signal generator circuit 1010, according to some embodiments, generates a correction signal component at the corresponding harmonic frequency, as described above. In such embodiments, closed-loop correction of harmonic distortion can be provided.
[0164] In some embodiments, the frequency tuning words FTW2 to FTWm for correcting harmonic distortion at corresponding harmonic frequencies 2f0 to mf0 are determined and stored in registers 10022 to 1002 during manufacturing. m In this type of embodiment, the frequency tuning words FTW2 to FTWm obtained by the harmonic distortion measurement circuit 1030 are implemented off-chip, for example, by a test device. In these embodiments, registers 10002 to 1000 m It can be implemented using non-volatile memory (e.g., electrically programmable or fuse-programmable memory locations).
[0165] Figure 15 This is a flowchart of a binary search method according to some embodiments for obtaining frequency tuning words FTW2 to FTWm, thereby generating the corresponding component of the correction signal applied in DAC 1000. Figure 15 The process can be performed, for example, by external testing equipment, or by the harmonic distortion measurement circuit 1030 within the DAC 1000. This will be combined with... Figure 16 The example shown is used to describe Figure 15 The process of operation.
[0166] In process 1502, a harmonic k is selected to determine its frequency tuning word FTWk. In process 1504, a distortion signal at frequency kf0 and a selected phase is generated, for example, by an external test circuit system or by a signal generator circuit 1010, and applied to DAC 1000 as a sample stream of DAC input code V[n]. This distortion signal may be applied in combination with the DAC input code V[n] of the tone at fundamental frequency f0. In process 1506, the amplitude of the harmonic distortion at frequency kf0 at the output of DAC 1000 is measured, for example, by an external test device or harmonic distortion measurement circuit 1030. In process 1510, the distortion signal at frequency kf0 and different selected phases is applied to DAC 1000, and the harmonic distortion at these different phases is measured. Therefore, harmonic distortion at frequency f0 is measured for at least two phases in processes 1506 and 1510. In some embodiments, process 1510 may be repeated one or more times. In process 1512, the measured values of harmonic distortion at the selected phase are compared.
[0167] exist Figure 16 In the example, the left-hand graph corresponds to the first set of measurement results, that is, to... Figure 15The flowchart shows processes 1506 and 1510. For example, vector 1600 corresponds to the distortion signal at frequency kf0 and phase 0° (e.g., generated and measured in processes 1504 and 1506), and vector 1601 corresponds to the distortion signal at phase 180° (e.g., generated and measured in process 1510). The comparison of harmonic distortion measured at phases 0° and 180° indicates which phase better compensates for the harmonic distortion of the DAC1000 at frequency kf0 (e.g., resulting in less measured distortion).
[0168] exist Figure 15 In process 1514, one or more phases can be selected for the next iteration of harmonic distortion measurement based on the results of process 1512. For Figure 16 For example, the distortion measurement result at phase 180° is lower than the distortion measurement result at 0°, so phases 135° and 225° are selected in process 1512, as shown in the intermediate figure. In process 1516, the distortion signal at the phase selected in process 1514 is applied to the DAC 1000, and the harmonic distortion at these phases is measured and compared. The comparison in process 1516 may also include harmonic distortion measurements previously obtained for other phases (e.g., phases selected in process 1504 or in previous iterations of process 1514). Figure 16 As shown, vector 1620 represents the distorted signal at a phase of 135°, and vector 1621 represents the distorted signal at a phase of 225°.
[0169] Decision 1517 determines whether the convergence criterion for compensating for the distortion signal's phase has been met. An example of a convergence criterion is whether the measured harmonic distortion of one of the phases selected in procedure 1514 is below a predetermined limit. Alternatively (or additionally), the convergence criterion may be a pre-selected number of iterations. If the convergence criterion is not met (Decision 1517 is "No"), procedure 1514 is executed again to select one or more additional phases based on the comparison results in procedure 1516.
[0170] exist Figure 16 In the example, the comparison in process 1516 has determined that the harmonic distortion at phase 135° is less than the harmonic distortion at phase 225°, but greater than the harmonic distortion at phase 180°. Therefore, it can be concluded that the correct compensation phase lies between 135° and 180°. In this case, the next iteration of process 1514 can select a single phase, for example, at the midpoint 157.5°, by... Figure 16 Vector 1620 in the right-hand diagram represents this. Alternatively, two or more phases can be selected in this iteration of process 1514 (e.g., if the lowest distortion measurement is at phase 135°, then phases 112.5° and 157.5° can be selected).
[0171] Then in one or more selected phases (e.g., Figure 16 In the example of 157.5°, process 1516 is executed again. Decision 1517 is executed again to determine whether the convergence criterion has been met; if not (decision 1517 is "no"), the process continues with the additional phase selection in process 1514.
[0172] The phase assessment of harmonic frequency kf0 is completed when the convergence criterion is met (decision 1517 is "yes"). This indicates that... Figure 15 The frequency tuning word FTWk, which identifies the amplitude and phase during processing, is stored in register 1002. k In the denominator, kf0 is used to represent the harmonic frequency.
[0173] Then, decision 1519 is executed to determine whether it is still necessary to determine the frequency tuning word for other harmonic frequencies. If so (decision 1519 is "yes"), then procedure 1502 is executed again to select the next harmonic k for analysis, and the above procedure is repeated. If all harmonics have been evaluated (decision 1519 is "no"), then... Figure 15 The process is complete.
[0174] Exemplary embodiments of this disclosure are outlined herein. Other embodiments may also be understood from the entire specification and claims submitted herein.
[0175] Example 1. A digital-to-analog converter circuit comprising: a thermometer segment corresponding to a number of T input bits and having a first output terminal and a second output terminal, the thermometer segment comprising: a first plurality of resistors, the number of which is M, M being at least 2T, each of the first plurality of resistors being coupled to a first reference voltage terminal, the first plurality of resistors having substantially equal resistance to each other; and a first plurality of switches, the number of which is at least 2T, each of the first plurality of switches being associated with and coupled on one side to a corresponding one of the first plurality of resistors, each of the first plurality of switches being configured to, in response to a control signal of the switch, couple its associated resistor to the first output terminal or the second output terminal; and an output amplifier having an input coupled to the first output terminal.
[0176] Example 2. The circuit according to Example 1 further includes a ground buffer having an output coupled to the second output terminal.
[0177] Example 3. A circuit according to one of Examples 1 or 2, further comprising: switching logic having inputs configured to receive T input bits and having outputs coupled to the first plurality of switches, the switching logic being configured to: receive T input bits representing a first digital value V[n]; in response to the first digital value V[n], provide control signals to the first plurality of switches such that M × V[n] switches select the first output terminal and the remaining switches select the second output terminal; receive T input bits representing a second digital value V[n+1]; and in response to the second digital value V[n+1], change a selected number C of the control signals provided to the first plurality of switches such that M × V[n+1] switches select the first output terminal and the remaining switches select the second output terminal, the number C being a constant regardless of whether the second digital value V[n+1] is greater than, less than, or equal to the first digital value V[n].
[0178] Example 4. A circuit according to any one of Examples 1 to 3, wherein the switching logic is configured to, in response to the second digital value V[n+1], modify the C control signals provided to the first plurality of switches by: encoding a thermometer code in response to the second digital value V[n+1], the thermometer code being represented as consecutive "1" bits and consecutive "0" bits; comparing the second digital value V[n+1] with the first digital value V[n]; changing a pointer value by an amount determined in response to whether the second digital value V[n+1] is greater than, less than, or equal to the first digital value V[n] and in response to a random value; shifting the thermometer code in response to the changed pointer value; and providing control signals to the first plurality of switches according to the shifted thermometer code.
[0179] Example 5. A circuit according to one of Examples 1 to 4, wherein the switching logic includes a cyclic shifter, wherein the switching logic is further configured to: store the thermometer code in the cyclic shifter; and shift the stored thermometer code by applying a shift value corresponding to the pointer value to the shifter, wherein each of the first plurality of switches is associated with a bit position of the cyclic shifter.
[0180] Example 6. A circuit according to any one of Examples 1 to 5, wherein the quantity C is 2, wherein the switching logic is further configured to randomly select the random value as either a positive or negative value, and wherein the switching logic is further configured to change the pointer value by: changing the pointer value by the random value in response to the second digital value V[n+1] being equal to the first digital value V[n]; changing the pointer value by the random value in response to the second digital value V[n+1] being greater than the first digital value V[n]; and changing the pointer value by the difference between the first digital value and the second digital value minus the random value in response to the second digital value V[n+1] being less than the first digital value V[n].
[0181] Example 7. A circuit according to any one of Examples 1 to 6, further comprising: a binary segment corresponding to a quantity B input bits and having an output terminal coupled to the first input of the output amplifier, the binary segment comprising: a second plurality of resistors, each associated with one of the B input bits and having a resistance twice that of the resistor associated with the next most significant bit of the B input bits; and a second plurality of switches, each associated with a corresponding one of the second plurality of resistors and coupled on one side to the corresponding one of the second plurality of resistors, each of the second plurality of switches being configured to selectively couple its associated resistor to the first output terminal in response to a control signal of the switch; and switch logic having an input configured to receive a digital value comprising T input bits and B input bits, the T input bits having higher bit weights than the B input bits in the digital value, and having an output configured to provide a control signal to the first plurality of switches and the second plurality of switches.
[0182] Example 8. According to one of Examples 1 to 7, the circuit further comprises: an R-2R segment corresponding to a number of L input bits and having an output terminal coupled to the input of the output amplifier, the R-2R segment comprising: a third plurality of resistors comprising a first resistor and a second resistor for each of the L input bits, wherein the first resistor for the L input bits is coupled in series between the binary segment and a common potential, and wherein the second resistor for each of the L input bits is coupled on one side to its associated first resistor; and a third plurality of switches, each associated with one of the L input bits and coupled on one side to the second resistor associated with its input bit, each of the third plurality of switches being configured to selectively couple its associated resistor to the first output terminal in response to a control signal of the switch; and wherein the input of the switch logic is configured to receive a digital value comprising T input bits, B input bits, and L input bits, the L input bits having a lower bit weight than the B input bits in the digital value, the switch logic further comprising an output configured to provide a control signal to the third plurality of switches.
[0183] Example 9. A circuit according to any one of Examples 1 to 8, wherein the thermometer segment further comprises: a second plurality of resistors, numbered at least 2T, each of the second plurality of resistors being coupled to a second reference voltage terminal, the second plurality of resistors having substantially equal resistance to each other; and a second plurality of switches, numbered at least 2T, each of the second plurality of switches being associated with and coupled on one side to a corresponding one of the second plurality of resistors, each of the second plurality of switches being configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a control signal of the switch, wherein each of the second plurality of switches is configured to operate in a complementary manner relative to one of the first plurality of switches associated with it; and wherein the second output terminal is coupled to a second input of the output amplifier.
[0184] Example 10. A digital-to-analog converter circuit comprising: a binary segment having a first output terminal and a second output terminal, the binary segment comprising one or more slices, each slice corresponding to one of a number B input bits of an input code, each slice comprising: a first plurality of resistors, each coupled to a first reference voltage terminal, the first plurality of resistors having substantially equal resistances to each other; a first plurality of switches, each associated with and coupled to a corresponding one of the first plurality of resistors, each of the first plurality of switches being configured to, in response to a control signal of the switch, select either the first output terminal or the second output terminal to couple to its associated resistor; a second plurality of resistors, each coupled to a second reference voltage terminal, the second plurality of resistors having substantially equal resistances to each other and substantially equal to the resistances of the first plurality of resistors associated with their respective positions; and a second plurality of switches, each associated with and coupled to a corresponding one of the second plurality of resistors on one side, each of the second plurality of switches being configured to, in response to a control signal of the switch, associate its... A resistor is coupled to either the first output terminal or the second output terminal; an output amplifier having an input coupled to the first output terminal; and switching logic having inputs configured to receive B input bits of the input code and configured to provide control signals to the first plurality of switches and the second plurality of switches of each slice of the binary segment, in response to the input bit corresponding to the slice having a first logic state, coupling a single resistor of the first plurality of resistors to the first output terminal and coupling the other resistors of the first plurality of resistors and each of the second plurality of resistors to the second output terminal, and in response to the input bit corresponding to the slice having a second logic state, coupling a single resistor of the second plurality of resistors to the first output terminal and coupling the other resistors of the second plurality of resistors and each of the first plurality of resistors to the second output terminal; wherein the resistance of each of the first plurality of resistors and the second plurality of resistors of each slice is twice the resistance of the resistor of the slice corresponding to the next most significant input bit of the input code.
[0185] Example 11. The circuit according to Example 10, wherein the switching logic is further configured to: sequentially receive B input bits of a plurality of input codes; wherein providing control signals to the first plurality of switches and the second plurality of switches in response to receiving the second input code value comprises changing the state of a number J of the first plurality of switches and the second plurality of switches in each of the slices of the binary segment, the number J being a constant with respect to the plurality of input codes.
[0186] Example 12. A circuit according to one of Examples 10 or 11, wherein the switching logic is further configured to: for each of the plurality of slices corresponding to an input code bit having the first logic state in the first input code, provide a control signal to the first plurality of switches to couple another single resistor of the first plurality of resistors to the first output terminal in response to the input code bit of the next consecutive input code also having the first logic state; and for each of the plurality of slices corresponding to an input code bit having the second logic state in the first input code, provide a control signal to the second plurality of switches to couple another single resistor of the second plurality of resistors to the first output terminal in response to the input code bit of the next consecutive input code also having the second logic state.
[0187] Example 13. A circuit according to one of Examples 10 to 12, wherein the number of resistors in each of the first plurality of resistors and the second plurality of resistors in each of the plurality of slices is greater than two.
[0188] Example 14. A circuit according to one of Examples 10 to 13, wherein the second reference voltage terminal receives a negative voltage having the same magnitude as the voltage received at the first reference voltage terminal.
[0189] Example 15. A circuit according to any one of Examples 10 to 14, further comprising: a thermometer segment having a first output terminal and a second output terminal, the binary segment comprising a plurality of slices, each slice corresponding to one of the number T input bits of the input code, each slice comprising: a third plurality of resistors, numbered at least two, each of the third plurality of resistors being coupled to the first reference voltage terminal, the third plurality of resistors having substantially equal resistance to each other; and a third plurality of switches, numbered at least two, each of the third plurality of switches being associated with and coupled on one side to a corresponding one of the third plurality of resistors, each of the third plurality of switches being configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a control signal of the switch; and a fourth plurality of resistors, numbered at least two, each of the fourth plurality of resistors being coupled to the second reference voltage terminal, the third... Four plurality of resistors having substantially equal resistance to each other; and a fourth plurality of switches, numbering at least two, each of the fourth plurality of switches being associated with and coupled on one side to a corresponding one of the fourth plurality of resistors, each of the fourth plurality of switches being configured to select either a first output terminal or a second output terminal to couple to its associated resistor in response to a control signal of the switch; wherein the first output terminal of the thermometer segment is coupled to the input of the output amplifier; wherein the input of the switch logic is further configured to receive T input bits of the input code, the T input bits having higher bit weights than the B input bits in the input code; and wherein the switch logic is further configured to provide control signals to the third plurality of switches and the fourth plurality of switches of each of the slices of the thermometer segment in response to the values represented by the received T input bits of the input code.
[0190] Example 16. A circuit according to one of Examples 10 to 15, further comprising: an R-2R segment corresponding to the number L input bits of the input code, the R-2R segment comprising: a fifth plurality of resistors comprising a first resistor and a second resistor for each of the L input bits, wherein the first resistor for the L input bits is coupled in series between the binary segment and a common potential, and wherein the second resistor for each of the L input bits is coupled on one side to its associated first resistor; and a fifth plurality of switches, each associated with one of the L input bits and coupled on one side to the first resistor associated with its input bit. Two resistors, each of the third plurality of switches is configured to selectively couple its associated resistor to the first output terminal in response to a control signal of the switch; wherein the first output terminal of the R-2R segment is coupled to the input of the output amplifier; wherein the input of the switch logic is further configured to receive L input bits of the input code, the L input bits having lower bit weights than the B input bits in the input code; and wherein the switch logic is further configured to provide at least L control signals to the fourth plurality of switches and the fifth plurality of switches in response to the values represented by the received L input bits of the input code.
[0191] Example 17. A digital-to-analog converter circuit includes: a thermometer segment having a first output terminal and a second output terminal, and further including: a plurality of slices, numbered T, wherein each slice includes a plurality of elements of number M, each element being coupled to a first reference voltage terminal and having substantially equal resistances to each other; an output amplifier having a first input coupled to the first output terminal; and switching logic coupled to the plurality of slices and configured to: receive T input code bits representing a first digital value VT[n]; in response to the first digital value VT[n], provide control signals to the plurality of slices to couple M × VT[n] elements between the first reference voltage terminal and the first output terminal; receive T input code bits representing a second digital value VT[n+1]; and in response to the second digital value VT[n+1], change a selected number C of the control signals to couple M × VT[n+1] elements between the first reference voltage terminal and the first output terminal, wherein the number C is a constant regardless of whether the second digital value VT[n+1] is greater than, less than, or equal to the first digital value VT[n].
[0192] Example 18. The circuit according to Example 17, wherein the thermometer segment has a second output terminal, wherein each of the plurality of elements in each slice is also coupled to a second reference voltage terminal, and wherein the switching logic is further configured to provide a control signal to the plurality of slices to couple each element not coupled between the first reference voltage terminal and the first output terminal to the second reference voltage terminal and the second output terminal.
[0193] Example 19. A circuit according to one of Examples 17 or 18, wherein the switching logic is configured to, in response to the second digital value VT[n+1], modify the C control signals provided to the plurality of slices by: encoding a thermometer code in response to the second digital value VT[n+1], the thermometer code being represented as consecutive "1" bits and consecutive "0" bits; comparing the second digital value VT[n+1] with the first digital value VT[n]; changing a pointer value by an amount determined in response to whether the second digital value VT[n+1] is greater than, less than, or equal to the first digital value VT[n] and in response to a random value; shifting the thermometer code in response to the changed pointer value; and providing control signals to the plurality of slices according to the shifted thermometer code.
[0194] Example 20. A circuit according to one of Examples 17 to 19, further comprising: a binary segment having a first output terminal and a second output terminal coupled to the first output terminal and the second output terminal of the thermometer segment, and comprising a plurality of binary slices, each binary slice being associated with one of B input code bits, the B input code bits having lower bit weights than the T input code bits, wherein each binary slice comprises: a first plurality of resistors, each coupled to the first reference voltage terminal, the first plurality of resistors having substantially equal resistances to each other; a first plurality of switches, each associated with and coupled to a corresponding one of the first plurality of resistors, each of the first plurality of switches being configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a control signal of the switch; a second plurality of resistors, each coupled to the second reference voltage terminal, the second plurality of resistors having substantially equal resistances to each other and substantially equal to the resistances of the first plurality of resistors associated with their bit positions; and a second plurality of switches, each associated with a corresponding one of the second plurality of resistors and coupled on one side to the first... For one of two plurality of resistors, each of the second plurality of switches is configured to, in response to a control signal of the switch, couple its associated resistor to the first output terminal or the second output terminal; wherein the switch logic is further configured to, in response to B input code bits, provide control signals to the first plurality of switches and the second plurality of switches for each binary slice of the binary segment, to couple a single resistor of the first plurality of resistors to the first output terminal and the other resistors of the first plurality of resistors and each of the second plurality of resistors to the second output terminal in response to the input code bit corresponding to the binary slice having a first logic state, and to couple a single resistor of the second plurality of resistors to the first output terminal and the other resistors of the second plurality of resistors and each of the first plurality of resistors to the second output terminal in response to the input code bit corresponding to the binary slice having a second logic state; wherein the resistance of each of the first plurality of resistors and each of the second plurality of resistors in each binary slice is twice the resistance of the resistor of the slice corresponding to the next most significant input code bit.
[0195] Example 21. A digital-to-analog converter system comprising: a digital-to-analog converter (DAC) having a digital input, having an analog output, and including a number of N+E slices arranged in one or more segments; and a signal generator circuit having an output coupled to the digital input of the DAC, the signal generator circuit being configured to generate a digital multitone signal in response to an N-bit first frequency tuning word (FTW) corresponding to a first tone and an N-bit second FTW corresponding to a second tone by: providing a first code value of the multitone signal to the DAC at an output pipeline stage; and simultaneously, performing calculation of a second code value of the multitone signal at a previous pipeline stage.
[0196] Example 22. The system according to Example 21, wherein the first tone is at the fundamental frequency and the second tone is at a harmonic of the fundamental frequency.
[0197] Example 23. A system according to one of Examples 21 or 22, wherein the signal generator circuit is configured to perform the calculation of the second code value by: applying the first FTW and the second FTW to a first phase accumulator and a second phase accumulator, respectively; in a first pipeline stage, sequentially applying the remainders from the first phase accumulator and the second phase accumulator to a lookup table to obtain a first sine value and a second sine value, respectively; and in a second pipeline stage, adding the first sine value and the second sine value.
[0198] Example 24. A system according to one of Examples 21 to 23, wherein the signal generator circuit is configured to add the first sine value and the second sine value at the second pipeline stage to obtain the second code value of the multi-tone signal, while applying one of the first FTW and the second FTW to the lookup table at the first pipeline stage to obtain the third code value of the multi-tone signal.
[0199] Example 25. A system according to one of Examples 21 to 24, wherein the first tone is at the fundamental frequency and the second tone is at a harmonic of the fundamental frequency, the system further comprising a harmonic distortion measurement circuit having an input coupled to the analog output of the DAC, configured to iteratively calculate the second FTW having amplitude and phase responsive to the output analog signal from the DAC.
[0200] Example 26. A system according to one of Examples 21 to 25, wherein the first tone is at the fundamental frequency and the second tone is at a harmonic of the fundamental frequency, and the signal generator circuit is further configured to generate the digital multi-tone signal in response to an N-bit third FTW corresponding to a third tone at a harmonic of the fundamental frequency.
[0201] Example 27. A system according to one of Examples 21 to 26, wherein the DAC comprises: an R-2R segment corresponding to a number L+E of the least effective N+E segments series coupled between a first reference voltage terminal and a common potential, each segment comprising: a first resistor; a second resistor having a resistance twice that of the first resistor of its segment and coupled on one side to the first resistor of its segment; and a switch coupled on one side to the second resistor and configured to selectively couple its second resistor to the first output terminal in response to a switch control signal from the signal generator of the segment; and an output amplifier having an input coupled to the first output terminal; wherein the first resistors of the L+E segments are series coupled between the first reference voltage terminal and the common potential; and wherein the signal generator is configured to output digital samples of the multi-tone signal, each digital sample comprising a switch control signal of each of the L+E segments of the R-2R segment.
[0202] Example 28. A system according to any one of Examples 21 to 27, wherein the DAC further comprises: a binary segment having a first output terminal and a second output terminal, the binary segment comprising a plurality of slices corresponding to a number B slices in the N+E slices, each slice of the binary segment comprising: a first plurality of resistors, each coupled to the first reference voltage terminal, the first plurality of resistors having substantially equal resistance to each other; a first plurality of switches, each associated with and coupled to a corresponding one of the first plurality of resistors, each of the first plurality of switches being configured to select either the first output terminal or the second output terminal in response to a switch control signal. The output terminal is coupled to its associated resistor; a second plurality of resistors, each coupled to a second reference voltage terminal, the second plurality of resistors having resistances substantially equal to each other and substantially equal to those of the first plurality of resistors associated with their positions; and a second plurality of switches, each associated with and coupled on one side to a corresponding one of the second plurality of resistors, each of the second plurality of switches being configured to, in response to a switch control signal, couple its associated resistor to either the first output terminal or the second output terminal; wherein the resistance of each of the first plurality of resistors and each of the second plurality of resistors in each slice is equal to that of the next... The resistance of the resistor corresponding to the highest effective slice is twice that of the slice; wherein the slice of the binary segment corresponds to the input code bit with higher bit weight of the FTW compared to the slice of the R-2R segment; wherein the signal generator is further configured to provide a switch control signal in each digital sample of the multi-tone signal to the first plurality of switches and the second plurality of switches of each slice of the binary segment, in response to the input code bit of the multi-tone signal corresponding to the slice having a first logic state, to couple a single resistor of the first plurality of resistors to the first output terminal and to couple the other resistors of the first plurality of resistors to each of the second plurality of resistors. The signal generator provides a switch control signal to the first plurality of switches and the second plurality of switches of each slice of the binary segment of the second digital sample by changing the number J of the control signal provided from the first digital sample to each of the slices of the binary segment, wherein the number J is a constant for the plurality of slices.
[0203] Example 29. A system according to one of Examples 21 to 28, wherein the DAC further comprises: a thermometer segment comprising T slices corresponding to a number of T input code bits, and having a first output terminal and a second output terminal, each slice of the thermometer segment comprising: a third plurality of resistors, the number of which is M, where M is at least 2T, each of the third plurality of resistors being coupled to a first reference voltage terminal, the third plurality of resistors having substantially equal resistance to each other; and a third plurality of switches, the number of which is at least two, each of the third plurality of switches being associated with and coupled on one side to a corresponding one of the third plurality of resistors, each of the third plurality of switches being configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a switch control signal; wherein the first output terminal of the thermometer segment is coupled to the input of the output amplifier; wherein, compared to the slice of the binary segment, the thermometer segment's The slice corresponds to an input code bit with higher bit weight; wherein the signal generator is further configured to provide switch control signals in each digital sample of the multi-tone signal to the third plurality of switches and the fourth plurality of switches of each slice of the thermometer segment by: receiving a value V[n] represented by T bits of the first input code value of the multi-tone signal; in response to the value V[n], providing switch control signals to the first plurality of switches such that M×V[n] switches select the first output terminal and the remaining switches select the second output terminal; receiving a value V[n+1] represented by T bits of the second input code value; and in response to the value V[n+1], changing a selected number C of the switch control signals provided to the first plurality of switches such that M×V[n+1] switches select the first output terminal and the remaining switches select the second output terminal, the number C being a constant regardless of whether the value V[n+1] is greater than, less than or equal to the value V[n].
[0204] Example 30. A digital-to-analog converter circuit comprising: a signal generator circuit including: a plurality of registers, each for storing an N-bit frequency tuning word (FTW) associated with a tone; a plurality of phase accumulators, each associated with one of the plurality of registers; a multiplexer having inputs coupled to the outputs of the plurality of phase accumulators and having a selection input; a first mapping circuit having inputs coupled to the outputs of the multiplexer and configured to output a sine value; a summing circuit having inputs coupled to the outputs of the first mapping circuit; a buffer having inputs coupled to the outputs of the summing circuit; pipelined control logic configured to pipeline the multiplexer, the first mapping circuit, the summing circuit, and the buffer; and a DAC array having inputs coupled to the outputs of the buffers and configured to output an analog signal in response to an input bitstream received at its input.
[0205] Example 31. The circuit according to Example 30, wherein the pipeline control unit is configured to synchronously control the multiplexer, the first mapping circuit, the summing circuit, and the buffer in response to a clock signal by: in a first clock cycle, controlling the multiplexer to apply the output of a first phase accumulator associated with a first tone to the first mapping circuit; in a second clock cycle: controlling the multiplexer to apply the output of a second phase accumulator associated with a second tone to the first mapping circuit; and applying a mapping value corresponding to the first tone to the summing circuit; in a third clock cycle: controlling the multiplexer to apply the output of a third phase accumulator associated with a third tone to the first mapping circuit; and applying a mapping value corresponding to the second tone to the summing circuit to add to the mapping value corresponding to the first tone; and in a fourth clock cycle, storing a first input code value corresponding to the sum of the mapping values of the first tone, the second tone, and the third tone in the buffer.
[0206] Example 32. A circuit according to one of Examples 30 or 31, wherein the pipeline control unit is configured to control the multiplexer, the first mapping circuit, the summing circuit, and the buffer by: in the fourth clock cycle, controlling the multiplexer to apply the output of one of the phase accumulators to the first mapping circuit to obtain a mapped value of the tone of the second input code.
[0207] Example 33. A circuit according to one of Examples 30 to 32, wherein the signal generator circuit further includes a second mapping circuit having an input coupled to the output of the first mapping circuit and an output coupled to the input of the summing circuit, wherein the first mapping circuit maps the value at its input according to a triangular waveform, and the second mapping circuit maps the value at its input to an N+E bit sine value.
[0208] Example 34. A circuit according to one of Examples 30 to 33, wherein the signal generator circuit further includes a fine-tuning circuit having an input coupled to the output of the summing circuit and an output coupled to the input of the buffer, the fine-tuning circuit being configured to apply static correction.
[0209] Example 35. A circuit according to one of Examples 30 to 34, wherein the DAC comprises N+E slices arranged in one or more segments: R-2R segments corresponding to L+E slices in the least effective N+E slices series coupled between a first reference voltage terminal and a common potential, each slice comprising: a first resistor; a second resistor having a resistance twice that of the first resistor of its slice and coupled to the first resistor of its slice on one side; and a switch coupled to the second resistor on one side and configured to selectively couple its second resistor to the first output terminal in response to a switch control signal from the signal generator of the slice; and an output amplifier having an input coupled to the first output terminal; wherein the first resistors of the L+E slices are series coupled between the first reference voltage terminal and the common potential; and wherein the signal generator circuit outputs an input code value, the input code value comprising a switch control signal of each of the L+E slices of the R-2R segments.
[0210] Example 36. A digital-to-analog converter system comprising: a digital-to-analog converter (DAC) having a digital input, having an analog output, and including a number of N+E slices arranged in one or more segments; a signal generator circuit having an output coupled to the digital input of the DAC, the signal generator circuit being configured to generate a digital multitone signal in response to an N-bit first frequency tuning word (FTW) corresponding to a fundamental frequency and an N-bit second FTW corresponding to a harmonic frequency of the fundamental frequency by: providing a first code value of the multitone signal to the DAC at an output pipeline stage; and simultaneously, at a previous pipeline stage, performing calculation of a second code value of the multitone signal; and a harmonic distortion measurement circuit having an input coupled to the analog output of the DAC, configured to iteratively calculate the second FTW, the second FTW having an amplitude and phase responsive to the output analog signal from the DAC.
[0211] Example 37. According to the system of Example 36, wherein the harmonic distortion measurement circuit is configured to iteratively calculate the second FTW by: applying a distortion signal at the harmonic frequency and at a first phase and a second phase to the DAC; measuring and comparing the distortion at the analog output of the DAC in response to the distortion signal at the harmonic frequency in each of the first phase and the second phase; applying a distortion signal at the harmonic frequency and at one or more additional phases to the DAC in response to the comparison of the distortion at the first phase and the second phase; measuring the distortion at the harmonic frequency in the one or more additional phases; determining whether a convergence criterion is met in response to the measured distortion at the harmonic frequency in the one or more additional phases; repeatedly applying the distortion signal at the harmonic frequency and at one or more phases to the DAC, measuring the distortion, and determining whether the convergence criterion is met in response to not meeting the convergence criterion; and storing the second FTW at the harmonic frequency in a register in response to meeting the convergence criterion.
[0212] Example 38. A system according to one of Examples 36 or 37, wherein the signal generator circuit is configured to perform the calculation of the second code value by: applying the first FTW and the second FTW to a first phase accumulator and a second phase accumulator, respectively; in a first pipeline stage, sequentially applying the remainders from the first phase accumulator and the second phase accumulator to a lookup table to obtain a first sine value and a second sine value, respectively; and in a second pipeline stage, adding the first sine value and the second sine value; and wherein the signal generator circuit is configured to add the first sine value and the second sine value in the second pipeline stage to obtain the second code value of the multi-tone signal, while applying one of the first FTW and the second FTW to the lookup table in the first pipeline stage to obtain a third code value of the multi-tone signal.
[0213] Example 39. A system according to one of Examples 36 to 38, wherein the harmonic distortion measurement circuit iteratively calculates the second FTW when manufacturing an integrated circuit including the DAC.
[0214] Example 40. A system according to one of Examples 36 to 39, wherein the DAC comprises a plurality of slices arranged in one or more segments, the one or more segments comprising: an R-2R segment corresponding to a plurality of R-2R slices series coupled between a first reference voltage terminal and a common potential, each R-2R slice comprising: a first resistor; a second resistor having a resistance twice that of the first resistor of its slice and coupled on one side to the first resistor of its R-2R slice; and a switch coupled on one side to the second resistor and configured to selectively couple its second resistor to the first output terminal in response to a switch control signal from the signal generator of the R-2R slice; and an output amplifier having an input coupled to the first output terminal; wherein the first resistor of the R-2R slice is series coupled between the first reference voltage terminal and the common potential; and wherein the signal generator circuit outputs an input code value, the input code value comprising the switch control signal of each of the R-2R slices. The examples described in this specification are implemented in digital-to-analog conversion circuits and systems, as such implementations may be advantageous in this case. However, aspects of these examples can be beneficially applied to alternative applications, such as larger integrated systems that include one or more DAC functions. Therefore, the above description is provided as an example only and is not intended to limit the true scope of the claimed protection.
[0215] Unless otherwise stated, "about," "approximately," or "generally" preceding a value means + / - 10% of the stated value. Modifications to the described examples are possible within the scope of the claims, and other examples are also possible.
[0216] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.
[0217] The circuits or devices described herein as containing certain components may alternatively be adapted to be coupled to those components used to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacturing, for example by an end user and / or a third party, to form the described structure. While in some example embodiments, some elements are included in the integrated circuit and others are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as outside the integrated circuit may be included in the integrated circuit, and / or some features shown as inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.
[0218] The circuits described herein may be reconfigurable to include replaced components, thereby providing functionality at least partially similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.
[0219] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are possible.
Claims
1. A digital-to-analog converter circuit, comprising: A thermometer segment, corresponding to a quantity of T input bits, and having a first output terminal and a second output terminal, the thermometer segment comprising: A plurality of resistors, M in number, wherein M is at least 2T, are each coupled to a first reference voltage terminal, and the plurality of resistors have substantially equal resistances to each other; and A plurality of switches, numbering at least 2T, each of the plurality of switches being associated with and coupled on one side to a corresponding one of the plurality of resistors, each of the plurality of switches being configured to, in response to a control signal of the switch, couple its associated resistor to either the first output terminal or the second output terminal; and An output amplifier having an input coupled to the first output terminal.
2. The circuit according to claim 1, further comprising: A grounding buffer having an output coupled to the second output terminal.
3. The circuit according to claim 1, further comprising: A switching logic having inputs configured to receive T input bits and outputs coupled to the first plurality of switches, the switching logic being configured to: Receive T input bits representing the first digital value V[n]; In response to the first digital value V[n], a control signal is provided to the first plurality of switches so that M×V[n] switches select the first output terminal and the remaining switches select the second output terminal; Receive T input bits representing the second digital value V[n+1]; and In response to the second digital value V[n+1], a selected number C of the control signals provided to the first plurality of switches are changed so that M×V[n+1] switches select the first output terminal and the remaining switches select the second output terminal, wherein the number C is a constant regardless of whether the second digital value V[n+1] is greater than, less than or equal to the first digital value V[n].
4. The circuit of claim 3, wherein the switching logic is configured to, in response to the second digital value V[n+1], change the C control signals provided to the first plurality of switches by: In response to the second digital value V[n+1], the thermometer code is encoded, the thermometer code being represented as consecutive "1" bits and consecutive "0" bits; Compare the second digital value V[n+1] with the first digital value V[n]; The pointer value is changed by a certain amount, which is determined in response to whether the second digital value V[n+1] is greater than, less than or equal to the first digital value V[n] and in response to a random value; In response to the changed pointer value, the thermometer code is shifted; as well as The control signal is provided to the first plurality of switches according to the shifted thermometer code.
5. The circuit of claim 4, wherein the switching logic includes a cyclic shifter: The switching logic is further configured as follows: The thermometer code is stored in the cyclic shifter; and The stored thermometer code is shifted by applying a shift value corresponding to the pointer value to the shifter, and each of the first plurality of switches is associated with a bit position of the cyclic shifter.
6. The circuit of claim 4, wherein the quantity C is 2, wherein the switching logic is further configured to randomly select the random value as either a positive or a negative value, and wherein the switching logic is further configured to change the pointer value by: In response to the second digital value V[n+1] being equal to the first digital value V[n], the pointer value is changed by the amount of the change to the random value; In response to the second digital value V[n+1] being greater than the first digital value V[n], the pointer value is changed by the amount of the change being the difference between the first digital value and the second digital value minus the random value; and In response to the second digital value V[n+1] being less than the first digital value V[n], the pointer value is changed by the amount of the difference between the first digital value and the second digital value plus the random value.
7. The circuit according to claim 1, further comprising: A binary segment, corresponding to a quantity of B input bits, and having an output terminal coupled to the first input of the output amplifier, the binary segment comprising: A second plurality of resistors, each associated with one of the B input bits, and having a resistance twice that of the resistor associated with the next most significant bit of the B input bits; and A second plurality of switches, each associated with and coupled on one side to a corresponding one of the second plurality of resistors, wherein each of the second plurality of switches is configured to selectively couple its associated resistor to the first output terminal in response to a control signal of the switch; and A switching logic having an input configured to receive a digital value comprising T input bits and B input bits, wherein the T input bits have higher bit weights than the B input bits in the digital value, and having an output configured to provide a control signal to a first plurality of switches and a second plurality of switches.
8. The circuit according to claim 7, further comprising: The R-2R segment, corresponding to L input bits and having an output terminal coupled to the input of the output amplifier, includes: A third plurality of resistors comprising a first resistor and a second resistor for each of the L input bits, wherein the first resistor for each of the L input bits is coupled in series between the binary segment and the common potential, and wherein the second resistor for each of the L input bits is coupled on one side to its associated first resistor; and A third plurality of switches, each associated with one of the L input bits and coupled on one side to a second resistor associated with its input bit, each of the third plurality of switches being configured to selectively couple its associated resistor to the first output terminal in response to a control signal of the switch. Furthermore, the input of the switch logic is configured to receive a digital value comprising T input bits, B input bits, and L input bits, wherein the L input bits have a lower bit weight than the B input bits in the digital value, and the switch logic further includes an output configured to provide a control signal to the third plurality of switches.
9. The circuit according to claim 3, wherein the thermometer section further comprises: The second plurality of resistors, having a quantity of at least 2T, are each coupled to a second reference voltage terminal, and the second plurality of resistors have substantially equal resistance to each other. as well as The second plurality of switches, numbering at least 2T, are each associated with and coupled on one side to a corresponding one of the second plurality of resistors. Each of the second plurality of switches is configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a control signal of the switch. Each of the second plurality of switches is configured to operate in a complementary manner relative to the first plurality of switches associated with it. And wherein the second output terminal is coupled to the second input of the output amplifier.
10. A digital-to-analog converter circuit, comprising: A binary segment having a first output terminal and a second output terminal, the binary segment comprising one or more slices, each slice corresponding to one of the number B input bits of the input code, each slice comprising: The first plurality of resistors, each coupled to a first reference voltage terminal, have substantially equal resistances to each other; A plurality of switches, each associated with and coupled to a corresponding one of the plurality of resistors, wherein each of the plurality of switches is configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a control signal of the switch. A second plurality of resistors, each coupled to a second reference voltage terminal, having resistances substantially equal to and substantially equal to those of the first plurality of resistors associated with their respective positions; and The second plurality of switches are each associated with a corresponding one of the second plurality of resistors and coupled on one side to the corresponding one of the second plurality of resistors. Each of the second plurality of switches is configured to, in response to a control signal of the switch, couple its associated resistor to the first output terminal or the second output terminal. An output amplifier having an input coupled to the first output terminal; and A switching logic having inputs configured to receive B input bits of the input code, and configured to provide control signals to a first plurality of switches and a second plurality of switches for each slice of the binary segment, wherein, in response to the input bit corresponding to the slice having a first logic state, a single resistor of the first plurality of resistors is coupled to a first output terminal and the other resistors of the first plurality of resistors and each of the second plurality of resistors are coupled to a second output terminal; and, in response to the input bit corresponding to the slice having a second logic state, a single resistor of the second plurality of resistors is coupled to the first output terminal and the other resistors of the second plurality of resistors and each of the first plurality of resistors are coupled to the second output terminal. Each of the first plurality of resistors and the second plurality of resistors in each slice has a resistance that is twice the resistance of the resistor in the slice corresponding to the next most significant input bit of the input code.
11. The circuit of claim 10, wherein the switching logic is further configured to: It sequentially receives B input bits of multiple input codes; The first plurality of switches and the second plurality of switches that provide control signals to each slice of the binary segment in response to receiving the second input code value include changing the state of a number J of the first plurality of switches and the second plurality of switches in each of the slices of the binary segment, the number J being a constant with respect to the plurality of input codes.
12. The circuit of claim 11, wherein the switching logic is further configured to: For each of the plurality of slices corresponding to an input code bit in the first input code that has the first logic state, a control signal is provided to the plurality of switches to couple another single resistor of the plurality of resistors to the first output terminal in response to the input code bit of the next consecutive input code also having the first logic state; and For each of the plurality of slices corresponding to the input code bit in the first input code that has the second logic state, a control signal is provided to the second plurality of switches to couple another single resistor of the second plurality of resistors to the first output terminal in response to the input code bit of the next consecutive input code also having the second logic state.
13. The circuit of claim 12, wherein the number of resistors in each of the first plurality of resistors and the second plurality of resistors in each of the plurality of slices is greater than two.
14. The circuit of claim 10, wherein the second reference voltage terminal receives a negative voltage having the same magnitude as the voltage received at the first reference voltage terminal.
15. The circuit of claim 10, further comprising: The thermometer segment has a first output terminal and a second output terminal. The binary segment includes multiple slices, each slice corresponding to one of the T input bits of the input code. Each slice includes: A third plurality of resistors, numbered at least two, each coupled to the first reference voltage terminal, the third plurality of resistors having substantially equal resistance to each other; and A third plurality of switches, numbering at least two, each of the third plurality of switches being associated with and coupled on one side to a corresponding one of the third plurality of resistors, each of the third plurality of switches being configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a control signal of the switch. A fourth plurality of resistors, numbered at least two, each coupled to the second reference voltage terminal, the fourth plurality of resistors having substantially equal resistance to each other; and A fourth plurality of switches, the number of which is at least two, each of the fourth plurality of switches being associated with and coupled on one side to a corresponding one of the fourth plurality of resistors, each of the fourth plurality of switches being configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a control signal of the switch. The first output terminal of the thermometer segment is coupled to the input of the output amplifier; The input of the switching logic is further configured to receive T input bits of the input code, wherein the T input bits have higher bit weights than the B input bits in the input code; Furthermore, the switching logic is further configured to provide control signals to the third and fourth plurality of switches of each of the slices of the thermometer segment in response to the values represented by the received T input bits of the input code.
16. The circuit of claim 15, further comprising: The R-2R segment, which corresponds to the number L input bits of the input code, includes: A fifth plurality of resistors comprising a first resistor and a second resistor for each of the L input bits, wherein the first resistor for each of the L input bits is coupled in series between the binary segment and a common potential, and wherein the second resistor for each of the L input bits is coupled on one side to its associated first resistor; and A fifth plurality of switches, each associated with one of the L input bits and coupled on one side to a second resistor associated with its input bit, and each of the third plurality of switches being configured to selectively couple its associated resistor to the first output terminal in response to a control signal of the switch. The first output terminal of the R-2R segment is coupled to the input of the output amplifier; The input of the switching logic is further configured to receive L input bits of the input code, wherein the L input bits have a lower bit weight than the B input bits in the input code; Furthermore, the switching logic is configured to provide at least L control signals to the fourth plurality of switches and the fifth plurality of switches in response to the values represented by the received L input bits of the input code.
17. A digital-to-analog converter circuit, comprising: A thermometer segment having a first output terminal and a second output terminal, and including: Multiple slices, numbered T, wherein each slice comprises multiple elements numbered M, each element being coupled to a first reference voltage terminal and having substantially equal resistance to each other; An output amplifier having a first input coupled to the first output terminal; and Switching logic, coupled to the plurality of slices, is configured to: Received representation of the first digital value V T [n] T input code points; In response to the first digital value V T [n], provides control signals to the plurality of slices to convert M×V T [n] components are coupled between the first reference voltage terminal and the first output terminal; Received representation of the second digital value V T [n+1] T input code points; and In response to the second digital value V T [n+1], change the selected number C of the control signals to M×V T [n+1] components are coupled between the first reference voltage terminal and the first output terminal, the number C being a constant regardless of the second digital value V. T Is [n+1] greater than, less than, or equal to the first numerical value V? T [n].
18. The circuit of claim 17, wherein the thermometer segment has a second output terminal; Each of the plurality of elements in each slice is also coupled to a second reference voltage terminal; Furthermore, the switching logic is configured as follows: Control signals are provided to the plurality of slices to couple each element that is not coupled between the first reference voltage terminal and the first output terminal to the second reference voltage terminal and the second output terminal.
19. The circuit of claim 18, wherein the switching logic is configured to respond to the second digital value V T [n+1], the C control signals provided to the plurality of slices are changed by the following operations: In response to the second digital value V T [n+1], encoding the thermometer code, which is represented by consecutive "1" bits and consecutive "0" bits; The second digital value V T [n+1] and the first numerical value V T [n] is used for comparison; The pointer value is changed by a certain amount, said amount being in response to the second digital value V. T Is [n+1] greater than, less than, or equal to the first numerical value V? T [n] and determined in response to random values; In response to the changed pointer value, the thermometer code is shifted; as well as The control signal is provided to the plurality of slices according to the shifted thermometer code.
20. The circuit of claim 17, further comprising: A binary segment having a first output terminal and a second output terminal coupled to the first output terminal and the second output terminal of the thermometer segment, and comprising a plurality of binary slices, each binary slice being associated with one of B input code bits, the B input code bits having lower bit weights than the T input code bits, wherein each binary slice comprises: The first plurality of resistors, each coupled to the first reference voltage terminal, have substantially equal resistances to each other; A plurality of switches, each associated with and coupled to a corresponding one of the plurality of resistors, wherein each of the plurality of switches is configured to select either the first output terminal or the second output terminal to couple to its associated resistor in response to a control signal of the switch. A second plurality of resistors, each coupled to the second reference voltage terminal, having resistances substantially equal to and substantially equal to those of the first plurality of resistors associated with their respective positions; and The second plurality of switches are each associated with a corresponding one of the second plurality of resistors and coupled on one side to the corresponding one of the second plurality of resistors. Each of the second plurality of switches is configured to, in response to a control signal of the switch, couple its associated resistor to the first output terminal or the second output terminal. Furthermore, the switching logic is further configured to, in response to B input code bits, provide control signals to the first plurality of switches and the second plurality of switches of each binary slice of the binary segment, in response to the input code bit corresponding to the binary slice having a first logic state, couple a single resistor of the first plurality of resistors to the first output terminal and couple the other resistors of the first plurality of resistors and each of the second plurality of resistors to the second output terminal, and in response to the input code bit corresponding to the binary slice having a second logic state, couple a single resistor of the second plurality of resistors to the first output terminal and couple the other resistors of the second plurality of resistors and each of the first plurality of resistors to the second output terminal; Each of the first plurality of resistors and the second plurality of resistors in each binary slice has a resistance that is twice the resistance of the resistor in the slice corresponding to the next most significant input code bit.
Citation Information
Patent Citations
Multiplying Digital-to-Analog Converter
US20260058670A1