A bottom plate sampling SAR ADC based on capacitance mismatch error shaping

Abstract

The application belongs to the technical field of analog integrated circuits and analog-to-digital converters, and particularly relates to a lower plate sampling SAR ADC based on capacitor mismatch error shaping. Compared with a traditional high-precision SAR ADC with lower plate sampling, the application divides CDAC into a high-bit sampling capacitor array and a low-bit error shaping capacitor array, so that the high-bit sampling capacitor array undertakes lower plate sampling of an input signal, and the low-bit error shaping capacitor array retains a low-bit code word state in a sampling phase to realize the combination of lower plate sampling and MES. The application solves the conflict problem of the traditional MES and lower plate sampling, and solves the input signal attenuation problem by combining the split capacitor method, so that the MES technology can be introduced into the high-precision SAR ADC with lower plate sampling, the harmonics and spurs caused by capacitor mismatch are reduced, and the precision of the SAR ADC is improved.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuits and analog-to-digital converters, and particularly relates to a SAR ADC based on lower plate sampling successive approximation of capacitor mismatch error shaping. Background Technology

[0002] SAR ADCs (Successive Approximation Analog-to-Digital Converters) are widely used in medium-to-high precision sensor readout, low-power data acquisition, and oversampling analog-to-digital conversion scenarios due to their simple structure, low power consumption, and digital friendliness. SAR ADCs typically utilize CDACs (Capacitive Digital-to-Analog Converters) for input sampling and successive approximation conversion. As conversion accuracy increases, capacitor mismatch in the CDAC can cause weights to deviate from ideal values, generating harmonics in the ADC output spectrum and limiting the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR) of the analog-to-digital converter.

[0003] In existing technologies, methods such as Dynamic Element Matching (DEM), Digital Calibration, or Mismatch Error Shaping (MES) can be used to reduce the impact of CDAC mismatch. The basic idea of ​​MES is to remember the deviation in the previous conversion and generate a deviation in the opposite direction in the current conversion; in this way, the errors of two adjacent conversions will be subtracted. After this processing, the error in the low-frequency range will be significantly reduced, thereby improving the conversion accuracy of the ADC.

[0004] Although MES can solve the problem of low-position capacitor array mismatch and make SAR ADC more accurate, currently most MES can only be combined with upper plate sampling.

[0005] In the upper-plate sampling stage, the input signal is directly connected to the upper plate of the capacitor array, i.e., the side closest to the comparator input. After sampling, the upper plate is usually disconnected from the input and connected to the comparator, and then successive approximation conversion is completed through the lower-plate switch array. Since the input directly acts on the comparator input node, it is quite sensitive to the linearity of the sampling switches, their on-resistance, and clock feedthrough.

[0006] Compared to upper-plate sampling, lower-plate sampling connects the input signal to the lower plate of the capacitor array during the sampling phase, while the upper plate remains in a fixed state. After sampling, the lower plate switches from the input voltage to the reference voltage, achieving charge redistribution through bottom-plate voltage switching, and transferring the input signal to the upper plate. Because the comparator input is not directly connected to the input sampling switch, lower-plate sampling reduces the impact of sampling switch injection and clock feedthrough on the comparator input, and is therefore more common in high-precision SAR ADCs.

[0007] However, in bottom-plate sampling SAR ADCs, the bottom plate of the capacitor array typically needs to be connected to the input signal during the sampling phase to complete the sampling of the input signal. Meanwhile, MES (Mean Encoding and Sequence Control) requires the bottom plate of the low-order capacitor array to maintain the state of the previous cycle's low-order codeword during the sampling phase. Therefore, the same low-order capacitor array must both connect to the input signal for sampling and maintain the previous cycle's codeword for MES, creating a conflict in terms of capacitor connection state and timing requirements. Consequently, traditional MES is difficult to directly apply to bottom-plate sampling SAR ADCs, necessitating a new capacitor array partitioning method and sampling conversion timing that retains the advantages of bottom-plate sampling while enabling the low-order capacitor array to perform MES operations, thereby reducing harmonics caused by capacitor mismatch. Summary of the Invention

[0008] To address the aforementioned problems and shortcomings, and to resolve the issue that existing mismatch error shaping techniques are not well-suited for lower-plate sampling SAR ADCs, this invention provides a lower-plate sampling successive approximation analog-to-digital converter (SAR ADC) based on capacitor mismatch error shaping, as shown in the attached figure. Figure 1 As shown.

[0009] A lower plate sampling SAR ADC based on capacitor mismatch error shaping includes four modules: sampling switch S0, CDAC, comparator, and SAR LOGIC.

[0010] The CDAC is divided into two parts: a high-level CDAC and a low-level CDAC. The high-level CDAC consists of a high-level capacitor array CN to CM and corresponding switching switches SN to SM. The low-level CDAC consists of a low-level capacitor array CM-1 to C1 and corresponding switching switches SM-1 to S1.

[0011] The upper plates of the high-order CDAC and low-order CDAC are connected, and the entire upper plate of the CDAC is connected to S0 and the comparator input. The lower plates of the high-order CDAC are connected one-to-one with single-pole four-throw switches SN~SM, receiving control signals from the SAR LOGIC and selecting from Vi, Vcm, Vrefp, and Vrefn. The lower plates of the low-order CDAC are connected one-to-one with single-pole three-throw switches SM~S1, receiving control signals from the SAR LOGIC and selecting from Vcm, Vrefp, and Vrefn. Input signal Vi is connected to the lower plate of the high-order CDAC; Vrefp is the high-level reference voltage; Vrefn is the low-level reference voltage; and Vcm is the common-mode voltage.

[0012] Where the sampling signal Φ S This is the control signal for the sampling switch S0. When it is high, the input signal Vi is sampled. Φ MSBsThis is the control signal for SN to SM, and it serves as the sampling signal for the high-order CDAC. When set high, the high-order CDAC performs sampling. Φ MSBr This is the control signal for SN~SM, and also serves as the reset signal for the high-order CDAC. Setting it high resets the high-order CDAC. Φ LSBr It serves as the control signal for SM-1 to S1, and also as the reset signal for the lower-order CDAC. When set high, it resets the lower-order CDAC.

[0013] Since the higher-order CDACs participate in Vi sampling while the lower-order CDACs do not, Vi will be attenuated to the sum of the higher-order CDAC capacitance values ​​divided by the sum of the entire CDAC capacitance values. To ensure correct quantization later, the weight value of each capacitor in the entire capacitor array should be attenuated by the same coefficient.

[0014] The input of the comparator is connected to the upper plate of the entire CDAC, comparing the voltage of the upper plate, and the comparison result is sent to the SAR LOGIC. CLK This is the control signal for the comparator. When set high, the comparator performs comparisons and enters the quantization stage.

[0015] The SAR LOGIC receives the comparison result output by the comparator and generates codewords based on the comparison result to control the switching of the entire capacitor array CDAC, guiding the selection of the corresponding switches SN~S1 for the high-order CDAC and the low-order CDAC.

[0016] The sampling switch S0 is connected to the upper plate of the entire CDAC. When S0 is closed, the common-mode voltage is transmitted to the upper plate of the entire CDAC to complete the sampling.

[0017] The circuit's timing sequence and circuit states at each stage are shown in the attached figure. Figure 2 and attached Figure 3 As shown in the figure. Here, "0" refers to the common-mode voltage Vcm, "+1" refers to the reference level Vrefp, and "-1" refers to the reference level Vrefn.

[0018] First stage sampling, Φ S and Φ MSBs When set high, the common-mode voltage Vcm is connected to the upper plate of the capacitor array. The lower plate of the high-order capacitor array is connected to Vi for sampling. The lower plate of the low-order capacitor array retains the low-order codeword of the previous cycle.

[0019] Second-stage reset, Φ S Φ MSBr Lower, while Φ MSBr Φ LSBrWhen set high, Vcm is disconnected, the upper plate of the capacitor array floats, and the lower plates of the high-position capacitor array and the low-position capacitor array switch to 0. Since the upper plate of the capacitor array is already floating, this action will inject the mismatch error between the input signal Vi and the low-position capacitor array of the previous cycle into the upper plate of the capacitor array.

[0020] The third stage of quantification, Φ MSBr Lower, Φ LSBr Lower, Φ CLK When the value is set high, the comparator enters the quantization process, generating the current cycle's capacitor array code value and simultaneously generating the current cycle's low-order capacitor array mismatch error. In this way, the low-order mismatch error in the current cycle's output is the difference between the current error and the error of the previous cycle.

[0021] Furthermore, the specific method for capacitor attenuation is as follows: each capacitor is split into two groups. The sum of the capacitance values ​​in the first group is the attenuation coefficient multiplied by the capacitance value, and the sum of the capacitance values ​​in the second group is the remaining capacitance value of the capacitor. The lower plate of the first group of capacitors maintains the codeword from the previous cycle during sampling; it is connected to Vcm during reset; and it receives the SAR LOGIC control codeword during the quantization phase and is connected to Vrefn or Vrefp. The second group of small capacitors is divided into two equal parts, named Little1 and Little2. They are not controlled by the SAR LOGIC codeword but undergo a fixed level switch in each working cycle, thereby shaping the mismatch error between Little1 and Little2. During sampling, the lower plate of Little1 is connected to Vrefn, and the lower plate of Little2 is connected to Vrefp; during reset, the lower plates of Little1 and Little2 are connected to Vcm; during quantization, the lower plate of Little1 is connected to Vrefn, and the lower plate of Little2 is connected to Vrefp, the same as during sampling.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] Compared to traditional high-precision SAR ADCs using lower-plate sampling, this invention divides the CDAC (capacitor array) into a high-bit sampling capacitor array and a low-bit error shaping capacitor array. The high-bit sampling capacitor array handles the lower-plate sampling of the input signal, while the low-bit error shaping capacitor array retains the low-bit codeword state of the previous cycle during sampling. This achieves a combination of lower-plate sampling and MES (Mechanical Estimate). This invention resolves the conflict between traditional MES and lower-plate sampling; and by combining the capacitor splitting method, it addresses the input signal attenuation problem. This allows the introduction of MES technology into a high-precision SAR ADC using lower-plate sampling, reducing harmonics and spurious emissions caused by capacitor mismatch and improving the accuracy of the SAR ADC. Attached Figure Description

[0024] Figure 1This is a schematic diagram of the structure of the present invention;

[0025] Figure 2 This is a timing diagram of the MES of the present invention;

[0026] Figure 3 This is a flowchart of the MES workflow of the present invention;

[0027] Figure 4 This is a schematic diagram illustrating the MES implementation method of the embodiment;

[0028] Figure 5 This is a flowchart of the MES workflow for an example.

[0029] Figure 6 This is a flowchart illustrating the process of splitting the capacitor in the embodiment. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0031] The architecture used in this embodiment is shown in the attached figure. Figure 4 As shown, this circuit is a 12-bit SAR ADC, consisting of four modules. Module 401 is a sampling switch; module 402 is a high-order CDAC (the first two bits are selected as the high-order bits in this embodiment); module 403 is a low-order CDAC (the last 10 bits are selected as the low-order bits in this embodiment); module 404 is a comparator, its input port connected to the upper plate of the capacitor array to compare the voltage of the upper plate; module 405 is a SAR logic, which receives the comparison result from the comparator and generates the output codeword B<12:1> to control the switching of the capacitor array; module 406 is the highest-order capacitor at the P-terminal, its splitting method and operation are shown in the appendix. Figure 6 The splitting method and working process of the remaining capacitors are similar.

[0032] Vrefp is the high-level reference voltage, which is equal to the power supply voltage in this embodiment; Vrefn is the low-level reference voltage, which is ground in this embodiment; Vip and Vin are differential input signals, which are connected to the lower plate of the capacitor array, respectively, for the P and N terminals; Vcm is the common-mode level, which can be expressed as:

[0033]

[0034] In the appendix Figure 6 In this context, "0" refers to the common-mode voltage Vcm, "+1" refers to the reference level Vrefp, and "-1" refers to the reference level Vrefn.

[0035] Divide C12,p into 8 equal parts, named C1 to C8 respectively. Assume that:

[0036]

[0037] In the first step, the upper plate of the eight split capacitors is connected to a common-mode voltage Vcm, and the lower plate is connected to the input signal Vip. At this point, the total charge stored in all the split capacitors can be expressed as:

[0038]

[0039] In the second step, the upper plates of the eight split capacitors are disconnected from Vcm, and the upper plates float. The lower plates of the four split capacitors on the left are connected to -1, and the lower plates of the four split capacitors on the right are connected to 1. Assuming the voltage of the upper plates is V1, the total charge stored in all the split capacitors at this time can be expressed as:

[0040]

[0041] Since the upper plate is floating, the total charge remains unchanged, therefore:

[0042]

[0043] Solving for:

[0044]

[0045] Therefore, the input signal Vip is transmitted to the upper plate, and the lower plate is reset.

[0046] Third step, keep the upper plate floating, B <12> Control S12,p to switch, if B <12> If the voltage is 1, then the lower plate of C12,p switches to "+1". Assuming the voltage of the upper plate is V1' at this time, the total charge stored in all the split capacitors can be expressed as:

[0047]

[0048] Since the upper plate is floating, the total charge remains unchanged, therefore:

[0049]

[0050] Solving for:

[0051]

[0052]

[0053] If B <12> If the value is 0, then the lower plates of C5 to C7 switch to "-1". Similarly, the following can be calculated:

[0054]

[0055]

[0056] In the appendix Figure 5 In the text, "0" refers to the common-mode voltage Vcm connected to the lower plate of the capacitor, and "+1" refers to the voltage connected to the lower plate of the capacitor. "-1" indicates the lower plate of the capacitor is connected. .

[0057] In the first stage of sampling, the high 2 bits are sampled, so the sampled voltage of the high-order capacitor can be expressed as:

[0058]

[0059]

[0060]

[0061] The lower 10 bits retain the codeword from the previous cycle, so the sampling voltage of the lower-order capacitor can be expressed as:

[0062] The total sampled voltage can be expressed as the following equation:

[0063]

[0064] Because the input signal Vi is scaled back to its original value. The corresponding reference voltage range is also scaled by the same coefficient to ensure proper quantization later.

[0065] The new reference voltage is expressed as:

[0066]

[0067]

[0068]

[0069] In the second stage of reset, the lower plate is connected to 0, and Vsample is placed on the upper plate. At this time, the voltage at the comparator input can be expressed as follows:

[0070]

[0071] In the third stage of quantization, the CDAC completes the successive approximation conversion of the current cycle according to the SAR control logic. Let the low-order capacitor mismatch error of the current cycle be E(n). When the last bit is quantized, the voltage at the comparator input can be expressed as:

[0072]

[0073]

[0074] Assuming the comparator input voltage is 0 after the last bit is quantized, the final quantization result can be expressed as follows:

[0075]

[0076]

[0077] Finally, the transfer function of the low-side capacitor mismatch error can be obtained as follows: .

[0078] As can be seen from the above embodiments, this invention resolves the state conflict between traditional MES and lower plate sampling by separating the input sampling function and the MES function within the capacitor array. This allows the high-order capacitor array to complete the lower plate sampling, while the low-order capacitor array retains the low-order codeword from the previous cycle and performs error shaping. This solution can reduce low-frequency nonlinear errors caused by capacitor mismatch and improve the linearity and spectral performance of the SAR ADC without relying on complex capacitor calibration.

Claims

1. A lower-plate sampling SAR ADC based on capacitor mismatch error shaping, characterized in that: It includes four modules: sampling switch S0, CDAC, comparator, and SAR LOGIC. The CDAC is divided into two parts: a high-level CDAC and a low-level CDAC. The high-level CDAC consists of a high-level capacitor array CN to CM and corresponding switching switches SN to SM. The low-level CDAC consists of a low-level capacitor array CM-1 to C1 and corresponding switching switches SM-1 to S1. The upper plates of the high-order CDAC and the low-order CDAC are connected, and the entire upper plate of the CDAC is connected to S0 and the comparator input. The lower plate of the high-position CDAC is connected to the single-pole four-throw switch SN~SM one by one, which receives the control signal from SAR LOGIC and selects from Vi, Vcm, Vrefp and Vrefn; The lower plate of the low-level CDAC is connected one-to-one with the single-pole three-throw switches SM-1 to S1, receiving control signals from the SAR LOGIC and selecting from Vcm, Vrefp, and Vrefn; the input signal Vi is connected to the lower plate of the high-level CDAC; Vrefp is the high-level reference voltage; Vrefn is the low-level reference voltage; and Vcm is the common-mode voltage. Where the sampling signal Φ S The control signal for the sampling switch S0 is high; when it is high, the input signal Vi is sampled. Φ MSBs SN to SM are control signals, and are also used as sampling signals for the high-order CDAC. When set high, the high-order CDAC performs sampling; Φ MSBr SN to SM are control signals, and also serve as the reset signal for the high-order CDAC; setting them high resets the high-order CDAC. Φ LSBr It serves as the control signal for SM-1 to S1, and also as the reset signal for the lower-order CDAC. When set high, it resets the lower-order CDAC. The weight value of each capacitor in the entire CDAC is attenuated by the same coefficient; The input terminal of the comparator is connected to the upper plate of the entire CDAC, compares the voltage of the upper plate, and sends the comparison result to SAR LOGIC. Φ CLK This is the control signal for the comparator. When set high, the comparator performs comparisons and enters the quantization stage. The SAR LOGIC receives the comparison result output by the comparator and generates codewords based on the comparison result to control the switching of the entire capacitor array CDAC, guiding the selection of the corresponding switches SN~S1 of the high-order CDAC and the low-order CDAC. The sampling switch S0 is connected to the upper plate of the entire CDAC. When S0 is closed, the common-mode voltage is transmitted to the upper plate of the entire CDAC to complete the sampling.

2. The lower plate sampling SAR ADC based on capacitor mismatch error shaping as described in claim 1, characterized in that, The specific timing sequence and circuit states at each stage are as follows: First stage sampling, Φ S and Φ MSBs When set high, the common-mode voltage Vcm is connected to the upper plate of the CDAC. The lower plate of the high-bit CDAC is connected to Vi for sampling. The lower plate of the low-bit CDAC retains the low-bit codeword of the previous cycle. Second-stage reset, Φ S Φ MSBr Lower, while Φ MSBr Φ LSBr When set high, Vcm is disconnected, the upper plate of CDAC floats, and the lower plates of high-position CDAC and low-position CDAC switch to Vcm. Since the upper plate of CDAC is already floating, this action will inject the mismatch error between the input signal Vi and the low-position CDAC of the previous cycle into the upper plate of CDAC. The third stage of quantification, Φ MSBr Lower, Φ LSBr Lower, Φ CLK When set high, the comparator enters the quantization process, generating the current period's capacitor array code value, and simultaneously generating the current period's low-order CDAC mismatch error; The low-order CDAC mismatch error in the current cycle output is the difference between the current error and the error of the previous cycle.

3. The lower plate sampling SAR ADC based on capacitor mismatch error shaping as described in claim 1, characterized in that, The specific method for capacitor attenuation is as follows: Each capacitor is split into two groups. The sum of the capacitance values ​​in the first group is the attenuation coefficient multiplied by the capacitance value. The sum of the capacitance values ​​in the second group is the remaining capacitance value of the capacitor. The lower plate of the first group of capacitors retains the codeword from the previous cycle during sampling; it is connected to Vcm during reset; and it receives the SAR LOGIC control codeword during quantization and is connected to Vrefn or Vrefp. The second group of small capacitors is divided into two equal parts, named Clittle1 and Clittle2. They are not controlled by the SAR LOGIC codeword, but instead undergo a fixed level switch in each working cycle, thereby shaping the mismatch error between Clittle1 and Clittle2. During sampling, the lower plate of Clittle1 is connected to Vrefn, and the lower plate of Clittle2 is connected to Vrefp. During reset, the lower plates of Clittle1 and Clittle2 are connected to Vcm. During quantization, the lower plate of Clittle1 is connected to Vrefn, and the lower plate of Clittle2 is connected to Vrefp, the same as during sampling.

4. The lower plate sampling SAR ADC based on capacitor mismatch error shaping as described in claim 1, characterized in that: For a 12-bit SAR ADC, the first two bits of its CDAC are used as the high-order bits, and the last 10 bits are used as the low-order bits. The transfer function of the low-order capacitor mismatch error is: .

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