Calibration excitation data generation method, apparatus, and timing calibration apparatus
Patent Information
- Application Number
- CN202610904043.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-22
- Publication Date
- 2026-10-27
Smart Images
Figure CN122993709A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing technology, and in particular to a calibration excitation data generation method, apparatus, and timing calibration apparatus. Background Technology
[0002] In the field of semiconductor testing, high-speed DACs (digital-to-analog converters) are frequently used. However, the data input of high-speed DACs is usually from an FPGA, which typically only has a data interface and no accompanying clock interface. In this case, due to different hardware PCB traces, the data received by the DAC from the FPGA input may be metastable, potentially leading to abnormal acquisition and abnormal output waveforms, thus affecting semiconductor test performance. Therefore, timing calibration of the digital-to-analog converter is necessary before testing.
[0003] Traditional timing calibration methods use a sine wave or an increasing waveform as calibration excitation data, which is then delayed before being sent to a DAC for digital-to-analog conversion. The sine wave or increasing waveform contains a large amount of consecutive identical data, resulting in a low flip rate and consequently low timing calibration accuracy. Summary of the Invention
[0004] Therefore, it is necessary to provide a calibration excitation data generation method, apparatus, and timing calibration device that can improve the accuracy of timing calibration, in order to address the above problems.
[0005] The first aspect of this application provides a method for generating calibration excitation data, comprising:
[0006] The pseudo-random sequence is obtained and truncated to obtain multiple segmented periodic data;
[0007] The segmented periodic data is shuffled in bit order to generate shuffled periodic data.
[0008] Invert the data of the target bit of the scrambled periodic data to generate inverted periodic data;
[0009] The segmented periodic data, the scrambled periodic data, and the inverted periodic data are combined to obtain calibration excitation data.
[0010] The aforementioned calibration stimulus data generation method extracts multiple segmented periodic data from a pseudo-random sequence, scrambles the bit order of these segmented periodic data to generate scrambled periodic data, inverts the target bit of the scrambled periodic data to generate inverted periodic data, and finally combines the segmented periodic data, scrambled periodic data, and inverted periodic data to obtain the calibration stimulus data. This achieves a higher flip rate, making timing tests more accurate and improving timing calibration precision.
[0011] In one embodiment, the segmented periodic data includes a first segmented periodic data obtained by truncating the low bits of the pseudo-random sequence and a second segmented periodic data obtained by truncating the high bits of the pseudo-random sequence. This is used to combine segmented periodic data of different bits for subsequent processing, thereby increasing the diversity of data combinations.
[0012] In one embodiment, the segmented periodic data is shuffled in bit order to generate shuffled periodic data. This includes: sequentially selecting bits from the first and second segmented periodic data and rearranging them in an odd-even alternation pattern to generate shuffled periodic data. By shuffling the bit order, the correlation between adjacent bits can be broken, and each bit becomes independent.
[0013] In one embodiment, the target bit of the scrambled periodic data is inverted to generate inverted periodic data. This includes keeping the even bits unchanged and inverting the odd bits, or keeping the odd bits unchanged and inverting the even bits, to generate inverted periodic data, which can improve the diversity of data combinations.
[0014] In one embodiment, the segmented periodic data, the scrambled periodic data, and the inverted periodic data are combined to obtain calibration excitation data, including:
[0015] The segmented periodic data, the shuffled periodic data, and the inverted periodic data are inverted respectively to obtain inverted segmented periodic data, inverted shuffled periodic data, and inverted inverted periodic data. These three data sets are then combined to obtain the calibration excitation data for the complete cycle required for one calibration excitation. Inverting and combining different data sets to generate calibration excitation data further improves the diversity of data combinations.
[0016] A second aspect of this application provides a calibration excitation data generation apparatus, comprising:
[0017] The pseudo-random sequence truncation module is used to acquire pseudo-random sequences and truncate them to obtain multiple segmented periodic data.
[0018] The shuffling module is used to shuffle the bit order of the segmented periodic data to generate shuffled periodic data.
[0019] The inverting and combining module is used to invert the target bit of the scrambled periodic data to generate inverted periodic data; and to combine the segmented periodic data, the scrambled periodic data and the inverted periodic data to obtain calibration excitation data.
[0020] The aforementioned calibration excitation data generation device comprises a pseudo-random sequence extraction module that extracts multiple segmented periodic data from a pseudo-random sequence, scrambles the bit order of these segmented periodic data to generate scrambled periodic data, a scrambling module that inverts the target bit of the scrambled periodic data to generate inverted periodic data, and an inverted combination module that inverts the target bit of the scrambled periodic data to generate inverted periodic data. Combining the segmented periodic data, scrambled periodic data, and inverted periodic data yields the calibration excitation data, achieving a higher flip rate, resulting in more accurate timing tests and improved timing calibration precision.
[0021] A third aspect of this application provides a timing calibration apparatus, comprising:
[0022] The data output module is connected to the delay module and outputs calibration excitation data to the delay module according to the above method;
[0023] The delay module is connected to the delay control module and the digital-to-analog converter. Based on the delay values sent by the delay control module, the calibration excitation data is delayed and then sent to the digital-to-analog converter.
[0024] The aforementioned timing calibration device combines segmented periodic data, shuffled periodic data, and inverted periodic data to obtain calibration excitation data. Delaying the transmission of this calibration excitation data to the analog-to-digital converter allows for more accurate timing testing and improves timing calibration precision.
[0025] In one embodiment, the device further includes a readback data recording module; the delay control module is also connected to the readback data recording module, and synchronously sends gradually changing delay values to the delay module and the readback data recording module in sequence.
[0026] The readback data recording module is connected to the digital-to-analog converter. After the delay module sends the calibration excitation data to the digital-to-analog converter according to different delay values, it obtains the status register result inside the digital-to-analog converter. It then performs calibration by combining the status register results corresponding to different delay values to obtain the calibration success / failure result. The status register result indicates whether the timing in the digital-to-analog converter is normal under the current delay value.
[0027] In this embodiment, the readback data recording module is used to obtain the status register result that characterizes whether the timing of the digital-to-analog converter is normal under the current delay value. The status register result corresponding to different delay values is combined to perform calibration and obtain the calibration success / failure result, thereby achieving accurate calibration of the digital-to-analog converter.
[0028] In one embodiment, the data output module includes a calibration data generation module, an arbitrary waveform data transmission module, and a data selection module. The data selection module is connected to the calibration data generation module, the arbitrary waveform data transmission module, the delay module, and the delay control module. The calibration data generation module is connected to the delay control module and the readback data recording module.
[0029] The delay control module outputs a switching signal to the data selection module, controlling the data selection module to send the calibration excitation data output by the calibration data generation module to the delay module, or controlling the data selection module to send the arbitrary waveform data output by the arbitrary waveform data sending module to the delay module, and sending the calibration result as a delay value to the delay module;
[0030] After receiving the start signal sent by the delay control module, the calibration data generation module outputs calibration excitation data and stops outputting after sending the calibration excitation data corresponding to the current delay value. The data transmission end signal is sent to the readback data recording module.
[0031] After receiving the data transmission end signal, the readback data recording module reads the status register result corresponding to the current delay value from the digital-to-analog converter, and returns the status read end signal to the delay control module after the reading is completed.
[0032] After receiving the status reading end signal, the delay control module sends a start signal to the data output module again and sends the next delay value to the delay module until the number of times the delay value is sent reaches the preset delay number threshold.
[0033] In this embodiment, the data output module, the readback data recording module, and the delay control module interact with each other to accurately execute different delays on the calibration excitation data and read the corresponding status register results, thereby ensuring the accuracy of timing calibration.
[0034] In one embodiment, the calibration success / failure result includes a calibration success / failure flag and a corresponding calibration result; the readback data recording module uses the delay value as an address and the status register result as the result data for corresponding binding and storage, gradually traversing the result data corresponding to different addresses, obtaining the longest length of consecutive 1s in the result data, determining the cache length and the corresponding start address and end address; the readback data recording module compares the cache length with a preset length threshold to obtain the calibration success / failure flag, and combines it with the start address and the end address to determine the calibration result, and sends the calibration success / failure result to the delay control module.
[0035] In this embodiment, the longest length of consecutive 1s in the result data analysis is determined by combining the delay value and the corresponding result data, thereby determining the cache length and the corresponding start address and end address, and then accurately analyzing and obtaining the calibration success / failure result. Attached Figure Description
[0036] Figure 1 This is a flowchart of a calibration excitation data generation method in one embodiment;
[0037] Figure 2 This is a structural block diagram of a calibration excitation data generation device in one embodiment;
[0038] Figure 3 This is a structural block diagram of a timing calibration device in one embodiment;
[0039] Figure 4 This is a schematic diagram of the timing calibration device in one embodiment;
[0040] Figure 5 This is a schematic diagram of the calibration process of a timing calibration device in one embodiment. Detailed Implementation
[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. It is understood that the term "connection" in the following embodiments, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, should be understood as "electrical connection," "communication connection," etc.
[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0044] High-speed DACs typically receive data input from an FPGA, which only has a data interface and no accompanying clock interface. In this case, different hardware PCB traces can cause metastability in the data received by the DAC from the FPGA input. A sampling clock (sample_clk) generated by a clock chip is input to the DAC chip. This DAC chip has a double interpolation function. The data clock (data_clk) generated by the DAC chip is obtained by dividing the sampling clock (sample_clk). The DAC chip sends the data clock (data_clk) to the FPGA, which then sends multiple bits of parallel data to the DAC chip based on the data clock (data_clk). The data clock (data_clk) first needs to pass through the PCB traces to enter the FPGA (creating a delay t1). Inside the FPGA, it passes through a clock buffer and outputs parallel data. The parallel data travels from the FPGA's internal logic to the pin location, creating a delay t2. The parallel data travels through the PCB traces to the DAC chip, creating a delay t3. Therefore, the interval between the data and clock signals at the DAC chip is t1 + t2 + t3. Due to differences in hardware and components across different test boards, t1, t2, and t3 are not consistent. Therefore, timing calibration is required to ensure that the data acquired by the DAC meets the requirements.
[0045] The DAC chip has the function of automatically detecting whether there are timing abnormalities in the input data. In addition to the normal sampling data, it will collect two extra sets of test data. One set of sampled data is latched before the actual data sampling point, and the other set is latched after the actual data sampling point. If the two sets of extra sampled data are consistent with the actual data, the sampling is considered normal. If the two sets of extra sampled data are inconsistent with the actual sampled data, the sampling is considered abnormal and the timing margin is insufficient, which will raise the error flag. The status register result, which represents whether the timing of the digital-to-analog converter is normal at the current delay value, can be obtained by reading the relevant registers.
[0046] Traditional timing calibration methods use sine waves or incremental waveforms as calibration stimulus data, resulting in insufficient bit-to-bit flip rate and low timing accuracy. To improve accuracy, longer testing times are required. Therefore, this application provides a calibration stimulus data generation method that extracts multiple segmented periodic data from a pseudo-random sequence. The bit order of these segmented periodic data is then shuffled to generate shuffled periodic data. The target bit of the shuffled periodic data is inverted to generate inverted periodic data. Finally, the segmented periodic data, shuffled periodic data, and inverted periodic data are combined to obtain the calibration stimulus data. By modifying the pseudo-random sequence to generate a higher flip rate, fewer long consecutive code patterns, and more uniform bit transitions, calibration accuracy is improved while maintaining testing efficiency.
[0047] In one embodiment, such as Figure 1 As shown, a method for generating calibration excitation data is provided, including:
[0048] Step S100: Obtain the pseudo-random sequence and truncate it to obtain multiple segmented periodic data.
[0049] This can be achieved by first generating a pseudo-random sequence and then truncating it to obtain multiple segmented periodic data; or by acquiring a pseudo-random sequence generated by an external device and truncating it to obtain multiple segmented periodic data. Specifically, using a pseudo-random sequence based on an LFSR (Linear Feedback Shift Register) can achieve a higher flip rate. In the generation of common bit error rate test data such as prbs31 and prbs15, the flip rate of prbs15 is approximately 46%. By using prbs31 to truncate 16 bits, the flip rate is approximately 49.2%, achieving a higher flip rate. In this embodiment, a 32-bit pseudo-random sequence is generated using the prbs31 polynomial. The initial random seed is 0xBE29CB73, and the polynomial is x^32+x^22+X^2+X^1+X^0. The pseudo-random sequence Y is: Y[31:0]={Y[30:0],Y
[31] ^Y
[21] ^Y[1]^Y[0]^1}, which means shifting bits 0 to 30 to the left by 1 bit, and simultaneously XORing bits 31 with bits 21, 1, 0, and the number 1, placing the result at bit 0. The sequence Y is: 0x8E29CB73, 0x1C5396E7...
[0050] There is no single way to obtain segmented periodic data from a pseudo-random sequence. The number of segmented periodic data can be two, three, or more, depending on the actual needs. In this embodiment, the segmented periodic data includes a first segmented periodic data obtained by truncating the low bits of the pseudo-random sequence, and a second segmented periodic data obtained by truncating the high bits of the pseudo-random sequence. These are used to combine segmented periodic data of different bit positions for subsequent processing, increasing the diversity of data combinations.
[0051] Taking a 32-bit pseudo-random sequence as an example, the lower 16 bits of the 32-bit pseudo-random sequence are truncated to output the first segment periodic data: Y1[15:0] = Y[15:0], indicating that the lower 16 bits of the 32-bit pseudo-random sequence are truncated as the first segment periodic data Y1. The sequence of Y1 is: 0xCB73, 0x96E7... The higher 16 bits of the 32-bit pseudo-random sequence are truncated to output the second segment periodic data: Y2[15:0] = Y[31:16], indicating that the higher 16 bits of the generated 32-bit random data are truncated as the second segment periodic data Y2. The sequence of Y2 is: 0x8E29, 0x1C53...
[0052] Step S200: Shuffle the bit order of the segmented periodic data to generate shuffled periodic data.
[0053] After obtaining multiple segmented periodic data, a portion of bits are selected from each segmented periodic data and their order is shuffled to obtain shuffled periodic data. It is understood that the bit selection and shuffling methods are not unique and can be set according to actual needs. In one embodiment, step S200 includes: sequentially selecting bits from the first and second segmented periodic data and rearranging them in an odd-even alternation pattern to generate shuffled periodic data. By shuffling the bit order, the correlation between adjacent bits can be broken, and each bit becomes independent.
[0054] Specifically, since the LFSR is output by sequential shifting, bit0->bit1->bit2->... shifting sequentially, each bit is highly correlated. By shuffling the bit order, the correlation of the shifts can be broken, so that the probability of 0 / 1 of each bit in the 16-bit shuffled periodic data Y3 is close to 50%, and each bit is independent of each other. In this embodiment, the shuffled periodic data Y3 is: Y3[15:0]={Y
[23] ,Y[7],Y
[22] ,Y[6],Y
[21] ,Y[5],Y
[20] ,Y[4],Y
[19] ,Y[3],Y
[18] ,Y[2],Y
[17] ,Y[1],Y
[16] ,Y[0],Y[0] to Y[7] represent the lower 8 bits of the first segment periodic data Y1, and Y
[16] to Y
[23] represent the lower 8 bits of the second segment periodic data Y2. By rearranging odd and even numbers, the correlation of pseudo-random sequences can be destroyed, thereby further improving randomness.
[0055] Step S300: Invert the data of the target bit of the scrambled periodic data to generate inverted periodic data.
[0056] The number and specific position of the target bits are not unique. For example, the target bits can be either odd or even bits in the scrambled periodic data Y3. Inverting the target bits of the scrambled periodic data means changing 1 to 0 and 0 to 1. In one embodiment, step S300 includes: keeping the even bits unchanged and inverting the odd bits, or keeping the odd bits unchanged and inverting the even bits, to generate inverted periodic data, which can improve the diversity of data combinations.
[0057] Specifically, the 16-bit scrambled periodic data Y3 can be XORed with 0xAA55 to output the 16-bit inverted periodic data Y4. This results in fewer long consecutive code patterns, making the transitions of each bit more uniform and avoiding prolonged periods of all 0s / all 1s. Here, 0xAA is represented by the binary representation 10101010, equivalent to even bits remaining unchanged and odd bits being inverted; 0x55 is represented by the binary representation 01010101, equivalent to odd bits remaining unchanged and even bits being inverted. In this embodiment, the inverted periodic data Y4 is obtained by XORing the scrambled periodic data Y3 with 0xAA55: Y4[15:0] = Y3[15:0] ^ 0xAA55, indicating that the scrambled periodic data Y3 is XORed with 0xAA55, and the sequence of Y4 is: 0x37D2, 0xDC4A...
[0058] Step S400: Combine the segmented periodic data, the shuffled periodic data, and the inverted periodic data to obtain the calibration excitation data.
[0059] After obtaining the segmented periodic data, scrambled periodic data, and inverted periodic data, these periodic data can be combined directly, or they can be processed first and then combined. In one embodiment, step S400 includes: inverting the segmented periodic data, scrambled periodic data, and inverted periodic data respectively to obtain inverted segmented periodic data, inverted scrambled periodic data, and inverted inverted periodic data; combining the segmented periodic data, scrambled periodic data, inverted periodic data, inverted segmented periodic data, inverted scrambled periodic data, and inverted inverted periodic data to obtain the calibration excitation data for the complete cycle that needs to be sent for one calibration excitation.
[0060] Specifically, after obtaining the first segmented periodic data Y1, the second segmented periodic data Y2, the shuffled periodic data Y3, and the inverted periodic data Y4, each periodic data is inverted, and all bits are processed by changing 1 to 0 and 0 to 1. Continuing with the Y1, Y2, Y3, and Y4 sequences mentioned above as examples, the inverted first segmented periodic data ~Y1 sequence is: 0x328C, 0x6918..., the inverted second segmented periodic data ~Y2 sequence is: 0x71D6, 0xE3AC..., the inverted shuffled periodic data ~Y3 sequence is: 0x6278, 0x89E0..., and the inverted periodic data ~Y4 sequence is: 0xC82D, 0x23B5.... The complete cycle of calibration stimulus data that needs to be sent for one calibration stimulus is (Y1, Y2, Y3, Y4, ~Y1, ~Y2, ~Y3, ~Y4). Different data are inverted and combined to generate calibration excitation data, which further improves the diversity of data combinations, so that each bit gets the maximum flip and randomness, increases the flip rate and randomness of the signal, and improves the accuracy of timing calibration.
[0061] The aforementioned calibration stimulus data generation method extracts multiple segmented periodic data from a pseudo-random sequence. The bit order of these segmented periodic data is shuffled to generate shuffled periodic data. The target bit of the shuffled periodic data is then inverted to generate inverted periodic data. Finally, the segmented periodic data, shuffled periodic data, and inverted periodic data are combined to obtain the calibration stimulus data. This achieves a higher flip rate, making timing tests more accurate and improving timing calibration precision. Compared to traditional methods, this approach avoids excessively long consecutive 0s or 1s, has a higher flip density, and provides evenly staggered bit transitions, making it suitable for stress testing scenarios.
[0062] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0063] Based on the same inventive concept, this application also provides a calibration excitation data generation apparatus for implementing the calibration excitation data generation method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the calibration excitation data generation apparatus provided below can be found in the limitations of the calibration excitation data generation method described above, and will not be repeated here.
[0064] In one embodiment, such as Figure 2 As shown, a calibration excitation data generation device is provided, comprising: a pseudo-random sequence extraction module 100, a sequence shuffling module 200, and an inversion and combination module 300, wherein:
[0065] The pseudo-random sequence truncation module 100 is used to acquire pseudo-random sequences and truncate them to obtain multiple segmented periodic data.
[0066] The scrambling module 200 is used to scramble the bit order of segmented periodic data to generate scrambled periodic data.
[0067] The inversion and combination module 300 is used to invert the data of the target bit of the scrambled periodic data to generate inverted periodic data; and to combine the segmented periodic data, the scrambled periodic data and the inverted periodic data to obtain calibration excitation data.
[0068] In one embodiment, the shuffling module 200 is used to sequentially select bits from the first segmented periodic data and the second segmented periodic data respectively for odd-even cross-sorting to generate shuffled periodic data.
[0069] In one embodiment, the inverting combination module 300 is used to keep the even bits unchanged and invert the odd bits in the scrambled periodic data, or keep the odd bits unchanged and invert the even bits to generate inverted periodic data.
[0070] In one embodiment, the inversion and combination module 300 is used to invert the segmented periodic data, the scrambled periodic data, and the inverted periodic data respectively to obtain the inverted segmented periodic data, the inverted scrambled periodic data, and the inverted inverted periodic data; and to combine the segmented periodic data, the scrambled periodic data, the inverted periodic data, the inverted segmented periodic data, the inverted scrambled periodic data, and the inverted inverted periodic data to obtain the calibration excitation data for the complete cycle that needs to be sent for one calibration excitation.
[0071] Each module in the aforementioned calibration excitation data generation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0072] The aforementioned calibration excitation data generation device comprises a pseudo-random sequence extraction module that extracts multiple segmented periodic data from a pseudo-random sequence, scrambles the bit order of these segmented periodic data to generate scrambled periodic data, a scrambling module that inverts the target bit of the scrambled periodic data to generate inverted periodic data, and an inverted combination module that inverts the target bit of the scrambled periodic data to generate inverted periodic data. Combining the segmented periodic data, scrambled periodic data, and inverted periodic data yields the calibration excitation data, achieving a higher flip rate, resulting in more accurate timing tests and improved timing calibration precision.
[0073] In one embodiment, such as Figure 3As shown, a timing calibration device is also provided, including a data output module 120 and a delay module 130. The data output module 120 is connected to the delay module 130 and outputs calibration excitation data to the delay module 130 according to the above method. The delay module 130 is connected to the delay control module 110 and the digital-to-analog converter. According to the delay values sent by the delay control module 110, the calibration excitation data is delayed and then sent to the digital-to-analog converter.
[0074] Furthermore, the device also includes a delay control module 110 and a readback data recording module 140. The delay control module 110 is also connected to the readback data recording module 140, synchronously sending each delay value to the delay module 130 and the readback data recording module 140. The readback data recording module 140 is connected to the digital-to-analog converter. After the delay module 130 sends the calibration excitation data to the digital-to-analog converter according to different delay values, it obtains the status register result inside the digital-to-analog converter. It then performs calibration by combining the status register results corresponding to different delay values, obtaining a calibration success / failure result. The status register result (stored as 1 under normal conditions and 0 under abnormal conditions) indicates whether the timing of the digital-to-analog converter is normal under the current delay value. By using the readback data recording module 140 to obtain the status register result indicating whether the timing of the digital-to-analog converter is normal under the current delay value, and combining it with the status register results corresponding to different delay values, calibration success / failure results are obtained, thus achieving accurate calibration of the digital-to-analog converter.
[0075] The delay control module 110, data output module 120, delay module 130, and readback data recording module 140 can be at least one of the host computer, main control board, and test board, respectively. In this embodiment, the delay control module 110, data output module 120, delay module 130, and readback data recording module 140 are all located in the FPGA of the test board. By building a timing calibration device on the test board, the calibration process does not require back-and-forth communication between the host computer and the test board for calibration control, which can improve calibration efficiency and avoid inconsistencies between the calibration stimulus data and the actual running program caused by the host computer sending calibration stimulus data to the test board, thus ensuring calibration accuracy.
[0076] Specifically, the delay control module 110 sequentially and synchronously sends gradually changing delay values to the delay module 130 and the readback data recording module 140. The delay values can be gradually increasing or gradually decreasing. Depending on the structure of the delay module 130, the specific type of delay value will also differ. For example, if the delay module 130 uses an IODELAY structure for data delay, the delay value is specifically a delay tap value. After the data output module 120 sets the calibration excitation data for a complete cycle required for one calibration excitation according to the above method, the data output module 120 outputs a complete cycle of calibration excitation data for each delay value sent by the delay control module 110. The delay module 130 delays the complete cycle of calibration excitation data based on the received delay value before sending it to the digital-to-analog converter.
[0077] The readback data recording module 140 can be connected to the digital-to-analog converter (DAC) via an interface such as SPI. Each time the delay control module 110 sends a delay value, the readback data recording module 140 reads the internal status register of the DAC to obtain the status register result indicating whether the timing of the DAC is normal at the current delay value. Specifically, the status register result includes comparison results at three positions: the sampling point, before the sampling point, and after the sampling point. Combining the status register results corresponding to different delay values, calibration is performed to obtain a calibration success / failure result. The calibration success / failure result includes a calibration success / failure flag and the corresponding calibration result. Furthermore, after reading the internal status register of the DAC, the readback data recording module 140 also clears the internal status register to ensure that the initial status register is normal each time calibration begins.
[0078] The aforementioned timing calibration device combines segmented periodic data, shuffled periodic data, and inverted periodic data to obtain calibration excitation data. Delaying the transmission of this calibration excitation data to the analog-to-digital converter allows for more accurate timing testing and improves timing calibration precision.
[0079] In one embodiment, such as Figure 4As shown, the delay control module 110 is also connected to the data output module 120. After receiving the start signal sent by the delay control module, the data output module 120 outputs calibration excitation data to the delay module 130, and stops outputting after sending the calibration excitation data corresponding to the current delay value, and sends the data transmission end signal Tx_once_finish to the readback data recording module 140. After receiving the data transmission end signal Tx_once_finish, the readback data recording module 140 reads the status register result corresponding to the current delay value from the digital-to-analog converter (DAC), and returns the status read end signal Rd_reg_finish to the delay control module 110 after reading. After receiving the status read end signal Rd_reg_finish, the delay control module 110 sends the start signal start to the data output module 120 again, and sends the next delay value to the delay module 130, until the number of times the delay value is sent reaches the preset delay number threshold.
[0080] The digital-to-analog converter (DAC) is also connected to a clock chip, receives the sampling clock Sample_clk output by the clock chip, divides the sampling clock Sample_clk to obtain the data clock Data_clk, and sends it to the data output module 120. The data output module 120 outputs calibration excitation data according to the data clock Data_clk, and after being delayed by the delay module 130, it is sent to the DAC. The DAC performs digital-to-analog conversion on the received data according to the sampling clock Sample_clk.
[0081] Specifically, the delay control module 110 sequentially and synchronously sends progressively increasing delay values Delay_tap to the delay module 130 and the readback data recording module 140. The initial value of the delay value Delay_tap can be set to 0. Each time the delay value Delay_tap is sent, it increases by a preset step size (e.g., 1). The threshold value for the number of delays is not unique and can be set according to actual needs. For example, if the threshold value for the number of delays is 512 and the preset step size is 1, then the delay control module 110 sequentially sends delay values Delay_tap = 0, 1, 2, ..., 511. Each time the calibration excitation output is performed, the delay control module 110 sends a start signal start to the data output module 120 and synchronously sends a delay value Delay_tap to the delay module 130 and the readback data recording module 140. The data output module 120 receives a start signal and outputs a complete cycle of calibration excitation data. After outputting, it sends a data transmission end signal Tx_once_finish to the readback data recording module 140. Upon receiving the Tx_once_finish signal, the readback data recording module 140 reads its internal status register from the digital-to-analog converter (DAC) to obtain the status register result corresponding to the current delay value Delay_tap. This result is cached in the internal storage unit of the readback data recording module 140. After reading, it returns a status read end signal Rd_reg_finish to the delay control module 110. Upon receiving the Rd_reg_finish signal, the delay control module 110 performs the next calibration excitation output until the delay value Delay_tap = 511. The internal storage unit of the readback data recording module 140 can be of various types, including RAM, registers, and FIFOs. In this embodiment, the internal storage unit is RAM.
[0082] In this embodiment, the data output module 120, the readback data recording module 140, and the delay control module 110 interact with each other to accurately perform different delays on the calibration excitation data and read the corresponding status register results, thereby ensuring the accuracy of timing calibration.
[0083] In one embodiment, continue to refer to Figure 2The data output module 120 includes a calibration data generation module 122, an arbitrary waveform data transmission module 124, and a data selection module 126. The data selection module 126 is connected to the calibration data generation module 122, the arbitrary waveform data transmission module 124, the delay module 130, and the delay control module 110. The calibration data generation module 122 is connected to the delay control module 110 and the readback data recording module 140. The delay control module 110 outputs a switching signal to the data selection module 126, controlling the data selection module 126 to send the calibration excitation data output by the calibration data generation module 122 to the delay module 130, or to send the arbitrary waveform data output by the arbitrary waveform data transmission module 124 to the delay module 130, and send the calibration result as a delay value to the delay module 130. After receiving the start signal from the delay control module 110, the calibration data generation module 122 outputs calibration excitation data and stops outputting after sending the calibration excitation data corresponding to the current delay value. It then sends a data transmission end signal Tx_once_finish to the readback data recording module 140. Upon receiving the data transmission end signal Tx_once_finish, the readback data recording module 140 reads the status register result corresponding to the current delay value from the digital-to-analog converter (DAC). After reading, it returns a status read end signal Rd_reg_finish to the delay control module 110.
[0084] Depending on the actual working mode, the delay control module 110 can send a switching signal Cali_mode_sel to the data selection module 126, thereby controlling the data selection module 126 to switch between outputting calibration excitation data or arbitrary waveform data to adapt to different working scenarios. For example, in calibration mode, the delay control module 110 controls the data selection module 126 to send the calibration excitation data output by the calibration data generation module 122 to the delay module 130; in working mode, the delay control module 110 controls the data selection module 126 to send the arbitrary waveform data output by the arbitrary waveform data sending module 124 to the delay module 130, and sends the calibration result as a delay value to the delay module 130. Specifically, the data selection module 126 sends the received calibration excitation data or arbitrary waveform data to the delay module 130 for delay according to the data clock data_clk. The delayed data is then sent to the digital-to-analog converter (DAC) for digital-to-analog conversion according to the sampling clock Sample_clk.
[0085] Furthermore, the data output module 120 outputs multi-bit parallel data, and the delay module 130 is an IODELAY module. Each bit of parallel data is delayed using an IODELAY link based on the same current delay value before being sent to the digital-to-analog converter (DAC). For example... Figure 2As shown, taking the output of 16-bit parallel data by the data output module 120 as an example, the data selection module 126, based on the received switching signal Cali_mode_sel, sends the 16-bit parallel data output by the calibration data generation module 122 or the arbitrary waveform data transmission module 124 to the delay module 130. The delay module 130 uses 16 IODELAY links to delay each bit of parallel data based on the same current delay value. In this embodiment, multiple IODELAY links are used to delay each bit of parallel data based on the same current delay value to ensure accurate delay.
[0086] In one embodiment, the readback data recording module 140 uses the delay value as the address and the status register result as the result data for corresponding binding and storage. It iterates through the result data corresponding to different addresses, obtains the longest consecutive string of 1s in the result data, and determines the buffer length and the corresponding start and end addresses. The readback data recording module 140 compares the buffer length with a preset length threshold to obtain a calibration success / failure flag, and combines this with the start and end addresses to determine the calibration result. The resulting calibration success / failure result is then sent to the delay control module 110. By combining the delay value and the corresponding result data to analyze the longest consecutive string of 1s in the result data, the buffer length and the corresponding start and end addresses are determined, thereby accurately analyzing and obtaining the calibration success / failure result.
[0087] The preset length threshold value is not unique and can be set according to actual needs. Specifically, the readback data recording module 140 gradually traverses the result data corresponding to different addresses. When before_data=0 and current_data=1, the current address addr is assigned to the starting address; when current_data=1, the length of the cache where consecutive result data equals 1 begins to be recorded; when current_data=0, the length is cleared to zero, and counting restarts when current_data=1; when before_data=1 and current_data=0, the current address addr is assigned to the ending address. If the current cache length is greater than the previous cache length, the current cache length and the corresponding starting and ending addresses are latched simultaneously. Here, current_data represents the result data at the current address addr, and before_data represents the result data at address addr-1. The calibration result is the average of the starting and ending addresses.
[0088] like Figure 4As shown, the readback data recording module 140 compares the final buffer length with a preset length threshold (e.g., 32, 64). If the buffer length is greater than or equal to the preset length threshold, the timing calibration requirements are considered met, and a calibration success flag cali_success (with calibration completion information) and the corresponding calibration result cali_data = (start_addr + stop_addr) / 2 are output to the delay control module 110. If the buffer length is less than the preset length threshold, a calibration failure flag (with calibration completion information) and the corresponding calibration result cali_data = (start_addr + stop_addr) / 2 are output to the delay control module 110.
[0089] In this embodiment, the result data of the current address addr and the result data of address addr-1 are analyzed step by step to avoid data omission, accurately extract the longest cache length and the corresponding start address and end address for latching, and use the average value of the start address and end address as the calibration result cali_data to complete the timing calibration.
[0090] In one embodiment, when the delay control module 110 receives the calibration success flag cali_success returned by the readback data recording module 140, it sends the corresponding calibration result cali_data as a delay value Delay_tap to the delay module 130 and sends a start signal stat to the data output module 120, so that the delay module 130 delays the calibration excitation data output by the data output module 120 again according to the received delay value Delay_tap before sending it to the digital-to-analog converter DAC; the readback data recording module 140 reads the status register result after delaying the calibration excitation data as a delay value and sending it to the digital-to-analog converter DAC, and analyzes the read status register result to obtain the verification success / failure status and returns it to the delay control module 110.
[0091] Specifically, after successful calibration, the delay control module 110 sends the corresponding calibration result cali_data as the delay value Delay_tap to the delay module 130, and sends a start signal stat to the calibration data generation module 122, instructing the calibration data generation module 122 to generate calibration excitation data. The readback data recording module 140 reads the status register result of the digital-to-analog converter (DAC). If the status register is 1, the verification is successful, and a verification success status Check_success is sent to the delay control module 110; if the status register is 0, the verification is unsuccessful, and a verification failure status is sent to the delay control module 110.
[0092] In this embodiment, when calibration is successful, the corresponding calibration result is used as a delay value to delay the calibration excitation data before sending it to the digital-to-analog converter (DAC). The readback data recording module 140 reads the corresponding status register result to analyze and verify the success / failure status, and accurately performs timing verification.
[0093] Furthermore, after receiving a calibration failure flag or a verification success / failure status returned by the readback data recording module 140, the delay control module 110 controls the data output module 120 to output arbitrary waveform data to the delay module 130. After completing calibration and verification, the delay control module 110 sends a switching signal Cali_mode_sel to the data selection module 126 to switch to the working mode. The data selection module 126 sends the arbitrary waveform data output by the arbitrary waveform data sending module 124 to the delay module 130. The delay module 130 uses the calibration result as the delay value Delay_tap to delay the arbitrary waveform data. In this embodiment, after calibration failure or obtaining a verification success / failure status, the delay module 120 is also controlled to output arbitrary waveform data for a delay before sending it to the digital-to-analog converter (DAC) for digital-to-analog conversion.
[0094] Specifically, after the test board is powered on and initialized, the timing calibration device on the FPGA automatically performs timing calibration. After calibration, the host computer checks whether the calibration was successful. If calibration fails, a log is printed indicating that the calibration of channel xx failed. A timing calibration device can be set for each channel on the test board, and all channels are calibrated simultaneously upon power-on. Furthermore, after power-on calibration is complete, commands can be sent from the host computer to independently control the calibration of one or more channels as needed. Figure 5 As shown, timing calibration includes the following steps:
[0095] Step 1: After the test board is powered on and the reset is released, the FPGA internal delay control module 110 automatically starts calibration;
[0096] Set the initial value of the delay value Delay_tap to 0;
[0097] A start signal is sent to the calibration data generation module 122, instructing the calibration data generation module 122 to start generating calibration excitation data; at the same time, a switching signal Cali_mode_sel is sent to the data selection module 126, instructing the data selection module 126 to select the 16-bit parallel data output from the calibration data generation module 122.
[0098] The delay value Delay_tap is sent to the delay module 130. The delay module 130 controls IODELAY to delay the calibration excitation data output by the calibration data generation module 122 according to the input delay value Delay_tap before outputting it.
[0099] Send the delay value Delay_tap=0 to the readback data recording module 140.
[0100] Step 2: After the calibration data generation module 122 outputs calibration excitation data for one complete cycle, it indicates that the calibration excitation data for one delay value has been sent. Data output stops, and a data transmission end signal Tx_once_finish is sent to the readback data recording module 140.
[0101] Step 3: After receiving the data transmission end signal Tx_once_finish, the readback data recording module 140 indicates that the calibration excitation data for the current delay value Delay_tap has been transmitted.
[0102] Readout of Analog-to-Digital Converter (DAC) Status: The readback data recording module 140 sends a read command to the DAC via SPI to read the status register result of the DAC. The status register result of the DAC can provide feedback on whether the timing is normal under the current delay value.
[0103] Clear the status of the digital-to-analog converter (DAC): After reading the status register result of the DAC, the readback data recording module 140 sends a clear command to the DAC via SPI to clear the status register of the DAC, ensuring that it is normal at the beginning of each calibration.
[0104] Readback status cache: The readback data recording module 140 stores the read status register result into the local RAM cache, using the delay value Delay_tap as the RAM address and the status register result as the RAM result data;
[0105] After reading the status of the digital-to-analog converter (DAC), a status reading end signal Rd_reg_finish is sent to the delay control module 110 to indicate that the reading of the status register is complete and the next delay value Delay_tap calibration can be performed.
[0106] Step 4: After receiving the status reading end signal Rd_reg_finish, the delay control module 110 increments the delay value Delay_tap by 1, and then repeats steps 1 to 4 until Delay_tap = 511, then proceeds to step 5.
[0107] Step 5: When the delay value Delay_tap = 511, after the data reading and recording module 140 finishes reading the DAC status register, there are 512 data entries in the buffer RAM. The calibration result is then determined based on the data in the RAM. A serial bit-by-bit run-length segmentation algorithm can be used to sequentially traverse the RAM from address 0 to address 511. The specific process is as follows:
[0108] 1) In the initial stage, the following parameters are set in the FPGA's internal registers: before_data, current_data, start_addr, stop_addr, and length. Before_data represents the result data at address addr-1, with an initial value of 0. Current_data represents the result data at the current address addr. Start_addr is the start address of the latch, stop_addr is the end address of the latch, and length is the latch length with consecutive data of 1, with an initial value of 0.
[0109] 2) Initially, addr=0. When (before_data=0¤t_data=1), it means that the first data is the starting address, so the starting address is counted as 0; when (before_data=0¤t_data=0), it means that the first data is not the starting address, so the starting address is counted as 511.
[0110] 3) Iterate through RAM addresses addr: 0~511 step by step. Examples of the results for each addr are as follows:
[0111] 10000111111000000000000000000001111111111111111111111100000000000111111111101111.
[0112] When (before_data = 0 ¤t_data = 1), it means that addr is the starting address, and addr is assigned to the starting address; when current_data = 1, the length of consecutive data equal to 1 is recorded; when current_data = 0, the length is cleared to zero, and counting starts again when current_data = 1.
[0113] When (before_data=1¤t_data=0), it means that addr is the end address. Addr is assigned to the end address. It is determined that the current cache length is greater than the previous cache length. At the same time, the start address, cache length, and end address are latched and latched into start_addr, stop_addr, and length respectively, until 511 bits have been traversed.
[0114] 4) Determine if the calibration data is valid. Check if the length is greater than or equal to the preset length threshold. Only if it is greater than or equal to the preset length threshold does it indicate that the timing calibration requirements are met. If the length is greater than or equal to the preset length threshold, output a calibration success flag cali_success (with calibration completion information) to the delay control module 110, and send the calibration result cali_data = (start_addr + stop_addr) / 2 to the delay control module 110. If the length is less than the preset length threshold, output a calibration failure flag (with calibration completion information) to the delay control module 110, and send the calibration result cali_data = (start_addr + stop_addr) / 2 to the delay control module 110 (even if the calibration fails, the closest correct calibration result will be sent to the control module 110).
[0115] Step 6: Calibration data verification: The delay control module 110 receives the calibration success / failure result sent by the readback data recording module 140. If the calibration is successful, execute steps (1) to (4); if the calibration fails, execute step 7 and wait for the host computer to read the calibration status.
[0116] Step (1): The delay control module 110 sends the calibration result cali_data as the delay value Delay_tap to the delay module 130;
[0117] Step (2): The delay control module 110 sends a start signal to the calibration data generation module 122, instructing the calibration data generation module 122 to start generating calibration excitation data;
[0118] Step (3): Perform steps 2 and 3;
[0119] Step (4): The data recording module 140 reads the status register of the digital-to-analog converter (DAC) and determines whether the status register result is 1. If it is 1, the verification is successful; if it is 0, the verification is unsuccessful. The verification success / failure status is returned to the delay control module 110, and the host computer is waited to read the calibration success / failure result and the verification success / failure status.
[0120] Step 7: Restore the working state of the arbitrary waveform data transmission module 124 (AWG): The delay control module 110 sends a switching signal Cali_mode_sel to instruct the data selection module 126 to select the data from the arbitrary waveform data transmission module 124 for output.
[0121] In addition to supporting automatic calibration of the test board upon power-on, improving the efficiency and accuracy of timing calibration, the above solution also supports switching between working mode and calibration mode at any time during the operation of the test machine, supports independent calibration of multiple channels, and each channel can independently receive control commands from the host computer after calibration to run calibration or AWG functions, making it more flexible in use.
[0122] Upon completion of calibration and entry into working mode, control commands can be sent from the host computer to the delay control module 110. The delay control module 110 will then perform a second calibration operation, during which time AWG channel data will be stopped. Simultaneously, the relays on the test board, such as the range switches and filters, must be restored to their default states and disconnected from external relays to ensure that the calibration process does not affect the DUT chip. The relays will not reset after calibration; the AWG needs to be reconfigured if it needs to operate again.
[0123] When a timing calibration of a test board fails, it can be re-calibrated. After calibration, the calibration results are read back from RAM to analyze the board's timing. This method provides a complete understanding of the test board's timing characteristics, analyzes the distribution of 1s and 0s in RAM, and identifies the cause of the timing anomaly. For example, the following scenarios might involve reading the results from RAM:
[0124] Scene 1:
[0125] If the result data is all abnormal, it is necessary to check whether the control logic is sending and calibrating normally; or check whether the peripheral chip is normal, such as the chip power supply and the chip SPI communication status.
[0126] Scene 2:
[0127] 1000011111100000000000000000001111111111111111111111100000000000111111111101111; The result data contains both normal and abnormal data, but the normal and abnormal data are scattered in many places. At this time, it is necessary to check the quality of the external clock signal, whether the clock signal is jumping, or whether the clock spurious is too high, resulting in large sampling clock jitter.
[0128] Scene 3:
[0129] The result data shows several consecutive normal data points followed by abnormal data, which is relatively normal. This indicates that the clock and chip are working normally. At this point, the investigation should focus on why the calibration failed. Is it because the number of consecutive 1s is insufficient? Is there an insufficient calibration adjustment range? It is necessary to check whether the 16-bit signal group inside the program is of equal length and how much the signal trace deviation is between each bit. If the difference is too large, it may be a scenario where calibration fails.
[0130] In addition, the timing of some test boards is greatly affected by power supply fluctuations. Abnormalities will only occur when the power supply is under the maximum working pressure. No abnormalities will occur when the AWG is not working normally. When multiple channels are working normally, timing calibration can be performed on only one or more channels with problems, which is more in line with actual use scenarios and facilitates problem analysis and localization.
[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0132] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for generating calibration excitation data, characterized in that, include: The pseudo-random sequence is obtained and truncated to obtain multiple segmented periodic data; The segmented periodic data is shuffled in bit order to generate shuffled periodic data. Invert the data of the target bit of the scrambled periodic data to generate inverted periodic data; The segmented periodic data, the scrambled periodic data, and the inverted periodic data are combined to obtain calibration excitation data.
2. The method according to claim 1, characterized in that, The segmented periodic data includes first segmented periodic data obtained by truncating the low bits of the pseudo-random sequence, and second segmented periodic data obtained by truncating the high bits of the pseudo-random sequence.
3. The method according to claim 2, characterized in that, The process of shuffling the bit order of the segmented periodic data to generate shuffled periodic data includes: sequentially selecting bits from the first segmented periodic data and the second segmented periodic data and rearranging them in an odd-even alternation manner to generate shuffled periodic data.
4. The method according to claim 3, characterized in that, Inverting the target bit of the scrambled periodic data to generate inverted periodic data includes: keeping the even bits unchanged and inverting the odd bits, or keeping the odd bits unchanged and inverting the even bits, to generate inverted periodic data.
5. The method according to any one of claims 1 to 4, characterized in that, The segmented periodic data, the scrambled periodic data, and the inverted periodic data are combined to obtain calibration excitation data, including: The segmented periodic data, the shuffled periodic data, and the inverted periodic data are inverted respectively to obtain the inverted segmented periodic data, the inverted shuffled periodic data, and the inverted inverted periodic data. The segmented periodic data, the scrambled periodic data, the inverted periodic data, the inverted segmented periodic data, the inverted scrambled periodic data, and the inverted inverted periodic data are combined to obtain the calibration excitation data for the complete cycle that needs to be sent for one calibration excitation.
6. A calibration excitation data generation device, characterized in that, include: The pseudo-random sequence truncation module is used to acquire pseudo-random sequences and truncate them to obtain multiple segmented periodic data. The shuffling module is used to shuffle the bit order of the segmented periodic data to generate shuffled periodic data. The inverting and combining module is used to invert the target bit of the scrambled periodic data to generate inverted periodic data; and to combine the segmented periodic data, the scrambled periodic data and the inverted periodic data to obtain calibration excitation data.
7. A timing calibration device, characterized in that, include: The data output module is connected to the delay module and outputs calibration excitation data to the delay module according to any one of claims 1 to 5. The delay module is connected to the delay control module and the digital-to-analog converter. Based on the delay values sent by the delay control module, the calibration excitation data is delayed and then sent to the digital-to-analog converter.
8. The apparatus according to claim 7, characterized in that, It also includes a readback data recording module; the delay control module is also connected to the readback data recording module, and synchronously sends gradually changing delay values to the delay module and the readback data recording module in sequence. The readback data recording module is connected to the digital-to-analog converter. After the delay module sends the calibration excitation data to the digital-to-analog converter with different delay values, it obtains the status register result inside the digital-to-analog converter. It then performs calibration by combining the status register result corresponding to different delay values to obtain the calibration success / failure result. The status register result indicates whether the timing of the digital-to-analog converter is normal at the current delay value.
9. The apparatus according to claim 8, characterized in that, The data output module includes a calibration data generation module, an arbitrary waveform data transmission module, and a data selection module. The data selection module is connected to the calibration data generation module, the arbitrary waveform data transmission module, the delay module, and the delay control module. The calibration data generation module is connected to the delay control module and the readback data recording module. The delay control module outputs a switching signal to the data selection module, controlling the data selection module to send the calibration excitation data output by the calibration data generation module to the delay module, or controlling the data selection module to send the arbitrary waveform data output by the arbitrary waveform data sending module to the delay module, and sending the calibration result as a delay value to the delay module; After receiving the start signal sent by the delay control module, the calibration data generation module outputs calibration excitation data and stops outputting after sending the calibration excitation data corresponding to the current delay value. The data transmission end signal is sent to the readback data recording module. After receiving the data transmission end signal, the readback data recording module reads the status register result corresponding to the current delay value from the digital-to-analog converter, and returns the status read end signal to the delay control module after the reading is completed. After receiving the status reading end signal, the delay control module sends a start signal to the data output module again and sends the next delay value to the delay module until the number of times the delay value is sent reaches the preset delay number threshold.
10. The apparatus according to claim 9, characterized in that, The calibration success / failure result includes a calibration success / failure flag and the corresponding calibration result; The readback data recording module uses the delay value as the address and the status register result as the result data for corresponding binding and storage. It gradually traverses the result data corresponding to different addresses, obtains the longest length of consecutive 1s in the result data, and determines the cache length and the corresponding start and end addresses. The readback data recording module compares the cache length with the preset length threshold to obtain a calibration success / failure identifier, and determines the calibration result by combining the start address and the end address, and sends the calibration success / failure result to the delay control module.