A full temperature current steering DAC calibration circuit that maintains a constant total current

Abstract

The application discloses a full-temperature current steering DAC calibration circuit for keeping total current constant, comprising: a bias generation circuit for generating a global bias voltage, a first temperature-dependent bias current and a second temperature-independent bias current according to a bias current source selection signal and a sub-DAC current control code; a double-parameter calibration compensation unit for generating a compensation current based on a variable bias cross-iteration single-cell calibration logic according to a first temperature-dependent calibration current control code, a second temperature-independent calibration current control code and the first and second bias currents; a DAC main current source array and a DAC reference current source for generating a main current source current and a reference current source current based on a bottom-up reference transfer calibration logic according to the global bias voltage and the compensation current; and a digital control circuit for updating the bias current source selection signal, the sub-DAC current control code and the first and second calibration current control codes according to a comparison result of a current comparator.

Description

Technical Field

[0001] This invention belongs to the field of analog and mixed-signal integrated circuit design technology, specifically relating to a full-temperature current-rudder DAC calibration circuit that maintains a constant total current. Background Technology

[0002] In the rapid development of quantum computing and quantum information technology, quantum measurement and control systems place extremely stringent demands on the performance of underlying hardware. The manipulation and readout of qubits such as superconducting, semiconductor quantum dots, or ion traps typically require high-precision, ultra-high-speed digital-to-analog converters (DACs) with sampling rates as high as several GSPS or even tens of GSPS to synthesize microwave control pulses with extremely low noise floor and extremely high fidelity. Using advanced deep submicron CMOS technology, current-controlled DACs, with their excellent high-frequency dynamic performance and driving capability, have become the core device in the quantum measurement and control chain.

[0003] However, with the miniaturization of process nodes, unavoidable random mismatch of current sources severely limits the static and dynamic linearity of DACs, causing high-frequency harmonic distortion, which directly degrades the waveform fidelity of quantum manipulation pulses. To improve current source matching accuracy, front-end calibration techniques are typically employed. However, existing front-end calibration techniques generally face three inherent system-level technical challenges in practical applications, especially in cutting-edge scenarios such as quantum measurement and control, where environmental stability, system gain, and power consumption are extremely sensitive: First, there is the issue of single-temperature failure (temperature drift sensitivity). Traditional front-end calibration is typically performed at a single temperature. When the chip's ambient temperature deviates from the calibration temperature, the original calibration accuracy drops significantly due to the different temperature characteristics of the transistor threshold voltage and current factor, leading to a deterioration in the long-term stability of the quantum control pulse and affecting the coherence time of the quantum state.

[0004] Second, there is the issue of total power consumption and system gain drift caused by unidirectional calibration. To address single-temperature failure, existing technologies have proposed dual-parameter temperature compensation schemes. However, such front-end calibration processes are typically unidirectional, meaning they can only add supplementary current to the main current source to compensate for mismatch. With the completion of full-array DAC calibration, the actual output current of each internal current source increases to varying degrees, inevitably leading to a larger total full-scale output current of the DAC. This disordered drift of the total current directly introduces system-level absolute gain error—in quantum measurement and control applications, even a small drift in microwave pulse amplitude can cause fatal phase rotation errors and distortions in quantum gate operations. Simultaneously, the additional static power consumption caused by the increased total current also imposes a significant thermal noise and heat dissipation burden on quantum measurement and control systems operating in extremely low-temperature environments.

[0005] Third, there are issues with the system complexity and hardware overhead of full-array multi-range calibration. Traditional full-array calibration schemes, due to the need to handle multiple current sources with different weights within a segmented DAC, typically require matching multiple reference current sources and comparison networks with different ranges, or employing extremely complex cross-array cross-comparison logic. This not only significantly increases the design difficulty and layout area of ​​the calibration system, limiting the integration density of high-density multi-channel quantum measurement and control chips, but also easily introduces additional propagation errors during the switching between different ranges.

[0006] Therefore, there is an urgent need for a brand-new DAC calibration system architecture that can perform high-precision dual-parameter calibration across the entire temperature range through extremely simple hardware logic, and maintain an absolute constant total current at full scale after calibration, thereby meeting the extreme requirements of pulse amplitude stability and extremely low power consumption in cutting-edge fields such as quantum measurement and control. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a full-temperature current-steering DAC calibration circuit that maintains a constant total current. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a full-temperature current-rudder DAC calibration circuit that maintains a constant total current. The full-temperature current-rudder DAC calibration circuit includes: The bias generation circuit is used to generate a global bias voltage, a temperature-dependent first bias current, and a temperature-independent second bias current based on the bias current source selection signal and the sub-DAC current control code; wherein, the bias current required by the bias generation circuit is generated by the DAC reference current source. The dual-parameter calibration compensation unit is used to generate a compensation current based on the variable bias cross-iteration single-unit calibration logic according to the temperature-related first calibration current control code, the temperature-independent second calibration current control code, the first bias current, and the second bias current. The DAC main current source array and DAC reference current source are used to generate the main current source current and reference current source current that meet the current ratio requirements based on the global bias voltage and compensation current and the bottom-up reference transfer calibration logic. A current comparator is used to compare the main current source current with the reference current source current. A digital control circuit is used to update the bias current source selection signal, the sub-DAC current control code, the first calibration current control code, and the second calibration current control code based on the comparison result. The DAC output circuit is used to output the main current source current that meets the current ratio requirements after calibration.

[0008] In one embodiment of the present invention, the dual-parameter calibration compensation unit includes a temperature-dependent current compensation array, a temperature-independent current compensation array, and a compensation current output circuit; the temperature-dependent current compensation array includes transistor NM. 21 ~Transistor NM 24 The temperature-independent current compensation array includes transistor NM 25 ~Transistor NM 28 The compensation current output circuit includes a transistor PM 21 and PM 22 ;in, transistor NM 21 The drain of the transistor NM 21 Gate, transistor NM 22 The first bias current is generated in the gate and bias generation circuit. I cal_T The output terminal is connected to transistor NM. 22 The drain of the transistor NM 23 drain, transistor NM 24 The source connection of the transistor NM 21 The source of the transistor NM 22 The sources of the transistors are all grounded, NM 23 The gate is connected to the second calibration current control code in the digital control circuit via an inverter. D ZTC The output terminal is connected to transistor NM. 23 The source of the transistor is connected to the power supply VDD. 24 The gate and the second calibration current control code in the digital control circuit D ZTC The output terminal is connected to transistor NM. 24 The drain of the transistor NM 28 drain, transistor PM 21 The drain connection of the transistor NM 25 The drain of the transistor NM 25 Gate, transistor NM 26 A second bias current is generated in the gate and bias generation circuit. I cal_ZCT The output terminal is connected to transistor NM. 26 The drain of the transistor NM 27 drain, transistor NM 28 The source connection of the transistor NM 25 The source of the transistor NM 26 The sources of the transistors are all grounded, NM 27 The gate is connected to the first calibration current control code in the digital control circuit via an inverter. D TThe output terminal is connected to transistor NM. 27 The source of the transistor is connected to the power supply VDD. 28 The gate and the first calibration current control code in the digital control circuit D T The output terminal is connected to the transistor PM. 21 The source of the transistor is connected to the power supply VDD. 21 Gate and transistor PM 22 Gate connection, transistor PM 22 The source of the transistor is connected to the power supply VDD. 22 The drain is used as a compensation current. I cal The output terminal.

[0009] In one embodiment of the present invention, the dual-parameter calibration compensation unit generates a compensation current based on a variable bias cross-iteration single-unit calibration logic according to a temperature-related first calibration current control code, a temperature-independent second calibration current control code, a first bias current, and a second bias current, including: Fix the first calibration current control code, adjust the second calibration current control code, and calibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula. The bias current required by the bias generation circuit is adjusted according to the sub-DAC current control code and the bias current source selection signal, so that the bias current required by the current iteration bias generation circuit is reduced. Fix the second calibration current control code, adjust the first calibration current control code, and recalibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula. Determine whether the first and second calibration current control codes of adjacent iterations are equal. If they are equal, calculate the compensation current based on the first and second bias currents of the current iteration. Otherwise, continue to adjust the bias current required by the bias generation circuit according to the sub-DAC current control code and the bias current source selection signal, so that the bias current required by the bias generation circuit of the current iteration increases. Fix the first calibration current control code, adjust the second calibration current control code, and calibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula until the first and second calibration current control codes of adjacent iterations are equal.

[0010] In one embodiment of the present invention, the calibration formula is: ; in, This represents the output current of the DAC main current source array. This represents the output current of the DAC reference current source. Indicates the first The second calibration current control code during the next iteration. Indicates the first The first calibration current control code during the next iteration. Indicates the first The binary coefficient corresponding to the second calibration current control code in the next iteration. Indicates the first The binary coefficient corresponding to the first calibration current control code in the next iteration. Indicates the first The second bias current generated by the bias generation circuit during the next iteration. Indicates the first The first bias current generated by the bias generation circuit during the next iteration.

[0011] In one embodiment of the present invention, the DAC main current source array includes 8 parallel LSB units, 7 parallel ISB units, and 31 parallel MSB units; each LSB unit includes 7 parallel MOS transistors; each ISB unit includes 2 parallel ISB sub-units, each ISB sub-unit includes 8 parallel MOS transistors; each MSB unit includes 128 parallel MOS transistors. The DAC reference current source includes 1 LSB ref Unit, 3 parallel MSBs ref Unit; LSB ref The unit consists of 8 parallel MOS transistors; each MSB ref The unit consists of 128 MOS transistors connected in parallel; In this configuration, the gates of all MOSFETs are connected to a global bias voltage. V bias The sources of all MOSFETs are connected to the power supply VDD, and the drains of all MOSFETs serve as the outputs of the corresponding units and sub-units.

[0012] In one embodiment of the present invention, the DAC main current source array and the DAC reference current source generate a main current source current and a reference current source current that meet the current ratio requirements based on a bottom-up reference transfer calibration logic according to the global bias voltage and the compensation current, including: Based on the global bias voltage, the output current of each of the eight LSB units in the DAC main current source array is calibrated to the LSB in the DAC reference current source. ref The unit's output current; Inject compensation current into the DAC reference current source LSB ref unit; Based on the global bias voltage, the output currents of the 8 LSB cells and the output current of each ISB sub-cell in the 7 ISB cells of the DAC main current source array are calibrated to the LSB in the DAC reference current source. ref The sum of the unit's output current and compensation current; The first MSB in the DAC reference current source is determined based on the global bias voltage. ref The unit's output current is calibrated to the sum of the output currents of the seven ISB units in the DAC main current source array and the output currents of any two LSB units; Based on the global bias voltage, the output current of the 31 MSB cells in the DAC main current source array and the third MSB cell in the DAC reference current source are compared. ref The output current of each unit is calibrated to the first MSB of the calibrated DAC reference current source. ref The unit's output current; The calibrated DAC main current source array and DAC reference current source generate the main current source current and reference current source current that meet the current ratio requirements, respectively. Among them, the second MSB in the DAC reference current source ref The unit's output current remains constant.

[0013] In one embodiment of the present invention, the bias generation circuit includes switch SW1, switch SW2, and transistor PM. 11 ~Transistor PM 13 , resistor R1, resistor R2, operational amplifier (AP), and sub-DAC module; among which, One end of switch SW1 and one end of switch SW2 are respectively connected to the second MSB in the DAC reference current source. ref Unit, third MSB ref Unit connection: the other end of switch SW1 and one end of switch SW2 are both connected to transistor PM. 11 The source connection, transistor PM 11 The drain and transistor PM 12 The source connection, transistor PM 12 The drain and transistor PM 13 The source connection, transistor PM 13 The drain of transistor PM is connected to the non-inverting input of op-amp AP and one end of resistor R2. 11 Gate, transistor PM 12 Gate, transistor PM 13The gates of each are connected to the corresponding bias voltages. The inverting input of the operational amplifier AP is connected to the output of the sub-DAC module and one end of the resistor R1. The output of the operational amplifier AP serves as the output of the bias generation circuit to generate the global bias voltage. The input of the sub-DAC module is connected to the output of the digital control circuit to generate the sub-DAC current control code. The switching states of switches SW1 and SW2 are controlled by the bias current source selection signal generated by the digital control circuit.

[0014] In one embodiment of the present invention, when the bias current source selection switch SW1 is closed and SW2 is open, the bias current required by the bias generation circuit is generated by the second MSB in the DAC reference current source. ref Unit generation; When the bias current source selection switch SW1 is open and SW2 is closed, the bias current required by the bias generation circuit is supplied by the third MSB of the DAC reference current source. ref Unit generation.

[0015] The beneficial effects of this invention are: This invention proposes a full-temperature current-steering DAC calibration circuit that maintains a constant total current. This circuit addresses the problems of increased total DAC current and high system design complexity caused by multi-range comparisons in existing calibration techniques. It achieves precise matching and strict alignment of the weight ratios of each current source across the entire temperature range, while maintaining absolute stability of total power consumption and improving system linearity. Specifically, this invention introduces a temperature-dependent and temperature-independent dual-parameter calibration compensation mechanism to completely decouple and compensate for the different effects of temperature drift on threshold voltage and current factor. Combined with a bottom-up reference transfer strategy, it ensures that the equivalent output current of current sources with different weights in the DAC main current source array always perfectly maintains the ideal weight ratio initially calibrated when the ambient temperature changes drastically, fundamentally guaranteeing the DAC's ultra-high linearity across the entire temperature range.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a full-temperature current-rudder DAC calibration circuit that maintains a constant total current, provided by an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of the dual-parameter calibration and compensation unit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the calibration iteration logic of the dual-parameter calibration compensation unit provided in an embodiment of the present invention; Figure 4This is a schematic diagram of the structure of the DAC main current source array and the DAC reference current source provided in the embodiments of the present invention; Figure 5 This is a schematic diagram of the calibration logic for transferring two range quantization references between the DAC main current source array and the DAC reference current source provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the current comparator provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the bias generation circuit provided in an embodiment of the present invention. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0019] Please see Figure 1 This invention provides a full-temperature current-rudder DAC calibration circuit that maintains a constant total current. The full-temperature current-rudder DAC calibration circuit includes: The bias generation circuit is used to generate a global bias voltage, a temperature-dependent first bias current, and a temperature-independent second bias current based on the bias current source selection signal and the sub-DAC current control code; wherein, the bias current required by the bias generation circuit is generated by the DAC reference current source. The dual-parameter calibration compensation unit is used to generate a compensation current based on the variable bias cross-iteration single-unit calibration logic according to the temperature-related first calibration current control code, the temperature-independent second calibration current control code, the first bias current, and the second bias current. The DAC main current source array and DAC reference current source are used to generate the main current source current and reference current source current that meet the current ratio requirements based on the global bias voltage and compensation current and the bottom-up reference transfer calibration logic. A current comparator is used to compare the main current source current with the reference current source current. A digital control circuit is used to update the bias current source selection signal, the sub-DAC current control code, the first calibration current control code, and the second calibration current control code based on the comparison result. The DAC output circuit is used to output the main current source current that meets the current ratio requirements after calibration.

[0020] During operation, the DAC main current source array to be calibrated and the DAC reference current source array are respectively connected to the input terminals of the current comparator. The digital control circuit generates sub-DAC current control codes in real time, and simultaneously executes a successive approximation algorithm based on the comparison results of the current comparator to generate calibration current control codes to control the compensation current magnitude of the dual-parameter calibration compensation unit. After calibration, the bias current source selection signal generated by the digital control circuit controls the switching of the bias current in the bias generation circuit, restoring the overall total current of the DAC to its pre-calibration current magnitude.

[0021] Next, each part of the full-temperature current-rudder DAC calibration circuit will be described in detail.

[0022] In this embodiment of the invention, the dual-parameter calibration and compensation unit is as follows: Figure 2 As shown, it includes a temperature-dependent current compensation array, a temperature-independent current compensation array, and a compensation current output circuit; the temperature-dependent current compensation array includes transistor NM. 21 ~Transistor NM 24 The temperature-independent current compensation array includes transistor NM 25 ~Transistor NM 28 The compensation current output circuit includes a transistor PM 21 and PM 22 Among them, transistor NM 21 The drain of the transistor NM 21 Gate, transistor NM 22 The first bias current is generated in the gate and bias generation circuit. I cal_T The output terminal is connected to transistor NM. 22 The drain of the transistor NM 23 drain, transistor NM 24 The source connection of the transistor NM 21 The source of the transistor NM 22 The sources of the transistors are all grounded, NM 23 The gate is connected to the second calibration current control code in the digital control circuit via an inverter. D ZTC The output terminal is connected to transistor NM. 23 The source of the transistor is connected to the power supply VDD. 24 The gate and the second calibration current control code in the digital control circuit D ZTC The output terminal is connected to transistor NM. 24 The drain of the transistor NM 28 drain, transistor PM 21 The drain connection of the transistor NM 25 The drain of the transistor NM 25 Gate, transistor NM26 A second bias current is generated in the gate and bias generation circuit. I cal_ZCT The output terminal is connected to transistor NM. 26 The drain of the transistor NM 27 drain, transistor NM 28 The source connection of the transistor NM 25 The source of the transistor NM 26 The sources of the transistors are all grounded, NM 27 The gate is connected to the first calibration current control code in the digital control circuit via an inverter. D T The output terminal is connected to transistor NM. 27 The source of the transistor is connected to the power supply VDD. 28 The gate and the first calibration current control code in the digital control circuit D T The output terminal is connected to the transistor PM. 21 The source of the transistor is connected to the power supply VDD. 21 Gate and transistor PM 22 Gate connection, transistor PM 22 The source of the transistor is connected to the power supply VDD. 22 The drain is used as a compensation current. I cal The output terminal.

[0023] The core precision unit of a current-controlled DAC is the current source, which is typically implemented using a MOS transistor operating in the saturation region, and its bias current... It can be represented as: ; in, , Indicates carrier mobility. This represents the gate oxide capacitance per unit area. Indicates the length of the MOS transistor. Indicates the width of the MOS transistor. This represents the gate-source voltage of a MOS transistor. This represents the threshold voltage of a MOS transistor. For two adjacent current sources with identical designs, current mismatch... This mainly stems from random fluctuations in the physical parameters of transistors, which can be precisely described by the following formula: ; in, Indicates transconductance, This indicates a current factor mismatch. This indicates a threshold voltage mismatch, and the two mismatch components have different temperature and bias dependence characteristics.

[0024] Based on the Pelgrom model and measured data It remains essentially unchanged with temperature and can be considered a constant. However, transconductance... Strongly dependent on carrier mobility ,and It decreases as temperature increases. Therefore, the component... and It is directly proportional, exhibiting a significant temperature dependence. Meanwhile, due to... This component It also varies with the square root of the bias current. This component is not sensitive to temperature. Directly with bias current It is directly proportional to the current, exhibiting a linear current dependence, and its temperature characteristics are mainly mediated by... Temperature coefficient transfer, if If it is designed to be independent of temperature, then the component is also essentially independent of temperature.

[0025] The calibration scheme of this invention incorporates a compensating current source. Components, i.e. = Another compensation current source compensates Components, i.e. = This ensures that all mismatch components are compensated, resulting in identical output currents for the DAC main current source array and DAC reference current source at all temperatures after compensation. If the bias current of the DAC main current source array is changed from... Become ( If the mismatch component becomes: ; At the same time, the compensation current also scales according to the same rule. , By using different bias points ( and Calibration can be achieved by measuring and adjusting the compensation current.

[0026] Please see Figure 3 In this embodiment of the invention, the dual-parameter calibration compensation unit generates a compensation current based on a variable bias cross-iteration single-unit calibration logic, according to a temperature-related first calibration current control code, a temperature-independent second calibration current control code, a first bias current, and a second bias current. This includes: Fix the first calibration current control code, adjust the second calibration current control code, and calibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula. The bias current required by the bias generation circuit is adjusted according to the sub-DAC current control code and the bias current source selection signal, so that the bias current required by the current iteration bias generation circuit is reduced. Fix the second calibration current control code, adjust the first calibration current control code, and recalibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula. Determine whether the first and second calibration current control codes of adjacent iterations are equal. If they are equal, calculate the compensation current based on the first and second bias currents of the current iteration. Otherwise, continue to adjust the bias current required by the bias generation circuit according to the sub-DAC current control code and the bias current source selection signal, so that the bias current required by the bias generation circuit of the current iteration increases. Fix the first calibration current control code, adjust the second calibration current control code, and calibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula until the first and second calibration current control codes of adjacent iterations are equal.

[0027] The calibration formula in this embodiment of the invention is as follows: ; in, This represents the output current of the DAC main current source array. This represents the output current of the DAC reference current source. Indicates the first The second calibration current control code during the next iteration. Indicates the first The first calibration current control code during the next iteration. Indicates the first The binary coefficient corresponding to the second calibration current control code in the next iteration. Indicates the first The binary coefficient corresponding to the first calibration current control code in the next iteration. Indicates the first The second bias current generated by the bias generation circuit during the next iteration. Indicates the first The first bias current generated by the bias generation circuit during the next iteration.

[0028] This invention employs a single-unit calibration logic based on variable bias cross-iteration: First bias state comparison: under bias current Below, keep The compensation branch remains unchanged, and is adjusted by the digital control circuit using the SAR algorithm. Adjust the size of the compensation branch until the total current equals the reference current.

[0029] Second bias state comparison: The bias current is proportionally reduced to [value] using a digital control circuit. (For example = 0.25). At this point, the transconductance undergoes a nonlinear change ( This causes a change in the proportional relationship between the two errors. Maintaining the adjusted state under these conditions is crucial. Unchanged, Adjusted The branch current continues until the total current is balanced again.

[0030] Repeat the above two steps alternately, and after several cross-iterations, and The calibration current control code of the branch circuit fully converges, achieving accurate compensation across the entire temperature range.

[0031] Furthermore, such as Figure 4 As shown, in this embodiment of the invention, the DAC main current source array includes 8 parallel LSB units, 7 parallel ISB units, and 31 parallel MSB units; each LSB unit includes 7 parallel MOS transistors; each ISB unit includes 2 parallel ISB sub-units, each ISB sub-unit includes 8 parallel MOS transistors; each MSB unit includes 128 parallel MOS transistors. The DAC reference current source includes 1 LSB ref Unit, 3 parallel MSBs ref Unit; LSB ref The unit consists of 8 parallel MOS transistors; each MSB ref The unit consists of 128 MOS transistors connected in parallel; In this configuration, the gates of all MOSFETs are connected to a global bias voltage. V bias The sources of all MOSFETs are connected to the power supply VDD, and the drains of all MOSFETs serve as the outputs of the corresponding units and sub-units.

[0032] In this embodiment of the invention, the DAC main current source array and the DAC reference current source generate the main current source current and the reference current source current that meet the current ratio requirements based on the global bias voltage and the compensation current, using a bottom-up reference transfer calibration logic. This includes: Based on the global bias voltage, the output current of each of the eight LSB units in the DAC main current source array is calibrated to the LSB in the DAC reference current source. ref The unit's output current; Inject compensation current into the DAC reference current source LSB ref unit; Based on the global bias voltage, the output currents of the 8 LSB cells and the output current of each ISB sub-cell in the 7 ISB cells of the DAC main current source array are calibrated to the LSB in the DAC reference current source. ref The sum of the unit's output current and compensation current; The first MSB in the DAC reference current source is determined based on the global bias voltage. ref Unit (MSB) ref1 The output current of the unit is calibrated to the sum of the output currents of the 7 ISB units and any 2 LSB units in the DAC main current source array; Based on the global bias voltage, the output current of the 31 MSB cells in the DAC main current source array and the third MSB cell in the DAC reference current source are compared. ref Unit (MSB) ref3 The output current of each unit is calibrated to the first MSB of the calibrated DAC reference current source. ref The unit's output current; The calibrated DAC main current source array and DAC reference current source generate the main current source current and reference current source current that meet the current ratio requirements, respectively. Among them, the second MSB in the DAC reference current source ref Unit (MSB) ref2 The output current of the unit remains constant.

[0033] As can be seen, the DAC main current source array of this invention adopts a 16-bit segmented architecture: the lower 8 bits (LSB) are an R-2R network structure, and the middle 3 bits (ISB) and the upper 5 bits (MSB) are a thermometer decoding structure. Ideally, the output current ratio of a single LSB, ISB, and MSB is 1:2:16. To accommodate the "only increasing, never decreasing" unidirectional supplementary calibration mechanism and statistically cover manufacturing deviations, Figure 4 The image shows the asymmetric redundancy matching configuration on the underlying physical layout: LSB array cell: Composed of 7 unit MOS transistors (reduced by 1 unit size compared to the ideal 8, allowing for a 12.5% ​​positive calibration margin). ISB array cell: Divided into 2 independent subarrays based on weights, each subarray consists of 8 MOS transistors. MSB array cell: Due to its large device area and extremely small manufacturing tolerances, it consists directly of 128 MOS transistors. Reference scale: The system's built-in LSB. ref Composed of 8 MOSFETs, MSB ref It consists of 128 MOSFETs.

[0034] This invention simplifies the comparison of the entire DAC main power supply array to only require the transmission of two basic scales, "8" and "128", such as... Figure 5 As shown, the specific bottom-up two-range quantization reference transfer calibration flow is as follows: Bottom pre-alignment: The basic LSB cells (7 MOS) are unidirectionally compensated by a temperature-independent calibration current until they are equal to the preset LSBref (8 MOS).

[0035] Establish a full-temperature anchor point: artificially inject initial-state dual-parameter calibration compensation current into LSBref to construct a full-temperature tracking baseline, for example, by setting its equivalent total current to 8.5 MOS.

[0036] Mid-to-low bit alignment: Each pre-aligned LSB is fed into a comparator and precisely compensated to an equivalent of 8.5 MOS; for each ISB cell, its two 8-MOS sub-cells are sequentially calibrated to 8.5 MOS. After merging, the equivalent current of a complete ISB cell precisely reaches 17 MOS.

[0037] High-level scale transfer and calibration: The preset backup reference MSBref1 (physical 128 MOS) is compensated to an equivalent of 136 MOS (i.e., 128+8) using the low-level calibrated merged current. Then, using this as the high-level scale, all MSB main cells with physical 128 MOS and MSBref3 used for bias callback are compensated to an equivalent of 136 MOS.

[0038] At this point, the equivalent current ratio of the entire array is LSB:ISB:MSB=8.5:17:136, perfectly satisfying the strict ratio of 1:2:16.

[0039] This invention adopts an asymmetric redundant array underlying architecture design, which breaks through the limitation of traditional DACs strictly following binary or thermometer weight symmetric matching. By artificially introducing a size reduction margin of 1 unit MOS transistor (7 MOS transistors) in the underlying physical layout (LSB), it provides a perfect physical anti-collision buffer for subsequent "only increase and no decrease" unidirectional full array calibration.

[0040] This invention innovatively proposes a bottom-up calibration reference transfer strategy, cleverly simplifying the comparison of multi-weighted current sources to comparing only two baseline sizes (approximately the LSB level of 8 MOSFETs and the MSB level of approximately 128 MOSFETs). The entire system requires only one LSB. ref and three MSBs ref This eliminates the need to design complex comparison networks for different weights, significantly reducing the design difficulty of calibration hardware and chip area overhead.

[0041] Furthermore, thanks to the aforementioned bottom-up reference transfer process, this invention only requires the design and use of two current comparators with corresponding ranges, which are responsible for the comparison of approximately 8 MOS levels and approximately 128 MOS levels, respectively. Figure 6 This is a schematic diagram of the circuit structure of the high-precision, wide-range composite load current comparator used in this invention. EN is the enable signal for the current comparator. This is the control clock for the current comparator. Reset the output switch of the current comparator. and For input differential current, and To output the difference comparison results. For example... Figure 6 As shown, to address the challenge of extracting extremely small errors under large background current, a composite dynamic load is used in the output node of the current comparator.

[0042] Amplify phase: Control clock By connecting the diode to both the PMOS array and the cross-coupled PMOS array and turning them on, the two are connected in parallel and present a very large forward impedance, resulting in a very high small-signal transimpedance gain. Latch phase: Control clock Disconnect the diode from the grounding switch of the PMOS array. At this point, the output node is dominated only by the cross-coupled PMOS, exhibiting negative resistance characteristics. This triggers strong positive feedback regeneration, converting the minute current difference into logic high and low levels for high-precision decision-making. After the current comparator output is successfully read by the digital control circuit, turn on... Reset the differential output level.

[0043] Furthermore, the bias generation circuit in this embodiment of the invention is as follows: Figure 7 As shown, it includes switch SW1, switch SW2, and transistor PM. 11 ~Transistor PM 13 , resistor R1, resistor R2, operational amplifier (AP), and sub-DAC module; among which, One end of switch SW1 and one end of switch SW2 are respectively connected to the second MSB in the DAC reference current source. ref Unit, third MSB ref Unit connection: the other end of switch SW1 and one end of switch SW2 are both connected to transistor PM. 11 The source connection, transistor PM 11 The drain and transistor PM 12 The source connection, transistor PM 12 The drain and transistor PM 13 The source connection, transistor PM 13 The drain of transistor PM is connected to the non-inverting input of op-amp AP and one end of resistor R2. 11Gate, transistor PM 12 Gate, transistor PM 13 The gates of each are connected to the corresponding bias voltages. The inverting input of the operational amplifier AP is connected to the output of the sub-DAC module and one end of the resistor R1. The output of the operational amplifier AP serves as the output of the bias generation circuit to generate the global bias voltage. The input of the sub-DAC module is connected to the output of the digital control circuit to generate the sub-DAC current control code. The switching states of switches SW1 and SW2 are controlled by the bias current source selection signal generated by the digital control circuit.

[0044] In this embodiment of the invention, when the bias current source selection switch SW1 is closed and SW2 is open, the bias current required by the bias generation circuit is generated by the second MSB in the DAC reference current source. ref The bias current source is generated by the unit; when the bias current source selection switch SW1 is open and SW2 is closed, the bias current required by the bias generation circuit is generated by the third MSB in the DAC reference current source. ref Unit generation.

[0045] like Figure 7 As shown, the bias generation circuit includes a first branch (current controlled by the sub-DAC module) and a second branch (containing two multiplexed switches and a switchable reference current network). The non-inverting and inverting inputs of the error operational amplifier (AP) are connected to the nodes of the two branches respectively. Its feedback loop forces the currents of the two branches to be equal and outputs a global bias voltage to drive the entire DAC main current source array and the DAC reference current source.

[0046] Calibration phase: Two-way multiplexers (SW1, SW2) connect the second branch to the uncalibrated second MSB. ref The unit (128 MOS) maintains a constant global base bias and simultaneously controls the sub-DAC module to achieve a bias current magnitude through sub-DAC current control codes generated by the digital control circuit. and The ability to switch back and forth between them.

[0047] Post-calibration callback phase: After all calibrations are completed, the two-way multiplexer switches will switch the second branch to the calibrated third MSB. ref The cell (internally containing the equivalent current of 136 MOS). Due to the third MSB ref The unit includes additional calibration current. To maintain the total current of the second branch equal to the output current of the sub-DAC module, the negative feedback loop automatically raises the global bias voltage of the differential op-amp AP output. V biasThis global bias voltage is applied to the gates of the PMOS current sources across the entire array, achieving a proportional reduction in the base current: the actual equivalent output LSB is reduced from 8.5 to 8, the ISB from 17 to 16, and the MSB from 136 to 128. Ultimately, this completely eliminates the artificially high calibration current, pulling the total full-scale current of the DAC back to its initial design value.

[0048] This invention employs a global bias dynamic callback mechanism based on dual-state switching. By introducing a switchable reference module with a pure base state and a calibration fusion state into the bias negative feedback loop, it cleverly utilizes the negative feedback characteristics of the operational amplifier to automatically compress the base bias current of the entire array after calibration, perfectly offsetting the sum of the calibration current injected in the early stage. This completely solves the technical pain points of increased DAC power consumption and full-scale current drift caused by traditional unidirectional calibration.

[0049] It should be noted that the bias generation circuit in this embodiment only illustrates the circuit structure corresponding to the generation of a global bias voltage based on the bias current source selection signal and the sub-DAC current control code. The circuit structures for generating a temperature-dependent first bias current and a temperature-independent second bias current are not illustrated; existing corresponding circuit structures are used, requiring only circuits capable of generating both temperature-dependent and temperature-independent bias currents. Similarly, the digital control circuit, DAC output circuit, and sub-DAC module utilize existing corresponding circuit structures, requiring only that they achieve their respective functions and output the corresponding signals.

[0050] In summary, the full-temperature current-steering DAC calibration circuit that maintains a constant total current proposed in this invention addresses the problems of increased total DAC current and high system design complexity caused by multi-range comparisons resulting from existing calibration techniques. It achieves precise matching and strict alignment of the weight ratios of each current source across the entire temperature range, while maintaining absolute stability of total power consumption while improving system linearity. Specifically, this invention introduces a temperature-dependent and temperature-independent dual-parameter calibration compensation mechanism to completely decouple and compensate for the different effects of temperature drift on threshold voltage and current factor. Combined with a bottom-up reference transfer strategy, it ensures that the equivalent output current of current sources with different weights in the DAC main current source array always perfectly maintains the ideal weight ratio initially calibrated when the ambient temperature changes drastically, fundamentally guaranteeing the DAC's ultra-high linearity across the entire temperature range.

[0051] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0053] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A full-temperature current-rudder DAC calibration circuit that maintains a constant total current, characterized in that, The full-temperature current-rudder DAC calibration circuit includes: The bias generation circuit is used to generate a global bias voltage, a temperature-dependent first bias current, and a temperature-independent second bias current based on the bias current source selection signal and the sub-DAC current control code; wherein, the bias current required by the bias generation circuit is generated by the DAC reference current source. The dual-parameter calibration compensation unit is used to generate a compensation current based on the variable bias cross-iteration single-unit calibration logic according to the temperature-related first calibration current control code, the temperature-independent second calibration current control code, the first bias current, and the second bias current. The DAC main current source array and DAC reference current source are used to generate the main current source current and reference current source current that meet the current ratio requirements based on the global bias voltage and compensation current and the bottom-up reference transfer calibration logic. A current comparator is used to compare the main current source current with the reference current source current. A digital control circuit is used to update the bias current source selection signal, the sub-DAC current control code, the first calibration current control code, and the second calibration current control code based on the comparison result. The DAC output circuit is used to output the main current source current that meets the current ratio requirements after calibration.

2. The full-temperature current-rudder DAC calibration circuit that maintains a constant total current according to claim 1, characterized in that, The dual-parameter calibration and compensation unit includes a temperature-dependent current compensation array, a temperature-independent current compensation array, and a compensation current output circuit; the temperature-dependent current compensation array includes transistor NM. 21 ~Transistor NM 24 The temperature-independent current compensation array includes transistor NM 25 ~Transistor NM 28 The compensation current output circuit includes a transistor PM 21 and PM 22 ;in, transistor NM 21 The drain of the transistor NM 21 Gate, transistor NM 22 The first bias current is generated in the gate and bias generation circuit. I cal_T The output terminal is connected to transistor NM. 22 The drain of the transistor NM 23 drain, transistor NM 24 The source connection of the transistor NM 21 The source of the transistor NM 22 The sources of the transistors are all grounded, NM 23 The gate is connected to the second calibration current control code in the digital control circuit via an inverter. D ZTC The output terminal is connected to transistor NM. 23 The source of the transistor is connected to the power supply VDD. 24 The gate and the second calibration current control code in the digital control circuit D ZTC The output terminal is connected to transistor NM. 24 The drain of the transistor NM 28 drain, transistor PM 21 The drain connection of the transistor NM 25 The drain of the transistor NM 25 Gate, transistor NM 26 A second bias current is generated in the gate and bias generation circuit. I cal_ZCT The output terminal is connected to transistor NM. 26 The drain of the transistor NM 27 drain, transistor NM 28 The source connection of the transistor NM 25 The source of the transistor NM 26 The sources of the transistors are all grounded, NM 27 The gate is connected to the first calibration current control code in the digital control circuit via an inverter. D T The output terminal is connected to transistor NM. 27 The source of the transistor is connected to the power supply VDD. 28 The gate and the first calibration current control code in the digital control circuit D T The output terminal is connected to the transistor PM. 21 The source of the transistor is connected to the power supply VDD. 21 Gate and transistor PM 22 Gate connection, transistor PM 22 The source of the transistor is connected to the power supply VDD. 22 The drain is used as a compensation current. I cal The output terminal.

3. The full-temperature current-rudder DAC calibration circuit that maintains a constant total current according to claim 1, characterized in that, The dual-parameter calibration compensation unit generates a compensation current based on a temperature-dependent first calibration current control code, a temperature-independent second calibration current control code, a first bias current, and a second bias current, using a variable bias cross-iteration single-unit calibration logic. This includes: Fix the first calibration current control code, adjust the second calibration current control code, and calibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula. The bias current required by the bias generation circuit is adjusted according to the sub-DAC current control code and the bias current source selection signal, so that the bias current required by the current iteration bias generation circuit is reduced. Fix the second calibration current control code, adjust the first calibration current control code, and recalibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula. Determine whether the first and second calibration current control codes of adjacent iterations are equal. If they are equal, calculate the compensation current based on the first and second bias currents of the current iteration. Otherwise, continue to adjust the bias current required by the bias generation circuit according to the sub-DAC current control code and the bias current source selection signal, so that the bias current required by the bias generation circuit of the current iteration increases. Fix the first calibration current control code, adjust the second calibration current control code, and calibrate the output current of the DAC main current source array to the output current of the DAC reference current source according to the calibration formula until the first and second calibration current control codes of adjacent iterations are equal.

4. The full-temperature current-rudder DAC calibration circuit that maintains a constant total current according to claim 3, characterized in that, The calibration formula is: ； in, This represents the output current of the DAC main current source array. This represents the output current of the DAC reference current source. Indicates the first The second calibration current control code during the next iteration. Indicates the first The first calibration current control code during the next iteration. Indicates the first The binary coefficient corresponding to the second calibration current control code in the next iteration. Indicates the first The binary coefficient corresponding to the first calibration current control code in the next iteration. Indicates the first The second bias current generated by the bias generation circuit during the next iteration. Indicates the first The first bias current generated by the bias generation circuit during the next iteration.

5. The full-temperature current-rudder DAC calibration circuit that maintains a constant total current according to claim 1, characterized in that, The DAC main current source array includes 8 parallel LSB units, 7 parallel ISB units, and 31 parallel MSB units; each LSB unit includes 7 parallel MOS transistors; each ISB unit includes 2 parallel ISB sub-units, each ISB sub-unit includes 8 parallel MOS transistors; each MSB unit includes 128 parallel MOS transistors. The DAC reference current source includes 1 LSB ref Unit, 3 parallel MSBs ref Unit; LSB ref The unit consists of 8 parallel MOS transistors; each MSB ref The unit consists of 128 MOS transistors connected in parallel; In this configuration, the gates of all MOSFETs are connected to a global bias voltage. V bias The sources of all MOSFETs are connected to the power supply VDD, and the drains of all MOSFETs serve as the outputs of the corresponding units and sub-units.

6. The full-temperature current-rudder DAC calibration circuit that maintains a constant total current according to claim 5, characterized in that, The DAC main current source array and DAC reference current source generate the main current source current and reference current source current that meet the current ratio requirements based on the global bias voltage and compensation current, using a bottom-up reference transfer calibration logic. These include: Based on the global bias voltage, the output current of each of the eight LSB units in the DAC main current source array is calibrated to the LSB in the DAC reference current source. ref The unit's output current; Inject compensation current into the DAC reference current source LSB ref unit; Based on the global bias voltage, the output currents of the 8 LSB cells and the output current of each ISB sub-cell in the 7 ISB cells of the DAC main current source array are calibrated to the LSB in the DAC reference current source. ref The sum of the unit's output current and compensation current; The first MSB in the DAC reference current source is determined based on the global bias voltage. ref The unit's output current is calibrated to the sum of the output currents of the seven ISB units in the DAC main current source array and the output currents of any two LSB units; Based on the global bias voltage, the output current of the 31 MSB cells in the DAC main current source array and the third MSB cell in the DAC reference current source are compared. ref The output current of each unit is calibrated to the first MSB of the calibrated DAC reference current source. ref The unit's output current; The calibrated DAC main current source array and DAC reference current source generate the main current source current and reference current source current that meet the current ratio requirements, respectively. Among them, the second MSB in the DAC reference current source ref The unit's output current remains constant.

7. The full-temperature current-rudder DAC calibration circuit that maintains a constant total current according to claim 6, characterized in that, The bias generation circuit includes switch SW1, switch SW2, and transistor PM. 11 ~Transistor PM 13 , resistor R1, resistor R2, operational amplifier (AP), and sub-DAC module; among which, One end of switch SW1 and one end of switch SW2 are respectively connected to the second MSB in the DAC reference current source. ref Unit, third MSB ref Unit connection: the other end of switch SW1 and one end of switch SW2 are both connected to transistor PM. 11 The source connection, transistor PM 11 The drain and transistor PM 12 The source connection, transistor PM 12 The drain and transistor PM 13 The source connection, transistor PM 13 The drain of transistor PM is connected to the non-inverting input of op-amp AP and one end of resistor R2. 11 Gate, transistor PM 12 Gate, transistor PM 13 The gates of each are connected to the corresponding bias voltages. The inverting input of the operational amplifier AP is connected to the output of the sub-DAC module and one end of the resistor R1. The output of the operational amplifier AP serves as the output of the bias generation circuit to generate the global bias voltage. The input of the sub-DAC module is connected to the output of the digital control circuit to generate the sub-DAC current control code. The switching states of switches SW1 and SW2 are controlled by the bias current source selection signal generated by the digital control circuit.

8. The full-temperature current-rudder DAC calibration circuit that maintains a constant total current according to claim 7, characterized in that, When the bias current source selection switch SW1 is closed and SW2 is open, the bias current required by the bias generation circuit is supplied by the second MSB in the DAC reference current source. ref Unit generation; When the bias current source selection switch SW1 is open and SW2 is closed, the bias current required by the bias generation circuit is supplied by the third MSB of the DAC reference current source. ref Unit generation.

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