Multi-channel signal synchronous acquisition and real-time processing method and system thereof

Abstract

The present application relates to signal acquisition and processing technical field, disclose a kind of multi-channel signal synchronous acquisition and real-time processing method and system thereof, comprising: five steps of constructing clock synchronization network and performing picosecond level delay calibration, multi-channel parallel sampling and adaptive quantization encoding, pipeline parallel data processing and ping-pong buffer relay, channel consistency online calibration and digital compensation, adaptive processing parameter feedback optimization, form double closed-loop collaborative architecture.

Description

Technical Field

[0001] This invention relates to the field of signal acquisition and processing technology, and in particular to a method and system for multi-channel signal synchronous acquisition and real-time processing applicable to multi-channel high-speed synchronous sampling applications such as radar, sonar and bioelectric signal monitoring. Background Technology

[0002] With the ever-increasing demands for signal processing performance in fields such as radar detection, sonar imaging, and bioelectrical signal monitoring, the design of multi-channel synchronous signal acquisition systems faces increasingly stringent technical challenges. In typical applications such as phased array radar signal processing, multi-lead ECG or EEG signal monitoring, and underwater acoustic array beamforming, the system needs to simultaneously sample dozens or even hundreds of analog signals at high speed and complete backend digital signal processing within an extremely short time to meet the dual constraints of real-time performance and high accuracy. However, existing multi-channel acquisition schemes have significant shortcomings in both inter-channel synchronization accuracy and backend processing throughput, becoming a core bottleneck restricting the overall performance improvement of the system.

[0003] Regarding inter-channel synchronization performance, traditional multi-channel acquisition schemes mostly employ a discrete analog-to-digital converter (ADC) architecture. This involves configuring an independent ADC chip for each acquisition channel and attempting to achieve sampling synchronization between channels by sharing a reference clock. However, due to unavoidable manufacturing differences in printed circuit board trace length, clock signal transmission path impedance characteristics, and internal aperture delay of the ADC chip, this discrete approach struggles to control the sampling timing deviation between channels to a sufficiently small level. In practical engineering, when the sampling frequency reaches 100 MSPS or higher, even inter-channel delay inconsistencies on the order of hundreds of picoseconds can lead to serious problems such as beam pointing errors and spectral leakage in array signal processing.

[0004] Chinese patent CN110557121A discloses a method for synchronous calibration of multi-channel high-speed sampling data based on FPGA. The core idea of ​​this method is to establish a first-in-first-out buffer at the back end of the analog-to-digital converter of each channel, and to detect the position deviation of the rising edge of the signal in the buffer by inputting a synchronous calibration test signal to each channel. Then, the sampling time difference between channels is compensated by adjusting the depth of the buffer of each channel. While this method addresses the issue of data alignment between multiple channels to some extent, it still has the following limitations: First, it only achieves data-level synchronization alignment by adjusting the buffer depth, without addressing the sampling time deviation of each channel at the clock source. Its calibration accuracy is limited by the discrete length of the sampling clock period, making it difficult to achieve picosecond-level synchronization accuracy. Second, this method only calibrates the time deviation between channels, without addressing the gain mismatch and phase mismatch issues between channels. These inconsistencies between channels will also significantly reduce the effective resolution of the system in high-frequency signal acquisition. Third, this method is a foreground calibration scheme, requiring the injection of calibration signals and the pausing of normal data reception during the system hard-start phase. It cannot track and compensate for the gradual changes in channel characteristics caused by temperature drift or device aging in real time during system operation.

[0005] Regarding back-end digital signal processing capabilities, existing solutions also exhibit significant limitations. Traditional solutions typically employ digital signal processors (DSPs) or general-purpose processors as the back-end computing core. However, these processors are essentially serial instruction execution architectures, resulting in severely insufficient throughput when faced with multi-channel, high-speed data streams. While some solutions introduce field-programmable gate arrays (FPGAs) as auxiliary acceleration devices, they are mostly used only for simple data buffering and format conversion, failing to fully leverage their hardware parallel processing advantages to build a complete multi-channel signal processing pipeline. Furthermore, existing solutions lack effective coordination mechanisms between the acquisition front-end and back-end processing. Processing results cannot be fed back to the acquisition front-end in real time to optimize sampling parameters, limiting the system to fixed operating modes and hindering its adaptability to complex and variable signal environments.

[0006] In summary, there is an urgent need for a multi-channel signal synchronous acquisition and real-time processing solution that can guarantee picosecond-level inter-channel synchronization accuracy from the clock source, while possessing high-throughput parallel signal processing capabilities and an online closed-loop calibration mechanism. Especially in multi-lead physiological signal monitoring scenarios, even slight time deviations between lead channels directly affect the morphological feature extraction of electrocardiogram waveforms and the accuracy of automatic arrhythmia detection. Therefore, the requirement for inter-channel synchronization accuracy has been tightened from the nanosecond level to the hundreds of picosecond level. Similarly, in underwater acoustic array beamforming applications, the gain and phase consistency between array element channels directly determine key indicators such as the main lobe width and sidelobe level. Any inconsistency between channels will lead to beam pattern distortion and an increase in the false alarm rate of target detection. These practical application requirements place comprehensive performance demands on multi-channel synchronous acquisition systems, including both hardware-level synchronization accuracy assurance and software-level real-time processing capabilities and adaptive optimization mechanisms. Existing technical solutions cannot simultaneously meet these multi-dimensional performance requirements. Summary of the Invention

[0007] To address the technical problems existing in the prior art, this invention provides a method and system for multi-channel signal synchronous acquisition and real-time processing. Through the collaborative design of clock synchronization network and pipeline parallel processing, it achieves picosecond-level inter-channel synchronization accuracy and microsecond-level signal processing delay, effectively solving the shortcomings of existing solutions in terms of inter-channel synchronization accuracy and back-end processing throughput.

[0008] To achieve the above objectives, the present invention provides a method for multi-channel signal synchronous acquisition and real-time processing, comprising the following steps: Step S1, constructing a clock synchronization network and performing picosecond-level delay calibration: based on a low-jitter reference clock source, a clock distribution network distributes the same sampling clock signal to each acquisition channel, and applies precise delay compensation to the clock transmission path of each channel to bring the sampling time deviation of each channel to within a preset synchronization accuracy threshold; Step S2, performing multi-channel parallel sampling and adaptive quantization encoding: driven by the clock synchronization network, each channel's high-speed analog-to-digital converter performs parallel sampling of the analog input signal based on the synchronous clock edge and adaptively adjusts the quantization gain parameter; Step S3, performing pipelined parallel data processing and ping-pong buffer relay: the data from each channel is processed in parallel... The digital sampling sequence is input into a multi-stage pipeline processing architecture, which sequentially performs digital down-conversion and multi-stage decimation filtering. Then, the baseband signal output from the multi-stage decimation filtering is subjected to parallel spectrum transformation analysis and adaptive filtering. Adjacent pipeline stages achieve seamless data relay transmission through a ping-pong buffer mechanism. Step S4: Perform online channel consistency calibration and digital compensation: periodically inject calibration reference signals into each channel, estimate the gain mismatch parameters and phase mismatch parameters of each channel in real time, and apply digital compensation. At the same time, the mismatch parameters are fed back to the clock synchronization network of step S1 to dynamically correct the delay compensation amount. Step S5: Perform adaptive processing parameter feedback optimization: perform inter-channel consistency evaluation on the output data of each channel after compensation, and adaptively adjust the processing parameters of each stage of the pipeline accordingly.

[0009] Another aspect of the present invention provides a multi-channel signal synchronous acquisition and real-time processing system, comprising: a clock synchronization network construction and picosecond-level delay calibration module for distributing homogeneous sampling clocks to each channel and applying precise delay compensation; a multi-channel parallel sampling and adaptive quantization encoding module for performing parallel sampling and adaptive quantization on analog signals of each channel; a pipelined parallel data processing and ping-pong buffer relay module for performing multi-stage pipelined processing on digital sequences of each channel; a channel consistency online calibration and digital compensation module for estimating and compensating mismatch parameters of each channel online and feeding the mismatch parameters back to the clock synchronization network; and an adaptive processing parameter feedback optimization module for evaluating inter-channel consistency and adaptively adjusting pipeline processing parameters.

[0010] Compared with existing technologies, the beneficial effects of this invention are as follows: First, through the collaborative design of a low-jitter clock distribution network and a programmable delay chain, the synchronization accuracy between channels is controlled within 100ps from the clock source, which is at least an order of magnitude higher than the existing technology that relies solely on buffer depth adjustment. Second, a complete pipelined processing architecture integrating digital downconversion, decimation filtering, spectrum analysis, and adaptive filtering is constructed based on a field-programmable gate array (FPGA). Combined with a ping-pong buffer relay mechanism, the signal processing delay is controlled at the microsecond level, meeting the requirements of demanding real-time scenarios such as phased array radar. Third, an online calibration closed-loop mechanism is introduced, which can continuously estimate and compensate for gain mismatch and phase mismatch of each channel during normal system operation, avoiding the defect of traditional front-end calibration schemes that require pausing data reception. Fourth, steps S4 and S5 provide feedback information to steps S1 and S3, respectively, forming a dual closed-loop optimization mechanism, giving the system the ability to adaptively adjust to environmental changes. Attached Figure Description

[0011] Figure 1 This is a flowchart of the multi-channel signal synchronous acquisition and real-time processing method of the present invention.

[0012] Figure 2 This is an architecture diagram of the multi-channel signal synchronous acquisition and real-time processing system of the present invention. Detailed Implementation

[0013] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0014] like Figure 1 As shown, an embodiment of the present invention provides a multi-channel signal synchronous acquisition and real-time processing method comprising the following five core steps, forming a deeply coupled closed-loop collaborative architecture: the clock synchronization output of step S1 provides a unified time base for the parallel sampling of step S2; the digital sampling sequence of step S2 is directly fed into the pipelined processing architecture of step S3; the calibration compensation result of step S4 is fed back to step S1 to correct the clock delay parameters; and the optimization result of step S5 is fed back to step S3 to dynamically adjust the processing parameters. This dual closed-loop structure combining feedforward driving and feedback correction results in a synergistic effect between the steps that far exceeds that of simple superposition.

[0015] Step S1: Construct a clock synchronization network and perform picosecond-level delay calibration. The clock synchronization network design of this invention begins with the selection of a reference clock source. The system selects an ultra-low noise crystal oscillator with a root mean square jitter of no more than 0.5 ps as the global reference clock source. Preferably, in a specific embodiment, a 100 MHz oven-controlled crystal oscillator is selected. This oscillator can maintain a phase noise performance better than -155 dBc / Hz@1 kHz offset frequency within an industrial temperature range of -40℃ to +85℃. The output signal of the reference clock source is output via a differential low-voltage positive emitter coupled logic interface to suppress the impact of common-mode noise on the integrity of the clock signal.

[0016] The topology design of the clock distribution network is a key step in achieving multi-channel synchronous sampling. This invention employs a tree-shaped fan-out topology to achieve multi-path distribution of clock signals. Preferably, in this embodiment, a dedicated low-jitter clock distribution chip is used as the distribution node of the tree topology. This chip has a built-in phase-locked loop circuit, which can multiply the input reference clock to the required sampling frequency, while simultaneously filtering and shaping the jitter of the input clock during the frequency multiplication process. In a typical 8-channel acquisition configuration, the reference clock signal first enters the first-level distribution node, is multiplied by the phase-locked loop to a sampling frequency of 200MHz, and then fans out as two differential clock signals. Each differential clock signal then enters the second-level distribution node, each fanning out as four differential clock signals, ultimately forming eight homogeneous sampling clocks, which drive eight high-speed analog-to-digital converters. The printed circuit board traces of each branch path in the tree topology adopt an equal-length matching design, with the trace length difference controlled within 0.5mm, and the corresponding transmission delay difference not exceeding 3.3ps.

[0017] To further eliminate residual clock skew caused by PCB manufacturing tolerances and device packaging differences, this invention sets a programmable delay chain at the clock input of each acquisition channel. Preferably, the programmable delay chain is implemented using input / output delay elements within a field-programmable gate array (FPGA), which have an adjustment step size of 5ps to 20ps and an adjustment range of 0ps to 500ps. During system initialization, the delay calibration process is performed as follows: First, a square wave calibration signal with a frequency of 1 / 10 of the sampling frequency is simultaneously input to the analog-to-digital converters of all channels; then, the sampling time deviation between any two channels is calculated by precisely timing the rising edge position of the square waves sampled from each channel. The estimation of the sampling time deviation uses a high-precision delay estimation algorithm based on cross-correlation, and its calculation formula is: ,in, For the first Channel and the The estimated time delay deviation between channels, in units of sampling periods, has a range of values ​​of [value range missing]. , The sampling period; and The first Channel and the Discrete sampling sequence of the channel, For sampling point index, This represents the total number of sampling points participating in the cross-correlation operation, ranging from 1024 to 4096. The larger the value, the higher the accuracy of the time delay estimation. The search term is the time delay variable. The peak position of this normalized cross-correlation operation corresponds to the optimal time delay estimate between the two channels. The theoretical estimation accuracy can reach less than 1 / 100 of the sampling period, that is, when the sampling frequency is 200MHz, the theoretical accuracy can reach less than 50ps.

[0018] After obtaining the estimated delay deviation between channels, the system uses the channel with the smallest delay deviation as the reference channel and sequentially adjusts the programmable delay chains of the other channels to align with the reference channel. Preferably, the delay calibration adopts a step-by-step approximation strategy: first, coarse adjustment is performed with the maximum adjustment step size to reduce the deviation between channels to within 50 ps; then, fine adjustment is performed with the minimum adjustment step size until the deviation between channels converges to within a preset synchronization accuracy threshold. In a preferred embodiment, the preset synchronization accuracy threshold is set to 50 ps, ​​and the measured synchronization accuracy between channels after calibration can reach 30 ps to 50 ps.

[0019] It is worth noting that the clock synchronization network established in step S1 not only performs a one-time calibration during system initialization but also receives feedback information from step S4 during normal system operation. When step S4 detects that the phase mismatch parameter of a certain channel exceeds a preset threshold, it sends the delay correction amount of that channel to the programmable delay chain control register in step S1, realizing online fine-tuning of the clock delay and effectively compensating for clock offsets caused by temperature drift or device aging. This feedback mechanism enables the clock synchronization accuracy to remain stable throughout the entire system lifecycle, a technical effect that the one-time front-end calibration scheme in CN110557121A cannot achieve.

[0020] Step S2: Perform multi-channel parallel sampling and adaptive quantization encoding. Driven by the same sampling clock provided by the clock synchronization network constructed in step S1, the high-speed analog-to-digital converters (ADCs) of each channel synchronously perform analog-to-digital conversion operations. The sampling rate of each high-speed ADC is not less than 100 MSPS, and the quantization accuracy is not less than 14 bits. Preferably, in this embodiment, the ADCs of each channel are high-speed pipelined ADC chips with a sampling rate of 200 MSPS and a quantization accuracy of 16 bits. Each ADC uses the rising edge of the same differential sampling clock output in step S1 as the sampling trigger reference, and performs one sample-and-hold and quantization encoding operation on the analog signal input to its respective channel within each sampling clock cycle. After quantization encoding, the analog signal of each channel is converted into a 16-bit wide digital sampling sequence, and the output rate of the digital sampling sequence of each channel is the same as the sampling clock frequency, i.e., 200 MSPS.

[0021] This invention introduces an adaptive quantization gain adjustment mechanism based on parallel sampling to address real-world scenarios where the dynamic range of input signals from different channels varies significantly. In phased array radar receiving applications, the amplitude of the echo signal received by each array element channel may differ by more than 20 dB due to factors such as target distance, scattering cross-section, and array element position. If all channels use a fixed quantization gain setting, some channels may experience overflow saturation, while other channels may only utilize the lower bit range of the quantization range, resulting in a significant reduction in the effective quantization bit depth.

[0022] To address the aforementioned issues, this invention incorporates a programmable gain amplifier at the front end of the analog-to-digital converter in each acquisition channel. The gain adjustment range of the programmable gain amplifier is -6dB to +18dB, with an adjustment step not exceeding 0.5dB. The specific execution method of adaptive quantization gain adjustment is as follows: First, within each adjustment cycle, the system statistically analyzes the percentage of sampling points in the digital sampling sequence of each channel whose amplitude exceeds 85% of the full-scale range, denoted as the overload rate. Simultaneously, the root mean square amplitude of the sampling sequences for each channel is calculated. With full-scale amplitude The ratio between them is denoted as utilization rate. When the overload rate of a certain channel Exceeding the overload rate threshold When this happens, the system automatically reduces the gain value of the programmable gain amplifier for that channel by a certain amount. When the utilization rate of a certain channel Below the utilization lower limit threshold When this happens, the system automatically increases the gain value of that channel by an amount equal to [value missing]. .in The value range is from 0.001 to 0.01, with a preferred value of 0.005; The value ranges from 0.1 to 0.3, with a preferred value of 0.2; and The values ​​range from 0.5dB to 3dB, with a preferred value of 1dB. The gain adjustment period is from 1ms to 10ms. Within this period, the system uses approximately 200,000 to 2,000,000 sampling points to estimate the statistic, thus obtaining sufficient statistical reliability.

[0023] To ensure smooth convergence of the gain adjustment process and avoid gain oscillations, this invention further introduces a gain smoothing strategy based on an exponentially weighted moving average. Specifically, the actual gain setpoint applied to the programmable gain amplifier... Instead of directly using the calculated value of the current adjustment period, it uses a smoothed value obtained by exponentially weighting and smoothing the historical gain values. The update formula is as follows: ,in, For the first The actual gain setting value for each adjustment cycle, in dB; For the first The target gain value, in dB, is calculated based on the overload rate and utilization rate for each adjustment cycle. The actual gain setting value for the previous adjustment cycle; This is a smoothing factor, with a value ranging from 0.05 to 0.3, and a preferred value of 0.1. A smaller value results in a smoother gain change but a slower response time. Through the above adaptive quantization gain adjustment, the effective quantization bit depth of each channel can be maintained within the range of 13.5 bits to 15.5 bits, which is 2 to 3 bits more dynamic margin compared to the fixed gain scheme.

[0024] After each channel completes analog-to-digital conversion, the digital sampling sequence is output to the field-programmable gate array (FPGA) via a dual data rate differential signal interface. Preferably, in this embodiment, a low-voltage differential signal interface is used between the analog-to-digital converter and the FPGA. Each channel has a data bit width of 16 bits, employs a double data rate transmission mode, has a physical clock frequency of 100MHz, and a data throughput rate of 200MSPS × 16bit = 3.2Gbps. Internally, the FPGA uses an input serial-to-parallel conversion module and a cross-clock domain synchronization module to convert the high-speed serial data of each channel into a parallel data stream synchronized with the internal processing clock, providing uniformly formatted input data for the pipelined processing in subsequent step S3.

[0025] Step S3: Execute pipelined parallel data processing and ping-pong buffer relay. Step S3 is the core step in achieving high-throughput real-time signal processing in this invention. This step constructs a complete multi-stage pipelined parallel data processing architecture within the field-programmable gate array (FPGA). This architecture includes a digital down-conversion stage and a multi-stage decimation filtering stage connected in series, as well as a spectrum transformation analysis stage and an adaptive filtering stage located in parallel after the multi-stage decimation filtering stage. The output of the digital down-conversion stage is fed into the multi-stage decimation filtering stage, and the baseband signal output from the multi-stage decimation filtering stage is then fed into the two parallel branches of the spectrum transformation analysis stage and the adaptive filtering stage, respectively. Adjacent processing stages with data transmission relationships achieve seamless data relay through a ping-pong buffer mechanism, ensuring that each processing stage is in working condition at any given time and that the pipeline does not stop due to data waiting.

[0026] The first stage of the pipeline is a digital down-conversion module. In applications such as radar and sonar, the sampled digital signal is usually located in the intermediate frequency band, requiring digital down-conversion to shift the signal components of interest to the baseband for subsequent processing. The digital down-conversion is implemented by generating a configurable digital local oscillator signal within a field-programmable gate array (FPGA). This digital local oscillator signal is then multiplied by complex numbers with the input sampling sequences of each channel to obtain the mixed in-phase and quadrature components. Preferably, the digital local oscillator signal is generated by a direct digital frequency synthesizer (DDS) with a frequency resolution of [insert frequency resolution here]. ,in The sampling frequency is 200MHz. The phase accumulator has a bit width of 32 bits, resulting in a frequency resolution of approximately 0.047 Hz. The center frequency of the digital local oscillator is set according to the carrier frequency of the received signal, with an adjustment range of 0 Hz to... The sine and cosine coefficients in complex multiplication operations are obtained through a lookup table with a depth of 4096 points. The phase quantization bit width is 16 bits, and the amplitude quantization bit width is 18 bits, ensuring that the spurious-free dynamic range of the digital local oscillator is better than 100dB.

[0027] The second stage of the pipeline is a multi-stage decimation filtering module. The bandwidth of the signal after digital down-conversion to baseband is typically much less than half the sampling frequency; therefore, decimation is necessary to reduce the data rate and alleviate the computational burden on subsequent processing stages. This invention employs a multi-stage decimation structure combining cascaded integrator-comb filters and half-band filters. Preferably, in one specific embodiment, the total decimation factor is between 8 and 256 times, preferably designed to be 64 times, achieved by cascading three stages of integrator-comb filters and three stages of half-band filters. The first-stage cascaded integrator-comb filter has an order of 4, a differential delay of 1, and a decimation factor of 8, performing coarse decimation and anti-aliasing filtering. The second-stage half-band filter has an order of 23 and a decimation factor of 2, further suppressing out-of-band noise. The parameters of the third and fourth-stage half-band filters are similar to those of the second stage, each performing a 2x decimation. The fifth-stage half-band filter has an order of 47 and a decimation factor of 2, providing higher stopband attenuation to meet the spectral purity requirements of the final output. After a 64x decimation, the data rate of each channel is reduced from 200 MSPS to approximately 3.125 MSPS, while the signal-to-noise ratio of the passband signal is improved by approximately 9dB due to the oversampling gain.

[0028] The third stage of the pipeline is the spectrum transformation and analysis module. This stage works in parallel with the fourth-stage adaptive filtering module, and both receive the baseband signal output from the second-stage multi-stage decimation filtering module as their input signal. This stage employs a radix-2 Fast Fourier Transform (FFT) algorithm based on butterfly operations to transform the time-domain signal to the frequency domain for spectrum analysis. The number of transformation points in the FFT ranges from 1024 to 8192, preferably set to 4096, corresponding to a frequency resolution of [missing information]. ,in The extracted data rate is 3.125MHz. With 4096 transformation points, the frequency resolution is approximately 763 Hz. The Fast Fourier Transform (FFT) is implemented pipelined within a Field Programmable Gate Array (FPGA). Each butterfly operation has a delay of 2 clock cycles, resulting in a total delay of 24 clock cycles for 12 butterfly operations. Before the data is input to the FFT module, a Hanning window is applied to the time-domain sequence to suppress spectral leakage. The output of the spectral transform is the complex frequency domain coefficients at 4096 frequency points, from which the power spectral density is further calculated. : ,in, For the first Power spectral density values ​​at each frequency point, in units of ; For the first The Fast Fourier Transform of each frequency point outputs complex coefficients; The number of transformation points is 4096; The power normalization factor for the window function is given by the Hanning window. The power spectral density is used in two ways: firstly, to evaluate the signal-to-noise ratio performance of each channel in subsequent step S5; and secondly, to feed back to the fourth-stage adaptive filtering module for dynamically adjusting its step size factor.

[0029] The fourth stage of the pipeline is an adaptive filtering module. This stage performs adaptive noise cancellation and interference suppression processing on the decimated and filtered baseband signal. This stage is set up in parallel with the third-stage spectrum transformation and analysis module, and both receive the same input signal, which is the baseband signal output from the second-stage multi-stage decimation filtering module. Preferably, the adaptive filter adopts an adaptive filtering algorithm based on the normalized minimum mean square error criterion, and its weight coefficient update formula is: ,in, For the first The filter weight coefficient vector of the next iteration has dimension . , The filter order is denoted by 128, and its value ranges from 32 to 256. For the first The input signal vector for the next iteration has the same dimension as the weight coefficient vector; For the first The error signal of the next iteration is defined as the difference between the expected output and the actual output; This is the step size factor, with a value ranging from 0.001 to 0.1, and a preferred value of 0.01. Here is the regularization constant, and its value is [value]. to This is used to prevent numerical instability caused by a denominator of zero; The energy of the input signal vector serves as a normalization factor to ensure that the algorithm's convergence speed is unaffected by changes in input signal power. Building upon this, this stage further dynamically adjusts the step size factor based on the power spectral density output by the third-stage spectrum transform analysis module: when the power spectral density indicates an increase in the input signal's in-band power, the step size factor is decreased to suppress steady-state misalignment; conversely, when the in-band power decreases, the step size factor is increased to accelerate convergence. This ensures that the adaptive filtering maintains a balance between convergence speed and steady-state accuracy under varying input signal power conditions.

[0030] In the aforementioned pipelined processing architecture, dual buffers are configured between the digital downconversion stage and the multi-stage decimation filtering stage, and between the two parallel branches—the multi-stage decimation filtering stage and the spectrum transformation analysis stage, and the multi-stage decimation filtering stage and the adaptive filtering stage—to achieve ping-pong buffer relay. Taking any pair of adjacent processing stages with data transfer relationships as an example, in the first... Level and First Two first-in-first-out (FIFO) buffers of equal capacity are set between levels, denoted as buffer A and buffer B respectively. Within any frame processing cycle, the first... The first stage writes its processing result to buffer A, while the second stage... The first level reads the previous frame's data from buffer B for processing; once the frame is processed, the read and write roles of buffer A and buffer B are switched, i.e., the second level reads the previous frame's data from buffer B for processing. The first level is changed to write to buffer B, while the second level... The stage then reads data from buffer A. This alternating read / write mechanism ensures seamless data transfer between pipeline stages, eliminating pipeline pauses caused by read / write conflicts or data waiting. The depth of each buffer is 1 to 2 times the length of a single frame of data, preferably 1.5 times, i.e., a depth of 4096 × 1.5 = 6144 data points, to provide sufficient buffer margin. Buffer switching is triggered by the frame synchronization signal, with a switching delay not exceeding one sampling clock cycle. The end-to-end processing latency of the entire pipeline architecture does not exceed 10 μs, preferably not exceeding 8 μs, meeting the stringent microsecond-level latency requirements of phased array radar signal processing.

[0031] Step S4: Perform online calibration and digital compensation for channel consistency. Step S4 is a key step in ensuring the long-term stable operation of the multi-channel system. Unlike the scheme in CN110557121A, which only performs a one-time calibration at system startup, step S4 of this invention performs online calibration continuously and periodically during normal system operation. This allows for real-time tracking and compensation for gradual changes in the characteristics of each channel caused by factors such as temperature variations, device aging, and power supply voltage fluctuations.

[0032] The design of the calibration reference signal is fundamental to the accuracy of online calibration. Preferably, in this embodiment, a single-frequency sine wave signal is used as the calibration reference signal. The frequency of this signal is set to a specific non-harmonic frequency point of the sampling frequency, specifically a value... ,in If the sampling frequency is 200MHz, then The purpose of selecting non-harmonic frequencies is to avoid the calibration signal falling on the frequency grid of the Fast Fourier Transform and thus aliasing with the spectral characteristics of the normal signal, thereby achieving frequency domain separation between the calibration signal and the normal signal. The amplitude of the calibration reference signal is set to 50% of the full-scale range of the analog-to-digital converter to ensure that the signal has a sufficient signal-to-noise ratio while avoiding trigger overflow.

[0033] The calibration reference signal is injected using a time-division multiplexing mechanism. The system simultaneously injects the calibration reference signal into each channel at periodic intervals ranging from 100ms to 1000ms, with each injection lasting from 10μs to 100μs. During the injection period, the analog-to-digital converters of each channel sample the calibration reference signal, and the system extracts the frequency domain response of each channel's sampled sequence at the calibration frequency to calculate the gain and phase parameters of each channel. Specifically, a discrete Fourier transform is performed on the data acquired by each channel during the calibration injection period, and the frequency is extracted to... Frequency domain complex coefficients subscript Indicates the channel index. Gain mismatch parameters for each channel. and phase mismatch parameters The calculation formulas are as follows: , , in, For the first The gain mismatch parameter of a channel, in dB, represents the gain deviation of the channel relative to the reference channel. For the first The phase mismatch parameter of a channel, in radians, represents the phase deviation of the channel relative to the reference channel. and The first The amplitude and phase response of the channel at the calibration frequency; and These represent the amplitude and phase responses of the reference channel at the calibration frequency, respectively. The reference channel was selected as the one with the smallest gain and phase mismatch during initial calibration.

[0034] After obtaining the gain mismatch and phase mismatch parameters for each channel, the system applies digital compensation to the processed data of each channel output in step S3. Gain compensation is achieved by multiplying the data of each channel by a gain correction factor. To achieve this, in which This is the linear value corresponding to the reciprocal of the gain mismatch parameter for each channel. Phase compensation is achieved by applying a phase rotation to the data of each channel, with the rotation amount being... Specifically, this is achieved by multiplying the complex data of each channel by a phase rotation factor. After gain compensation and phase compensation, the gain consistency between channels can be controlled within 0.1dB, and the phase consistency can be controlled within 1°.

[0035] More importantly, after completing the digital compensation for this channel, step S4 also feeds back the mismatch parameter information of each channel to the clock synchronization network of step S1. Specifically, when the phase mismatch parameter of a certain channel... After three consecutive calibration cycles, the phase offset exceeded the preset threshold. When the value is preferably 5°, the system determines that the clock path of the channel has slowly drifted, and then converts the phase offset into an equivalent clock delay offset. and will The correction increment is sent to the programmable delay chain control register of the corresponding channel in step S1 to achieve online fine-tuning of the clock delay. This feedback path from step S4 to step S1 constitutes the first closed-loop path of the present invention, ensuring that the synchronization accuracy between channels of the system does not gradually deteriorate due to long-term operation.

[0036] Furthermore, to avoid interference from the calibration reference signal to normal signal processing, the system synchronously records the injection timestamp and duration during the calibration injection, and marks the data of this period as calibration data in the pipeline processing of step S3. The pipeline processing module automatically removes the marked calibration data when outputting the results to ensure the continuity and integrity of normal signal processing. Preferably, the calibration injection period is set to 500ms, and the duration of a single injection is 50μs, so the proportion of calibration data is only 0.01%, and its impact on normal signal processing is negligible.

[0037] Step S5: Perform adaptive processing parameter feedback optimization. Step S5 is the top-level optimization step of the closed-loop collaborative architecture of this invention. It is responsible for performing a global performance evaluation of the output data of each channel after compensation in step S4, and adaptively adjusting the processing parameters of each stage of the pipeline in step S3 accordingly, forming the second closed-loop path of this invention. This step enables the system to automatically optimize its processing strategy according to changes in the actual signal environment, rather than always operating in a fixed parameter mode.

[0038] Inter-channel consistency assessment is the primary task of step S5. The system extracts two types of core evaluation metrics from the output data of each channel after compensation in step S4. The first type of metric is the signal-to-noise ratio (SNR) of each channel. The calculation method is as follows: using the power spectral density output from the spectrum transformation analysis stage in step S3, take the logarithm (base 10) of the ratio of the total power in the signal band to the total power in the noise band, and multiply by 10 to obtain the signal-to-noise ratio (SNR) value in dB. The second type of index is the inter-channel correlation index, specifically expressed as the correlation between any two channels... and Normalized cross-correlation coefficients between The calculation formula is as follows: ,in, For the first Channel and the The normalized cross-correlation coefficient between channels has a range of values. The closer the absolute value is to 1, the better the consistency between the two channels. and The first Channel and the The output data sequence of the channel after compensation in step S4; The number of data points participating in the cross-correlation calculation ranges from 4096 to 65536. This serves as an index for data points. In an ideal, perfectly consistent multichannel system, the cross-correlation coefficient between any two channels receiving the same signal should approach 1.

[0039] Based on the two types of evaluation metrics mentioned above, step S5 performs adaptive adjustment of the processing parameters according to the following strategy. First, regarding the signal-to-noise ratio (SNR) metric, when the signal-to-noise ratio of a certain channel... Below the minimum signal-to-noise ratio threshold set by the system When the preferred value is 60dB, the system automatically adjusts the order and step size factor of the adaptive filter for that channel in step S3: increasing the filter order from the current value to 1.5 times the current value (rounded up to the nearest power of 2), and simultaneously adjusting the step size factor. Reduce it to half of the current value to enhance noise suppression. Accordingly, when consistently higher At this time, the system appropriately reduces the filter order and increases the step size factor to reduce computational resource consumption and improve the algorithm tracking speed.

[0040] Secondly, regarding the inter-channel correlation index, when the cross-correlation number between any two channels... Below the preset consistency threshold When the value is preferably 0.98, step S5 determines that the consistency between the channel pairs does not meet the requirements, triggering the following parameter optimization actions: re-evaluate whether the local oscillator frequency of the digital down-conversion module in step S3 is accurately aligned with the signal carrier frequency; if there is a deviation, automatically fine-tune the local oscillator frequency setting; check whether the passband boundary frequency of the decimation filter module completely covers the effective signal bandwidth; if some signals are truncated, appropriately widen the filter passband. Preferably, the automatic fine-tuning step size of the local oscillator frequency is the frequency resolution. The minimum adjustment unit is an integer multiple of 0.047Hz.

[0041] In addition, step S5 performs trend analysis of global performance indicators. The system records the changing trends of the signal-to-noise ratio and inter-channel correlation of each channel over the most recent 100 evaluation periods using a sliding window method. When a certain indicator is detected to show a continuous downward trend (lower than the previous period for 10 consecutive evaluation periods), the system triggers an early warning mechanism and actively initiates a more aggressive parameter optimization strategy, including increasing the adjustment range of the adaptive filter order and shortening the injection period of the calibration reference signal in step S4. Preferably, the evaluation period is set to 10ms to 100ms, with a preferred value of 50ms.

[0042] After step S5 completes the parameter optimization calculation, the optimized processing parameters are synchronously updated to the pipeline processing modules of each channel in step S3 via the control register interface. Parameter updates are performed atomically, meaning all parameters are updated uniformly during the ping-pong buffer switching interval after the current frame data processing is completed, avoiding data discontinuity caused by parameter changes during frame processing. Through this feedback path from step S5 to step S3, the system's signal processing performance can continuously and adaptively optimize according to changes in the actual signal environment, achieving a leap from fixed parameter processing to adaptive intelligent processing.

[0043] In summary, the method of this invention, through feedforward data flow driving in steps S1→S2→S3 and dual closed-loop feedback optimization in steps S4→S1 and S5→S3, achieves performance indicators far exceeding those of existing technologies in both multi-channel signal synchronous acquisition and real-time processing. The deep coupling between steps ensures that performance improvements in any step benefit other steps through the closed-loop feedback mechanism, resulting in a significant synergistic effect where 1+1>2.

[0044] like Figure 2 As shown, another embodiment of the present invention provides a multi-channel signal synchronous acquisition and real-time processing system, which corresponds one-to-one with each step in the above method embodiment and includes the following five functional modules.

[0045] The clock synchronization network construction and picosecond-level delay calibration module corresponds to step S1 in the method embodiment. At the hardware level, this module includes an ultra-low noise oven-controlled crystal oscillator as a global reference clock source, a tree-shaped clock distribution network composed of one or more dedicated low-jitter clock distribution chips, and a programmable delay chain located at the clock input of each acquisition channel. Preferably, the oven-controlled crystal oscillator has a frequency of 100MHz and a root mean square jitter of no more than 0.5ps. The clock distribution chip has a built-in phase-locked loop circuit, which can multiply the reference clock to a sampling frequency of 200MHz and fan out multiple co-source differential clocks. The programmable delay chain is integrated into the input / output delay elements within the field-programmable gate array (FPGA) chip, with an adjustment step size of 5ps to 20ps and an adjustment range of 0ps to 500ps. The control logic of this module is implemented within the FPGA, responsible for executing the cross-correlation-based delay estimation and successive approximation calibration algorithm as described in step S1 of the method embodiment, and receiving feedback information from the channel consistency online calibration and digital compensation module to achieve online fine-tuning of the delay parameters.

[0046] The multi-channel parallel sampling and adaptive quantization encoding module corresponds to step S2 in the method embodiment. At the hardware level, this module includes multiple high-speed pipelined analog-to-digital converter (ADC) chips and programmable gain amplifiers (PGA) located at the front end of each channel. Preferably, each channel uses an ADC chip with a sampling rate of 200 MSPS and a quantization accuracy of 16 bits, and is configured with a PGA with a gain adjustment range of -6dB to +18dB. The differential clock input of each ADC is connected to the same sampling clock signal output by the clock synchronization network construction and picosecond-level delay calibration module. The digital output interface of the ADC is connected to the high-speed serial receiving port of the field-programmable gate array (FPGA) via a low-voltage differential signal bus. The control logic for adaptive quantization gain adjustment is implemented within the FPGA, periodically updating the gain setting value of each channel's PGA according to the overload rate and utilization rate statistical strategy described in step S2 of the method embodiment.

[0047] The pipelined parallel data processing and ping-pong buffer relay module corresponds to step S3 in the method embodiment. This module is fully implemented within a field-programmable gate array (FPGA) and consists of four signal processing intellectual property cores: digital down-conversion, multi-stage decimation filtering, fast Fourier transform (FFT), and adaptive filtering, as well as inter-stage ping-pong buffer units. The digital down-conversion intellectual property core and the multi-stage decimation filtering intellectual property core are connected in series, while the FFT intellectual property core and the adaptive filtering intellectual property core are arranged in parallel after the multi-stage decimation filtering intellectual property core. The first stage is the digital down-conversion intellectual property core, containing a direct digital frequency synthesizer and a complex multiplier; the second stage is the multi-stage decimation filtering intellectual property core, containing a cascaded integrator-comb filter and a multi-stage half-band filter; the third stage is the FFT intellectual property core, employing a radix-2 butterfly operation structure, supporting configurable transform lengths from 1024 to 8192 points; the fourth stage is the adaptive filtering intellectual property core, implementing an adaptive filtering algorithm based on the normalized minimum mean square error criterion. Adjacent stages with data transfer relationships achieve data relay through ping-pong buffer units composed of dual-port block random access memory. Preferably, each buffer in the ping-pong buffer unit has a depth of 6144 data points and a data bit width of 32 bits. The pipelined processing architecture of each channel adopts a resource reuse strategy. Under the resource constraints of the field-programmable gate array, the eight channels can share the same set of pipelined processing hardware. The data of each channel is processed in turn in each processing clock cycle through time-division multiplexing, wherein the effective processing clock frequency of each channel is one-eighth of the main clock frequency.

[0048] The online calibration and digital compensation module for channel consistency corresponds to step S4 in the method embodiment. This module includes a calibration reference signal generation unit, a multi-channel response extraction unit, a mismatch parameter estimation unit, and a digital compensation execution unit. The calibration reference signal generation unit generates a single-frequency sinusoidal calibration signal of 6.201MHz within a field-programmable gate array (FPGA) using a direct digital frequency synthesizer. This signal is then output via a digital-to-analog converter (DAC) and simultaneously injected into the analog front-end of each acquisition channel. The multi-channel response extraction unit acquires digital data from each channel during calibration signal injection and extracts the amplitude and phase responses at the calibration frequency using discrete Fourier transform. The mismatch parameter estimation unit calculates the gain mismatch parameter and phase mismatch parameter for each channel according to the formula described in step S4 of the method embodiment. The digital compensation execution unit inserts a gain correction multiplier and a phase rotation multiplier into the pipelined data processing path to perform real-time compensation on the data from each channel. This module also includes a feedback control interface. When the phase mismatch parameter is detected to continuously exceed a threshold, a delay correction command is sent to the clock synchronization network construction and picosecond-level delay calibration module via a control register.

[0049] The adaptive processing parameter feedback optimization module corresponds to step S5 in the method embodiment. This module is implemented within the field-programmable gate array (FPGA) and includes a signal-to-noise ratio (SNR) evaluation unit, an inter-channel cross-correlation calculation unit, a trend analysis unit, and a parameter update control unit. The SNR evaluation unit calculates the SNR index of each channel using the power spectral density output of the spectrum transform analysis stage. The inter-channel cross-correlation calculation unit calculates the correlation coefficient between any two channels according to the normalized cross-correlation formula described in step S5 of the method embodiment. The trend analysis unit tracks the historical trend of each evaluation index using a sliding window method. The sliding window length is set to 100 evaluation periods, which can effectively detect slow variation trends and distinguish between transient disturbances and persistent degradation. The parameter update control unit generates optimized processing parameters based on the evaluation results and atomically updates them to the pipelined parallel data processing and ping-pong buffer relay module through the control register interface during ping-pong buffer switching intervals.

[0050] At the overall system integration level, the five functional modules mentioned above achieve data interaction and control coordination between modules through a unified system bus architecture. Preferably, this embodiment uses an advanced scalable interface bus as the on-chip interconnect architecture, with each functional module connected to the bus as a slave device. The system control state machine acts as the bus master device, uniformly scheduling the working sequence and data flow of each module. The system control state machine is responsible for coordinating the initialization sequence, calibration triggering timing, parameter update synchronization, and anomaly recovery handling of each module. When the system powers on, the control state machine completes system initialization in a fixed sequence: clock synchronization network initialization, analog-to-digital converter configuration, pipeline processing core loading, and calibration execution. After entering normal operating mode, the control state machine enters a cyclic monitoring state, periodically triggering calibration and parameter optimization processes. In addition, the system is also configured with an external communication interface module, supporting real-time transmission of the processing results of each channel to an external host or display terminal via Gigabit Ethernet or high-speed serial bus. The data transmission bandwidth is not less than 1Gbps, meeting the real-time output requirements of 8-channel processed data. The field-programmable gate array (FPGA) resource utilization rate of the entire system is about 75%, of which the pipelined processing module occupies about 50% of the logic resources and 80% of the digital signal processing multiplier resources. The remaining resources are used for clock management, communication interfaces and system control logic.

[0051] To verify the practical effectiveness of the technical solution of this invention, system-level testing was conducted on an 8-channel high-speed signal acquisition and processing platform. This test platform uses a Xilinx Kintex UltraScale series field-programmable gate array (FPGA) as the core processing device, configured with eight high-speed analog-to-digital converter (ADC) chips with a sampling rate of 200 MSPS and a quantization accuracy of 16 bits. The reference clock source is a temperature-controlled crystal oscillator with a root mean square jitter of 0.3 ps, and the clock distribution network adopts a two-level tree topology. The operating temperature of the test platform was maintained at 25℃±2℃, and the supply voltage stability was better than 0.1%. The signal source used in the test was an Agilent high-precision RF signal generator, capable of generating standard test signals with a frequency accuracy better than 0.01 Hz and an amplitude accuracy better than 0.01 dB.

[0052] Regarding inter-channel synchronization accuracy, test results show that after clock synchronization network construction and picosecond-level delay calibration in step S1, the maximum sampling time deviation among the eight channels is 38 ps, and the average sampling time deviation is 22 ps, both better than the design target of 100 ps. In contrast, without delay calibration, the maximum sampling time deviation among channels is 420 ps, ​​and the deviation is reduced by approximately 11 times after calibration. Compared with the buffer depth adjustment-based scheme in CN110557121A, the synchronization accuracy of this invention is improved by more than an order of magnitude. This is because the calibration accuracy of the buffer depth adjustment scheme is limited by the discrete length of the sampling clock cycle. Taking a sampling frequency of 200 MHz as an example, its minimum calibration granularity is 5 ns, i.e., one sampling clock cycle, while this invention can achieve continuous picosecond-level accuracy adjustment. Furthermore, temperature cycling tests were conducted within an extended temperature range of -20℃ to +60℃. The results show that the maximum synchronization deviation among channels remains within 65 ps throughout the entire temperature range, thanks to the real-time compensation for temperature drift by the closed-loop feedback mechanism from step S4 to step S1.

[0053] In terms of signal processing performance, the end-to-end latency of the four-stage pipelined processing architecture was measured to be 6.8 μs, with the digital down-conversion stage latency being approximately 0.2 μs, the multi-stage decimation filtering stage latency being approximately 3.5 μs, the Fast Fourier Transform stage latency being approximately 2.3 μs, and the adaptive filtering stage latency being approximately 0.8 μs. The real-time processing throughput of each channel is 200 MSPS × 16 bits × 8 channels = 25.6 Gbps, far exceeding the processing capabilities of traditional digital signal processor solutions. The ping-pong buffer mechanism enables the pipeline throughput efficiency to reach over 99.9%, with an inter-frame data loss rate of less than 0.01%. In the performance test of the adaptive filtering stage, using white noise as the reference input and a broadband signal containing narrowband interference as the desired input, the filter converged to a steady state within 200 iterations, with the steady-state error power reduced by more than 35 dB compared to the initial error power.

[0054] Regarding channel consistency, after online calibration and digital compensation in step S4, the gain consistency among the eight channels was controlled within 0.08dB, and the phase consistency within 0.5°. In a long-term stability test lasting 48 hours, the gain consistency fluctuation among channels did not exceed 0.05dB, and the phase consistency fluctuation did not exceed 0.3°, demonstrating that the online closed-loop calibration mechanism can effectively compensate for the gradual changes in channel characteristics caused by temperature drift. The adaptive parameter optimization in step S5 maintained the signal-to-noise ratio of each channel above 72dB across the entire bandwidth, exceeding the design target of 70dB. Furthermore, tests of the adaptive quantization gain adjustment mechanism showed that, even with a 25dB difference in input signal amplitude among the channels, the effective quantization bit depth of each channel remained above 13.8 bits, an improvement of 2.5 bits compared to the fixed-gain scheme.

[0055] In the application verification of phased array radar signal processing, the received signals of an 8-element linear array were simulated using 8 channels to test the beamforming pointing accuracy and sidelobe suppression performance. Test results show that after signal acquisition and processing using the scheme of this invention, the beam pointing accuracy is 0.02°, a 7.5-fold improvement compared to 0.15° without the scheme; the first sidelobe level is -28.5dB, an 8.2dB improvement compared to -20.3dB without the scheme. These performance improvements are mainly attributed to the picosecond-level inter-channel synchronization accuracy and highly consistent gain-phase compensation of this invention. The synergistic effect of these two features significantly reduces pointing errors and sidelobe elevation in array signal processing. In the application verification of multi-lead physiological signal monitoring, the system of this invention simultaneously acquires 8 channels of ECG signals. The waveform correlation coefficient of each channel signal after processing reaches above 0.997, meeting the requirements for channel consistency in clinical-grade multi-lead ECG monitoring. The above test results fully verify the significant advantages of the five-step dual closed-loop collaborative architecture of the present invention over the prior art in terms of inter-channel synchronization accuracy, signal processing throughput and long-term stability. It provides a highly reliable and high-performance multi-channel signal synchronous acquisition and real-time processing solution for application scenarios with stringent real-time requirements, such as phased array radar signal processing, multi-lead physiological signal monitoring and underwater acoustic array beamforming.

[0056] The embodiments of the present invention are not limited to the specific embodiments described above. Those skilled in the art can make various equivalent changes or substitutions based on the technical solutions of the present invention, and all such changes or substitutions should be included within the protection scope of the present invention.

Claims

1. A method for synchronous acquisition and real-time processing of multi-channel signals, characterized in that, Includes the following steps: Step S1: Construct a clock synchronization network and perform picosecond-level delay calibration: Based on a low-jitter reference clock source, distribute the same sampling clock signal to each acquisition channel through a clock distribution network, and apply precise delay compensation to the clock transmission path of each channel to bring the sampling time deviation of each channel to within a preset synchronization accuracy threshold; the precise delay compensation is achieved by adjusting the phase offset of the clock signal of each channel through a programmable delay chain. Step S2, perform multi-channel parallel sampling and adaptive quantization encoding: Under the drive of the clock synchronization network, each channel high-speed analog-to-digital converter performs parallel sampling of the analog input signal with the synchronous clock edge as a reference, converts the analog signal into a digital sampling sequence, and adaptively adjusts the quantization gain parameter according to the dynamic range of each channel signal. Step S3, execute pipeline parallel data processing and ping-pong buffer relay: input the digital sampling sequence of each channel into the multi-stage pipeline processing architecture, perform digital down-conversion and multi-stage decimation filtering in sequence, and then perform spectrum transformation analysis and adaptive filtering processing on the baseband signal output by multi-stage decimation filtering in parallel. The ping-pong buffer mechanism enables seamless data relay transmission between adjacent pipeline stages. Step S4, perform online calibration and digital compensation for channel consistency: periodically inject calibration reference signals into each channel, estimate the gain mismatch parameters and phase mismatch parameters in real time by comparing the deviation between the actual response and the theoretical response of each channel, apply digital compensation to the data of each channel after pipeline processing, and feed back the mismatch parameters to the clock synchronization network of step S1 to dynamically correct the delay compensation amount. Step S5, perform adaptive processing parameter feedback optimization: perform inter-channel consistency assessment on the output data of each channel after compensation, extract the signal-to-noise ratio index and inter-channel correlation index, and adaptively adjust the processing parameters of each stage of the pipeline in step S3 accordingly.

2. The method for synchronous acquisition and real-time processing of multi-channel signals according to claim 1, characterized in that, In step S1, the root mean square jitter of the low jitter reference clock source does not exceed 0.5ps, the clock distribution network adopts a tree topology, the transmission delay difference of each branch path does not exceed 50ps, and the adjustment step size of the programmable delay chain is 5ps to 20ps, with an adjustment range of 0ps to 500ps.

3. The method for synchronous acquisition and real-time processing of multi-channel signals according to claim 1, characterized in that, In step S2, the sampling rate of the high-speed analog-to-digital converter of each channel is not less than 100 MSPS, the quantization accuracy is not less than 14 bits, and the adjustment range of the adaptive quantization gain parameter is -6dB to +18dB, with an adjustment step size not exceeding 0.5dB.

4. The method for synchronous acquisition and real-time processing of multi-channel signals according to claim 1, characterized in that, In step S3, the depth of each buffer in the ping-pong caching mechanism is 1 to 2 times the length of a single frame of data, the buffer switching delay does not exceed one sampling clock cycle, and the overall processing delay of the pipelined processing architecture does not exceed 10 μs.

5. The method for synchronous acquisition and real-time processing of multi-channel signals according to claim 1, characterized in that, In step S3, the digital down-conversion is achieved by multiplying the digital local oscillator with the input signal and then extracting the baseband component through low-pass filtering. The multi-stage decimation filtering includes a combination of cascaded integrator comb filters and half-band filters, with a total decimation factor of 8 to 256 times. The spectrum transformation analysis adopts a fast Fourier transform algorithm based on butterfly operation, with a transformation point count of 1024 to 8192 points.

6. The method for synchronous acquisition and real-time processing of multi-channel signals according to claim 1, characterized in that, In step S3, the adaptive filtering process adopts an adaptive filtering algorithm based on the normalized minimum mean square error criterion. The filter order is from 32 to 256, and the step size factor ranges from 0.001 to 0.

1. The adaptive filtering algorithm dynamically adjusts the step size factor according to the power spectral density characteristics of the input signal.

7. The method for synchronous acquisition and real-time processing of multi-channel signals according to claim 1, characterized in that, In step S4, the calibration reference signal is a single-frequency sine wave signal or a pseudo-random sequence signal, with an injection period of 100ms to 1000ms. The amplitude response and phase response of each channel are extracted during the injection of the calibration reference signal, and the difference is calculated with the theoretical amplitude value and the theoretical phase value to obtain the gain mismatch parameter and the phase mismatch parameter.

8. The method for synchronous acquisition and real-time processing of multi-channel signals according to claim 1, characterized in that, In step S4, the digital compensation is achieved by multiplying the data of each channel by a gain correction factor and superimposing a phase correction rotation amount. The gain correction factor is the reciprocal of the gain mismatch parameter of each channel, and the phase correction rotation amount is the negative value of the phase mismatch parameter of each channel.

9. The method for synchronous acquisition and real-time processing of multi-channel signals according to claim 1, characterized in that, In step S5, the inter-channel consistency assessment includes calculating the cross-correlation coefficient of the output data of any two channels. When the cross-correlation coefficient is lower than a preset consistency threshold, the processing parameters in step S3 are re-optimized. The preset consistency threshold is 0.95 to 0.

99.

10. A multi-channel signal synchronous acquisition and real-time processing system, used to implement the multi-channel signal synchronous acquisition and real-time processing method according to any one of claims 1-9, characterized in that, include: The clock synchronization network construction and picosecond-level delay calibration module is used to distribute the same sampling clock signal to each acquisition channel through the clock distribution network based on the low jitter reference clock source, and to apply precise delay compensation to the clock transmission path of each channel so that the sampling time deviation of each channel converges to within the preset synchronization accuracy threshold. The multi-channel parallel sampling and adaptive quantization encoding module is used to perform parallel sampling and analog-to-digital conversion on the analog input signals of each channel under the guidance of the clock synchronization network, with the synchronous clock edge as the trigger reference, and adaptively adjust the quantization gain parameter according to the dynamic range of each channel signal. The pipeline parallel data processing and ping-pong buffer relay module is used to input the digital sampling sequence of each channel into the multi-stage pipeline processing architecture to perform digital down-conversion and multi-stage decimation filtering in sequence. Then, the baseband signal output by the multi-stage decimation filtering is subjected to parallel spectrum transformation analysis and adaptive filtering. The ping-pong buffer mechanism is used to realize seamless relay transmission of data between adjacent pipeline stages. The channel consistency online calibration and digital compensation module is used to periodically inject calibration reference signals to estimate the gain mismatch parameters and phase mismatch parameters of each channel in real time and apply digital compensation. At the same time, the mismatch parameters are fed back to the clock synchronization network construction and picosecond delay calibration module to dynamically correct the delay compensation amount. The adaptive processing parameter feedback optimization module is used to perform inter-channel consistency assessment on the compensated output data of each channel and adaptively adjust the processing parameters of each stage in the pipeline parallel data processing and ping-pong buffer relay module according to the assessment results.

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