A synchronous sampling circuit for a multiphase drive system

Abstract

The present application relates to the technical field of semiconductor chip, particularly relates to a kind of synchronous sampling circuit of multiphase drive system.The synchronous sampling circuit includes: sampling and holding module, for the analog signal of each phase representing working current is synchronously sampled and kept as sampling voltage signal, the analog signal is single or double channel signal, double channel signal includes positive and negative signal;Signal amplification module is connected with the sampling and holding module, for amplifying the sampling voltage signal of each phase;Analog-digital converter is connected with the signal amplification module, for converting the digital quantity of each signal after amplification analog quantity.The present application realizes the synchronous sampling of multiphase analog signal, eliminates the time difference error of multichannel signal acquisition, while time quantization reduces the speed requirement of post-amplifier and analog-digital converter, can improve the synchronous precision of multiphase current sampling under the premise of not increasing hardware cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip technology, and in particular to a synchronous sampling circuit for a multiphase drive system. Background Technology

[0002] In multiphase drive systems (such as three-phase motor drives and multiphase power converters), it is often necessary to acquire and quantize multiple analog signals (such as current sampling signals of each phase) to achieve closed-loop control, status monitoring, or protection functions. Taking three-phase current sampling as an example, a typical implementation method is to use a multiplexer (MUX) to cycle through each phase in each current sampling cycle, sequentially connecting the analog voltage signals output by the sampling resistors or current sensors of each phase to the subsequent amplifier and analog-to-digital converter (ADC), thus completing the amplification and quantization of multiple signals in a time-division manner.

[0003] However, this time-division multiplexing sampling and quantization scheme has inherent drawbacks: the sampling times of each phase signal are different, resulting in a time difference. For high-precision applications such as field-oriented control (FOC), theoretically, three-phase current information at the same moment is required for perfect coordinate system transformation. Existing schemes rely on an approximate assumption that the change in current of each phase is much smaller than the current itself during the entire time period of three-phase sampling, thus allowing it to be approximated that each phase is sampled at the same moment. To reduce the error introduced by the asynchronous sampling time, it is usually necessary to increase the drive speed and conversion speed of the sampling path (including operational amplifiers and ADCs) to compress the total polling time. However, this significantly increases the difficulty and cost of hardware design and cannot fundamentally eliminate the error caused by the time difference. When the system has high-frequency current ripple or rapid load changes, the error introduced by time-division sampling may degrade control performance or even lead to system instability. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a synchronous sampling circuit for a multiphase drive system, eliminating the time difference in sampling the current of each phase in the multiphase drive system.

[0005] To achieve the above objectives, the present invention provides a synchronous sampling circuit for a multiphase drive system, comprising: The sample-and-hold module is used to synchronously sample and hold the analog signals representing the operating current in each phase of the multiphase drive system as sampled voltage signals. The analog signals are single-channel analog signals or dual-channel analog signals. The dual-channel analog signals include a positive analog signal and a negative analog signal. A signal amplification module is connected to the output terminal of the sample-and-hold module and is used to amplify and output the sampled voltage signals held in each phase. An analog-to-digital converter is connected to the output of the signal amplification module and is used to convert the corresponding amplified sampled voltage signals into digital signals and then output them.

[0006] Furthermore, the sample-and-hold module includes multiple sampling units, each sampling unit corresponding to one analog signal setting of one phase of the multiphase drive system. Each sampling unit includes a sampling capacitor, and the sampling unit is used to hold the sampled voltage signal in the sampling capacitor respectively.

[0007] Furthermore, the sampling unit includes: The sampling capacitor includes a first terminal and a second terminal, with the second terminal serving as the output terminal; The first switch receives an analog signal representing the operating current in one phase of the multiphase drive system at one end, and is connected to the first end of the sampling capacitor at the other end. The second switch has one end connected to the second terminal of the sampling capacitor and the other end connected to the common-mode voltage terminal. The third switch has one end connected to the reference voltage terminal and the other end connected to the first terminal of the sampling capacitor. The fourth switch has one end connected to the second end of the sampling capacitor and the other end as the output terminal.

[0008] Furthermore, the analog signal is a dual-channel analog signal; each channel is provided with two sampling units, respectively used to sample the positive analog signal and the negative analog signal, and each sampling unit includes: The sampling capacitor includes a first terminal and a second terminal, with the second terminal serving as the output terminal; The first switch receives an analog signal of the corresponding polarity at one end and is connected to the first end of the sampling capacitor at the other end. The second switch has one end connected to the second terminal of the sampling capacitor and the other end connected to the common-mode voltage terminal. The fourth switch has one end connected to the second terminal of the sampling capacitor, and the other end is the output terminal; A common switch is provided between the two sampling units of the same phase, and the two ends of the common switch are respectively connected to the first end of the sampling capacitor in the two sampling units.

[0009] Furthermore, the sampling unit includes: The sampling capacitor includes a first terminal and a second terminal, with the second terminal serving as the output terminal; The first switch receives an analog signal representing the operating current in one phase of the multiphase drive system at one end, and is connected to the first end of the sampling capacitor at the other end. The second switch has one end connected to the reference voltage terminal and the other end connected to the first terminal of the sampling capacitor.

[0010] Furthermore, the analog signal is a dual-channel analog signal; each channel is provided with two sampling units, respectively used to sample the positive analog signal and the negative analog signal, and each sampling unit includes: The sampling capacitor includes a first terminal and a second terminal, with the second terminal serving as the output terminal; The first switch receives an analog signal of the corresponding polarity at one end and is connected to the first end of the sampling capacitor at the other end. A common switch is provided between the two sampling units of the same phase, and the two ends of the common switch are respectively connected to the first end of the sampling capacitor in the two sampling units.

[0011] Furthermore, the signal amplification module includes: A shared operational amplifier is provided, with its first signal input terminal connected to the output terminal of each of the sampling units, and its inverting output terminal corresponding to the first signal input terminal outputting the amplified sampling voltage signal. A feedback capacitor is connected in parallel between the first signal input terminal and the inverting output terminal of the shared operational amplifier.

[0012] A reset switch is connected in parallel across the feedback capacitor. Furthermore, the signal amplification module also includes: The time-sharing output switch has its first terminal connected to the inverting output terminal of the shared operational amplifier and its second terminal connected to the input terminal of the analog-to-digital converter.

[0013] Furthermore, the signal amplification module includes multiple amplification sub-units, each corresponding to a sampling unit, including: The sub-operational amplifier has its first signal input terminal connected to the output terminal of the corresponding sampling unit, and its inverting output terminal corresponding to the first signal input terminal outputs the amplified sampling voltage signal. A sub-feedback capacitor is connected in parallel between the first signal input terminal and the inverting output terminal of the sub-operational amplifier.

[0014] A sub-reset switch is connected in parallel across the sub-feedback capacitor; The sub-output switch has one end connected to the inverting output terminal of the sub-operational amplifier and the other end connected to the input terminal of the analog-to-digital converter.

[0015] To achieve the above objectives, this application also provides a synchronous sampling method for a multiphase drive system, comprising: The analog signals characterizing the operating current in each phase of the multiphase drive system are synchronously sampled, and the sampled analog signals are kept as sampled voltage signals. The analog signals are single-channel analog signals or dual-channel analog signals, and the dual-channel analog signals include positive analog signals and negative analog signals. The sampled voltage signals held in each phase are amplified and then output; The amplified corresponding sampled voltage signals are then converted from analog to digital and output.

[0016] Furthermore, the specific steps for amplifying and outputting the sampled voltage signals held by each phase include: The sampled voltage signals held by each phase are amplified sequentially through a shared amplification path in a time-division manner and then output in a time-division manner.

[0017] Furthermore, the specific steps for amplifying and outputting the sampled voltage signals held by each phase include: The sampled voltage signals held by each phase are amplified in parallel through their respective independent amplification paths, and the amplified signals of each phase are then output in a time-division multiplexing manner.

[0018] To achieve the above objectives, this application also provides a driver chip including a synchronous sampling circuit for a multiphase drive system as described above.

[0019] The synchronous sampling circuit for a multiphase drive system provided by this invention achieves true synchronous sampling of multiphase analog signals. By using a sample-and-hold module to synchronously acquire the analog signals representing the operating current of each phase at the same time, and holding the acquired signals in their respective sampling capacitors, subsequent time-division quantization operations no longer affect the consistency of the sampling time. Regardless of the speed of the subsequent amplifiers and ADCs, the final output digital quantities of each phase correspond to the current information at the same time, fundamentally eliminating the phase difference error caused by asynchronous sampling times in traditional polling schemes, improving current sampling accuracy, and providing accurate synchronous current data for subsequent high-precision field-oriented control (FOC) or multiphase current sharing control.

[0020] The synchronous sampling circuit for the multiphase drive system provided by this invention can adapt to different cost and performance requirements. One implementation uses a single shared amplifier and a single ADC, processing each phase signal in a time-division manner through a channel gating switch network. This has the advantages of small circuit area and low power consumption, making it suitable for cost-sensitive applications with ample quantization time. Another implementation uses multiple dedicated amplifiers to process each phase signal separately, and then connects them to a shared ADC in a time-division manner through an output gating switch network. This maintains the consistency of synchronous sampling while enabling parallel amplification of each phase signal, thereby accelerating the overall quantization speed. This is suitable for real-time control systems with high response time requirements.

[0021] The synchronous sampling circuit of the multiphase drive system provided by this invention separates synchronous sampling from time-division quantization. During the quantization stage, the signals of each phase can be processed in a time-division manner at a lower speed. The subsequent amplifier and ADC do not need to have high-speed switching capability, which reduces the hardware design threshold and power consumption.

[0022] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the structure of the multiphase drive system of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the synchronous sampling circuit of the multiphase drive system in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the sampling and holding module according to Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of the sampling and holding module according to Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of the signal amplification module in Embodiment 4 of the present invention; Figure 6 This is a schematic diagram of the signal amplification module in Embodiment 5 of the present invention; Figure 7 This is a schematic diagram of the structure of the multiphase drive system of Embodiment 6 of the present invention; Figure 8 This is a schematic diagram of the synchronous sampling circuit of the multiphase drive system in Embodiment 6 of the present invention; Figure 9 This is a schematic diagram of the synchronous sampling circuit of the multiphase drive system in Embodiment 7 of the present invention; Figure 10 This is a schematic diagram of the synchronous sampling circuit of the multiphase drive system in Embodiment 8 of the present invention; Reference numerals: 10-Synchronous sampling circuit, 100-Sample-and-hold module, 200-Signal amplification module, 101-First sampling unit, 102-Second sampling unit, 103-Third sampling unit, 104-Fourth sampling unit, 105-Fifth sampling unit, 106-Sixth sampling unit, 107-Seventh sampling unit, 108-Eighth sampling unit, 109-Ninth sampling unit, 110-Tenth sampling unit, 111-Eleventh sampling unit, 112-Twelfth sampling unit, 113 -Thirteenth sampling unit, 114-Fourteenth sampling unit, 115-Fifteenth sampling unit, 116-Sixteenth sampling unit, 117-Seventeenth sampling unit, 118-Eighteenth sampling unit, 2011-First amplification subunit, 2012-Second amplification subunit, 2013-Third amplification subunit, 2014-Fourth sub-amplifier unit, 2015-Fifth sub-amplifier unit, 2016-Sixth sub-amplifier unit, 20-Multiphase drive system, 30-Drive control module, 700-Motor. Detailed Implementation

[0024] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the invention. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the invention.

[0025] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0026] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0027] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "A plurality of" should be understood as two or more.

[0028] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] Example 1 One embodiment of the present invention provides a synchronous sampling circuit for a multiphase drive system. Figure 1 This is a schematic diagram of the structure of the multiphase drive system of Embodiment 1 of the present invention. Figure 1 This illustrates a typical application scenario of the synchronous sampling circuit in a multiphase drive system according to this embodiment. For example... Figure 1 As shown: The multiphase drive system 20 (taking three-phase as an example, including three phases A, B, and C) includes power stage circuits (such as half-bridge switching transistors) and sampling resistors, and the drive control module 30 controls the operation of each phase to drive the motor 700.

[0030] Depend on Figure 1 It can be seen that when the operating current of each phase flows through the sampling resistor, a voltage drop is generated across the sampling resistor. This voltage drop is an analog signal (V) characterizing the corresponding phase's operating current. INA V INB V INC The analog signal and the operating current satisfy the proportional relationship determined by Ohm's law, that is, the amplitude of the analog signal is directly proportional to the magnitude of the operating current. Therefore, the analog signal can be used to indirectly characterize the operating current of the corresponding phase. In order to achieve accurate measurement and digital control of the operating current, these analog signals characterizing the operating current need to be accurately acquired and converted into digital quantities for use by the subsequent controller (such as MCU or DSP) for closed-loop control (such as FOC). In this embodiment, the synchronous sampling circuit 10 is connected to the multi-phase drive system 20, receives the analog signals of each phase, and outputs synchronously sampled and quantized digital signals.

[0031] In this embodiment, the analog signal is a single-ended analog signal, that is, the analog signal is V. INA V INB V INC The default reference for this signal is ground (GND).

[0032] In other implementations, differential analog signals can be used, without the need for a default reference, and the analog signals across the sampling resistor can be sampled directly.

[0033] Figure 2 This is a schematic diagram of the synchronous sampling circuit of the multiphase drive system in Embodiment 1 of the present invention; as shown Figure 2 As shown, the synchronous sampling circuit of the multiphase drive system of the present invention includes: The sample-and-hold module 100 is used to synchronously sample and hold the analog signals representing the operating current in each phase of the multiphase drive system as sampled voltage signals. The analog signals are single-channel analog signals or dual-channel analog signals. The dual-channel analog signals include a positive analog signal and a negative analog signal.

[0034] In this embodiment, a sampling capacitor is used to hold the sampled analog signal.

[0035] There is a definite correspondence between the sampled voltage signal and the analog signal. The sample-and-hold module 100 captures and stores the instantaneous values ​​of each phase's analog signal at the same time. The stored sampled voltage signal is numerically equal to the difference between the analog signal at the sampling time and the common-mode voltage provided at the common-mode voltage terminal. This difference signal has a definite linear relationship with the analog signal. The sampled voltage signal does not change with subsequent changes in the original analog signal after sampling, thus achieving the freezing and holding of the instantaneous value of the analog signal at a specific moment. Since there is a positive linear relationship between the sampled voltage signal and the analog signal characterizing the operating current, its amplitude indirectly reflects the instantaneous magnitude of the operating current of that phase.

[0036] Understandably, the core function of the sample-and-hold module 100 is: Ensure that all phase signals are captured at the same time, and ensure that the sampled voltage signals of each phase are perfectly aligned in time; After sampling, the instantaneous values ​​of each phase signal are stored independently, providing a time buffer for subsequent time-division processing, so that the subsequent circuit can complete the quantization of multi-phase signals without high-speed concurrent processing.

[0037] The signal amplification module 200 is connected to the output terminal of the sample and hold module 100 and is used to amplify and output the sampled voltage signals held in each phase. Since the sampling voltage signal output by the sample-and-hold module 100 is usually small in amplitude (limited by the sampling resistor value and current range), direct analog-to-digital conversion may not fully utilize the input dynamic range of the analog-to-digital converter, thus affecting the quantization accuracy.

[0038] The function of the signal amplification module 200 is to read the sampled voltage signals held in each phase from the sample and hold module 100, and to linearly amplify the sampled voltage signals according to the preset gain coefficient, so that the amplitude of the amplified signal is adapted to the optimal input range of the analog-to-digital converter A1, thereby obtaining a higher signal-to-noise ratio and quantization accuracy in the subsequent quantization process.

[0039] The signal amplification module 200 can read and amplify the sampled voltage signals of each phase in a time-division manner. Since the signals of each phase have been synchronously frozen in the sample-and-hold module 100, the time-division reading and amplification do not affect the consistency of the signals of each phase at the sampling time.

[0040] The analog-to-digital converter A1 is connected to the output terminal of the signal amplification module 200 and is used to convert the corresponding amplified sampled voltage signals into digital signals and then output them.

[0041] The function of analog-to-digital converter A1 is to convert the analog signal amplified by signal amplification module 200 into a corresponding digital quantity. While each phase is selected by signal amplification module 200 in a time-division multiplexing manner, analog-to-digital converter A1 quantizes the amplified analog signal of each phase one by one, outputting the digital quantity of each phase. This digital quantity, after calibration or conversion, can be restored to the value of the operating current of each phase, which is then used by the subsequent controller for closed-loop control.

[0042] In this embodiment, the synchronous sampling circuit 10 ensures the time consistency of each phase signal through the synchronous sampling of the sample-and-hold module 100. By "freezing" the signal at the synchronization moment through the sample-and-hold function, the subsequent signal amplification module 200 and analog-to-digital converter A1 can process each phase signal in a time-division manner without affecting the time synchronization relationship between the phase signals. This "synchronous sampling-time-division processing" architecture ensures the accuracy requirements of multi-phase current synchronous sampling while avoiding the high-speed concurrency requirements of the subsequent amplifiers and analog-to-digital converters, achieving a good balance between accuracy and cost.

[0043] It should be noted that in a multiphase drive system, the grounding terminal PGND of each phase sampling resistor must be uniformly connected to the reference ground plane of the synchronous sampling circuit. This ground plane also serves as the charge discharge loop for the sampling capacitor in the sample-and-hold module, the power supply reference ground for the operational amplifier in the signal amplification module, and the quantization reference ground for the analog-to-digital converter. By implementing a single-point common ground connection between the sampling resistor ground, operational amplifier ground, and ADC ground within the chip, it can be ensured that the reference potential between the sampled voltage signal, the amplified signal, and the analog-to-digital conversion reference is completely consistent, eliminating the measurement error introduced by the ground loop voltage drop, thereby improving the accuracy and stability of the single-ended analog signal in the entire sampling and quantization link.

[0044] The beneficial effects of this embodiment are as follows: True synchronous sampling of multi-phase analog signals is achieved. By using the sample-and-hold module 100 to synchronously acquire and hold the analog signals of each phase at the same time, the sampling times of each phase signal are completely consistent, fundamentally eliminating the phase error caused by asynchronous sampling times in the traditional polling scheme, and providing accurate synchronous current data for high-precision closed-loop control.

[0045] The separation of sampling, amplification, and quantization reduces the speed requirements of subsequent circuits. Since the signals of each phase are synchronously held, the signal amplification module 200 and the analog-to-digital converter A1 can process the signals of each phase at a lower speed in a time-sharing manner, without the need for high-speed switching capabilities, thereby reducing the hardware design threshold and power consumption.

[0046] Example 2 One embodiment of the present invention provides a synchronous sampling circuit for a multiphase drive system. This embodiment, based on Embodiment 1, defines the specific circuit structure of the sample-and-hold module 100. Figure 3 This is a schematic diagram of the sampling and holding module of Embodiment 2 of the present invention, as shown below. Figure 3 As shown: The sample-and-hold module 100 includes multiple sampling units, each corresponding to a phase of the multiphase drive system. Taking a three-phase system as an example, it includes a first sampling unit 101, a second sampling unit 102, and a third sampling unit 103. Each sampling unit has the same structure; taking the first sampling unit 101 as an example, it includes: Sampling capacitor C A It has a first end (upper electrode plate) and a second end (lower electrode plate); First switch S A1 One end receives the A-phase analog signal V. INA The other end is connected to the sampling capacitor C. A The first end; Second switch S A2 One end is connected to the sampling capacitor C A The second terminal is connected to the common-mode voltage terminal V. CM ; Third switch S A3 One end is connected to the reference voltage terminal V. REF The other end is connected to the sampling capacitor C. A The first end is used for pre-sampling reset; Fourth switch S A4 One end is connected to the sampling capacitor C A The second end is used as the output end.

[0047] Similarly, the second sampling unit 102 corresponds to phase B and includes a sampling capacitor C. B First switch S B1 Second switch S B2 Third switch S B3 and the fourth switch S B4 The third sampling unit 103 corresponds to phase C and includes the sampling capacitor C. C First switch S C1 Second switch S C2 Third switch S C3 and the fourth switch S C4 The structure and working principle of each sampling unit are exactly the same.

[0048] In this embodiment of the application, the common-mode voltage V CMTo provide a stable DC bias voltage for the sampling unit with sufficient driving capability, it is usually set to half of the power supply voltage (e.g., 2.5V for a 5V power supply). This invention adopts this setting, but the following situations are not excluded: if the signal error is acceptable in the subsequent signal amplification module signal processing, or if the system offset introduced by the difference between the common-mode voltage of the sampling unit and the common-mode voltage of the signal amplification module is reasonably handled, the common-mode voltage of the sampling unit can also be directly connected to ground or any other voltage.

[0049] In this embodiment of the application, the reference voltage V REF This is the reference voltage for the input signal, which has sufficient driving capability and is usually set to ground.

[0050] In other embodiments, if the signal is acceptable during signal processing in the subsequent signal amplification module, the reference voltage V... REF It can also be V CM Or any other voltage.

[0051] In other implementations, in the fully differential circuit implementation, the reference voltage V REF It can also be virtual ground voltage generated by floating.

[0052] In this embodiment of the application, the sampling capacitor C A The first terminal is connected to a changing input analog signal V INA The second end is connected to the second switch S. A2 Connect to a fixed common-mode voltage terminal V CM Therefore, the difference established and maintained across the sampling capacitor is (V INA -V CM This difference signal facilitates the normal operation of subsequent circuits at the set common-mode level.

[0053] The working process of this application embodiment is as follows: Reset Phase: For each sampling unit, close the second and third switches, while keeping the first and fourth switches open. Short-circuit the first and second terminals of the sampling capacitor to the common-mode voltage terminal to clear any residual charge on the sampling capacitor. After the reset is complete, disconnect the second and third switches.

[0054] Synchronous sampling phase: When entering the synchronous sampling phase, for phase A, the first switch S of the first sampling unit 101 is controlled. A1 Second switch S A2 Close, third switch S A3 and the fourth switch S A4 Keep it disconnected. At this time, the sampling capacitor C... A The first end is connected to the first switch S A1 Access A-phase analog signal V INAThe second end is connected to the second switch S. A2 Connect to common mode voltage terminal V CM Sampling capacitor C A Charging begins, and the voltage at its first terminal gradually follows the changes in the input signal. After a sufficient sampling time, the sampling capacitor C... A The voltage at the first terminal stabilizes at V. INA The pressure difference between the two ends is (V INA - V CM At this point, the first and second switches are disconnected, and the difference signal between the input analog signal and the common-mode voltage is sampled.

[0055] Meanwhile, the second sampling unit 102 and the third sampling unit 103 perform identical operations on the B-phase and C-phase analog signals. It is particularly important to note that after sufficient sampling time, all phases' first switches are ensured to open simultaneously on the same clock edge, achieving perfect time alignment of the three sampling paths and realizing true synchronous sampling. Other operations do not require strict time synchronization between different phases, making them easy to implement.

[0056] Hold Phase: After sampling is completed, the two ends of the sampling capacitor are in a floating state, and the charge on the sampling capacitor is in a hold state. Therefore, the sampling capacitor C... A Voltage difference V across the two ends INA - V CM This is how it is maintained. Similarly, in phase B and phase C, the sampling capacitors also enter a high-impedance holding state, each independently storing the sampled difference signal.

[0057] Output stage: By controlling the timing to close the third and fourth switches of the corresponding sampling unit, the sampled voltage signal held in the corresponding phase is output to the signal amplification module.

[0058] It should be noted that when the third and fourth switches are closed, the voltage difference across the sampling capacitor changes because the output of the sampling unit is clamped to V. CM Therefore, the voltage difference across the sampling capacitor will become V. REF - V CM That is, -V CM The output signal of the amplifier module is A*V INA A is the sampling capacitor C A and feedback capacitor C F The ratio of .

[0059] It should be noted that the outputs of each sampling unit can be connected to the same common node and share the subsequent signal amplification module; or they can be connected independently to their respective signal amplification modules. Regardless of the connection method, since the signals of each phase are frozen synchronously during the sampling stage, the order of subsequent output and amplification does not affect the temporal consistency of the signals of each phase.

[0060] The beneficial effects of this embodiment are as follows: By configuring independent sampling capacitors and sampling switch networks for each phase, synchronous sampling and independent holding of multiple analog signals are achieved. All sampling capacitors complete sampling at the same time, ensuring the time consistency of signals in each phase; after sampling, each capacitor is held independently without interference, providing a reliable signal source for subsequent time-division or parallel processing.

[0061] Each sampling unit has an identical structure, which facilitates matching wiring and symmetrical layout within the chip, helps improve the consistency of sampling channels in each phase, and reduces sampling errors caused by layout mismatch.

[0062] Example 3 One embodiment of the present invention provides a synchronous sampling circuit for a multiphase drive system. This embodiment, based on Embodiment 1, defines the specific circuit structure of the sample-and-hold module 100. Figure 4 This is a schematic diagram of the sampling and holding module of Embodiment 3 of the present invention, as shown below. Figure 4 As shown: The sample-and-hold module 100 includes multiple sampling units, each corresponding to a phase of the multiphase drive system. Taking a three-phase system as an example, it includes a fourth sampling unit 104, a fifth sampling unit 105, and a sixth sampling unit 106. Each sampling unit has the same structure and adopts a simplified structure. Taking the fourth sampling unit 104 as an example, it includes: Sampling capacitor C A It has a first end and a second end, with the second end directly serving as the output end; First switch S A1 One end receives the A-phase analog signal V. INA The other end is connected to the sampling capacitor C. A The first end; Second switch S A2 One end is connected to the reference voltage terminal V. REF The other end is connected to the sampling capacitor C. A The first end.

[0063] This embodiment omits the third and fourth switches from Embodiment 2, and the output is directly led out from the second terminal of the capacitor. This simplified structure reduces the number of switches, lowers the chip area and parasitic effects, and is suitable for applications that are area-sensitive and where the output can be directly connected to the subsequent amplifier circuit.

[0064] The working process of this embodiment is as follows: Synchronous sampling phase: Control the first switch S A1 Close, second switch S A2 Keep it disconnected. At this time, the sampling capacitor C... A The first end is connected to the first switch SA1 Access A-phase analog signal V INA The second terminal serves as the output terminal, directly connected to the subsequent signal amplification module. It should be noted that during the sampling phase, the input terminal of the subsequent signal amplification module is clamped to the common-mode voltage V through its internal reset switch or the virtual short characteristic of the operational amplifier. CM (This will be explained in detail in subsequent embodiments), therefore the sampling capacitor C A The second terminal is actually clamped to V by the subsequent circuit. CM After a sufficient sampling time, the sampling capacitor C A The voltage established at both ends is (V) INA - V CM At this point, the first switch is disconnected, and the difference signal between the input analog signal and the common-mode voltage is sampled.

[0065] Meanwhile, the fifth sampling unit 105 and the sixth sampling unit 106 perform identical operations on the B-phase and C-phase analog signals. It is particularly important to note that after sufficient sampling time, all phases' first switches are ensured to open simultaneously on the same clock edge, achieving perfect time alignment of the three sampling paths and realizing true synchronous sampling. Other operations do not require strict time synchronization between different phases, making them easy to implement.

[0066] Hold Phase: After sampling is completed, the first terminal of the sampling capacitor is in a floating state, and the charge on the sampling capacitor is in a hold state. Therefore, the sampling capacitor C... A Voltage difference V across the two ends INA - V CM This is how it is maintained. Similarly, in phase B and phase C, the sampling capacitors also enter a high-impedance holding state, each independently storing the sampled difference signal.

[0067] Output stage: By closing the second switch of the corresponding sampling unit, the sampled voltage signal held in phase is output to the signal amplification module. The voltage difference across the sampling capacitor becomes -V. CM The output signal of the amplifier module is A*V INA A is the sampling capacitor C A and feedback capacitor C F The ratio of .

[0068] It should be noted that the outputs of each sampling unit can be connected to the same common node and share the subsequent signal amplification module; or they can be connected independently to their respective signal amplification modules. Regardless of the connection method, since the signals of each phase are frozen synchronously during the sampling stage, the order of subsequent output and amplification does not affect the temporal consistency of the signals of each phase.

[0069] The beneficial effects of this embodiment are as follows: The sampling unit has a simple structure, requiring only two switches and one sampling capacitor per phase, which reduces chip area and power consumption, lowers costs, and is particularly suitable for applications with a large number of channels or those that are area-sensitive.

[0070] The second terminal of the sampling capacitor is directly connected to the subsequent amplifier circuit, which avoids the on-resistance, charge injection and clock feedthrough effects introduced by the output switch, thus improving the fidelity of the sampling signal.

[0071] Each sampling unit has an identical structure, which facilitates matching wiring and symmetrical layout within the chip and helps improve the consistency of sampling channels in each phase.

[0072] Example 4 One embodiment of the present invention provides a synchronous sampling circuit for a multiphase drive system. This embodiment, based on Embodiment 1, defines the specific circuit structure of the signal amplification module 200. Figure 5 This is a schematic diagram of the signal amplification module in Embodiment 4 of the present invention, as shown below. Figure 5 As shown: The signal amplification module 200 is connected to the output terminals of each sampling unit of the sample and hold module 100.

[0073] In this embodiment, the output terminal of each sampling unit (i.e., one end of each fourth switch in embodiment 2, or the second end of each sampling capacitor in embodiment 3) is connected to the same common node, which serves as the shared input terminal of each phase sampling voltage signal and is connected to the signal amplification module 200.

[0074] Signal amplification module 200 includes: Shared operational amplifier F F The first signal input terminal (inverting input terminal) is connected to the output terminal of each of the sampling units, sharing the operational amplifier F. F The output terminal outputs the amplified sampled voltage signal, and the second input terminal (non-inverting input terminal) is connected to the common-mode voltage terminal V. CM ; It should be noted that this embodiment uses a single-ended output shared operational amplifier. Shared operational amplifier F F The non-inverting input terminal is connected to V CM This allows the op-amp to operate in an inverting amplification configuration, with its output voltage being V. CM It oscillates around a central point. Taking phase A as an example, when the sampled voltage signal of phase A is connected to the shared operational amplifier F... F When the inverting input is connected, the expression for the op-amp's output voltage is: V OUT =V INA × (C A / C F )+ V CM In the formula, CA C is the capacitance value of the sampling capacitor for phase A. F This is the capacitance value of the feedback capacitor.

[0075] Feedback capacitor C F Parallel connection to shared operational amplifier F F The connection between the inverting input and output terminals is used to set the amplifier gain. The gain is determined by the ratio of the sampling capacitor to the feedback capacitor (Cs). A / C F By determining the appropriate capacitor ratio, the required amplification factor can be obtained, so that the amplified signal amplitude matches the optimal input range of the analog-to-digital converter A1. Reset switch S RST , connected in parallel to the feedback capacitor C F The two ends are used to control the feedback capacitor C during different phase switching. F Perform a reset to clear residual charge from the previous channel and avoid crosstalk between channels; In this embodiment of the application, a time-sharing output switch S is also provided. ADC Time-sharing output switch S ADC One end is connected to the shared operational amplifier F F The output terminal is connected to the other end of the circuit, and the input terminal is connected to the analog-to-digital converter A1. Time-sharing output switch S ADC Controlled by timing, the circuit closes after the signal amplification of the corresponding phase is completed and stabilized, sending the amplified sampled voltage signal to the analog-to-digital converter A1 for quantization. After quantization is completed, the circuit opens to prepare for the output of the next phase.

[0076] The working process of this embodiment is as follows: This includes the reset preparation stage and the time-division amplification and quantization stage. The following explanation uses a three-phase system as an example. Reset preparation phase: Close reset switch S RST The feedback capacitor C F Short-circuit the two ends to clear any residual charge from the previous cycle. At this point, the voltage across the feedback capacitor is locked to the common-mode voltage by the operational amplifier.

[0077] Time-division amplification and quantization stage: Disconnect reset switch S RST , so that the feedback capacitor C F It enters the working state and is ready to receive the charge signal. At this time, the first terminal of the feedback capacitor is locked to the common-mode voltage by the operational amplifier, and the voltage at the second terminal of the feedback capacitor is determined by both the charge and the common-mode voltage.

[0078] Taking phase A as an example, if the sampling unit structure of embodiment 2 is adopted, the timing control closes the third switch S of the first sampling unit 101 of phase A. A3 Fourth switch S A4 The sampling capacitor C of phase AA The second terminal is connected to the shared operational amplifier F F The inverting input terminal. At this time, the sampling capacitor C A The signal charge held on (corresponding to the sampled voltage signal V) INA The capacitor was "moved" to the feedback capacitor C. F Above, shared operational amplifier F F The output terminal generates an amplified analog signal. After the signal stabilizes, the time-division output switch S is closed. ADC The amplified signal is sent to analog-to-digital converter A1 for quantization. After quantization, the third switch S of phase A sampling unit is disconnected. A3 Fourth switch S A4 and time-sharing output switch S ADC Then close the reset switch S RST For the feedback capacitor C F Reset the circuit to prepare for phase B amplification. Repeat the above steps for phase B and phase C in sequence to complete the amplification and quantization of the sampled voltage signals of each phase.

[0079] Taking phase A as an example, if the simplified sampling unit structure described in Example 3 is adopted (the second end of the sampling capacitor is directly output, there is no fourth switch, and the second end of the sampling capacitor is always connected to the shared operational amplifier F), F During the sampling phase of the sample-and-hold module, the signal amplification module is in the preparation reset phase, and the inverting input of the operational amplifier is locked to the common-mode voltage. The sampling capacitor samples the difference between the input analog signal and the common-mode signal. Then, during the time-division multiplexing and quantization phase of the signal amplification module, the sample-and-hold module enters the output phase, closing the second switch S of the A-phase sampling unit. A2 At this time, the sampling capacitor C A The signal charge (V) held on INA The capacitor was "moved" to the feedback capacitor C. F Above, shared operational amplifier F F The output terminal generates an amplified analog signal, which is quantized by analog-to-digital converter A1. Then, the second switch S of the A-phase sampling unit is disconnected. A2 Then close the reset switch S RST For the feedback capacitor C F Reset the circuit to prepare for phase B amplification. Repeat the above steps for phase B and phase C in sequence to complete the amplification and quantization of the sampled voltage signals of each phase.

[0080] The beneficial effects of this embodiment are as follows: Each phase shares a single operational amplifier, feedback capacitor, reset switch, and output switch. Only a single analog-to-digital converter is needed to complete the time-division amplification and quantization of multi-phase signals, which greatly saves chip area and power consumption and reduces costs.

[0081] All phases share the same operational amplifier and feedback capacitor, and the signals of each phase pass through the exact same amplification path, eliminating gain mismatch and offset deviation between multiple amplification channels and improving the relative accuracy between the sampled signals of each phase.

[0082] Example 5 One embodiment of the present invention provides a synchronous sampling circuit for a multiphase drive system. This embodiment, based on Embodiment 1, defines the specific circuit structure of the signal amplification module 200. Figure 6 This is a schematic diagram of the signal amplification module in Embodiment 5 of the present invention, as shown below. Figure 6 As shown: The signal amplification module 200 includes multiple amplification sub-units, each of which corresponds to a sampling unit. That is, each sampling unit is equipped with a dedicated amplification sub-unit to realize parallel amplification of the sampled voltage signals of each phase.

[0083] Taking a three-phase system as an example, the signal amplification module 200 includes a first amplification subunit 2011 (corresponding to phase A), a second amplification subunit 2012 (corresponding to phase B), and a third amplification subunit 2013 (corresponding to phase C). Each amplification subunit has the same structure. Taking the first amplification subunit 2011 as an example, it includes: Sub-operational amplifier F1 has its first signal input terminal (inverting input terminal) connected to the output terminal of the sampling unit of phase A. The output terminal outputs the amplified sampled voltage signal. Its non-inverting input terminal is connected to the common-mode voltage terminal V. CM ; In this embodiment, the non-inverting input terminal of the sub-operational amplifier F1 is connected to V. CM Its function is the same as described in Example 4: the non-inverting input terminal of sub-operational amplifier F1 is connected to V. CM Then, the operational amplifier operates in inverting amplification configuration, and its output voltage is V CM It oscillates around the center.

[0084] Sub-feedback capacitor C FA It is connected in parallel between the inverting input and output of the sub-operational amplifier F1 to set the gain of this amplification sub-unit. The gain is determined by the ratio of the sampling capacitor of the corresponding phase to the sub-feedback capacitor (C). A / C FA By determining the appropriate capacitance ratio, the required amplification factor can be obtained. Sub-reset switch S RSTA Parallel connection in the feedback capacitor C FA The two ends are used to adjust the sub-feedback capacitor C before the amplification subunit operates. FA Perform a reset to clear any residual charge; Sub-output switch S AOne end is connected to the output of the sub-operational amplifier F1, and the other end is connected to the input of the analog-to-digital converter A1. The sub-output switch S... A Controlled by timing, the circuit closes after the corresponding phase signal has been amplified and stabilized, and sends the amplified sampled voltage signal to the analog-to-digital converter A1 for quantization.

[0085] Similarly, the structure and working principle of the amplification subunits of phase B and phase C are exactly the same.

[0086] The working process of this application embodiment is as follows: Similar to the aforementioned embodiments, each sampling unit of the sample-and-hold module 100 synchronously samples the three-phase analog signal at the same time and holds the sampled voltage signal in its respective sampling capacitor.

[0087] After sampling is completed, each sampling capacitor enters a high-impedance holding state, and the signals of each phase are synchronously frozen. Then, the sub-reset switch S of each amplification subunit... RSTA S RSTB S RSTC The circuit closes, resetting each sub-feedback capacitor to prepare for subsequent amplification. After the sampling phase, the sampling capacitors of each phase have stored their respective difference signals. At this time, each amplification sub-unit synchronously enters the amplification state—because each phase has an independent sub-operational amplifier and sub-feedback capacitor, the sampled voltage signal of each phase is amplified in parallel by its respective sub-operational amplifier, without waiting for other phases. Taking phase A as an example, the output voltage expression of sub-operational amplifier F1 is: V OUTA = V INA × (C A / C FA )+ V CM Meanwhile, the sub-operational amplifiers F2 and F3 of phase B and phase C also perform their respective amplifications simultaneously without affecting each other.

[0088] It should be noted that the output signals of each amplification subunit are established simultaneously during the amplification stage. Since the signal paths of each phase are independent, there is no waiting time between channels, and the overall amplification speed is much faster than that of a shared operational amplifier scheme.

[0089] After each phase signal is amplified (and after sufficient settling time), the sub-output switches are closed in a time-division manner via timing control, and the amplified phase signals are sequentially sent to the analog-to-digital converter A1 for quantization. For example, the sub-output switch S is closed first. A The amplified signal from phase A is sent to analog-to-digital converter A1 for quantization; after quantization, S is disconnected. A Then close the sub-output switch S. B Perform phase B quantization; and so on.

[0090] It should be noted that the signal amplification module 200 of this embodiment is compatible with both sample-and-hold module structures of Embodiments 2 and 3. When the structure described in Embodiment 2 (including the fourth switch) is used, the output terminal of each phase sampling unit is connected to the corresponding amplification subunit through the fourth switch; when the simplified structure described in Embodiment 3 (the second terminal of the sampling capacitor is directly output) is used, the second terminal of the sampling capacitor is directly connected to the corresponding amplification subunit. Regardless of which sample-and-hold structure is used, the amplification principle of this embodiment is the same.

[0091] The beneficial effects of the embodiments of this application are as follows: Each phase is equipped with an independent sub-operational amplifier, and the signals of each phase are amplified in parallel without waiting for other phases to complete amplification. Therefore, the overall conversion speed is much faster than that of shared op-amp solutions. The time-division quantization stage only requires switching the output switch, without waiting for the amplifier settling time, making it particularly suitable for real-time control systems with high response speed requirements.

[0092] Each phase signal path is independent, avoiding the additional on-resistance, switching noise and charge injection error introduced by the multiplexer, and improving the signal-to-noise ratio and fidelity of small signal sampling.

[0093] The gain of each amplification subunit is set independently by the ratio of its sampling capacitor to its feedback capacitor. Different gains can be flexibly configured according to the actual situation of the signal amplitude of each phase, adapting to application scenarios where the current range of each phase is inconsistent.

[0094] Example 6 One embodiment of the present invention provides a synchronous sampling circuit for a multiphase drive system, suitable for differential analog signal scenarios. This embodiment adopts a sampling unit structure similar to that of Embodiment 2 (including first to fourth switches), and the positive and negative signals of each phase are collected and then connected to a shared fully differential operational amplifier for amplification. Figure 7 This is a schematic diagram of the multiphase drive system of Embodiment 6 of the present invention. Figure 7 As shown: The multiphase drive system 20 (taking three-phase as an example, including phases A, B, and C) includes power stage circuits (such as half-bridge switches) and sampling resistors. The drive control module 30 controls the operation of each phase to drive the motor 700. The operating current of each phase is converted into an analog signal (V) representing the magnitude of the current through the sampling resistors. INA+ V INB+ V INC+ V INA-、 V INB- V INC-These analog signals need to be accurately acquired and converted into digital quantities for use by subsequent controllers (such as MCUs or DSPs) for closed-loop control (such as FOC). In this embodiment, the synchronous sampling circuit 10 is connected to the multiphase drive system 20, receives the analog signals of each phase, and outputs synchronously sampled and quantized digital signals.

[0095] Figure 8 This is a schematic diagram of the synchronous sampling circuit of the multiphase drive system in Embodiment 6 of the present invention, as shown below. Figure 8 As shown: The sample-and-hold module 100 includes multiple sampling units, with two sampling units corresponding to one phase of the multiphase drive system. Taking a three-phase system as an example, each phase is equipped with two sampling units: the seventh sampling unit 107 is used to sample the positive analog signal V of phase A. INA+ The eighth sampling unit 108 is used to sample the negative analog signal V of phase A. INA- The ninth sampling unit 109 is used to sample the positive analog signal V of phase B. INB+ The tenth sampling unit 110 is used to sample the negative analog signal V of phase B. INB- The eleventh sampling unit 111 is used to sample the positive analog signal V of phase C. INC+ The twelfth sampling unit 112 is used to sample the negative analog signal V of phase C. INC- .

[0096] The structure of each sampling unit is the same as that of the sampling unit in Embodiment 2. Taking the seventh sampling unit 107 as an example, it includes: Sampling capacitor C A+ It has a first end (upper electrode plate) and a second end (lower electrode plate); First switch S A1+ One end receives the positive analog signal V of phase A. INA+ The other end is connected to the first terminal of the sampling capacitor C1; Second switch S A2+ One end is connected to the sampling capacitor C A+ The second terminal is connected to the common-mode voltage terminal V. CM ; Third switch S A3+ One end is connected to the reference voltage terminal V. REF The other end is connected to the sampling capacitor C. A+ The first end is used for pre-sampling reset; Fourth switch S A4+ One end is connected to the sampling capacitor C A+ The second end is used as the output end.

[0097] The output terminals of the sampling units (107, 109, 111) that sample the positive analog signals of each phase are connected to the same common node to form the first output terminal; the output terminals of the sampling units (108, 110, 112) that sample the negative analog signals of each phase are connected to another common node to form the second output terminal.

[0098] The signal amplification module 200 is connected to the sample-and-hold module 100. In this embodiment, the signal amplification module 200: Shared operational amplifier F F The inverting input terminal is connected to the first output terminal, and the non-inverting input terminal is connected to the second output terminal. Operational amplifier F... F The common-mode voltage setting terminal (VOCM pin) and the common-mode voltage terminal V CM The connection is used to set the common-mode level of the differential output signal, so that the output signal is V CM Centered on; First feedback capacitor C F+ Connected to the shared operational amplifier F F Between the inverting input terminal and the non-inverting output terminal; Second feedback capacitor C F- Connected to the shared operational amplifier F F Between the non-inverting input terminal and the inverting output terminal; First reset switch S R+ Parallel connection to the first feedback capacitor C F+ Both ends; Second reset switch S R- Parallel connection to the second feedback capacitor C F- Both ends.

[0099] First output switch S ADC+ One end is connected to the shared operational amplifier F F One end is connected to the non-inverting output terminal, and the other end is connected to one input terminal of the analog-to-digital converter A1; Second output switch S ADC- One end is connected to the shared operational amplifier F F One end is connected to the inverting output terminal, and the other end is connected to the other input terminal of the analog-to-digital converter A1.

[0100] Analog-to-digital converter A1 is a differential analog-to-digital converter, whose differential inputs receive signals from a shared fully differential operational amplifier F. F It outputs positive and negative phase signals and converts differential analog signals into digital outputs.

[0101] It is understood that this embodiment is described based on the sample-and-hold module structure of Embodiment 2. In actual implementation, the synchronous sampling of differential analog signals is not limited to this structure. For example, the sample-and-hold module can also adopt the simplified sampling unit structure described in Embodiment 3 (containing only the first and second switches, with the second end of the sampling capacitor directly serving as the output terminal). The output terminals of each phase positive terminal sampling unit and negative terminal sampling unit are also respectively aggregated to form the positive terminal bus and the negative terminal bus, and the structure and working principle of the shared fully differential operational amplifier are basically the same as in this embodiment.

[0102] The signal amplification module can also adopt the structure of multiple independent amplification sub-units described in Embodiment 5, with independent amplifiers configured for the positive and negative terminals of each phase to achieve parallel amplification of the signals of each phase. Therefore, the differential scheme of this embodiment can be flexibly adapted to the sample-and-hold module and signal amplification module structures in the aforementioned embodiments, and has good compatibility and scalability.

[0103] The working process of this application embodiment is as follows: The synchronous sampling phase is similar to the synchronous sampling process in Example 2, except that two sampling units (positive and negative terminals) are operated simultaneously in each phase. Taking phase A as an example, in the synchronous sampling phase, the first and second switches of the seventh sampling unit 107 and the eighth sampling unit 108 are closed simultaneously, while the third and fourth switches remain open. At this time, the sampling capacitor C... A+ The first terminal is connected to the positive analog signal V INA+ The second end is connected to V CM Sampling capacitor C A- The first terminal is connected to the negative analog signal V INA- The second end is connected to V CM The two sampling capacitors are charged synchronously, and the voltage difference between the two sampling capacitors is (V). INA+ - V CM ) and (V INA- -V CM Simultaneously, the positive and negative sampling units of phases B and C perform the same operation, ensuring that all sampling actions are completed at the same time. After sampling, the first switches of all phases are ensured to open simultaneously on the same clock edge, achieving complete time alignment of the three differential signal samplings and realizing true synchronous sampling. Other operations do not require strict time synchronization between different phases, making them easy to implement. After all second switches are opened, each sampling capacitor enters a high-impedance holding state.

[0104] During the time-division quantization phase, taking phase A as an example, the reset switch S is first closed. R+ and S R- For the feedback capacitor C F+ and C F-Perform a reset and clear the data, then disconnect the reset switch. Next, close the third switch corresponding to A (S switch of the seventh sampling unit 107). A3+ and the S of the eighth sampling unit 108 A3- ) and the fourth switch (S of the seventh sampling unit 107) A4+ and the S of the eighth sampling unit 108 A4- At this time, the output of the sampling unit will be clamped to V. CM Therefore, the voltage difference across the sampling capacitor will become V. REF -V CM That is, -V CM This allows the sampling voltage signal (V) held on the sampling capacitors at the positive and negative terminals of phase A to be further processed. INA- and V INA+ They are respectively connected to a shared fully differential operational amplifier F. F The inverting and non-inverting inputs are shared by the fully differential operational amplifier F. F The differential input signal is amplified, and its non-inverting and inverting output terminals output the amplified positive and inverted signals, respectively. After the signal stabilizes, the output switch S is closed. ADC+ and S ADC- The differential amplified signal is sent to analog-to-digital converter A1 for quantization. After quantization, the third switch, fourth switch, and output switch of phase A sampling unit are disconnected, and the above steps are repeated for phase B and phase C in sequence.

[0105] When using differential analog signal transmission, the difference (V) between the positive and negative analog signals is... INA+ -V INA- The signal directly represents the magnitude and direction of the operating current. Since the common-mode noise (such as power supply noise, ground bounce noise, etc.) contained in the two signals is canceled out during differential amplification, the differential scheme has stronger anti-common-mode interference capability and higher signal fidelity compared to the single-ended scheme.

[0106] The beneficial effects of the embodiments of this application are as follows: By configuring sampling units for the positive and negative terminals of each phase, synchronous sampling and independent holding of differential analog signals are achieved, and the positive and negative signals of each phase are completely consistent at the sampling time.

[0107] The positive and negative signals of each phase are respectively combined into two signal buses, which are connected to a shared fully differential operational amplifier. All phases share a single differential amplification and quantization circuit, which maximizes chip area and power consumption while achieving differential amplification.

[0108] Differential signal transmission effectively suppresses common-mode noise (such as power supply noise, ground bounce noise, electromagnetic interference, etc.), improves the signal-to-noise ratio and anti-interference capability, and is particularly suitable for application scenarios with complex electromagnetic environments or long-distance transmission.

[0109] Example 7 One embodiment of the present invention provides a synchronous sampling circuit for a multiphase drive system, suitable for differential analog signal scenarios. Figure 9 This is a schematic diagram of the synchronous sampling circuit of the multiphase drive system in Embodiment 7 of the present invention, as shown below. Figure 9 As shown, the difference between Embodiment 7 and Embodiment 6 of the present invention is as follows: In this embodiment of the invention, the signal amplification module can also adopt the structure of multiple independent amplification sub-units described in Embodiment 5, with independent amplifiers configured for the positive and negative terminals of each phase to achieve parallel amplification of the signals of each phase. For example, for phase A, a fourth sub-amplification unit 2014 is set up to sample the negative analog signal V from the thirteenth sampling unit 113. INA- The positive analog signal V sampled by the fourteenth sampling unit 114 INA+ Amplification is performed. For example, for phase B, a fifth sub-amplifier unit 2015 is set up to sample the negative analog signal V from the fifteenth sampling unit 115. INB- The positive analog signal V sampled by the sixteenth sampling unit 116 INB+ Amplification is performed. For example, for phase C, a sixth sub-amplifier unit 2016 is set up to sample the negative analog signal V from the seventeenth sampling unit 117. INC- The positive analog signal V sampled by the eighteenth sampling unit 118 INC+ Enlarge it.

[0110] The working process of this application embodiment is as follows: The synchronous sampling phase is similar to the synchronous sampling process in Example 6, except that two sampling units (positive and negative terminals) are operated simultaneously in each phase. Taking phase A as an example, in the synchronous sampling phase, the first and second switches of the thirteenth sampling unit 113 and the fourteenth sampling unit 114 are closed simultaneously, while the third and fourth switches remain open.

[0111] At this time, the sampling capacitor C A+ The first terminal is connected to the positive analog signal V INA+ The second end is connected to V CM Sampling capacitor C A- The first terminal is connected to the negative analog signal V INA- The second end is connected to V CM The two sampling capacitors are charged synchronously, and the voltage difference between the two sampling capacitors is (V). INA+ - V CM ) and (V INA- -V CM At the same time, the positive and negative sampling units of phase B and phase C perform the same operation synchronously to ensure that all sampling actions are completed at the same moment.

[0112] After sampling is complete, ensuring that the first switches of all phases open simultaneously on the same clock edge ensures perfect time alignment of the three differential signal samples, achieving true synchronous sampling. Other operations do not require strict time synchronization between different phases, making them easy to implement. After sampling is complete and all second switches are open, each sampling capacitor enters a high-impedance holding state.

[0113] Then, the sampled voltage signals held by each phase are amplified synchronously. Taking phase A as an example, the reset switch S is closed first. R+ and S R- For the feedback capacitor C F+ and C F- Perform a reset and clear the data, then disconnect the reset switch. Next, close the third switch corresponding to A (S1 of the fourteenth sampling unit 114). A3+ and the S of the thirteenth sampling unit 113 A3- ) and the fourth switch (S of the fourteenth sampling unit 114) A4+ and the S of the thirteenth sampling unit 113 A4- At this time, the output of the sampling unit will be clamped to V. CM Therefore, the voltage difference across the sampling capacitor will become V. REF -V CM That is, -V CM This allows the sampling voltage signal (V) held on the sampling capacitors at the positive and negative terminals of phase A to be further processed. INA- and V INA+ The inverting and non-inverting inputs of the sub-fully differential operational amplifier F1 are respectively connected. The sub-fully differential operational amplifier F1 amplifies the differential input signals, and its non-inverting and inverting outputs output the amplified positive and inverted signals, respectively. After the amplified signals of each phase have stabilized, the output switches of the corresponding phases are closed sequentially. Taking phase A as an example, the output switch S is closed. AA+ and S AA- The differential amplified signal is sent to the analog-to-digital converter A1 to complete the quantization.

[0114] Example 8 One embodiment of the present invention provides a synchronous sampling circuit for a multiphase drive system, suitable for differential analog signal scenarios.

[0115] Figure 10 This is a schematic diagram of the synchronous sampling circuit of the multiphase drive system in Embodiment 8 of the present invention, as shown below. Figure 10 As shown, the difference between Embodiment 8 and Embodiment 7 of the present invention is as follows: In the embodiments of this application, for two sampling units in the same phase, the two third switches are removed, and instead, a common switch is used to connect two sampling capacitors in series. For example, taking phase A as an example, compared to embodiment 7, S is removed. A3+ and S A3+ Two switches were used, with the addition of a common switch S. A Public switch S A The two ends are respectively connected to the sampling capacitor C C+ and sampling capacitor C C+ The first end.

[0116] In other embodiments, the sampling unit can be improved based on Embodiment 3. Each sampling unit includes only a sampling capacitor and a first switch, and a common switch is provided between two sampling units in the same phase. The two ends of the common switch are respectively connected to the first ends of the sampling capacitors in the two sampling units. That is, the second switch in the sampling unit of Embodiment 3 is removed, and a common switch is added.

[0117] The working process of this application embodiment is as follows: In the synchronous sampling phase, similar to the synchronous sampling process in Example 7, taking phase A as an example, during the synchronous sampling phase, the first switch (S) of the two sampling units of phase A is controlled. A+ and S A- The first and second switches are closed simultaneously, while the common switch and the fourth switch remain open. At this time, the sampling capacitor C... A+ The first terminal is connected to the positive analog signal V INA+ The second end is connected to V CM Sampling capacitor C A- The first terminal is connected to the negative analog signal V INA- The second end is connected to V CM The two sampling capacitors are charged synchronously, and the voltage difference between the two sampling capacitors is (V). INA+ - V CM ) and (V INA -V CM Simultaneously, the positive and negative sampling units of phases B and C perform the same operation, ensuring that all sampling actions are completed at the same time. After sampling, the first switches of all phases are ensured to open simultaneously on the same clock edge, achieving complete time alignment of the three differential signal samplings and realizing true synchronous sampling. Other operations do not require strict time synchronization between different phases, making them easy to implement. After all second switches are opened, each sampling capacitor enters a high-impedance holding state.

[0118] Then, the sampled voltage signals held by each phase are amplified synchronously. Taking phase A as an example, the reset switch S is closed first. R+ and S R- For the feedback capacitor CF+ and C F- Perform a reset and clear the system, then disconnect the reset switch. Next, close the common switch S corresponding to A. A And the fourth switch, at this time the output of the sampling unit will be clamped to V. CM The first terminal of the sampling capacitor will become the floating virtual ground voltage V. float Therefore, the voltage difference across the sampling capacitor will become V. float -V CM This allows the sampling voltage signal (V) held on the sampling capacitors at the positive and negative terminals of phase A to be further processed. INA- and V INA+ The inverting and non-inverting inputs of the sub-fully differential operational amplifier F1 are respectively connected to the floating virtual ground voltage, and the common-mode component introduced by the floating virtual ground voltage is eliminated by the common-mode feedback circuit. The sub-fully differential operational amplifier F1 amplifies the differential input signal, and its non-inverting and inverting outputs output the amplified positive and inverted signals, respectively. After the amplified signals of each phase have stabilized, the output switches of the corresponding phases are closed sequentially. Taking phase A as an example, the output switch S is closed. AA+ and S AA- The differential amplified signal is sent to the analog-to-digital converter A1 to complete the quantization.

[0119] Example 9 This application provides a driver chip, including the synchronous sampling circuit of the multiphase drive system described above.

[0120] During operation, the internal synchronous sampling circuit 10 of the chip automatically samples and holds the voltage across the three-phase sampling resistors at specific moments in each PWM cycle or control cycle. This data is then converted into digital quantities in a time-division multiplexing manner and output to the internal MCU or an external controller via a communication interface. Because the sampling is synchronous, the three-phase current data acquired by the controller can be directly used for field-oriented control (FOC) or other multi-phase cooperative algorithms without software compensation.

[0121] The advantages of this embodiment are as follows: By integrating the synchronous sampling function into the driver chip, users do not need external synchronous sampling circuits or high-speed ADCs, simplifying system design and reducing material costs. Simultaneously, the chip's internal synchronization timing can precisely match the PWM switching state, ensuring that the sampling time is within the window of minimum current ripple, further improving the sampling signal-to-noise ratio.

[0122] The above description is merely a partial embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0123] Furthermore, although the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the invention. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0124] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A synchronous sampling circuit for a multiphase drive system, characterized in that, include: The sample-and-hold module is used to synchronously sample and hold the analog signals representing the operating current in each phase of the multiphase drive system as sampled voltage signals. The analog signals are single-channel analog signals or dual-channel analog signals. The dual-channel analog signals include a positive analog signal and a negative analog signal. A signal amplification module is connected to the output terminal of the sample-and-hold module and is used to amplify and output the sampled voltage signals held in each phase. An analog-to-digital converter is connected to the output of the signal amplification module and is used to convert the corresponding amplified sampled voltage signals into digital signals and then output them.

2. The synchronous sampling circuit of the multiphase drive system according to claim 1, characterized in that, The sample-and-hold module includes multiple sampling units, each sampling unit corresponding to one analog signal setting of one phase of the multiphase drive system. Each sampling unit includes a sampling capacitor, and the sampling unit is used to hold the sampled voltage signal in the sampling capacitor respectively.

3. The synchronous sampling circuit of the multiphase drive system according to claim 2, characterized in that, The sampling unit includes: The sampling capacitor includes a first terminal and a second terminal, with the second terminal serving as the output terminal; The first switch receives an analog signal representing the operating current in one phase of the multiphase drive system at one end, and is connected to the first end of the sampling capacitor at the other end. The second switch has one end connected to the second terminal of the sampling capacitor and the other end connected to the common-mode voltage terminal. The third switch has one end connected to the reference voltage terminal and the other end connected to the first terminal of the sampling capacitor. The fourth switch has one end connected to the second end of the sampling capacitor and the other end as the output terminal.

4. The synchronous sampling circuit of the multiphase drive system according to claim 2, characterized in that, The analog signal is a dual-channel analog signal; each channel is equipped with two sampling units, used to sample the positive analog signal and the negative analog signal respectively, and each sampling unit includes: The sampling capacitor includes a first terminal and a second terminal, with the second terminal serving as the output terminal; The first switch receives an analog signal of the corresponding polarity at one end and is connected to the first end of the sampling capacitor at the other end. The second switch has one end connected to the second terminal of the sampling capacitor and the other end connected to the common-mode voltage terminal. The fourth switch has one end connected to the second terminal of the sampling capacitor, and the other end is the output terminal; A common switch is provided between the two sampling units of the same phase, and the two ends of the common switch are respectively connected to the first end of the sampling capacitor in the two sampling units.

5. The synchronous sampling circuit of the multiphase drive system according to claim 2, characterized in that, The sampling unit includes: The sampling capacitor includes a first terminal and a second terminal, with the second terminal serving as the output terminal; The first switch receives an analog signal representing the operating current in one phase of the multiphase drive system at one end, and is connected to the first end of the sampling capacitor at the other end. The second switch has one end connected to the reference voltage terminal and the other end connected to the first terminal of the sampling capacitor.

6. The synchronous sampling circuit of the multiphase drive system according to claim 2, characterized in that, The analog signal is a dual-channel analog signal; each channel is equipped with two sampling units, used to sample the positive analog signal and the negative analog signal respectively, and each sampling unit includes: The sampling capacitor includes a first terminal and a second terminal, with the second terminal serving as the output terminal; The first switch receives an analog signal of the corresponding polarity at one end and is connected to the first end of the sampling capacitor at the other end. A common switch is provided between the two sampling units of the same phase, and the two ends of the common switch are respectively connected to the first end of the sampling capacitor in the two sampling units.

7. The synchronous sampling circuit of the multiphase drive system according to claim 2, characterized in that, The signal amplification module includes: A shared operational amplifier is provided, with its first signal input terminal connected to the output terminal of each of the sampling units, and its inverting output terminal corresponding to the first signal input terminal outputting the amplified sampling voltage signal. A feedback capacitor is connected in parallel between the first signal input terminal and the inverting output terminal of the shared operational amplifier; A reset switch is connected in parallel across the feedback capacitor.

8. The synchronous sampling circuit of the multiphase drive system according to claim 7, characterized in that, The signal amplification module further includes: The time-sharing output switch has its first terminal connected to the inverting output terminal of the shared operational amplifier and its second terminal connected to the input terminal of the analog-to-digital converter.

9. The synchronous sampling circuit of the multiphase drive system according to claim 2, characterized in that, The signal amplification module includes multiple amplification sub-units, each corresponding to a sampling unit, including: The sub-operational amplifier has its first signal input terminal connected to the output terminal of the corresponding sampling unit, and its inverting output terminal corresponding to the first signal input terminal outputs the amplified sampling voltage signal. A sub-feedback capacitor is connected in parallel between the first signal input terminal and the inverting output terminal of the sub-operational amplifier; A sub-reset switch is connected in parallel across the sub-feedback capacitor; The sub-output switch has one end connected to the inverting output terminal of the sub-operational amplifier and the other end connected to the input terminal of the analog-to-digital converter.

10. A synchronous sampling method for a multiphase drive system, characterized in that, include: The analog signals characterizing the operating current in each phase of the multiphase drive system are synchronously sampled, and the sampled analog signals are kept as sampled voltage signals. The analog signals are single-channel analog signals or dual-channel analog signals, and the dual-channel analog signals include positive analog signals and negative analog signals. The sampled voltage signals held in each phase are amplified and then output; The amplified corresponding sampled voltage signals are then converted from analog to digital and output.

11. The synchronous sampling method for a multiphase drive system according to claim 10, characterized in that, The specific steps for amplifying and outputting the sampled voltage signals held by each phase include: The sampled voltage signals held by each phase are amplified sequentially through a shared amplification path in a time-division manner and then output in a time-division manner.

12. The synchronous sampling method for a multiphase drive system according to claim 8, characterized in that, The specific steps for amplifying and outputting the sampled voltage signals held by each phase include: The sampled voltage signals held by each phase are amplified in parallel through their respective independent amplification paths, and the amplified signals of each phase are then output in a time-division multiplexing manner.

13. A driver chip, characterized in that, The system includes a synchronous sampling circuit for the multiphase drive system as described in any one of claims 1-9.

Images