Successive comparison type AD converter, integrated circuit, AD converter, and comparator

Abstract

The present application provides a successive comparison type AD converter, an integrated circuit, an AD converter, and a comparator, which can suppress variation in offset error of a comparison circuit caused by variation in transistor characteristics based on NBTI or PBTI, etc. The successive comparison type AD converter is provided with a comparison circuit and a switching circuit. The comparison circuit can perform comparison of a comparison potential input to a first input terminal and a second input terminal and a reference potential, and output a comparison result as a result of the comparison at an output terminal. The switching circuit can switch from a first period to a second period, or from the second period to the first period, every time one or more AD conversion periods elapse. The first period is a period in which the comparison potential is input to the first input terminal and the reference potential is input to the second input terminal. The second period is a period in which the comparison potential is input to the second input terminal and the reference potential is input to the first input terminal.

Description

Technical Field

[0001] This disclosure relates to successive approximation analog-to-digital converters, integrated circuits, analog-to-digital converters, and comparators. Background Technology

[0002] In recent years, analog-to-digital (A / D) converters that convert analog signals to digital signals have been incorporated into all electronic devices. In particular, successive approximation A / D converters, which are low-cost, high-performance, and widely applicable, have recently become known. Successive approximation A / D converters are characterized by their ability to be implemented with relatively simple circuit structures, high compatibility with CMOS processes, and relatively inexpensive manufacturing. Therefore, they are widely used in various applications. For example, successive approximation A / D converters are used as A / D converters integrated into integrated circuits such as microcontrollers (MCUs).

[0003] In addition, it is known that the characteristics of MOS transistors change over time.

[0004] For example, in PMOS transistors, NBTI (Negative Bias Temperature Instability) is known. On the other hand, in NMOS transistors, PBTI (Positive Bias Temperature Instability) is known. NBTI refers to the phenomenon where, when a negative bias voltage is applied to a PMOS transistor, the transistor is exposed to a high-temperature environment for an extended period, causing changes in its characteristics. PBTI refers to the phenomenon where, when a positive bias voltage is applied to an NMOS transistor, the transistor is exposed to a high-temperature environment for an extended period, causing changes in its characteristics.

[0005] For example, Patent Document 1 discloses an AD converter using NMOS transistors and PMOS transistors. For example, Patent Document 2 and Non-Patent Documents 1-3 disclose NBTI and PBTI.

[0006] Patent Document 1: Japanese Patent Application Publication No. 5-346441

[0007] Patent Document 2: Japanese Patent Application Publication No. 2004-282121

[0008] Non-Patent Document 1: 2008 IEEE ELECTRON DEVICE LETTERS, VOL.29, NO.4, APRIL 2008 "PBTI-Associated High-Temperature Hot Carrier Degradation of nMOSFETs With Metal-Gate / High-k Dielectrics" Kyong Taek Lee, Chang Yong Kang, Senior Member, IEEE, Ook Sang Yoo, Rino Choi, Senior Member, IEEE, Byoung Hun Lee, Senior Member, IEEE, Jack C. Lee, Fellow, IEEE, Hi-Deok Lee, Member, IEEE, and Yoon-Ha Jeong, Senior Member, IEEE

[0009] Non-Patent Document 2: 2014 IEEE International Reliability Physics Symposium "Suitability of high-k gate oxides for III-V devices: A PBTI study in In0.53Ga0.47As devices with Al2O3" J. Franco; A. Alian; B. Kaczer; D. Lin; T. Ivanov; A. Pourghaderi

[0010] Non-Patent Document 3: 2015 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL.23, NO.7, JULY 2015 "A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k / Metal Gate Technology" Tony Tae-Hyoung Kim, Pong-Fei Lu, Keith A. Jenkins, and Chris H. Kim

[0011] When a MOS transistor is used in a comparator circuit, the transistor characteristics can vary due to factors such as NBTI or PBTI. This causes the comparator circuit's offset error to change over time, making it difficult to maintain the accuracy of the analog circuit in the long term. To address this, Patent Document 2 discloses a technique where the voltage required for the MOS transistor to operate is applied to each terminal only when the transistor is intended to operate; otherwise, the voltage at each terminal is kept constant. In the invention described in Patent Document 2, during the period when the voltage at each terminal of the MOS transistor is kept constant, variations in transistor characteristics caused by NBTI or PBTI are avoided, thus delaying the long-term variation of the comparator circuit's offset error. Summary of the Invention

[0012] However, when the technology described in Patent Document 2 is applied to applications such as the comparator circuit of an AD converter that requires the MOS transistor to operate almost continuously without rest, the effect of delaying the annual variation of the comparator circuit's offset error is relatively low. It is desirable to provide successive approximation AD converters, integrated circuits, AD converters, and comparators that can suppress variations in the comparator circuit's offset error caused by variations in the characteristics of transistors based on NBTI or PBTI.

[0013] One embodiment of this disclosure provides a successive approximation type AD converter capable of converting an analog input potential into an n-bit digital signal. This successive approximation type AD converter includes a comparison potential generation circuit, a comparator circuit, a first switching circuit, and a digital signal generation circuit. The comparison potential generation circuit generates a comparison potential for each bit based on the analog input potential. The comparator circuit compares the comparison potential generated by the comparison potential generation circuit with a reference potential. The first switching circuit is disposed before the comparator circuit. The digital signal generation circuit generates an n-bit digital signal based on the comparison result of the comparator circuit.

[0014] In this successive approximation type AD converter, the comparator circuit has a first input terminal and a second input terminal for input comparison potential and reference potential, and an output terminal for outputting the comparison result.

[0015] The comparator circuit compares the comparison potential input to the first and second input terminals with a reference potential, and outputs the comparison result at the output terminal. The period during which the comparison potential of an n-bit quantity is input to the comparator circuit is defined as the AD conversion period. At this time, the first switching circuit can switch from the first period to the second period, or from the second period to the first period, whenever one or more AD conversion periods have elapsed. The first period is the period during which the comparison potential is input to the first input terminal and the reference potential is input to the second input terminal. The second period is the period during which the comparison potential is input to the second input terminal and the reference potential is input to the first input terminal.

[0016] One embodiment of the integrated circuit disclosed herein includes one or more processors and one or more peripheral devices connected to the processors. One of the peripheral devices is a successive approximation analog-to-digital converter (ADC) that converts an analog input potential into an n-bit digital signal. This successive approximation ADC has the same structure as the successive approximation ADC described above.

[0017] An embodiment of the present disclosure provides an analog-to-digital converter (ADC) comprising a comparison potential generation circuit, a comparison circuit, a switching circuit, and a digital signal generation circuit. The comparison potential generation circuit generates a comparison potential based on an analog input potential. The comparison circuit has a first input terminal and a second input terminal, and is capable of comparing a pair of input potentials input to the first and second input terminals. The switching circuit switches between a first period and a second period. The first period is the period during which the comparison potential is input to the first input terminal and a reference potential is input to the second input terminal. The second period is the period during which the comparison potential is input to the second input terminal and a reference potential is input to the first input terminal. The digital signal generation circuit generates a digital signal based on the comparison result, synchronized with the switching operation of the switching circuit.

[0018] One embodiment of the comparator disclosed herein includes a comparison circuit and a switching circuit. The comparison circuit has a first input terminal and a second input terminal, and is capable of comparing a pair of input potentials input to the first input terminal and the second input terminal with each other. The switching circuit is capable of switching between a first period and a second period. The first period is the period during which a comparison potential is input to the first input terminal and a reference potential is input to the second input terminal. The second period is the period during which a comparison potential is input to the second input terminal and a reference potential is input to the first input terminal.

[0019] In a successive approximation type AD converter and integrated circuit according to one embodiment of this disclosure, in the comparator circuit, a comparison of the comparison potential and the reference potential input to the first input terminal and the second input terminal is performed, and the comparison result as the comparison result is output at the output terminal. Furthermore, in the first switching circuit, the voltage input to the first input terminal and the second input terminal is alternately switched every one or more AD conversion periods. Here, in the MOS transistor, the rate of change of transistor characteristics caused by NBTI or PBTI, etc., has a predetermined correlation with the magnitude of the gate potential and the degree of time change. The magnitude of the voltage input to the first input terminal and the degree of time change of the potential are called the first stress. The magnitude of the voltage input to the second input terminal and the degree of time change of the potential are called the second stress. At this time, by alternately switching the voltage input to the first input terminal and the second input terminal at a predetermined period, the first stress and the second stress accumulated over time can be made equal to each other. As a result, the variation in the offset error of the comparator circuit caused by the variation of transistor characteristics based on NBTI or PBTI, etc., can be suppressed.

[0020] In one embodiment of the AD converter and comparator disclosed herein, a comparison between a pair of input potentials input to a first input terminal and a second input terminal is performed in the comparator circuit. Furthermore, the voltage input to the first and second input terminals is switched in the switching circuit. Here, in the MOS transistor, the rate of change in transistor characteristics caused by NBTI or PBTI, etc., is correlated with the magnitude and time-varying degree of the gate potential of the MOS transistor. The magnitude and time-varying degree of the potential of the voltage input to the first input terminal are referred to as the first stress. The magnitude and time-varying degree of the potential of the voltage input to the second input terminal are referred to as the second stress. By switching the voltage input to the first and second input terminals at a predetermined period, the first and second stresses accumulated over time can be made equal. As a result, variations in the offset error of the comparator circuit caused by variations in transistor characteristics based on NBTI or PBTI, etc., can be suppressed. Attached Figure Description

[0021] The accompanying drawings are provided to further understand this disclosure, are incorporated in this specification, and form part of this specification. The drawings illustrate one embodiment and, together with the description, serve to illustrate the principles of this disclosure.

[0022] Figure 1 This is a diagram illustrating an example of the circuit structure of a successive approximation type AD converter according to a first embodiment of the present disclosure.

[0023] Figure 2 It is shown Figure 1 A diagram illustrating an example of the circuit structure of a comparison circuit.

[0024] Figure 3 This shows the input to Figure 1 A diagram illustrating an example of how the comparison potential and reference potential of a comparator circuit change over time.

[0025] Figure 4 It conceptually illustrates the process of inputting to the converter each time an A / D conversion occurs. Figure 1 A diagram showing the switching between the comparison potential and the reference potential in the comparison circuit.

[0026] Figure 5 It conceptually illustrates the input to... Figure 1 A diagram showing the switching between the comparison potential and the reference potential in the comparison circuit.

[0027] Figure 6 It is shown Figure 1 A diagram showing a variation of the circuit structure of a successive approximation type AD converter.

[0028] Figure 7 It is shown Figure 1 A diagram showing a variation of the circuit structure of a successive approximation type AD converter.

[0029] Figure 8 It is shown Figure 1 A diagram showing a variation of the circuit structure of a successive approximation type AD converter.

[0030] Figure 9 It is shown Figure 1 A diagram showing a variation of the circuit structure of a successive approximation type AD converter.

[0031] Figure 10 It is shown Figure 1 A diagram showing a variation of the circuit structure of a successive approximation type AD converter.

[0032] Figure 11 This is a diagram illustrating an example of the functional blocks of an integrated circuit according to a second embodiment of the present disclosure.

[0033] Figure 12 It is shown Figure 11 A diagram showing an example of the circuit structure of a comparator.

[0034] Figure 13 It is shown Figure 11 A diagram of a variant example of a functional block of an integrated circuit.

[0035] Label Explanation

[0036] 10…Successive approximation AD converter; 20…Comparator; 30…GPIO; 40…Processor; 50…Memory; 60…AD converter; 100…Capacitor DAC; 200…Reference potential generator; 300…Comparator circuit; 310…Operational amplifier; 320…Latch circuit; 400, 410, 420, 430, 440…Conversion data generator; 500, 600…Switching circuit; 510, 520, 620…Switching element; 610…NOT… Gate circuit; 700… Switching control circuit; Ctl1, Ctl2… Control signals; Dout… Digital signal; P1, P2… Input terminals; P3… Output terminal; T1… First period; T2… Second period; Tad… AD conversion period; V1, V2, Va, Vi, Vn… Comparison potentials; Vb, Vcmp, Vcmp', Vout… Comparison result; Vcc… Power supply potential; Vin… Analog signal; Vref… Reference potential; Vss… Ground potential. Detailed Implementation

[0037] <1. Background>

[0038] In recent years, analog-to-digital (A / D) converters that convert analog signals to digital signals have been incorporated into all electronic devices. In particular, successive approximation A / D converters, which are low-cost, high-performance, and widely applicable, have recently become known. Successive approximation A / D converters are characterized by their ability to be implemented with relatively simple circuit structures, high compatibility with CMOS processes, and relatively inexpensive manufacturing. Therefore, they are widely used in various applications. For example, successive approximation A / D converters are used as A / D converters integrated into integrated circuits such as microcontrollers (MCUs).

[0039] Furthermore, it is known that the characteristics of MOS transistors change over time. For example, in PMOS transistors, the NBTI (Non- ...

[0040] When a MOS transistor is used in a comparator circuit, the transistor characteristics can vary due to factors such as NBTI or PBTI. This causes the comparator circuit's offset error to change over time, making it difficult to maintain the accuracy of the analog circuit over the long term. To address this, Patent Document 2 discloses a technique where the voltage required for the MOS transistor's operation is applied to each terminal only when the transistor needs to be operated; otherwise, the voltage at each terminal is kept constant. In the invention described in Patent Document 2, during the period when the voltage at each terminal of the MOS transistor is kept constant, variations in transistor characteristics caused by NBTI or PBTI are prevented, thus delaying the long-term variation of the comparator circuit's offset error.

[0041] However, when the technology described in Patent Document 2 is applied to applications such as the comparator circuit of an AD converter that requires the MOS transistor to operate almost continuously without rest, the effect of delaying the annual variation of the comparator circuit's offset error is relatively low. It is desirable to provide successive approximation AD converters, integrated circuits, AD converters, and comparators that can suppress variations in the comparator circuit's offset error caused by variations in the characteristics of transistors based on NBTI or PBTI.

[0042] Hereinafter, several exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, the following description represents a specific example of the present disclosure and should not be construed as limiting the present disclosure. For example, elements including numerical values, circuits, the positions of each circuit, and the connection methods of each circuit are merely examples and should not be construed as limiting the present disclosure. Additionally, in the following exemplary embodiments, constituent elements not described in the independent items based on the highest-level concept of the present disclosure are arbitrary and can be designed as needed. The accompanying drawings are schematic and are not intended to be drawn to their original dimensions. In this specification and the accompanying drawings, constituent elements having substantially the same function and substantially the same structure are labeled with the same reference numerals, and repeated descriptions are omitted. Furthermore, constituent elements not directly related to an embodiment of the present disclosure are not shown in the accompanying drawings.

[0043] <2. First Implementation Method>

[0044] [structure]

[0045] Figure 1 An example of a functional block of a successive approximation type AD converter 10 according to a first embodiment of this disclosure is shown. The successive approximation type AD converter 10 is capable of converting an externally input analog signal Vin into an n-bit digital signal Dout. For example... Figure 1 As shown, the successive approximation type AD converter 10 includes, for example, a capacitor DAC 100, a reference potential generator 200, a comparator circuit 300, a conversion data generator 400, switching circuits 500 and 600, and a switching control circuit 700.

[0046] The successive approximation type AD converter 10 corresponds to a specific example of a "successive approximation type AD converter" or "AD converter" according to an embodiment of this disclosure. The capacitor DAC 100 corresponds to a specific example of a "comparison potential generation circuit" according to an embodiment of this disclosure. The comparator circuit 300 corresponds to a specific example of a "comparator circuit" according to an embodiment of this disclosure. The conversion data generator 400 corresponds to a specific example of a "digital signal generation circuit" according to an embodiment of this disclosure. The switching circuit 500 corresponds to a specific example of a "first switching circuit" or "switching circuit" according to an embodiment of this disclosure. The switching circuit 600 corresponds to a specific example of a "second switching circuit" according to an embodiment of this disclosure. The switching control circuit 700 corresponds to a specific example of a "control signal generation circuit" according to an embodiment of this disclosure. The circuit including the comparator circuit 300 and the switching circuits 500 and 600 corresponds to a specific example of a "comparator" according to an embodiment of this disclosure.

[0047] The capacitor DAC100 is configured as an array of capacitor elements having multiple capacitor elements and an array of switching elements having multiple switching elements. The capacitance of each capacitor element is, for example, defined by n bits of binary code. One end of each capacitor element is connected to a common node. The other end of each capacitor element is connected to a switching element. One switching element is allocated for each capacitor element. The switching element array allows each capacitor element's other end to be independently connected to any one of three wirings. These three wirings are, for example, a wiring for applying the analog signal Vin's potential (analog input potential), a wiring for applying the Lo reference potential, and a wiring for applying the Hi reference potential. The capacitor DAC100 is not limited to the above structure and may have a different structure.

[0048] The capacitor DAC 100 can generate a comparison potential Vi based on the sampled and held analog input potential. The capacitor DAC 100 can generate a comparison potential Vi corresponding to the sampled and held analog input potential. The comparison potential Vi corresponds to a specific example of "comparison potential" or "input potential" in one embodiment of this disclosure. Since the n-bit successive approximation type AD converter 10 performs n comparison operations, the capacitor DAC 100 can generate n comparison potentials. Hereinafter, each comparison potential in the n comparison potential generation will be referred to as V1, V2, ..., Vi, ..., Vn.

[0049] The capacitor DAC100 can switch each switching element based on the control signal Ctl1 input from the conversion data generator 400. By switching each switching element, the capacitor DAC100 switches the connections of multiple capacitor elements that accumulate charge corresponding to the analog input potential, thereby sequentially outputting comparison potentials V1, V2, ..., Vi, ..., Vn to a common node. The potential waveforms of the comparison potentials V1, V2, ..., Vi, ..., Vn are as follows: Figure 3 The waveform shown is one where the wave height gradually converges toward the reference potential Vref. The reference potential Vref corresponds to a specific example of the "reference potential" or "input potential" in one embodiment of this disclosure.

[0050] The reference potential generator 200 is capable of generating a reference potential Vref. The reference potential generator 200 includes, for example, a voltage divider circuit capable of generating the reference potential Vref by dividing the potential difference between the power supply potential Vcc and the ground potential Vss. The voltage divider circuit is configured, for example, to include multiple resistive elements connected in series. The reference potential generator 200 is not limited to the above structure and may also have a different structure. When the voltage divider circuit consists of two resistive elements with equal resistance values, the reference potential Vref becomes half the potential difference between the power supply potential Vcc and the ground potential Vss.

[0051] Comparison circuit 300 is capable of comparing a pair of input potentials (comparison potential Vi and reference potential Vref) with each other. Comparison circuit 300 is capable of comparing comparison potential Vi with reference potential Vref and outputting a comparison result Vcmp as the result of its comparison. Comparison circuit 300, for example, has a pair of input terminals P1 and P2 for the input comparison potential Vi and reference potential Vref, and an output terminal P3 for the output comparison result Vcmp. Comparison circuit 300 may also be configured to include a comparator. The comparator included in comparison circuit 300, for example, is capable of comparing the comparison potential Vi and reference potential Vref input to input terminals P1 and P2, and outputting the comparison result Vcmp as the result of its comparison at output terminal P3.

[0052] Input terminal P1 corresponds to a specific example of a "first input terminal" in one embodiment of this disclosure. Input terminal P2 corresponds to a specific example of a "second input terminal" in one embodiment of this disclosure. Output terminal P3 corresponds to a specific example of an "output terminal" in one embodiment of this disclosure. Comparison result Vcmp corresponds to a specific example of a "comparison result" in one embodiment of this disclosure.

[0053] For example, such as Figure 2As shown, the comparator circuit 300 is configured to include an operational amplifier 310 and a latch circuit 320. The operational amplifier 310, for example, includes a current mirror type operational amplifier, capable of amplifying the potential difference between the comparison potential Vi and the reference potential Vref, and outputting the resulting potential as the comparison result to the latch circuit 320. The latch circuit 320 can hold the potential input from the operational amplifier 310 as the comparison result. The comparator circuit 300 is not limited to the above structure and may also have a different structure.

[0054] The conversion data generator 400 can generate a control signal Ctl1 based on the output of the comparator circuit 300 (comparison result Vcmp) and output it to the capacitor DAC100. The conversion data generator 400 can also successively accumulate the output of the comparator circuit 300 (comparison result Vcmp) and output an n-bit digital signal Dout. The conversion data generator 400 can synchronously generate the digital signal Dout based on the comparison result Vcmp in the comparator circuit 300 with the switching operation of the switching circuit 500.

[0055] The switching circuit 500 is located before the comparator circuit 300. The switching circuit 500 can input the comparison potential Vi obtained from the capacitor DAC100 and the reference potential Vref obtained from the reference potential generator 200 to a pair of input terminals P1 and P2 of the comparator circuit 300.

[0056] Figure 4 , Figure 5 An example of a potential input from the switching circuit 500 to a pair of input terminals P1 and P2 of the comparator circuit 300 is shown, as well as an example of a potential (signal) output from the output terminal P3 of the comparator circuit 300 and the switching circuit 600. Figure 4 , Figure 5 In this context, the period during which the n-bit comparison potentials V1, V2, ..., Vi, ..., Vn are sequentially input from the switching circuit 500 to the comparator circuit 300 is described as the AD conversion period Tad. The period during which the comparison potentials V1, V2, ..., Vi, ..., Vn are input to input terminal P1 and the reference potential Vref is input to input terminal P2 is described as the first period T1. The period during which the comparison potentials V1, V2, ..., Vi, ..., Vn are input to input terminal P2 and the reference potential Vref is input to input terminal P1 is described as the second period T2.

[0057] For example, Figure 4 , Figure 5 As shown, the switching circuit 500 can switch between the first period T1 and the second period T2. For example, as Figure 4As shown, the switching circuit 500 can switch the first period T1 to the second period T2 each time the AD conversion period Tad passes, and switch the second period T2 back to the first period T1. For example, as Figure 5 As shown, the switching circuit 500 is capable of switching the first period T1 to the second period T2 whenever multiple (e.g., two) AD conversion periods Tad have elapsed, and switching the second period T2 back to the first period T1.

[0058] For example, such as Figure 1 As shown, the switching circuit 500 includes switching elements 510 and 520. Switching element 510 corresponds to a specific example of a "first switching element" in one embodiment of this disclosure. Switching element 520 corresponds to a specific example of a "second switching element" in one embodiment of this disclosure. Switching element 510 is capable of inputting either the comparison potential Vi or the reference potential Vref to the input terminal P1. Switching element 520 is capable of inputting a potential from the comparison potential Vi and the reference potential Vref that is different from the potential input to the input terminal P1 to the input terminal P2. The switching circuit 500 is capable of switching the potential input to the input terminals P1 and P2 from the comparison potential Vi to the reference potential Vref, and vice versa, through the operation of switching elements 510 and 520 each time one or more AD conversion periods Tad have elapsed.

[0059] Switching elements 510 and 520 are both 2-input, 1-output switching elements. In switching element 510, one terminal ("0" terminal) is connected to the output of capacitor DAC100, and the other terminal ("1" terminal) is connected to the output of reference potential generator 200. In switching element 510, one terminal ("0" terminal) is input with a comparison potential Vi, and the other terminal ("1" terminal) is input with a reference potential Vref. In switching element 520, one terminal ("0" terminal) is connected to the output of reference potential generator 200, and the other terminal ("1" terminal) is connected to the output of capacitor DAC100. In switching element 520, one terminal ("0" terminal) is input with a reference potential Vref, and the other terminal ("1" terminal) is input with a comparison potential Vi.

[0060] When the switching element 510 receives a signal from the switching control circuit 700 indicating that terminal "0" should be selected as the control signal Ctl2, it can select terminal "0" and output the comparison potential Vi to input terminal P1. When the switching element 510 receives a signal from the switching control circuit 700 indicating that terminal "1" should be selected as the control signal Ctl2, it can select terminal "1" and output the reference potential Vref to input terminal P1. When the switching element 520 receives a signal from the switching control circuit 700 indicating that terminal "0" should be selected as the control signal Ctl2, it can select terminal "0" and output the reference potential Vref to input terminal P2. When the switching element 510 receives a signal from the switching control circuit 700 indicating that terminal "1" should be selected as the control signal Ctl2, it can select terminal "1" and output the comparison potential Vi to input terminal P2.

[0061] That is, when the switching circuit 500 receives a signal from the switching control circuit 700 indicating that terminal "0" is selected as the control signal Ctl2, it can output the comparison potential Vi to input terminal P1 and the reference potential Vref to input terminal P2. When the switching circuit 500 receives a signal from the switching control circuit 700 indicating that terminal "1" is selected as the control signal Ctl2, it can output the reference potential Vref to input terminal P1 and the comparison potential Vi to input terminal P2. The switching circuit 500 can switch the switching elements 510 and 520 according to the control signal Ctl2 input from the switching control circuit 700.

[0062] The switching circuit 600 is located after the comparison circuit 300. The switching circuit 600 can output either the comparison result Vcmp obtained from the comparison circuit 300 or the comparison result Vcmp' obtained by inverting the comparison result Vcmp as the comparison result Vout to the conversion data generator 400. For example, as... Figure 4 , Figure 5 As shown, the switching circuit 600 can output the comparison result Vcmp as the comparison result Vout to the conversion data generator 400 during the first period T1, and output the comparison result Vcmp' as the comparison result Vout during the second period T2.

[0063] For example, such as Figure 1As shown, the switching circuit 600 includes a NOT gate 610 and a switching element 620. The NOT gate 610 corresponds to a specific example of a "NOT gate" in one embodiment of this disclosure. The switching element 620 corresponds to a specific example of a "third switching element" in one embodiment of this disclosure. The NOT gate 610 is connected to the output terminal P3. The switching element 620 can output either the comparison result Vcmp or the output of the NOT gate 610 (comparison result Vcmp') as the comparison result Vout to the conversion data generator 400. The switching circuit 600 can switch the signal (comparison result Vout) output to the conversion data generator 400 from the comparison result Vcmp to the comparison result Vcmp', or from the comparison result Vcmp' to the comparison result Vcmp, by the operation of the switching element 620 during one or more AD conversion periods Tad. The switching circuit 600 can switch the switching element 620 according to the control signal Ctl2 input from the switching control circuit 700.

[0064] Switching element 620 is a 2-input, 1-output switching element. In switching element 620, one terminal ("0" terminal) is connected to output terminal P3, and the other terminal ("1" terminal) is connected to the output terminal of NOT gate 610. In switching element 620, one terminal ("0" terminal) is input with the comparison result Vcmp, and the other terminal ("1" terminal) is input with the comparison result Vcmp'.

[0065] When the switching element 620 is controlled by the signal indicating that the "0" terminal is selected from the switching control circuit 700 as the control signal Ctl2, it can select the "0" terminal and output the comparison result Vcmp as the comparison result Vout. When the switching element 620 is controlled by the signal indicating that the "1" terminal is selected from the switching control circuit 700 as the control signal Ctl2, it can select the "1" terminal and output the comparison result Vcmp' as the comparison result Vout.

[0066] That is, when the switching circuit 600 receives a signal from the switching control circuit 700 indicating that terminal "0" is selected as the control signal Ctl2, it can output a comparison result Vcmp as the comparison result Vout. When the switching circuit 600 receives a signal from the switching control circuit 700 indicating that terminal "1" is selected as the control signal Ctl2, it can output a comparison result Vcmp' as the comparison result Vout. The switching circuit 600 can switch the switching element 620 according to the control signal Ctl2 input from the switching control circuit 700.

[0067] The switching control circuit 700 can generate a control signal Ctl2 and output it to the switching circuits 500 and 600. The control signal Ctl2 corresponds to a specific example of the "first control signal" in one embodiment of this disclosure. The switching control circuit 700 can, for example, generate a signal indicating selection of terminal 0 (first selection signal) or a signal indicating selection of terminal 1 (second selection signal) as the control signal Ctl2. The switching control circuit 700 can, for example, generate the first selection signal as the control signal Ctl2 during a first period T1. The switching control circuit 700 can, for example, generate the second selection signal as the control signal Ctl2 during a second period T2.

[0068] [Effect]

[0069] Next, the effect of the successive approximation type AD converter 10 will be explained.

[0070] In this embodiment, in the comparator circuit, the comparison potential Vi and the reference potential Vref input to the input terminals P1 and P2 are compared, and the comparison result Vcmp, which is the result of the comparison, is output to the output terminal. Furthermore, in the switching circuit 500, the voltage input to the input terminals P1 and P2 is alternately switched every one or more AD conversion periods Tad. Here, in the MOS transistor, the rate of change in transistor characteristics caused by NBTI or PBTI, etc., has a predetermined correlation with the magnitude and time-varying degree of the gate potential of the MOS transistor. The magnitude and time-varying degree of the voltage potential input to the input terminal P1 are called the first stress. The magnitude and time-varying degree of the voltage potential input to the input terminal P2 are called the second stress. By alternately switching the voltage input to the input terminals P1 and P2 at a predetermined period, the first stress and the second stress accumulated over time can be made equal to each other. As a result, the variation in the offset error of the comparator circuit 300 caused by the variation in transistor characteristics based on NBTI or PBTI, etc., can be suppressed.

[0071] In this embodiment, whenever one or more AD conversion periods Tad occur, the potentials input to the input terminals P1 and P2 are switched from the comparator potential Vi to the reference potential Vref by the operation of switching elements 510 and 520, and then switched back to the comparator potential Vi. This ensures that the first and second stresses accumulated over time are equal. As a result, variations in the offset error of the comparator circuit 300 caused by variations in transistor characteristics based on NBTI or PBTI, etc., can be suppressed.

[0072] In this embodiment, whenever one or more AD conversion periods Tad occur, the signal output to the conversion data generator 400 is switched from the comparison result Vcmp to the output of the NOT gate 610 (comparison result Vcmp') or from the output of the NOT gate 610 (comparison result Vcmp') to the comparison result Vcmp by the operation of the switching element 620. Therefore, even when the voltage input to input terminals P1 and P2 is switched, the same potential is input to the conversion data generator 400 as when the voltage input to input terminals P1 and P2 is not switched. As a result, data processing can be performed in the conversion data generator 400 without considering the switching of the voltage input to input terminals P1 and P2.

[0073] In this embodiment, the switching elements 510 and 520 of the switching circuit 500 are switched according to the control signal Ctl2, and the switching element 620 of the switching circuit 600 is also switched. Therefore, even when the voltage input to input terminals P1 and P2 is switched, the same potential is input to the conversion data generator 400 as when the voltage input to input terminals P1 and P2 is not switched. As a result, data processing can be performed in the conversion data generator 400 regardless of the switching of the voltage input to input terminals P1 and P2.

[0074] In this embodiment, a switching control circuit 700 is provided that can generate control signals Ctl2 for the switching circuits 500 and 600. Therefore, for external systems capable of controlling the successive approximation type AD converter 10, no design changes are required to generate the control signals Ctl2 for the switching circuits 500 and 600.

[0075] <3. Variations of the First Embodiment>

[0076] Next, a variation of the successive approximation type AD converter 10 of the first embodiment described above will be explained.

[0077] [Variation A]

[0078] In the first embodiment described above, for example, as Figure 6As shown, alternatively, the switching control circuit 700 can be omitted, and a switching data generator 410, which also has the function of the switching control circuit 700, can be provided instead of the switching data generator 400. That is, the switching data generator 410 can generate a control signal Ctl2 and output it to the switching circuits 500 and 600. As the control signal Ctl2, the switching data generator 410 can, for example, generate a signal indicating the selection of terminal 0 (first selection signal) or a signal indicating the selection of terminal 1 (second selection signal). For example, the switching data generator 410 can generate the first selection signal as the control signal Ctl2 during the first period T1. For example, the switching data generator 410 can generate the second selection signal as the control signal Ctl2 during the second period T2.

[0079] In this modified example, a conversion data generator 410 is provided that also functions as a switching control circuit 700. This allows for the suppression of variations in the offset error of the comparator circuit 300 caused by variations in transistor characteristics based on NBTI or PBTI, etc. Furthermore, for external systems capable of controlling the successive approximation type AD converter 10, no design changes are required to generate the control signal Ctl2 for the switching control circuits 500 and 600.

[0080] [Variation B]

[0081] In the first embodiment described above, for example, as Figure 7 As shown, alternatively, the switching control circuit 700 can be omitted, and the control signal Ctl2 can be input to the successive approximation type AD converter 10 from an external system. In this case, the circuit design of the successive approximation type AD converter 10 can be simplified accordingly by omitting the switching control circuit 700.

[0082] [Variation C]

[0083] In the first embodiment and the variations A and B described above, for example, as Figure 8 , Figure 9 , Figure 10 As shown, the switching circuit 600 can also be omitted. Figure 8 It shows Figure 1 A variation of the circuit structure of the successive approximation type AD converter 10. Figure 9 It shows Figure 6 A variation of the circuit structure of the successive approximation type AD converter 10. Figure 10 It shows Figure 7 A variation of the circuit structure of the successive approximation type AD converter 10.

[0084] In this variation, conversion data generators 420, 430, and 440 are used instead of conversion data generators 400 and 410. Conversion data generators 420, 430, and 440 can perform either the first process or the second process described later, depending on the switching state of switching elements 510 and 520. Conversion data generators 420, 430, and 440 can perform either the first process or the second process according to the control signal Ctl2. The first process is to directly use the comparison result Vcmp to generate an n-bit digital signal Dout without inverting the comparison result Vcmp. The second process is to use the comparison result Vcmp' obtained by inverting the comparison result Vcmp to generate an n-bit digital signal Dout.

[0085] In this modified example, the switching circuit 600 is omitted, and either the first processing or the second processing is performed in the conversion data generators 420, 430, and 440. This reduces the circuit area accordingly, which is equivalent to omitting the switching circuit 600.

[0086] <4. Second Implementation>

[0087] [structure]

[0088] Figure 11 An example of a functional block of an integrated circuit 1000 according to a second embodiment of this disclosure is shown. The integrated circuit 1000 is a specific example of an "integrated circuit" according to one embodiment of this disclosure. The integrated circuit 1000 is an integrated circuit such as a microcontroller (MCU). For example, such as... Figure 11 As shown, the integrated circuit 1000 includes the successive approximation type AD converter 10 described in the first embodiment and the variations A to C described above.

[0089] For example, such as Figure 11 As shown, the integrated circuit 1000 includes one or more processors 40 and a memory 50 connected to the one or more processors 40. For example, as Figure 11 As shown, the integrated circuit 1000, as one or more peripheral devices connected to one or more processors 40, includes a successive approximation type AD converter 10, a comparator 20, and a GPIO (General Purpose Input Output) 30. One or more processors 40 correspond to a specific example of "one or more processors" in one embodiment of this disclosure. The successive approximation type AD converter 10, comparator 20, and GPIO 30 correspond to a specific example of "one or more peripheral devices" in one embodiment of this disclosure. The comparator 20 corresponds to a specific example of "comparator" in one embodiment of this disclosure.

[0090] For example, such as Figure 12As shown, comparator 20 includes a comparator circuit 300 and switching circuits 500 and 600. Comparator circuit 300 corresponds to a specific example of a "comparator circuit" according to one embodiment of this disclosure. Switching circuit 500 corresponds to a specific example of a "switching circuit" according to one embodiment of this disclosure.

[0091] The switching circuit 500 can input a comparison potential Va obtained from one or more processors 40 and a reference potential Vref obtained from a reference potential generation circuit capable of generating a reference potential Vref to a pair of input terminals P1 and P2 of the comparison circuit 300. The switching circuit 600 can output either the comparison result Vcmp obtained from the comparison circuit 300 or the comparison result Vcmp' obtained by inverting the comparison result Vcmp as the comparison result Vb to one or more processors 40. One or more processors 40 can input a control signal Ctl2 to the switching circuits 500 and 600.

[0092] GPIO30 is a general-purpose I / O port. GPIO30 can output digital signals from one or more processors 40 to external circuits. GPIO30 can also input digital signals from external circuits to one or more processors 40.

[0093] One or more processors 40, for example, can perform prescribed operations utilizing the functions of the successive approximation type AD converter 10, comparator 20, and GPIO 30 by executing programs stored in memory 50. The one or more processors 40 may be, for example, one or more CPUs (Central Processing Units). Memory 50 may be configured to include, for example, RAM (Random-access memory) or ROM (Read Only Memory).

[0094] In this embodiment, the successive approximation type AD converter 10 of the first embodiment and the above-described variations A to C is provided in the integrated circuit 1000. As a result, high-precision AD conversion can be achieved by a single integrated circuit 1000, which does not have the variation of offset error of the comparator circuit 300 in the comparator 20 caused by the variation of transistor characteristics based on NBTI or PBTI, etc.

[0095] In this embodiment, comparator 20 is provided in integrated circuit 1000. Through comparator 20, the voltage inputs to input terminals P1 and P2 are alternately switched in switching circuit 500. Here, in MOS transistors, the rate of change in transistor characteristics caused by NBTI or PBTI, etc., has a predetermined correlation with the magnitude and time-varying degree of the gate potential of the MOS transistor. The magnitude and time-varying degree of the voltage potential input to input terminal P1 are referred to as the first stress. The magnitude and time-varying degree of the voltage potential input to input terminal P2 are referred to as the second stress. By alternately switching the voltage inputs to input terminals P1 and P2 at a predetermined period, the first and second stresses accumulated over time can be made equal. As a result, variations in the offset error of the comparator circuit 300 within comparator 20 caused by variations in transistor characteristics based on NBTI or PBTI, etc., can be suppressed.

[0096] In this embodiment, for example, such as Figure 13 As shown, an AD converter 60, different from the successive approximation type, can be used instead of the successive approximation type AD converter 10. The AD converter 60 can be, for example, a single-slope type, a cyclic type, or a Δ-Σ type. The AD converter 60 is configured to include a comparator 20. The AD converter 60 is also configured to include a comparison potential generation circuit that generates a comparison potential Va based on the analog input potential and inputs it to the switching circuit 500. The comparison potential generation circuit can, for example, include a circuit consisting of multiple capacitor elements connected in a ladder configuration, or a circuit consisting of multiple resistor elements connected in a ladder configuration. The AD converter 60 is also configured to include a digital signal generation circuit that generates a digital signal Dout based on the comparison result Vcmp in the comparator circuit 300, synchronously with the switching operation of the switching circuit 600. In this modified example, in this embodiment, the AD converter 60 is used instead of the successive approximation type AD converter 10. Even under such circumstances, in the AD converter 60, the voltage inputs to the input terminals P1 and P2 are switched alternately at a predetermined period, thus suppressing the variation in the offset error of the comparator circuit 300 within the comparator 20 caused by variations in transistor characteristics based on NBTI or PBTI, etc.

[0097] The present disclosure has been illustrated above with examples of various embodiments and modifications, but it is not limited to these embodiments and modifications, and various modifications are possible. The effects described in this specification are merely examples, and the effects of the present disclosure are not limited to those described in this specification. Therefore, other effects can also be obtained with respect to this disclosure.

[0098] Furthermore, this disclosure can be made in the following ways.

[0099] <1>

[0100] A successive approximation type analog-to-digital converter (ADC) is used to convert an analog input potential into an n-bit digital signal, wherein... The successive approximation type AD converter has the following features: The comparison potential generation circuit is capable of generating a comparison potential for each bit based on the analog input potential; A comparator circuit capable of comparing a reference potential with a comparison potential generated by the comparison potential generation circuit; A first switching circuit is disposed before the comparator circuit; and A digital signal generation circuit that generates the n-bit digital signal based on the comparison result of the comparison circuit. The comparator circuit has a first input terminal and a second input terminal for receiving the comparison potential and the reference potential, and an output terminal for outputting the comparison result. The comparator circuit is capable of comparing the comparison potential and the reference potential input to the first input terminal and the second input terminal, and outputting the comparison result as the result of the comparison at the output terminal. When the period during which the comparison potential, which inputs an n-bit quantity to the comparison circuit, is defined as the AD conversion period, the first switching circuit is capable of switching from a first period during which the comparison potential is input to the first input terminal and the reference potential is input to the second input terminal, or from the second period to the first period, whenever one or more AD conversion periods have elapsed.

[0101] <2>

[0102] according to <1> The successive approximation type AD converter, wherein, The first switching circuit includes: a first switching element capable of inputting either the comparison potential or the reference potential to the first input terminal; and a second switching element capable of inputting a potential from the comparison potential and the reference potential that is different from the potential input to the first input terminal to the second input terminal. The first switching circuit is capable of switching the potential input to the first input terminal and the second input terminal from the comparison potential to the reference potential and vice versa, through the operation of the first switching element and the second switching element, whenever one or more of the AD conversions have passed.

[0103] <3>

[0104] according to <2> The successive approximation type AD converter, wherein, The successive approximation type AD converter also includes a second switching circuit disposed after the comparator circuit. The second switching circuit includes: a NOT gate circuit connected to the output terminal; and a third switching element capable of outputting either the comparison result or the output of the NOT gate circuit to the digital signal generation circuit. The second switching circuit is capable of switching the signal output to the digital signal generation circuit from the comparison result to the output of the NOT gate circuit, or from the output of the NOT gate circuit to the comparison result, by the action of the third switching element, whenever one or more of the AD conversions have passed.

[0105] <4>

[0106] according to <3> The successive approximation type AD converter, wherein, The first switching circuit is capable of switching the first switching element and the second switching element according to the first control signal. The second switching circuit is capable of switching the third switching element according to the first control signal.

[0107] <5>

[0108] according to <2> The successive approximation type AD converter, wherein, The digital signal generation circuit can perform either a first process or a second process based on the switching state of the first switching element and the second switching element. The first process is to directly use the comparison result to generate the n-bit digital signal without inverting the comparison result, and the second process is to use the result obtained by inverting the comparison result to generate the n-bit digital signal.

[0109] <6>

[0110] according to <5> The successive approximation type AD converter, wherein, The first switching circuit is capable of switching the first switching element and the second switching element according to the first control signal. The digital signal generation circuit can perform any of the first processing and the second processing according to the first control signal.

[0111] <7>

[0112] according to <4> or <6> The successive approximation type AD converter, wherein, The first control signal is input from an external circuit to the successive approximation type AD converter.

[0113] <8>

[0114] according to <4> or <6> The successive approximation type AD converter, wherein, The digital signal generation circuit is capable of generating the first control signal.

[0115] <9>

[0116] according to <4> or <6> The successive approximation type AD converter, wherein, The successive approximation type AD converter also includes a control signal generation circuit capable of generating the first control signal.

[0117] <10>

[0118] An integrated circuit, wherein, The integrated circuit comprises: One or more processors; and One or more peripheral devices connected to the one or more processors One of the one or more peripheral devices is a successive approximation type AD converter that converts an analog input potential into an n-bit digital signal. The successive approximation type AD converter has the following characteristics: The comparison potential generation circuit is capable of generating a comparison potential for each bit based on the analog input potential; A comparator circuit capable of comparing a reference potential with a comparison potential generated by the comparison potential generation circuit; A first switching circuit is disposed before the comparator circuit; and A digital signal generation circuit that generates the n-bit digital signal based on the comparison result of the comparison circuit. The comparator circuit has a first input terminal and a second input terminal for receiving the comparison potential and the reference potential, and an output terminal for outputting the comparison result. The comparator circuit is capable of comparing the comparison potential and the reference potential input to the first input terminal and the second input terminal, and outputting the comparison result as the result of the comparison at the output terminal. When the period during which the comparison potential, which inputs an n-bit quantity to the comparison circuit, is defined as the AD conversion period, the first switching circuit is capable of switching from a first period during which the comparison potential is input to the first input terminal and the reference potential is input to the second input terminal, or from the second period to the first period, whenever one or more AD conversion periods have elapsed.

[0119] <11>

[0120] An AD converter, comprising: The comparison potential generation circuit can generate a comparison potential based on the analog input potential; A comparator circuit having a first input terminal and a second input terminal, capable of comparing a pair of input potentials input to the first input terminal and the second input terminal with each other; A switching circuit capable of switching between a first period and a second period, wherein the first period is the period during which the comparison potential is input to the first input terminal and the reference potential is input to the second input terminal, and the second period is the period during which the comparison potential is input to the second input terminal and the reference potential is input to the first input terminal; and A digital signal generation circuit that can generate a digital signal based on the comparison result in the comparison circuit in sync with the switching action of the switching circuit.

[0121] <12>

[0122] A comparator that has: A comparator circuit having a first input terminal and a second input terminal, capable of comparing a pair of input potentials input to the first input terminal and the second input terminal; and A switching circuit capable of switching between a first period and a second period, wherein the first period is when a comparison potential is input to the first input terminal and a reference potential is input to the second input terminal, and the second period is when the comparison potential is input to the second input terminal and the reference potential is input to the first input terminal.

Claims

1. A successive approximation type analog-to-digital converter (ADC) capable of converting an analog input potential into an n-bit digital signal, wherein, The successive approximation type AD converter has the following features: The comparison potential generation circuit is capable of generating a comparison potential for each bit based on the analog input potential; A comparator circuit capable of comparing a reference potential with a comparison potential generated by the comparison potential generation circuit; A first switching circuit is disposed before the comparator circuit; as well as A digital signal generation circuit that generates the n-bit digital signal based on the comparison result of the comparison circuit. The comparator circuit has a first input terminal and a second input terminal for receiving the comparison potential and the reference potential, and an output terminal for outputting the comparison result. The comparator circuit is capable of comparing the comparison potential and the reference potential input to the first input terminal and the second input terminal, and outputting the comparison result as the result of the comparison at the output terminal. When the period during which the comparison potential, which inputs an n-bit quantity to the comparison circuit, is defined as the AD conversion period, the first switching circuit is capable of switching from a first period during which the comparison potential is input to the first input terminal and the reference potential is input to the second input terminal, or from the second period to the first period, whenever one or more AD conversion periods have elapsed.

2. The successive approximation type AD converter according to claim 1, wherein, The first switching circuit has: a first switching element, which is capable of inputting the potential of either the comparison potential or the reference potential to the first input terminal; And a second switching element, which is capable of inputting a potential that differs from the potential input to the first input terminal from the comparison potential and the reference potential to the second input terminal. The first switching circuit is capable of switching the potential input to the first input terminal and the second input terminal from the comparison potential to the reference potential and vice versa, through the operation of the first switching element and the second switching element, whenever one or more of the AD conversions have passed.

3. The successive approximation type AD converter according to claim 2, wherein, The successive approximation type AD converter also includes a second switching circuit disposed after the comparator circuit. The second switching circuit includes: a NOT gate circuit connected to the output terminal; and a third switching element capable of outputting either the comparison result or the output of the NOT gate circuit to the digital signal generation circuit. The second switching circuit is capable of switching the signal output to the digital signal generation circuit from the comparison result to the output of the NOT gate circuit, or from the output of the NOT gate circuit to the comparison result, by the action of the third switching element, whenever one or more of the AD conversions have passed.

4. The successive approximation type AD converter according to claim 3, wherein, The first switching circuit is capable of switching the first switching element and the second switching element according to the first control signal. The second switching circuit is capable of switching the third switching element according to the first control signal.

5. The successive approximation type AD converter according to claim 2, wherein, The digital signal generation circuit can perform either a first process or a second process based on the switching state of the first switching element and the second switching element. The first process is to directly use the comparison result to generate the n-bit digital signal without inverting the comparison result, and the second process is to use the result obtained by inverting the comparison result to generate the n-bit digital signal.

6. The successive approximation type AD converter according to claim 5, wherein, The first switching circuit is capable of switching the first switching element and the second switching element according to the first control signal. The digital signal generation circuit can perform any of the first processing and the second processing according to the first control signal.

7. The successive approximation type AD converter according to claim 4 or 6, wherein, The first control signal is input from an external circuit to the successive approximation type AD converter.

8. The successive approximation type AD converter according to claim 4 or 6, wherein, The digital signal generation circuit is capable of generating the first control signal.

9. The successive approximation type AD converter according to claim 4 or 6, wherein, The successive approximation type AD converter also includes a control signal generation circuit capable of generating the first control signal.

10. An integrated circuit, wherein, The integrated circuit comprises: One or more processors; and One or more peripheral devices connected to the one or more processors One of the one or more peripheral devices is a successive approximation type AD converter that converts an analog input potential into an n-bit digital signal. The successive approximation type AD converter has the following characteristics: The comparison potential generation circuit is capable of generating a comparison potential for each bit based on the analog input potential; A comparator circuit capable of comparing a reference potential with a comparison potential generated by the comparison potential generation circuit; A first switching circuit is disposed before the comparator circuit; as well as A digital signal generation circuit that generates the n-bit digital signal based on the comparison result of the comparison circuit. The comparator circuit has a first input terminal and a second input terminal for receiving the comparison potential and the reference potential, and an output terminal for outputting the comparison result. The comparator circuit is capable of comparing the comparison potential and the reference potential input to the first input terminal and the second input terminal, and outputting the comparison result as the result of the comparison at the output terminal. When the period during which the comparison potential, which inputs an n-bit quantity to the comparison circuit, is defined as the AD conversion period, the first switching circuit is capable of switching from a first period during which the comparison potential is input to the first input terminal and the reference potential is input to the second input terminal, or from the second period to the first period, whenever one or more AD conversion periods have elapsed.

11. An AD converter, comprising: The comparison potential generation circuit can generate a comparison potential based on the analog input potential; A comparator circuit having a first input terminal and a second input terminal, capable of comparing a pair of input potentials input to the first input terminal and the second input terminal with each other; A switching circuit capable of switching between a first period and a second period, wherein the first period is when the comparison potential is input to the first input terminal and the reference potential is input to the second input terminal, and the second period is when the comparison potential is input to the second input terminal and the reference potential is input to the first input terminal; as well as A digital signal generation circuit that can generate a digital signal based on the comparison result in the comparison circuit in sync with the switching action of the switching circuit.

12. A comparator having: A comparator circuit having a first input terminal and a second input terminal, capable of comparing a pair of input potentials input to the first input terminal and the second input terminal; and A switching circuit capable of switching between a first period and a second period, wherein the first period is when a comparison potential is input to the first input terminal and a reference potential is input to the second input terminal, and the second period is when the comparison potential is input to the second input terminal and the reference potential is input to the first input terminal.

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