Unit capacitance, segmented bridge capacitor array structure, CDAC and layout method

Abstract

The application discloses a unit capacitance, a segmented bridge type capacitance array structure, a CDAC and a layout method, the unit capacitance comprises upper plate wiring PLUS, lower plate wiring MINUS and shielding ground wire GND; the lower plate wiring MINUS leading-out side outer ring is surrounded by the shielding ground wire GND on at least three sides, and the upper plate wiring PLUS leading-out side is not provided with a shielding ground wire GND surrounding structure; the two sides of the lower plate wiring MINUS leading-out side are wrapped with the two sides of the upper plate wiring PLUS leading-out side, the upper plate wiring PLUS leading-out side is isolated from the adjacent metal network, and the parasitic of the bridge capacitance is shielded. The application converts the harmful parasitic CPB and CPL into the plate-to-ground parasitic CPM without precision influence, eliminates the weight mismatch caused by the parasitic capacitance from the layout source under the premise that the segmented bridge type CDAC circuit topology is not changed, and improves the ADC conversion linearity; mature process device models are fully reused, and device development, digital calibration and redundant capacitance need not be newly added.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a unit capacitor, segmented bridge capacitor array structure, and CDAC suitable for successive approximation analog-to-digital converters (SAR-ADCs). Background Technology

[0002] To reduce the area of ​​the capacitor array chip, successive approximation analog-to-digital converters (SAR-ADCs) generally use a segmented bridge capacitor array as the core DAC unit, namely a segmented bridge CDAC. The segmented bridge CDAC includes the bridge capacitor CBG, the total capacitance CMSB on the MSB side, and the total capacitance CLSB on the LSB side. Figure 1 The diagram shows a single-ended segmented bridge SAR ADC capacitor array circuit. The circuit includes bridge capacitor CBG, comparator COMP, SAR logic unit, reference voltage VREF, input voltage VIN, common-mode voltage VCM, multi-stage capacitor array, switch array, and three types of parasitic capacitances: parasitic capacitance CPB between the upper and lower plates of the bridge capacitor, parasitic capacitance CPL between the upper plate of the bridge capacitor and ground, and parasitic capacitance CPM between the lower plate of the bridge capacitor and ground.

[0003] In an ideal parasitic-free environment, the SAR ADC converts the sampled voltage VIN into a 12-bit digital code through 12 successive approximations. The conversion weight is determined solely by the capacitance of the array capacitor itself, and the conversion linearity meets the design specifications.

[0004] During the physical implementation of chip layout, parasitic capacitances are generated between capacitor cells and metal traces. The three types of parasitic capacitances have different effects on conversion accuracy: 1. CPM only affects the conversion coefficient K and does not change the linearity of the ADC; 2. CPB and CPL will change the lower six-bit capacitor weighting coefficients, causing the actual conversion formula to deviate from the ideal formula, resulting in capacitor mismatch, which directly worsens the ADC conversion linearity and reduces the analog-to-digital conversion output accuracy.

[0005] To address the aforementioned differences, existing technologies have made the following improvements, but these still cannot solve the technical problem of unsatisfactory accuracy caused by these differences.

[0006] 1. Chinese Patent CN110323334A: It uses a customized dedicated capacitor to cancel parasitic capacitance, which requires independent development of device models and completion of multiple rounds of fabrication verification. The R&D cycle is uncontrollable and there is a risk of verification failure. 2. Chinese patent CN119561553A: It adopts layout optimization + redundant capacitor isolation parasitic, the redundant capacitor greatly increases the total area of ​​the capacitor array, the chip manufacturing cost increases, and it is not suitable for cost-sensitive chips. 3. Chinese patent CN111711449B: It uses digital domain background calibration to compensate for parasitic mismatch, which requires additional design and verification of digital calibration circuit, increasing the workload of chip design and the risk of iteration cycle. 4. Chinese Patent CN108365847A: It adopts simulation iteration + FIB correction parasitics after tape-out. Multiple simulations and tape-out tests consume a lot of R&D resources and prolong the project cycle.

[0007] None of the existing improvement solutions mentioned above can eliminate the linearity degradation problem caused by CPB and CPL from the source of the layout without increasing chip area, adding new digital circuits, extending the R&D cycle, or adding new device development processes. Summary of the Invention

[0008] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0009] The present invention aims to solve the following technical problems: 1) In the existing segmented bridge SAR ADC capacitor array layout, the parasitic capacitance CPB between the upper and lower plates of the bridge capacitor and the parasitic capacitance CPL between the upper plate of the LSB side of the bridge capacitor and ground will change the capacitor weight, causing capacitor mismatch and deterioration of ADC conversion linearity. 2) Existing improvement solutions have drawbacks such as increased chip area, addition of digital circuits, long development cycle of self-developed devices, and high cost of multiple tape-outs.

[0010] To address the aforementioned technical issues, this invention provides a method that shields CPB and CPL from the layout stage, eliminating the negative impact of parasitic capacitance on conversion linearity. This method is compatible with standard process library devices, requires no redundant capacitors, no additional digital calibration circuitry, does not increase device development steps, shortens chip development cycles, and reduces chip hardware costs. It also includes a segmented bridge capacitor array structure, a segmented bridge CDAC, and a segmented bridge CDAC layout method. This invention provides a unit capacitor, comprising: an upper plate trace PLUS, a lower plate trace MINUS, and a shielding ground line GND; The lower electrode wiring MINUS lead-out side has at least three sides of shielded ground wire GND surrounding the outer ring, while the upper electrode wiring PLUS lead-out side does not have a shielded ground wire GND surrounding structure. The traces on both sides of the MINUS lead-out side of the lower electrode wrap around the traces on both sides of the PLUS lead-out side of the upper electrode, isolating the PLUS lead-out side of the upper electrode from the adjacent metal network, in order to shield the parasitic bridge capacitor.

[0011] The present invention provides a segmented bridge capacitor array structure having multiple unit capacitors as described above, including: an MSB-side capacitor array and an LSB-side capacitor array composed of multiple unit capacitors, and a bridge capacitor CBG for connecting the capacitor arrays on each side. Two adjacent unit capacitors share a shielded ground wire GND in the middle to shield the parasitic coupling between adjacent capacitor units, thereby suppressing the parasitic CPL of the upper plate of the bridge capacitor to ground.

[0012] This invention provides a segmented bridge CDAC for a successive approximation analog-to-digital converter, which has the aforementioned segmented bridge capacitor array structure, and is configured as a single-ended circuit architecture, and further includes: Comparator COMP, SAR logic unit, input voltage terminal VIN, reference voltage terminal VREF, common-mode voltage terminal VCM; The output terminal VX of the segmented bridge capacitor array structure is connected to the input terminal of the comparator COMP, and the output terminal of the comparator COMP is connected to the SAR logic unit.

[0013] Preferably, the segmented bridge CDAC is further improved in that the segmented bridge CDAC is formed in a 6-6 segmented architecture, the MSB-side capacitor array contains 6-bit unit capacitors, the LSB-side capacitor array contains 6-bit unit capacitors, and the bridge capacitor CBG has a capacitance value equal to the unit capacitance value CU.

[0014] Preferably, the segmented bridge CDAC is further improved in that the MSB-side capacitor array and the LSB-side capacitor array are arranged symmetrically with bridge capacitors CBG and have metal traces of equal length, and dummy auxiliary capacitors are set at the array edges.

[0015] Preferably, the segmented bridge CDAC is further improved by configuring a digital back-end calibration module for secondary compensation of minor conversion errors in the digital domain.

[0016] This invention provides a segmented bridge CDAC layout method for a successive approximation analog-to-digital converter, used to fabricate the segmented bridge CDAC described in any of the above-mentioned methods, comprising the following steps: Step 1: Select the native standard unit capacitor from the wafer process library as the capacitor base, and do not create a new custom capacitor simulation model; Step 2: Modify the layout of a single unit capacitor: Run double-layer shielded ground wires GND on both sides of the lower plate MINUS to wrap around the upper plate PLUS. Run continuous shielded ground wires GND on three sides of the outer ring of the capacitor. Do not run surrounding ground wires at the lead-out end of the upper plate PLUS. Step 3: When arranging the array, adjacent unit capacitors share the middle shield ground line GND; Step 4: Connect the modified unit capacitors into MSB-side capacitor arrays and LSB-side capacitor arrays, with a bridge capacitor CBG connected in series in the middle, to build a segmented bridge CDA circuit. Step 5: Complete the parasitic extraction of the layout and module simulation, and proceed to the tape-out process.

[0017] Preferably, the capacitor layout design method is further improved by including in step 2: adjusting the shielding ground wire width and metal spacing parameters, and conducting simulation iterations to optimize the total parasitic amount after multiple layouts are performed.

[0018] The working principle of the present invention is explained below based on the above technical solution; This invention modifies the layout shielding structure based on the native unit capacitance of standard process technology. Through a triple layout design of three-sided GND ground line, double-layer ground line wrapping the PLUS plate on the MINUS side, and adjacent capacitors sharing a shielding ground line, it blocks the coupling path between the upper and lower plates of the bridge capacitor and the coupling path between adjacent capacitor units. It transforms harmful parasitic CPB and CPL into plate-to-ground parasitic CPM that has no accuracy impact. Without changing the topology of the segmented bridge CDAC circuit, it eliminates the weight mismatch caused by parasitic capacitance from the source of the layout, improving the linearity of ADC conversion. It reuses mature process device models throughout the process, without the need for new device development, digital calibration, or redundant capacitors.

[0019] Based on the above technical solution and working principle, the present invention can achieve at least the following technical effects compared with the prior art; 1. Existing technologies can only compensate for weighting errors caused by parasitics at the back end of the circuit and the digital back end, but cannot eliminate the root cause of layout coupling parasitics; This invention directly blocks the generation paths of parabolic CPB and CPL through ground wire shielding, eliminating residual error compensation. Its conversion linearity optimization effect is superior to digital calibration and redundant capacitor isolation schemes, thus improving ADC conversion linearity and eliminating errors at the source. 2. Compared with the self-developed and customized capacitor solution of CN110323334A, this invention reuses the standard capacitor model that has been maturely verified by the process plant, eliminating the need for device modeling and multi-stage fabrication verification. It eliminates the need for self-developed capacitors, avoids the risks of uncontrollable device development cycle and simulation distortion, simplifies analog circuit design and layout iteration process, and can shorten the development cycle.

[0020] 3. Compared with the redundant capacitor isolation scheme of CN119561553A, the present invention relies on ground line routing to achieve shielding, without adding dummy redundant capacitors, and the total area of ​​the capacitor array does not increase. It is suitable for ADC chip design with low cost and small area requirements.

[0021] 4. Compared with the CN111711449B digital calibration scheme, this invention only optimizes the analog layout structure, without adding digital logic, digital layout design and verification work, reducing the manpower input for chip design, reducing tape-out and simulation iterations, saving R&D resources, and reducing the risk of digital-analog joint verification iterations.

[0022] 5. Compared with the multi-round simulation + fabrication FIB correction scheme of CN108365847A, the layout shielding structure of this invention can suppress parasites in one design, without the need for multiple post-simulation iterations and post-fabrication physical corrections, which greatly saves fabrication costs and project cycle. Attached Figure Description

[0023] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0024] Figure 1 This is a schematic diagram of a single-ended capacitor array circuit in a segmented bridge SAR ADC.

[0025] Figure 2 This is a comparative schematic diagram of the existing unit capacitor layout and the unit capacitor of the present invention. The left side is the original capacitor from the process library, and the right side is the unit capacitor of the present invention.

[0026] Figure 3 This is a schematic diagram of the layout structure of two adjacent unit capacitors in this invention.

[0027] Figure 4 This is a schematic diagram of a single-ended circuit for a 6-6 segmented bridge CDAC array provided by the present invention.

[0028] Explanation of reference numerals in the attached figures: Parasitic capacitances of CBG bridge capacitor, CPB bridge capacitor (upper and lower plates), CPL bridge capacitor (upper plate to ground), CPM bridge capacitor (lower plate to ground), COMP comparator, SAR LOGIC successive approximation logic, VCM common-mode voltage, VREF reference voltage, VIN input voltage, GND ground line, PLUS capacitor upper plate trace, MINUS capacitor lower plate trace, GND shielded ground line. Detailed Implementation

[0029] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0030] First embodiment; refer to Figure 2 The present invention provides a unit capacitor, comprising: an upper plate trace PLUS, a lower plate trace MINUS, and a shield ground line GND; The lower electrode wiring MINUS lead-out side has at least three sides of shielded ground wire GND surrounding the outer ring, while the upper electrode wiring PLUS lead-out side does not have a shielded ground wire GND surrounding structure. The traces on both sides of the MINUS lead-out side of the lower electrode wrap around the traces on both sides of the PLUS lead-out side of the upper electrode, isolating the PLUS lead-out side of the upper electrode from the adjacent metal network, in order to shield the parasitic bridge capacitor.

[0031] Second embodiment; refer to Figure 3 As shown, the present invention provides a segmented bridge capacitor array structure having multiple unit capacitors as described in the first embodiment, including: an MSB-side capacitor array and an LSB-side capacitor array composed of multiple unit capacitors, and a bridge capacitor CBG for connecting the capacitor arrays on each side. Two adjacent unit capacitors share a shielded ground wire GND in the middle to shield the parasitic coupling between adjacent capacitor units, thereby suppressing the parasitic CPL of the upper plate of the bridge capacitor to ground.

[0032] Third embodiment; This invention provides a segmented bridge CDAC for a successive approximation analog-to-digital converter, which has the segmented bridge capacitor array structure described in the second embodiment, and is generally configured as a single-ended circuit architecture, and further includes: Comparator COMP, SAR logic unit, input voltage terminal VIN, reference voltage terminal VREF, common-mode voltage terminal VCM; The output terminal VX of the segmented bridge capacitor array structure is connected to the input terminal of the comparator COMP, and the output terminal of the comparator COMP is connected to the SAR logic unit. refer to Figure 4 As shown, the segmented bridge CDAC described in this embodiment is formed in a 6-6 segmented architecture. The MSB-side capacitor array contains 6-bit unit capacitors, and the LSB-side capacitor array contains 6-bit unit capacitors. The bridge capacitor CBG has a capacitance value equal to the unit capacitance value CU. The lower plates of the capacitor array are uniformly connected to a switch array, and the switches are respectively connected to VREF, VIN, and VCM. The output terminal VX of the capacitor array is connected to the comparator COMP, and the comparator output is connected to the SAR LOGIC successive approximation logic unit to complete 12 voltage successive approximation sampling conversions. The MSB-side capacitor array and the LSB-side capacitor array are symmetrically arranged with bridge capacitors (CBG) and have metal traces of equal length. Dummy auxiliary capacitors are set at the edge of the array.

[0033] Preferably, in a further improvement to the third embodiment described above, a digital back-end calibration module is also configured for secondary compensation of minor conversion errors in the digital domain.

[0034] Fourth embodiment; This invention provides a segmented bridge CDAC layout method for a successive approximation analog-to-digital converter, used to fabricate the segmented bridge CDAC described in the third embodiment, comprising the following steps: Step 1: Select the native standard unit capacitor from the wafer process library as the capacitor base, and do not create a new custom capacitor simulation model; Step 2: Modify the layout of a single unit capacitor: Run double-layer shielded ground wires GND on both sides of the lower plate MINUS to wrap around the upper plate PLUS. Run continuous shielded ground wires GND on three sides of the outer ring of the capacitor. Do not run surrounding ground wires at the lead-out end of the upper plate PLUS. Step 3: When arranging the array, adjacent unit capacitors share the middle shield ground line GND; Step 4: Connect the modified unit capacitors into an MSB-side capacitor array and an LSB-side capacitor array, with a bridge capacitor CBG connected in series in the middle, to build a segmented bridge CDAC circuit. Step 5: Complete the parasitic extraction of the layout and module simulation, and proceed to the tape-out process.

[0035] Preferably, in a further improvement of the fourth embodiment, step 2 also includes: adjusting the shielding ground wire width and metal spacing parameters, and conducting simulation iterations to optimize the total amount of parasites after multiple layouts.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0037] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A unit capacitor, characterized in that, include: Upper electrode plate wiring PLUS, lower electrode plate wiring MINUS, and shield ground wire GND; The lower electrode wiring MINUS lead-out side has at least three sides of shielded ground wire GND surrounding the outer ring, while the upper electrode wiring PLUS lead-out side does not have a shielded ground wire GND surrounding structure. The traces on both sides of the MINUS lead-out side of the lower electrode wrap around the traces on both sides of the PLUS lead-out side of the upper electrode, isolating the PLUS lead-out side of the upper electrode from the adjacent metal network, in order to shield the parasitic bridge capacitor.

2. A segmented bridge capacitor array structure, comprising multiple unit capacitors as described in claim 1, characterized in that, include: The MSB-side capacitor array and LSB-side capacitor array consist of multiple unit capacitors, and the bridge capacitor is used to connect the capacitor arrays on each side. Two adjacent unit capacitors share a shielded ground wire GND in the middle to shield the parasitic coupling between adjacent capacitor units and suppress the parasitic connection between the upper plate of the bridge capacitor and ground.

3. A segmented bridge CDAC for a successive approximation analog-to-digital converter, comprising the segmented bridge capacitor array structure as described in claim 2 or 3, characterized in that, Its overall structure is a single-ended circuit architecture, and also includes: Comparator COMP, SAR logic unit, input voltage terminal, reference voltage terminal, common-mode voltage terminal; The output of the segmented bridge capacitor array structure is connected to the input of the comparator COMP, and the output of the comparator COMP is connected to the SAR logic unit.

4. The segmented bridge capacitor array structure according to claim 3, characterized in that: The segmented bridge CDAC is configured as a 6-6 segmented architecture. The MSB-side capacitor array contains 6-bit unit capacitors, and the LSB-side capacitor array contains 6-bit unit capacitors. The bridge capacitor value is equal to the unit capacitor value.

5. The segmented bridge CDAC according to claim 3, characterized in that: The MSB-side capacitor array and the LSB-side capacitor array are arranged symmetrically with bridge capacitors and have metal traces of equal length. Dummy auxiliary capacitors are set at the edge of the array.

6. The segmented bridge CDAC according to claim 3, characterized in that: It is also equipped with a digital back-end calibration module for secondary compensation of minor conversion errors in the digital domain.

7. A segmented bridge CDAC layout method for use in a successive approximation analog-to-digital converter, used to fabricate the segmented bridge CDAC as described in any one of claims 3-6, characterized in that, Includes the following steps: Step 1: Select the native standard unit capacitor from the wafer process library as the capacitor substrate; Step 2: Modify the layout of a single unit capacitor: Run double-layer shielded ground wires GND on both sides of the lower plate MINUS to wrap around the upper plate PLUS. Run continuous shielded ground wires GND on three sides of the outer ring of the capacitor. Do not run surrounding ground wires at the lead-out end of the upper plate PLUS. Step 3: When arranging the array, adjacent unit capacitors share the middle shield ground line GND; Step 4: Connect the modified unit capacitors into an MSB-side capacitor array and an LSB-side capacitor array, with a bridge capacitor connected in series in the middle, to build a segmented bridge CDAC circuit. Step 5: Complete the parasitic extraction of the layout and module simulation, and proceed to the tape-out process.

8. The capacitor layout design method according to claim 7, characterized in that, Step 2 also includes: adjusting the shielding ground wire width and metal spacing parameters, and conducting simulation iterations to optimize the total amount of parasites after multiple layouts.

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