A three-stage pipelined successive approximation register analog-to-digital converter with intra-stage multi-channel architecture

Abstract

The application provides a three-stage pipeline successive approximation type analog-to-digital converter (Pipeline SAR ADC) with intra-stage multi-channel structure, comprising: a three-stage successive approximation analog-to-digital converter and a two-stage residual amplifier; the first stage and the second stage comprise a three-channel SAR ADC circuit, and the third stage comprises a two-channel SAR ADC circuit, and the stages are connected through the residual amplifier; the residual amplifier is realized in an open-loop structure. In the application, the intra-stage multi-channel SAR ADC is used to alternately perform sampling, quantization and residual amplification in Ping-Pong or multiphase timing, compared with the structure of the traditional Pipeline SAR ADC whose conversion time is determined by the sum of the three stages of sampling, quantization and residual amplification, the conversion time of the application is only determined by the quantization time, and the conversion speed of the ADC is significantly improved; meanwhile, the structure allocates a complete period for residual amplification, so that the residual amplifier has sufficient setting time, and the conversion precision of the Pipeline SAR ADC is improved.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more specifically to a three-stage pipelined successive approximation analog-to-digital converter (Pipeline SAR ADC) with an intra-stage multi-channel structure. Background Technology

[0002] Analog-to-digital converters (ADCs) are key components in electronic systems, used to convert analog signals into digital signals for processing in digital circuits or microprocessors. With the rapid development of fields such as the Internet of Things (IoT), medical electronics, communication engineering, and testing equipment, the performance requirements for ADCs are constantly increasing. At the same time, semiconductor process technology continues to evolve, and the feature size of CMOS devices is shrinking. Successive Approximation Register (SAR) ADCs, due to their excellent adaptability to advanced processes, have seen a significant improvement in operating speed. In high-speed ADC applications, multiple SAR ADCs are often cascaded and operated in a pipelined mode, thus achieving a trade-off between conversion speed, accuracy, and power consumption.

[0003] However, pipelined successive approximation analog-to-digital converters (Pipeline SAR ADCs) require inter-stage residual amplifiers. Their overall conversion speed is determined by the sum of the times for sampling, quantization, and residual amplification, with the residual amplification time often being the primary factor limiting the conversion speed. A typical three-stage Pipeline SAR ADC circuit structure is as follows: Figure 2 As shown, its working timing is as follows Figure 3 As shown, sampling, quantization, and residual amplification must be completed sequentially within a conversion cycle, making it difficult to further improve conversion efficiency. Summary of the Invention

[0004] This invention aims to provide a three-stage pipeline SAR ADC with an intra-stage multi-channel structure. By alternately sampling, quantizing, and generating residual signals using a single-stage multi-channel SAR ADC, it overcomes the conversion speed limitations of traditional pipeline SAR ADCs, achieving more efficient analog-to-digital conversion. Compared to traditional structures, the conversion time of this invention is not determined by the sum of the times for sampling, quantization, and residual amplification, but only by the quantization time of the first stage. Simultaneously, this invention allocates a complete cycle for residual amplification, reducing the bandwidth requirement of the residual amplifier and allowing sufficient settling time, which is beneficial for improving conversion accuracy.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure includes three stages of successive approximation analog-to-digital converters (SAR ADCs) and two stages of residual amplifiers. The first and second stage SAR ADCs each contain a three-channel SAR ADC circuit, and the third stage SAR ADC contains a two-channel SAR ADC circuit. The SAR ADCs at each stage are cascaded sequentially through residual amplifiers, which are implemented using an open-loop structure.

[0006] As a preferred technical solution, the SAR ADC circuit in each channel includes a sampling circuit, a switched capacitor DAC array, a comparator, a SAR logic circuit, and a multiphase clock generation circuit; The sampling circuit adopts a bootstrap switching circuit structure, and the sampled differential signal is sent to the switched capacitor DAC array. The differential input terminal of the comparator is connected to the differential output terminal of the switched capacitor DAC array, and the output terminal is connected to the SAR logic circuit. The SAR logic circuit asynchronously controls the charging and discharging operation of the switched capacitor DAC array, triggers the next comparison cycle based on the comparison result, and completes the setting of the capacitor array. The multiphase clock generation circuit is used to generate clocks for controlling the comparator comparison and reset, as well as the rising edge of the clock that triggers the SAR logic to store the comparison result.

[0007] As a preferred technical solution, the residual amplifier is configured in normally open mode, that is, its input terminal is always connected to the residual output terminal of the channel that has completed the quantization operation in the previous stage.

[0008] As a preferred technical solution, the Pipeline SAR ADC further includes a clock control module, which is connected to the first-stage, second-stage, and third-stage SAR ADCs and the two-stage residual amplifiers respectively; The clock control module is used for: The first-stage three-channel SAR ADC circuit is controlled to operate in a three-stage time cycle of sampling, quantization and residual establishment. The start-up phases of the three channels are sequentially separated by one conversion cycle, and the residual signals generated by each channel are alternately sent to the first-stage residual amplifier in a time-division manner. The second-stage three-channel SAR ADC circuit is controlled to operate in a three-stage time cycle of sampling, quantization and residual establishment. The start-up phases of the three channels are sequentially separated by one conversion cycle, and the residual signals generated by each channel are alternately sent to the second-stage residual amplifier in a time-division manner. The third-stage dual-channel SAR ADC circuit is controlled to alternately perform sampling and quantization.

[0009] As a preferred technical solution, the control process of the first-stage three-channel SAR ADC circuit includes: The first channel samples in the first cycle, completes quantization in the second cycle, and after quantization, maintains its residual voltage in the third cycle and outputs it to the first residual amplifier. This output process continues throughout the entire third cycle. During the quantization of the first channel, the second channel is sampled within the same second cycle; During the third cycle, the first channel maintains the residual voltage and outputs it to the first residual amplifier, the second channel performs quantization, and the third channel starts sampling. This cycle continues, with the start-up phases of the three channels differing by one conversion cycle, and the residual voltages generated by each channel are alternately fed into the first-stage residual amplifier in a time-division manner.

[0010] As a preferred technical solution, the control process of the second-stage three-channel SAR ADC circuit includes: The first channel samples in the first cycle, completes quantization in the second cycle, and after quantization, maintains its residual voltage in the third cycle and outputs it to the second-stage residual amplifier. This output process continues throughout the third cycle. The sampling window of the first channel covers the entire first cycle, and its sampling object is the residual voltage that the first-stage residual amplifier amplifies and establishes in the previous cycle. While the first channel is being quantized, the second channel begins sampling during the second cycle; During the third cycle, the first channel outputs the residual voltage to the second-stage residual amplifier, the second channel performs quantization, and the third channel starts sampling. This cycle continues, with the start-up phases of the three channels differing by one conversion cycle, and the residual voltages generated by each channel are alternately fed into the second-stage residual amplifier in a time-division manner.

[0011] As a preferred technical solution, the control process of the third-stage dual-channel SAR ADC circuit includes: The first channel samples in the first cycle, completes quantization and outputs digital code in the second cycle; While the first channel is being quantized, the second channel begins sampling during the second cycle; After the first channel completes quantization, the second channel enters the quantization stage and outputs a digital code, while the first channel begins a new round of sampling; this alternating cycle is repeated to achieve dual-channel Ping-Pong sampling and quantization.

[0012] As a preferred technical solution, the amplification time of both the first-stage and second-stage residual amplifiers is one full conversion cycle.

[0013] The beneficial effects of this invention are as follows: 1. This invention sets up multiple SAR ADCs to work alternately within a stage. Compared with the traditional Pipeline SAR ADC, its conversion time is not determined by the sum of the times of sampling, quantization and residual amplification, but only by the first stage quantization time. This can shorten the conversion cycle by the time of residual amplification, significantly improving the conversion speed of Pipeline SAR ADC.

[0014] 2. The residual amplification time of the present invention is one whole conversion cycle, while the residual amplification time of the traditional structure is one conversion cycle minus the sampling and quantization stage time. The present invention significantly increases the settling time of the residual amplifier without reducing the overall conversion speed, thereby reducing the requirements for amplifier bandwidth and gain, which is beneficial to improving conversion accuracy. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of the three-stage Pipeline SAR ADC of the present invention; Figure 2 This is a detailed circuit diagram of a conventional three-stage pipeline SAR ADC; Figure 3 This is a timing diagram of a typical three-level pipeline SAR ADC. Figure 4 This is a detailed circuit diagram of the three-stage Pipeline SAR ADC of the present invention; Figure 5 This is a timing diagram showing the specific operation of the three-level Pipeline SAR ADC of this invention. Detailed Implementation

[0016] The following will refer to the accompanying drawings in the embodiments of the present invention ( Figures 1 to 5 The technical solutions in the embodiments of the present invention will be clearly and completely described.

[0017] like Figure 1 As shown, the present invention provides a three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure, including a three-stage successive approximation analog-to-digital converter (SAR ADC) and a two-stage residual amplifier; wherein, the first and second stage SAR ADCs each contain a three-channel SAR ADC circuit, and the third stage SAR ADC contains a two-channel SAR ADC circuit; the SAR ADCs at each stage are cascaded sequentially through residual amplifiers; and the residual amplifiers are implemented using an open-loop structure.

[0018] The core of this invention lies in deploying multiple SAR ADC sub-channels within each stage of the pipeline and controlling them to alternately perform sampling, quantization, and residual establishment operations in a Ping-Pong or multi-phase timing manner. This allows the inter-stage residual amplifier to occupy a complete conversion cycle for amplification, thereby shortening the overall conversion speed from the sum of the three stages of "sampling + quantization + amplification" to being determined solely by the quantization time of the first stage. At the same time, it reduces the bandwidth requirements of the residual amplifier and improves conversion accuracy.

[0019] The following combination Figure 4 The circuit structure shown and Figure 5 The timing diagram shown illustrates the specific working principle of the three-stage Pipeline SAR ADC of this invention, taking the input signal as a differential analog voltage as an example.

[0020] like Figure 4 As shown, the three-level Pipeline SAR ADC in this embodiment includes: First stage: A three-channel SAR ADC, with channels S1a, S1b, and S1c. Each channel includes a bootstrap sampling switch, a CDAC capacitor array, a dynamic comparator, SAR logic control circuitry, and a multiphase clock generation circuit. The outputs of the three channels are connected to the input of the first-stage residual amplifier RA1 via switches S1a_ra, S1b_ra, and S1c_ra.

[0021] The first-stage residual amplifier RA1 adopts an open-loop structure, and its output is connected to the input of the second-stage SAR ADC.

[0022] The second stage consists of a three-channel SAR ADC, channels S2a, S2b, and S2c, each with a structure similar to the first stage. The outputs of the three channels are connected to the input of the second-stage residual amplifier RA2 via switches S2a_ra, S2b_ra, and S2c_ra.

[0023] The second-stage residual amplifier RA2 is also an open-loop structure, and its output is connected to the input of the third-stage SAR ADC.

[0024] Level 3: Dual-channel SAR ADC, channels S3a and S3b, directly outputs the final digital code.

[0025] refer to Figure 5 The timing diagram is shown below. The alternating operation process of each channel is described in detail below, taking channel S1 for six consecutive conversion cycles as an example.

[0026] The three channels of the first stage, S1a, S1b and S1c, strictly alternate between sampling quantization and residual preservation.

[0027] At the beginning of T1, the sampling switch S1a_samp of S1a is closed, and S1a enters the sampling phase, sampling the analog input signal Vin onto its CDAC. After sampling continues for a full cycle, S1a_samp is turned off.

[0028] At time T2, S1a immediately enters the quantization stage, starting with successive approximation controlled by the asynchronous clock, and sequentially completing coarse quantization. During quantization, the SAR logic controls the switching of the lower plate of the CDAC bit by bit according to the comparator result, ultimately obtaining the first-level digital code.

[0029] At the end of S1a quantization, at time T3, switch S1a_ra closes, connecting the residual voltage stored on the upper plate of the CDAC of S1a to the input of residual amplifier RA1. RA1 begins to amplify the residual voltage. At this time, because RA1 adopts an open-loop structure, its output immediately follows the input change, requiring a full cycle time to complete the final setup.

[0030] Meanwhile, after the sampling phase of S1a is completed, at time T2, channel S1b starts working: the sampling switch S1b_samp is closed, and S1b samples the new analog input signal.

[0031] After sampling by S1b is completed, at time T3, S1b enters the quantization stage. Channel S1c starts working: the sampling switch S1c_samp is closed, and S1c samples the new analog input signal.

[0032] When S1b quantization ends, time T4 begins. At this point, S1b_ra closes, connecting the residual voltage of S1b to the input of RA1, which then amplifies it. Meanwhile, S1a has completed its residual voltage output, and S1a_samp closes again, allowing S1a to sample and quantize the new input signal. Simultaneously, S1c performs quantization.

[0033] Thus, in subsequent moments, S1a, S1b, and S1c alternately feed the residual into RA1, and RA1 is always in an amplification state with no idle time. Since the amplification time of RA1 is equal to a complete cycle T, its establishment accuracy is much higher than that of the amplification in traditional structures, which only takes half a cycle or even less.

[0034] The second stage contains three channels, S2a, S2b, and S2c, which sequentially perform sampling, quantization, and residual phase establishment, forming a three-stage pipeline. The outputs of the three channels are alternately connected to RA2.

[0035] At time T3, S2a enters the sampling stage, synchronized with the channel amplification stage in the first stage S1a. The sampling switch S2a_samp is closed, and S2a samples the amplified residual voltage output by RA1.

[0036] After sampling by S2a, at time T4, S2a enters the quantization phase, performing medium-precision quantization. Simultaneously, during the quantization of S2a, switch S2b_samp closes, and S2b begins sampling the next amplified residual voltage output by RA1.

[0037] After S2a completes quantization, at time T5, its residual voltage is maintained on its CDAC, switch S2a_ra is closed, connecting the capacitor board to the input of RA2, and RA2 begins amplification; at the same time, after S2b completes sampling, it enters the quantization stage; S2c then begins sampling the third output voltage of RA1.

[0038] At time T6, channel S2a is connected to the output of RA1 to start a new round of sampling; channel S2b is connected to RA2 to amplify the residual voltage held by the capacitor array; and channel S2c begins quantization.

[0039] With the three-channel pipeline, the input of RA2 is always valid, and the amplification time of each residual voltage on RA2 is also a complete conversion cycle T.

[0040] The third stage only performs sampling and quantization, without outputting residuals. Its dual channels S3a and S3b alternately sample the amplified residual voltage output by RA2 in a Ping-Pong manner and complete the final digital conversion.

[0041] At time T5, S3a enters the sampling stage, which is synchronized with the channel amplification stage in the second stage S2a. The sampling switch S3a_samp is closed, and S3a samples the amplified residual voltage output by RA2.

[0042] After sampling by S3a, at time T6, S3a enters the quantization stage, performs fine quantization, and outputs the final digital code. Simultaneously, during the quantization of S3a, switch S3b_samp closes, and S3b begins sampling the second output voltage of RA2.

[0043] At time T6, S3b enters the quantization phase, and S3a samples a new value, and so on.

[0044] Since the third stage does not require residual amplification, its dual-channel alternation can achieve continuous conversion, and the conversion time is synchronized with the first and second stages.

[0045] In summary, the workflow of the three-stage Pipeline SAR ADC of this invention during continuous conversion can be summarized as follows: The first stage uses three channels to alternately sample the input signal. After coarse quantization, the residual voltage is immediately sent to RA1, and RA1 completes the amplification in one full cycle.

[0046] The second-stage three-channel pipeline sequentially samples the output of RA1, performs medium-precision quantization, and then sends its residual to RA2. RA2 also completes the amplification in one full cycle.

[0047] The third-level dual-channel alternating sampling of the RA2 output completes the final fine quantization and outputs the digital code.

[0048] Data stream alignment is ensured between different levels through synchronous sampling clocks, while asynchronous quantization clocks ensure rapid internal switching.

[0049] The first and second stages of this invention adopt a three-channel structure, and the third stage adopts a Ping-Pong structure. The capacitor size and amplifier parameters of each stage can be optimized according to the different accuracy and speed requirements of each stage, so as to achieve a fine trade-off between overall performance and power consumption.

[0050] Compared to Figure 2 , Figure 3 Compared to the conventional Pipeline SAR ADC shown, this invention does not require reserving a residual amplification time window in each cycle, thus achieving a higher conversion speed; at the same time, the residual amplifier has ample settling time, allowing the use of amplifiers with lower power consumption and higher linearity, resulting in a significant improvement in overall performance.

[0051] The technical means disclosed in this invention are not limited to those disclosed in the above embodiments, but also include technical solutions composed of any combination of the above technical features. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications are also considered within the scope of protection of this invention.

Claims

1. A three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure, characterized in that, It includes a three-stage successive approximation analog-to-digital converter (SAR ADC) and a two-stage residual amplifier; wherein the first and second stage SAR ADCs each contain a three-channel SAR ADC circuit, and the third stage SAR ADC contains a two-channel SAR ADC circuit; the SAR ADCs at each stage are cascaded sequentially through residual amplifiers; and the residual amplifiers are implemented using an open-loop structure.

2. The three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure according to claim 1, characterized in that, The SAR ADC circuitry in each channel includes a sampling circuit, a switched-capacitor DAC array, a comparator, SAR logic circuitry, and a multiphase clock generation circuitry. The sampling circuit adopts a bootstrap switching circuit structure, and the sampled differential signal is sent to the switched capacitor DAC array. The differential input terminal of the comparator is connected to the differential output terminal of the switched capacitor DAC array, and the output terminal is connected to the SAR logic circuit. The SAR logic circuit asynchronously controls the charging and discharging operation of the switched capacitor DAC array, triggers the next comparison cycle based on the comparison result, and completes the setting of the capacitor array. The multiphase clock generation circuit is used to generate clocks for controlling the comparator comparison and reset, as well as the rising edge of the clock that triggers the SAR logic to store the comparison result.

3. The three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure according to claim 1, characterized in that, The residual amplifier is configured in normally open mode, meaning its input is always connected to the residual output of the channel that has already undergone quantization in the previous stage.

4. The three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure according to claim 1, characterized in that, It also includes a clock control module, which is connected to the first-stage, second-stage, and third-stage SAR ADCs and two-stage residual amplifiers, respectively; The clock control module is used for: The first-stage three-channel SAR ADC circuit is controlled to operate in a three-stage time cycle of sampling, quantization and residual establishment. The start-up phases of the three channels are sequentially separated by one conversion cycle, and the residual signals generated by each channel are alternately sent to the first-stage residual amplifier in a time-division manner. The second-stage three-channel SAR ADC circuit is controlled to operate in a three-stage time cycle of sampling, quantization and residual establishment. The start-up phases of the three channels are sequentially separated by one conversion cycle, and the residual signals generated by each channel are alternately sent to the second-stage residual amplifier in a time-division manner. The third-stage dual-channel SAR ADC circuit is controlled to alternately perform sampling and quantization.

5. A three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure according to claim 4, characterized in that, The control process of the first-stage three-channel SAR ADC circuit includes: The first channel samples in the first cycle, completes quantization in the second cycle, and after quantization, maintains its residual voltage in the third cycle and outputs it to the first residual amplifier. This output process continues throughout the entire third cycle. During the quantization of the first channel, the second channel is sampled within the same second cycle; During the third cycle, the first channel maintains the residual voltage and outputs it to the first residual amplifier, the second channel performs quantization, and the third channel starts sampling. This cycle continues, with the start-up phases of the three channels differing by one conversion cycle, and the residual voltages generated by each channel are alternately fed into the first-stage residual amplifier in a time-division manner.

6. The three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure according to claim 4, characterized in that, The control process of the second-stage three-channel SAR ADC circuit includes: The first channel samples in the first cycle, completes quantization in the second cycle, and after quantization, maintains its residual voltage in the third cycle and outputs it to the second-stage residual amplifier. This output process continues throughout the third cycle. The sampling window of the first channel covers the entire first cycle, and its sampling object is the residual voltage that the first-stage residual amplifier amplifies and establishes in the previous cycle. While the first channel is being quantized, the second channel begins sampling during the second cycle; During the third cycle, the first channel outputs the residual voltage to the second-stage residual amplifier, the second channel performs quantization, and the third channel starts sampling. This cycle continues, with the start-up phases of the three channels differing by one conversion cycle, and the residual voltages generated by each channel are alternately fed into the second-stage residual amplifier in a time-division manner.

7. A three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure according to claim 4, characterized in that, The control process of the third-stage dual-channel SAR ADC circuit includes: The first channel samples in the first cycle, completes quantization and outputs digital code in the second cycle; While the first channel is being quantized, the second channel begins sampling during the second cycle; After the first channel completes quantization, the second channel enters the quantization stage and outputs a digital code, while the first channel begins a new round of sampling; this alternating cycle is repeated to achieve dual-channel Ping-Pong sampling and quantization.

8. The three-stage pipelined successive approximation analog-to-digital converter with an intra-stage multi-channel structure according to claim 1, characterized in that, The amplification time of both the first and second stage residual amplifiers is one full conversion cycle.

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