Sar-ADC circuit and chip

Abstract

The application relates to the technical field of integrated circuits, and discloses a SAR-ADC circuit and a chip. In the circuit: a DAC capacitor array adopts the mode of increasing redundant bits and reducing the resistance value of unit capacitors, uses charge redistribution among capacitors to complete a binary search algorithm to output a differential analog signal; a comparator is used for comparing the size of the differential analog signal to output an original comparison result; a bit latch is used for saving the original comparison result in the form of a binary digital signal to obtain a multi-bit comparison result; and a combination logic unit is used for converting the multi-bit comparison result into a multi-bit ADC output through redundant calculation. The application can balance the speed and accuracy of the SAR-ADC, so that the area and power consumption of an ADC with more than 10 bits can be smaller.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to SAR-ADC circuits and chips. Background Technology

[0002] The conversion speed and accuracy of an ADC (Analog-to-Digital Converter) are often at odds, especially in the capacitor array design of a SAR-ADC (Successive Approximation Register ADC). On one hand, limitations in capacitor accuracy and mismatch issues during manufacturing processes prevent the minimum unit capacitor value from being too small. A small capacitor value means a significant reduction in capacitor area, leading to noticeable process mismatch. This mismatch increases the proportion of tolerance-related errors, resulting in capacitor mismatches and impacting ADC accuracy. On the other hand, if the minimum unit capacitor is not small enough, it limits the conversion speed of the SAR-ADC, making it difficult to reduce the area and power consumption of ADCs with 10 bits or more. Summary of the Invention

[0003] This invention provides a SAR-ADC circuit and chip to solve the problem that existing SAR-ADCs cannot balance speed and accuracy, making it difficult to reduce the area and power consumption of 10-bit or higher ADCs.

[0004] In a first aspect, the present invention provides a SAR-ADC circuit, including a DAC capacitor array, a comparator, a bit latch, a combinational logic unit, and a clock logic unit; The input terminal of the DAC capacitor array is used to receive the sampled signal, the output terminal of the DAC capacitor array is connected to the input terminal of the comparator, the first clock receiving terminal of the DAC capacitor array is connected to the latch terminal of the bit latch, and the second clock receiving terminal of the DAC capacitor array is connected to the first clock output terminal of the clock logic unit. The DAC capacitor array includes a capacitor array with multiple redundant bits arranged in binary and a switch. By increasing the redundant bits and reducing the resistance value of the unit capacitor, the binary search algorithm is completed by redistributing the charge between capacitors to output a differential analog signal. The comparator's output is connected to the bit latch's input, and the comparator's reset terminal is connected to the second clock output of the clock logic unit. The comparator is used to compare the magnitudes of differential analog signals to output the original comparison result. The output of the bit latch is connected to the input of the combinational logic unit, and the reset terminal of the bit latch is connected to the third clock output of the clock logic unit. The bit latch is used to save the original comparison result bit by bit as a multi-bit comparison result in the form of a binary digital signal. The clock receiver of the combinational logic unit is connected to the fourth clock output of the clock logic unit. The combinational logic unit is used to convert multi-bit comparison results into multi-bit ADC outputs through redundant calculations. The clock logic unit provides a sample-and-hold clock to the DAC capacitor array, a reset clock to the comparator and bit latch, and a synchronization clock to the combinational logic unit.

[0005] In one alternative implementation, the unit capacitance in the DAC capacitor array is the parasitic capacitance between metals.

[0006] In one alternative implementation, the capacitance value of the unit capacitor is 0.8fF.

[0007] In one optional implementation, the multi-bit comparison result is a 15-bit comparison result.

[0008] In one alternative implementation, the multi-bit ADC output is a 12-bit ADC output.

[0009] In one alternative implementation, the 12-bit ADC output has 2 redundant bits with a redundancy factor of 1.81.

[0010] In one alternative implementation, the differential analog signal comprises 15 sets of differential signals.

[0011] In one alternative implementation, the DAC capacitor array includes 14 groups of capacitors whose access states are controlled by switches, and the capacitance ratio between the groups is 1:1:1:2:3:3:7:14:24:42:76:140:254:458.

[0012] In one alternative implementation, the minimum capacitance value of the capacitors in the DAC capacitor array is a unit capacitance.

[0013] In a second aspect, the present invention provides a chip including the SAR-ADC circuit of the first aspect above or any corresponding embodiment thereof.

[0014] The technical solution provided by this invention has at least the following beneficial effects: By configuring the DAC capacitor array as a binary-arranged capacitor array with multiple redundant bits and switches, and by increasing the redundant bits and reducing the resistance of the unit capacitor, a binary search algorithm is completed using the charge redistribution between capacitors to output a differential analog signal. A comparator compares the magnitudes of the differential analog signals to output the original comparison result. A bit latch stores the original comparison result bit by bit as a multi-bit comparison result in binary digital signal form. A combinational logic unit converts the multi-bit comparison result into a multi-bit ADC output through redundant calculation. In this way, the ADC area can be compressed and the ADC speed can be improved by reducing the resistance of the unit capacitor. The reduction in accuracy and the influence of capacitor mismatch caused by reducing the resistance of the unit capacitor are reduced by redundant bit setting and redundant calculation. This balances the speed and accuracy of SAR-ADC, and allows ADCs with more than 10 bits to be made smaller in area and power consumption. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a structural block diagram of a SAR-ADC circuit according to an embodiment of the present invention; Figure 2 This is a circuit schematic diagram including a DAC capacitor array and a comparator according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a unit capacitor according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0019] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0021] This invention provides a SAR-ADC circuit that achieves a balance between the speed and accuracy of SAR-ADC by adding redundant bits to the DAC capacitor array, reducing the resistance of the unit capacitor, and using redundant calculations in the combinational logic unit. This allows for a smaller area and power consumption for 10-bit or higher ADCs.

[0022] This embodiment provides a SAR-ADC circuit, such as Figure 1 and Figure 2 It includes a DAC capacitor array, comparators, bit latches, combinational logic units, and clock logic units; The input terminal of the DAC capacitor array is used to receive the sampled signal, the output terminal of the DAC capacitor array is connected to the input terminal of the comparator, the first clock receiving terminal of the DAC capacitor array is connected to the latch terminal of the bit latch, and the second clock receiving terminal of the DAC capacitor array is connected to the first clock output terminal of the clock logic unit. The DAC capacitor array includes a capacitor array with multiple redundant bits arranged in binary and a switch. By increasing the redundant bits and reducing the resistance value of the unit capacitor, the binary search algorithm is completed by redistributing the charge between capacitors to output a differential analog signal. The comparator's output is connected to the bit latch's input, and the comparator's reset terminal is connected to the second clock output of the clock logic unit. The comparator is used to compare the magnitudes of differential analog signals to output the original comparison result. The output of the bit latch is connected to the input of the combinational logic unit, and the reset terminal of the bit latch is connected to the third clock output of the clock logic unit. The bit latch is used to save the original comparison result bit by bit as a multi-bit comparison result in the form of a binary digital signal. The clock receiver of the combinational logic unit is connected to the fourth clock output of the clock logic unit. The combinational logic unit is used to convert multi-bit comparison results into multi-bit ADC outputs through redundant calculations. The clock logic unit provides a sample-and-hold clock to the DAC capacitor array, a reset clock to the comparator and bit latch, and a synchronization clock to the combinational logic unit.

[0023] Specifically, the multi-bit comparison result can be a 15-bit comparison result. The multi-bit ADC output can be a 12-bit ADC output. The specific operation of the SAR-ADC circuit in this embodiment is mainly based on the DAC capacitor array, including the sampling stage, comparison stage, and output stage.

[0024] In one specific implementation, combined with Figure 2 The initial states of switches SH and SH' are open. The initial states of switches S0-S13 and S0'-S13' are also open. In the open state: switches S0-S4 and S0'-S4' are both connected to 1 / 2 Vref, and Gnd is disconnected; switches S5-S13 and S5'-S13' are both connected to Vref, and Gnd is disconnected. In the closed state: switches S0-S4 and S0'-S4' are both connected to Gnd, and 1 / 2 Vref is disconnected; switches S5-S13 and S5'-S13' are both connected to Gnd, and Vref is disconnected.

[0025] Sampling phase: Close switches SH and SH', and charge the non-inverting and inverting input terminals of the comparator by input voltages VinP and VinN, respectively.

[0026] Comparison Phase: Switches SH and SH' are opened, and the first comparison is performed, yielding the first comparison result B0. If the input voltage VinP is greater than the input voltage VinN, then switch S13 is closed; otherwise, switch S13' is closed. The next comparison is then performed, yielding the second comparison result B1. If the in-phase voltage VshP is greater than the out-of-phase voltage VshN, then switch S12 is closed; otherwise, switch S12' is closed, and so on, yielding 15 comparison results B0, B1, ..., B14.

[0027] Output stage: The combinational logic unit converts the 15-bit comparison result into a parallel 12-bit ADC output through redundant calculations.

[0028] The SAR-ADC circuit in this embodiment configures the DAC capacitor array as a binary array of capacitors with multiple redundant bits and switches. By increasing the redundant bits and reducing the resistance of the unit capacitor, the binary search algorithm is completed using charge redistribution between capacitors to output a differential analog signal. A comparator compares the magnitude of the differential analog signal to output the original comparison result. A bit latch saves the original comparison result bit by bit as a multi-bit comparison result in binary digital signal form. A combinational logic unit converts the multi-bit comparison result into a multi-bit ADC output through redundant calculation. In this way, the ADC area can be reduced and the ADC speed can be improved by reducing the resistance of the unit capacitor. The reduction in accuracy and the influence of capacitor mismatch caused by reducing the resistance of the unit capacitor are reduced by setting redundant bits and redundant calculation. The speed and accuracy of SAR-ADC are balanced, and the area and power consumption of 10-bit or higher ADCs can be made smaller.

[0029] In one alternative implementation, the unit capacitance in the DAC capacitor array is the parasitic capacitance between metals.

[0030] Specifically, the structure of the unit capacitor C in this embodiment can be referred to Figure 3 , Figure 3 The middle line is a metal line. In this embodiment, the unit capacitance C can be formed using the parasitic capacitance between metals.

[0031] In one alternative implementation, the capacitance value of the unit capacitor is 0.8fF.

[0032] Specifically, in this embodiment, the capacitance value per unit capacitor is further reduced to 0.8fF compared to related technologies (1.5fF), thereby further reducing the area and improving the ADC speed. The additional inaccuracies and mismatches caused by the 0.8fF unit capacitor in this embodiment can be reduced by a redundancy algorithm based on redundant bit settings and redundant calculations.

[0033] In one optional implementation, the multi-bit comparison result is a 15-bit comparison result.

[0034] In one alternative implementation, the multi-bit ADC output is a 12-bit ADC output.

[0035] Specifically, the 15-bit comparison result can be represented by B0-B14. The 12-bit ADC output can be represented by D0-D11. The conversion relationship between the 15-bit comparison result and the 12-bit ADC output can be represented by Table 1.

[0036] Table 1:

[0037] In Table 1, the leftmost column represents the actual weights, which can be deduced from Table 1: D0=B0; D1 = B1 + B2 + B3; D2 = B7 + B6 + B5 + B4 + carry; D3 = B14 + B13 + B10 + B8 + B7 + B6 + B5 + carry; D4 = B13 + B12 + B11 + B8 + B7 + carry; D5 = B14 + B13 + B12 + B11 + B10 + B9 + B8 + carry; D6 = B13 + B9 + carry; D7 = B13 + B10 + carry; D8 = B14 + B13 + B11 + carry; D9 = B14 + B13 + B12 + carry; D10 = B14 + carry; D11 = Carry.

[0038] In one alternative implementation, the 12-bit ADC output has 2 redundant bits with a redundancy factor of 1.81.

[0039] Specifically, the redundancy coefficient can be expressed as The bit latch outputs a 15-bit comparison result, of which 1 bit is the remainder. That is, the 15-bit comparison result can be regarded as 14 bits. The redundancy coefficient is calculated based on 14 bits. After the redundancy calculation by the combinational logic unit, it becomes a 12-bit ADC output. That is, there are 2 bits of redundancy from the 15-bit comparison result to the 12-bit ADC output.

[0040] In one alternative implementation, the differential analog signal comprises 15 sets of differential signals.

[0041] In one alternative implementation, the DAC capacitor array includes 14 groups of capacitors whose access states are controlled by switches, and the capacitance ratio between the groups is 1:1:1:2:3:3:7:14:24:42:76:140:254:458.

[0042] Specifically, each of the 14 capacitor groups consists of two identical capacitors. The 14 capacitor groups are divided into two symmetrical capacitor combinations, which are connected to the non-inverting input and the inverting input of the comparator, respectively.

[0043] In one alternative implementation, the minimum capacitance value of the capacitors in the DAC capacitor array is a unit capacitance.

[0044] Specifically, in combination Figure 2Since the unit capacitance can be represented by C, the 14 groups of capacitors (i.e., the actual capacitors) are divided into two symmetrical capacitor combinations. Each combination of capacitors can be represented as 1C, 1C, 1C, 2C, 3C, 3C, 7C, 14C, 24C, 42C, 76C, 140C, 254C, and 458C. The relationship between the actual capacitance and the actual weight is shown in Table 2.

[0045] Table 2:

[0046] In Table 2, the higher-order actual capacitance is half the actual weight, while the lower-order capacitance cannot be less than one unit capacitance, so the minimum lower-order capacitance is one unit capacitance. The theoretical weight can be calculated based on the redundancy coefficient, and the actual weight is determined by adding the carry-over.

[0047] This embodiment also provides a chip, including the SAR-ADC circuit of the first aspect described above or any corresponding embodiment thereof.

[0048] The chip in this embodiment integrates the above-mentioned SAR-ADC circuit. By reducing the capacitance value of the unit capacitor, the ADC area in the chip can be effectively compressed and the ADC speed can be increased, thereby reducing the overall area and power consumption of the chip. At the same time, through redundant bit setting and redundant calculation, the accuracy reduction and the effect of capacitor mismatch caused by reducing the resistance value of the unit capacitor can be effectively reduced, and the chip has a high fault tolerance.

[0049] Since the processing and functions implemented by the chip in this embodiment are basically the same as those in the above embodiments and preferred embodiments, those already described will not be repeated.

[0050] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A SAR-ADC circuit, characterized in that, Includes DAC capacitor array, comparator, bit latch, combinational logic unit and clock logic unit; The input terminal of the DAC capacitor array is used to receive the sampling signal, the output terminal of the DAC capacitor array is connected to the input terminal of the comparator, the first clock receiving terminal of the DAC capacitor array is connected to the latch terminal of the bit latch, and the second clock receiving terminal of the DAC capacitor array is connected to the first clock output terminal of the clock logic unit. The DAC capacitor array includes a capacitor array with multiple redundant bits arranged in binary and a switch. By increasing the redundant bits and reducing the resistance value of the unit capacitor, the binary search algorithm is completed by redistributing the charge between capacitors to output a differential analog signal. The output of the comparator is connected to the input of the bit latch, and the reset terminal of the comparator is connected to the second clock output of the clock logic unit. The comparator is used to compare the magnitude of the differential analog signal to output the original comparison result. The output of the bit latch is connected to the input of the combinational logic unit, and the reset terminal of the bit latch is connected to the third clock output of the clock logic unit. The bit latch is used to save the original comparison result bit by bit as a multi-bit comparison result in the form of a binary digital signal. The clock receiving terminal of the combinational logic unit is connected to the fourth clock output terminal of the clock logic unit. The combinational logic unit is used to convert the multi-bit comparison result into a multi-bit ADC output through redundant calculation. The clock logic unit is used to provide a sample-and-hold clock to the DAC capacitor array, a reset clock to the comparator and the bit latch, and a synchronization clock to the combinational logic unit.

2. The SAR-ADC circuit according to claim 1, characterized in that, The unit capacitance in the DAC capacitor array is the parasitic capacitance between metals.

3. The SAR-ADC circuit according to claim 2, characterized in that, The capacitance of the unit capacitor is 0.8fF.

4. The SAR-ADC circuit according to claim 1, characterized in that, The multi-bit comparison result is a 15-bit comparison result.

5. The SAR-ADC circuit according to claim 4, characterized in that, The multi-bit ADC output is a 12-bit ADC output.

6. The SAR-ADC circuit according to claim 5, characterized in that, The 12-bit ADC output has 2 redundant bits, with a redundancy coefficient of 1.

81.

7. The SAR-ADC circuit according to claim 4, characterized in that, The differential analog signal includes 15 sets of differential signals.

8. The SAR-ADC circuit according to claim 4, characterized in that, The DAC capacitor array includes 14 groups of capacitors whose access status is controlled by switches. The capacitance ratio between the groups is 1:1:1:2:3:3:7:14:24:42:76:140:254:

458.

9. The SAR-ADC circuit according to claim 8, characterized in that, The minimum capacitance value of the capacitors in the DAC capacitor array is a unit capacitance.

10. A chip, characterized in that, Includes the SAR-ADC circuit as described in any one of claims 1 to 9.

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