Circuit module for multi-bit quantizer with feedback capacitor array weighted average
Patent Information
- Application Number
- CN202611121480.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-27
- Publication Date
- 2026-10-27
AI Technical Summary
[0005]针对现有技术所存在的上述缺点，本发明提供了用于多位量化器与反馈电容阵列加权平均的电路模块，能够有效克服现有技术所存在的难以在较小的额外开销下，对Δ-ΣADC的量化噪声与非线性谐波进行联合抑制的缺陷
[0026]与现有技术相比，本发明所提供的用于多位量化器与反馈电容阵列加权平均的电路模块，采样180nm标准CMOS工艺进行电路设计，通过对5位量化码进行高低位分解，在电路改动很少的基础上，仅将高3位粗量化码用于闭环反馈，使得数据加权平均控制电路与反馈开关的开销减小至原来的四分之一，使得模块布局布线变得更加便捷迅速，同时对低2位细量化码形成的细量化残差进行二阶数字滤波重构，使粗量化误差在数字域中得到抵消，从而能够在反馈电容阵列仅具有3位规模的情况下，实现5位由细量化误差决定的二阶噪声整形性能。
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Figure CN122993720A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to ADCs, and more particularly to a circuit module for weighted averaging of a multi-bit quantizer and a feedback capacitor array. Background Technology
[0002] Δ-Σ ADCs (Delta-Sigma ADCs, differential-integral ADCs) dominate in high-precision, low-noise measurements. Due to the need for loop stability of Δ-Σ modulators under large input signal amplitudes, multi-bit quantization and corresponding capacitor feedback techniques are often used in their design.
[0003] When the modulator order is fixed, the overall quantization noise in the loop is typically determined by the number of quantizer bits. In multi-bit quantization feedback processes, data weighted averaging is commonly used to suppress nonlinear harmonics and address the nonlinear errors caused by feedback capacitor array mismatch. However, when the number of quantizer bits is too high, the area and power consumption of the data weighted averaging control circuit increase exponentially. Therefore, optimizing the design for joint suppression of quantization noise and nonlinear harmonics in multi-bit quantized Δ-Σ ADCs with minimal additional overhead is a pressing technical challenge. Summary of the Invention
[0004] (a) Technical problems to be solved
[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a circuit module for weighted averaging of multi-bit quantizers and feedback capacitor arrays, which can effectively overcome the shortcomings of the prior art in jointly suppressing quantization noise and nonlinear harmonics of Δ-Σ ADC with relatively small additional overhead.
[0006] (II) Technical Solution
[0007] To achieve the above objectives, the present invention provides the following technical solution:
[0008] A circuit module for multi-bit quantizers and feedback capacitor array weighted averaging includes the following circuit components:
[0009] The Δ-Σ loop filter is the core of the ADC's signal processing. It receives the input analog signal and the feedback analog signal output from the 3-bit feedback capacitor array and performs second-order filtering.
[0010] A 5-bit successive approximation quantizer quantizes the output signal of the Δ-Σ loop filter, outputting the high 3 bits of coarse quantization code and the low 2 bits of fine quantization code;
[0011] The data weighted average control circuit cyclically changes the starting point of the unit feedback capacitor based on the high 3 bits of coarse quantization code, dynamically averages the capacitor mismatch error, and improves the linearity of the ADC.
[0012] A 3-bit feedback capacitor array, controlled by the high 3 bits of coarse quantization code, outputs a feedback analog signal;
[0013] The second-order digital filter, located off-chip, processes the lower 2 bits of fine quantization code and outputs the lower 2 bits of residual code.
[0014] The digital output merging circuit, located off-chip, merges the high 3 bits of coarse quantization code with the low 2 bits of residual code, and outputs a digital signal with second-order noise shaping effect determined by the fine quantization error.
[0015] Preferably, the 5-bit successive approximation quantizer quantizes the output signal of the Δ-Σ loop filter and outputs a 5-bit quantization code DOUT<4:0>, including the high 3 bits of coarse quantization code DOUT<4:2> and the low 2 bits of fine quantization code DOUT<1:0>.
[0016] The high 3 bits of coarse quantization code DOUT<4:2> are used to drive a 3-bit feedback capacitor array to achieve closed-loop feedback;
[0017] The lower 2 bits of the fine quantization code DOUT<1:0> do not participate in the closed-loop feedback and are directly output to an external second-order digital filter for processing.
[0018] Preferably, the high 3-bit coarse quantization code DOUT<4:2> is converted by thermometer code and then input into the data weighted average control circuit;
[0019] The data weighted average control circuit cyclically changes the starting point of the unit feedback capacitor selection according to the high 3 bits of the coarse quantization code DOUT<4:2> after transcoding, so that each unit feedback capacitor has an approximately equal average number of uses in multiple sampling periods. This dynamically averages the unit feedback capacitor mismatch error, reduces the capacitor mismatch error of the 3-bit feedback capacitor array, improves the linearity of the ADC, and outputs the capacitor array drive control signal DACCTL<7:0> to the feedback switch of the 3-bit feedback capacitor array.
[0020] Preferably, the 3-position feedback capacitor array consists of 8 unit feedback capacitors C DAC The system consists of components that, under the control of the capacitor array drive control signal DACCTL<7:0>, output a feedback analog signal to the Δ-Σ loop filter to achieve closed-loop feedback.
[0021] Preferably, the lower 2 bits of the fine quantization code DOUT<1:0> are decoded by residual polarity to form a fine quantization residual, which is then input into a second-order digital filter;
[0022] The second-order digital filter performs second-order noise shaping on the fine-quantization residual and outputs the lower 2 bits of the residual code to the digital output merging circuit.
[0023] Preferably, the transfer function of the second-order digital filter is (1 - z) / 2. -1 ) 2 , where z is the complex frequency variable of the Z-transform.
[0024] Preferably, the digital output merging circuit combines the high 3 bits of coarse quantization code DOUT<4:2> with the low 2 bits of residual code using an adder, so that the coarse quantization error generated during the coarse quantization process is canceled in the digital domain, and finally outputs a digital signal with second-order noise shaping effect determined by the fine quantization error.
[0025] (III) Beneficial Effects
[0026] Compared with existing technologies, the circuit module for weighted averaging of multi-bit quantizers and feedback capacitor arrays provided by this invention uses 180nm standard CMOS process for circuit design. By decomposing the 5-bit quantization code into high and low bits, and with minimal circuit modifications, only the high 3 bits of coarse quantization code are used for closed-loop feedback. This reduces the overhead of the data weighted averaging control circuit and feedback switch to one-quarter of the original, making module layout and routing more convenient and faster. At the same time, the fine quantization residual formed by the low 2 bits of fine quantization code is reconstructed by second-order digital filtering, so that the coarse quantization error is canceled in the digital domain. Thus, it is possible to achieve 5-bit second-order noise shaping performance determined by fine quantization error with only 3 bits of feedback capacitor array. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0028] Figure 1 This is a circuit diagram of the present invention;
[0029] Figure 2 This is a comparison diagram of the effects of the present invention and directly using a 5-bit feedback capacitor array circuit. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0031] The core of this invention is that it can achieve 5-bit second-order noise shaping performance determined by fine quantization error using only a 3-bit feedback capacitor array, thereby minimizing additional overhead while suppressing system quantization noise and ensuring system linearity.
[0032] The following describes the specific circuit components of the circuit module for weighted averaging of multi-bit quantizers and feedback capacitor arrays provided by this invention, using concrete examples (such as...). Figure 1 (as shown) and technical effects.
[0033] This invention includes the following circuit devices:
[0034] Δ-Σ loop filter (corresponding to) Figure 1 The Δ-Σ Loop Filter in the ADC is the core of the signal processing, receiving the input analog signal ( Figure 1 The feedback analog signal output from the VIP / VIN and 3-bit feedback capacitor array is subjected to second-order filtering.
[0035] 5-bit successive approximation quantizer (corresponding to) Figure 1 The 5-bit SAR ADC in the Δ-Σ loop filter quantizes the output signal and outputs the high 3 bits of coarse quantization code and the low 2 bits of fine quantization code.
[0036] Data weighted average control circuit (corresponding) Figure 1 The DWA (Dynamic Response Wafer) dynamically averages the capacitor mismatch error and improves the linearity of the ADC by cyclically changing the starting point of the unit feedback capacitor based on the high 3 bits of coarse quantization code.
[0037] 3-bit feedback capacitor array (corresponding to) Figure 1 C on the left side of the middle DAC (Capacitor array × 8), controlled by the high 3 bits of coarse quantization code, outputting a feedback analog signal;
[0038] Second-order digital filter (corresponding to) Figure 1 (1-z) on the right side of the middle -1 ) 2 Located outside the chip, it processes the lower 2 bits of fine quantization code and outputs the lower 2 bits of residual code;
[0039] Digital output merging circuit (corresponding) Figure 1 The adder on the right side of the chip is located off-chip. It combines the high 3 bits of coarse quantization code with the low 2 bits of residual code and outputs a digital signal with second-order noise shaping effect, which is determined by the fine quantization error.
[0040] I. 5-bit successive approximation quantizer
[0041] A 5-bit successive approximation quantizer quantizes the output signal of the Δ-Σ loop filter and outputs a 5-bit quantization code DOUT<4:0>, including the high 3 bits of coarse quantization code DOUT<4:2> and the low 2 bits of fine quantization code DOUT<1:0>.
[0042] The high 3 bits of coarse quantization code DOUT<4:2> are used to drive a 3-bit feedback capacitor array to achieve closed-loop feedback;
[0043] The lower 2 bits of the fine quantization code DOUT<1:0> do not participate in the closed-loop feedback and are directly output to an external second-order digital filter for processing.
[0044] II. Data Weighted Average Control Circuit
[0045] The high 3-bit coarse quantization code DOUT<4:2> is converted into thermometer code and then input into the weighted average control circuit.
[0046] The data weighted average control circuit cyclically changes the starting point of the unit feedback capacitor selection based on the high 3 bits of the coarse quantization code DOUT<4:2> after transcoding, so that each unit feedback capacitor has an approximately equal average number of uses in multiple sampling periods. This dynamically averages the unit feedback capacitor mismatch error, reduces the capacitor mismatch error of the 3-bit feedback capacitor array, improves the linearity of the ADC, and outputs the capacitor array drive control signal DACCTL<7:0> to the feedback switch of the 3-bit feedback capacitor array.
[0047] III. 3-position feedback capacitor array
[0048] A 3-bit feedback capacitor array consists of 8 unit feedback capacitors C DAC The system consists of components that, under the control of the capacitor array drive control signal DACCTL<7:0>, output a feedback analog signal to the Δ-Σ loop filter to achieve closed-loop feedback.
[0049] IV. Second-order digital filters
[0050] The lower 2 bits of the fine quantization code DOUT<1:0> are decoded by residual polarity to form a fine quantization residual, which is then input into a second-order digital filter.
[0051] The second-order digital filter performs second-order noise shaping on the fine-quantization residual and outputs the lower 2 bits of the residual code to the digital output merging circuit.
[0052] In the technical solution of this application, the transfer function of the second-order digital filter is (1 - z) -1 ) 2 , where z is the complex frequency variable of the Z-transform.
[0053] V. Digital Output Merging Circuit
[0054] The digital output merging circuit combines the high 3 bits of coarse quantization code DOUT<4:2> with the low 2 bits of residual code through an adder, so that the coarse quantization error generated during the coarse quantization process is canceled in the digital domain, and finally outputs a digital signal with second-order noise shaping effect determined by the fine quantization error.
[0055] This invention achieves an equivalent 5-bit quantization accuracy using only a 3-bit feedback capacitor array and an 8-bit data weighted average control circuit. This reduces the scale of the metric decoder, the number of data weighted average selection networks, the number of feedback switches, the number of unit feedback capacitors, and related power consumption, thereby reducing the design difficulty of multi-bit quantization and feedback Δ-Σ ADC circuits.
[0056] Figure 2 This is a comparison chart showing the performance of the present invention with that of directly using a 5-bit feedback capacitor array circuit (composed of 32 unit feedback capacitors). Considering non-ideal factors in actual circuits such as finite integrator gain, analog NTF zero-point offset, digital and analog coefficient mismatch, compensation path timing deviation, analog thermal noise, and residual mismatch of the feedback DAC after DWA, the noise transfer function of the present invention is very similar to that of a Δ-Σ ADC using 5-bit quantization and feedback in terms of residual noise floor and high-frequency noise shaping effect within the bandwidth. This verifies that the present invention can achieve joint optimization of multi-bit quantizers and feedback capacitor arrays in Δ-Σ ADCs with minimal overhead while ensuring performance is not affected in practical applications.
[0057] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A circuit module for weighted averaging of multi-bit quantizers and feedback capacitor arrays, characterized in that: Includes the following circuit components: The Δ-Σ loop filter is the core of the ADC's signal processing. It receives the input analog signal and the feedback analog signal output from the 3-bit feedback capacitor array and performs second-order filtering. A 5-bit successive approximation quantizer quantizes the output signal of the Δ-Σ loop filter, outputting the high 3 bits of coarse quantization code and the low 2 bits of fine quantization code; The data weighted average control circuit cyclically changes the starting point of the unit feedback capacitor based on the high 3 bits of coarse quantization code, dynamically averages the capacitor mismatch error, and improves the linearity of the ADC. A 3-bit feedback capacitor array, controlled by the high 3 bits of coarse quantization code, outputs a feedback analog signal; The second-order digital filter, located off-chip, processes the lower 2 bits of fine quantization code and outputs the lower 2 bits of residual code. The digital output merging circuit, located off-chip, merges the high 3 bits of coarse quantization code with the low 2 bits of residual code, and outputs a digital signal with second-order noise shaping effect determined by the fine quantization error.
2. The circuit module for weighted averaging of a multi-bit quantizer and a feedback capacitor array according to claim 1, characterized in that: The 5-bit successive approximation quantizer quantizes the output signal of the Δ-Σ loop filter and outputs a 5-bit quantization code DOUT<4:0>, including the high 3 bits of coarse quantization code DOUT<4:2> and the low 2 bits of fine quantization code DOUT<1:0>. The high 3 bits of coarse quantization code DOUT<4:2> are used to drive a 3-bit feedback capacitor array to achieve closed-loop feedback; The lower 2 bits of the fine quantization code DOUT<1:0> do not participate in the closed-loop feedback and are directly output to an external second-order digital filter for processing.
3. The circuit module for weighted averaging of a multi-bit quantizer and a feedback capacitor array according to claim 2, characterized in that: The high 3-bit coarse quantization code DOUT<4:2> is converted by thermometer code and then input into the data weighted average control circuit. The data weighted average control circuit cyclically changes the starting point of the unit feedback capacitor selection according to the high 3 bits of the coarse quantization code DOUT<4:2> after transcoding, so that each unit feedback capacitor has an approximately equal average number of uses in multiple sampling periods. This dynamically averages the unit feedback capacitor mismatch error, reduces the capacitor mismatch error of the 3-bit feedback capacitor array, improves the linearity of the ADC, and outputs the capacitor array drive control signal DACCTL<7:0> to the feedback switch of the 3-bit feedback capacitor array.
4. The circuit module for weighted averaging of a multi-bit quantizer and a feedback capacitor array according to claim 3, characterized in that: The 3-position feedback capacitor array consists of 8 unit feedback capacitors C DAC The system consists of components that, under the control of the capacitor array drive control signal DACCTL<7:0>, output a feedback analog signal to the Δ-Σ loop filter to achieve closed-loop feedback.
5. The circuit module for weighted averaging of a multi-bit quantizer and a feedback capacitor array according to claim 4, characterized in that: The lower 2 bits of the fine quantization code DOUT<1:0> are decoded by residual polarity to form a fine quantization residual, which is then input into a second-order digital filter. The second-order digital filter performs second-order noise shaping on the fine-quantization residual and outputs the lower 2 bits of the residual code to the digital output merging circuit.
6. The circuit module for weighted averaging of a multi-bit quantizer and a feedback capacitor array according to claim 5, characterized in that: The transfer function of the second-order digital filter is (1 - z) -1 ) 2 , where z is the complex frequency variable of the Z-transform.
7. The circuit module for weighted averaging of a multi-bit quantizer and a feedback capacitor array according to claim 5, characterized in that: The digital output merging circuit combines the high 3 bits of coarse quantization code DOUT<4:2> with the low 2 bits of residual code through an adder, so that the coarse quantization error generated during the coarse quantization process is canceled in the digital domain, and finally outputs a digital signal with second-order noise shaping effect determined by the fine quantization error.