Ternary encoding and decoding
Patent Information
- Application Number
- CN202610554094.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2026-01-22
- Filing Date
- 2026-04-24
- Publication Date
- 2026-10-27
Smart Images
Figure CN122993722A_ABST
Abstract
Description
Cross-reference of related applications
[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 793,650, filed April 24, 2025; No. 63 / 839,047, filed July 6, 2025; No. 63 / 861,030, filed August 10, 2025; and No. 63 / 965,521, filed January 22, 2026, all of which are incorporated herein by reference. Technical Field
[0002] This invention generally relates to digital data processing, and more particularly to methods and systems for encoding and decoding ternary data. Background Technology
[0003] In various computational domains such as artificial intelligence (AI) and digital signal processing, system performance can be enhanced by utilizing ternary values. In many cases, the data used in processing suffers from excessive precision due to traditional input sequences or sensor front-end systems. In this field, this problem of excessive precision is addressed by computationally reducing the number of bits used in certain representations. A ternary value, or "trit," can represent one of three states, such as {-1, 0, +1}. The use of ternary values can reduce the computational precision required for certain operations, which in turn can reduce power consumption and memory requirements, especially in resource-constrained devices such as embedded systems, autonomous systems, and mobile hardware.
[0004] However, traditional computing systems are based on binary logic and do not inherently support three-state data. This leads to inefficiencies in both storage and processing.
[0005] Now for reference Figure 1A , Figure 1B and Figure 1C These are schematic diagrams of data representation in existing technologies. Figure 1A The standard 8-bit binary value 110 is shown, where the bits are either 1 or 0. An 8-bit "byte" is the basic unit of data in most computer systems.
[0006] Figure 1B A single ternary value 120 with the values (1, -1, 1, 0, 0) is shown, representing the decimal value 63. Common existing techniques for storing the ternary value 120 are described below. Figure 1C As shown, each ternary value is represented by two bits, where (1,1) represents the ternary value 1, (0,0) represents the ternary value -1, and (0,1) or (1,0) represents the ternary value 0. Since two bits can represent four different states, using them to store only three states is inherently inefficient and results in wasted memory. Therefore, the ternary value 120 is represented as 10100 / 10111 in the two-bit representation 122. Attached Figure Description
[0007] The subject matter considered to be the present invention is specifically pointed out and explicitly claimed in the concluding section of the specification. However, the organization and operation of the invention, as well as its objects, features, and advantages, can be best understood by referring to the following detailed description, in conjunction with the accompanying drawings:
[0008] Figures 1A-1C This is a schematic diagram representing existing technology data;
[0009] Figure 2 This is a schematic block diagram of a trit encoder constructed and operated according to a preferred embodiment of the present invention;
[0010] Figure 3A It is constructed and operated according to a preferred embodiment of the present invention for decoding by Figure 2 A schematic block diagram of the trit encoder encoding the trit and the trit decoder;
[0011] Figure 3B It is by Figure 3A A conceptual diagram illustrating the bit-level operations performed by the decoder on the data stored in the row;
[0012] Figure 4 It can be used to implement Figure 2 and Figure 3A A schematic block diagram of the associated processing unit (APU) of the trit encoder and decoder;
[0013] Figure 5 This is a schematic block diagram of a trit encoder that implements an alternative mapping scheme, constructed and operated according to another preferred embodiment of the present invention;
[0014] Figure 6 It is constructed and operated according to another preferred embodiment of the invention, for decoding by Figure 5 A schematic block diagram of a trit encoder encoding a trit and a trit decoder; and
[0015] Figure 7 This is a schematic block diagram of another trit decoder for applications with sparse data.
[0016] It should be understood that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, reference numerals may be repeated in the figures where deemed appropriate to indicate corresponding or similar elements. Detailed Implementation
[0017] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known methods, processes, and components have not been described in detail so as not to obscure the invention.
[0018] The applicant has recognized that a major obstacle to the effective use of ternary data in high-performance hardware is the lack of computationally simple decoding methods. The complexity of conventional division and modulo operations in the hardware creates significant performance bottlenecks.
[0019] The applicant also recognizes that it is advantageous to use an encoding system of less than 2 bits / trit. The most dense possible form is one using 1.6 bits / trit. This invention encodes 1.58 bits / trit (i.e., using 8 bits to encode 5 trits).
[0020] The applicant has recognized that a decoding system using only Boolean operations is extremely efficient. The applicant also recognizes that encoding the trit using a base-3 representation makes it possible to decode the encoded trit using Boolean operations.
[0021] Now for reference Figure 2 , Figure 2 This is a schematic block diagram of a trit encoder 200 constructed and operated according to a preferred embodiment of the present invention. The trit encoder 200 can receive a set of input ternary values 210. Each input ternary value 210 can be a value from the set {-1, 0, +1}. Figure 2 In the example, the input ternary set has five trit values (-1, 0, +1, -1, +1). Encoder 200 generates a single encoded integer 250 from the input ternary value 210. In this example, the encoded integer 250 has 8 bits.
[0022] The trit encoder 200 may include a trit mapper 220, a weighted summer 230, and a binary converter 240. The trit mapper 220 may receive input ternary values 210 and may map each value to a corresponding non-negative integer. For example, the trit mapper 220 may add a 1 to each of the input ternary values 210 to produce a set of five mapped integers 225, each mapped integer having a value from the set {0, 1, 2}. Mathematically, this is written as: Equation (1) in It is the mapped integer value, and It is the trit value. In Figure 2 In the example, the five mapped integers 225 are (0, 1, 2, 0, 2).
[0023] The weighted summer 230 can receive the mapped integer 225. The weighted summer 230 can calculate the weighted sum WS by processing the mapped integer 225 into numbers represented by a base-3 matrix. The weighted summer 230 can multiply each of the five mapped integers by its corresponding power of 3 (i.e., 1, 3, 9, 27, and 81) and sum the results. Mathematically, this is written as: Equation (2) for Figure 2 For example, the weighted sum WS is 183.
[0024] The binary converter 240 can receive the weighted sum WS and convert it into an 8-bit encoded integer 250. Therefore, for Figure 2 For example, the weighted sum WS is converted to an 8-bit integer 10110111.
[0025] It should be understood that a maximum value for the weighted sum WS can exist, and this maximum value can fit within a predefined range defined by the number of binary bits. In the example of an 8-bit integer, the maximum value of the weighted sum WS is 242, which fits within the range of an 8-bit integer, from 0 to 256. This encoding method achieves the compression of five ternary values into eight bits.
[0026] Now for reference Figure 3A and Figure 3B , Figure 3A The invention illustrates a preferred embodiment of a method for decoding... Figure 2 A schematic block diagram of the TRIT encoder 200 encoding the TRIT and the TRIT decoder 300, and referenced. Figure 3B , Figure 3B An example of decoding is provided. The trit decoder 300 can accept an 8-bit encoded integer, denoted here as b, and can produce a set of five decoded ternary values T.
[0027] The trit decoder 300 may include a multiplier 320, a shifter 330, a remainder logic block 340, and a remapping logic block 350. The trit decoder 300 can iteratively process the encoded integer b to extract each of the five ternary values T(i).
[0028] In the first iteration, multiplier 320 can multiply the value of the encoded integer b by a predetermined integer constant K to produce a 17-bit integer S. The applicant has recognized that 171 is the smallest constant that guarantees exact division over the entire 8-bit byte range from 0 to 256, therefore K can have the value 171 (or hexadecimal 0xAB).
[0029] Shifter 330 can receive a 17-bit product S from multiplier 320 and can right-shift the encoded integers being multiplied by a fixed number of bits to produce a quotient q. For the 8-bit example given above, shifter 330 can right-shift the product S by 9 bits to give an 8-bit quotient q.
[0030] Then, the remainder logic 340 can use the encoded integer b and 3 multiplied by the quotient q to calculate the initial remainder R. The remainder R will be an integer from the set {0, 1, 2}.
[0031] In mathematics, this is written as: Equation (3) is R = b - 3q
[0032] The remapping logic 350 can receive the remainder R and can convert the remainder R into a ternary value by subtracting one (1). This can produce the first trit, T (1). For the next iteration, the variable b can be replaced by the current value of the quotient q to be used as a new input for the multiplier 320 for the next iteration, and the process can be repeated to extract subsequent ternary values to recover all five decoded ternary values T.
[0033] Figure 3B This shows data stored in some rows of registers. Figure 3A Example bitwise operations. The binary-encoded ternary value b (i.e., 10110111) is stored in the first row 360. Multiplier 320 multiplies the value b by 171, producing the bit value 00111101001011101 stored in the second row 362. Shifter 330 then shifts the bits in the second row 362 to the right by 9 bits to produce the quotient q (i.e., 00111101) stored in the row 364. In the decimal term, q has the value 61.
[0034] Then, remainder logic 340 multiplies the quotient q by 3 (i.e., 3). 61=183), generating the binary value 10110111, which is exactly the same as the current value of b (i.e., 10110111). Remainder logic 340 subtracts 3q from variable b to produce a remainder R, in which case the remainder R is 0. (R=b-3q=10110111-10110111=0). Then, trit is R-1, therefore, for the first iteration, trit T(1) is -1. Figure 2 The first value of the input trit.
[0035] In preparation for the next iteration, variable b is updated to the current value of q, and the iteration number i is incremented by 1. Therefore, the new b = q = 00111101 = 61. This process is repeated 4 times, at which point the original bytes will be exhausted (i.e., q will be 0 after the last iteration).
[0036] It should be understood that multiplying by 171 can be performed as a single operation or via four parts of 2. x The multiplication is performed in 1, 2, 8, 32 and 128, since 171 = 128+32+8+2+1.
[0037] This logic can be implemented using any suitable hardware or software. For example, it can be implemented using field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), leveraging gate-level primitives to achieve efficient hardware implementation without the need for division or modulo units. This compact logic gate implementation is suitable for edge artificial intelligence (AI), embedded machine learning (ML) systems, and neural network accelerators.
[0038] It should be understood that modern AI systems are based on neural networks with large neural networks activated by network weights. In the past, such neural networks used numerical weights (multi-bit values) or binary weights (unit values). The applicant has recognized that the present invention enables AI systems to use ternary weights due to reduced precision and power requirements.
[0039] The applicant has recognized that the trit decoder 300 is particularly well-suited for implementation in parallel computing architectures such as associative processing units (APUs). References are now available. Figure 4 It is a schematic block diagram of an APU400 (such as a Gemini APU) that can be commercially purchased from the applicant (GSI Technologies, Inc. of the USA).
[0040] The APU 400 may include an associative memory array 410 controlled by a controller 420, a row decoder 430, and a column decoder 440. The associative memory array 410 may be arranged as a grid of memory cells 412 organized into rows 416 and columns 414. In this architecture, multi-bit data items (such as 8-bit encoded integers) may be stored in a single column 414.
[0041] The APU 400 may also include multiple bitline processors 450, each associated with column 414. The controller 420 may issue commands to cause the bitline processors 450 to perform logical and arithmetic operations on the data within their respective columns in a massively parallel manner. Specifically, the controller 420 may activate row decoders 430 to simultaneously activate multiple rows, and activate column decoders 440 to activate multiple bitline processors 450. Each bitline processor 450 may sense the result of a Boolean operation on the data of the activated row in that column.
[0042] Return to reference Figure 3B The bit-level operations shown can be performed within a column 414 of the associative memory array 410 (rather than in a column 414). Figure 3B(This is performed in the register line shown). Therefore, if there are many encoded integers, such as the weights of a neural network layer, they can be decoded together in parallel.
[0043] The steps (multiplication, shifting, and subtraction) performed by the decoder 300 can be broken down into a series of simple bitwise logical operations commanded by the controller 420, as described below.
[0044] It should be understood that a right shift in column 414 can be performed by only performing the later steps (the steps shown in rows 364, 366 and 368) on the top 8 rows of the column (corresponding to the top 8 bits of the 17-bit product S).
[0045] ( Figure 4 The bit-line processor 450 can perform these operations simultaneously on all stored encoded integers. This parallel execution allows for the simultaneous decoding of a large number of values, thereby achieving extremely high throughput in a fixed, minimal number of clock cycles.
[0046] It should be understood that the APU can perform the entire quintet decoding operation in less than 6 cycles. For such operations, the decoding operation can overlap with the subsequent MAC acquisition, making the decoding operation bandwidth-dependent rather than latency-dependent.
[0047] It should be understood that the decoder 300 can be implemented in various ways. For example, it can operate on 32-bit streams. For these, the encoded integer can be multiplied by the reciprocal 0xAAAAAAB hexadecimal value and then shifted by the appropriate number of bits, such as 33 bits. The result can be four 8-bit bytes, each divided by 3 in parallel.
[0048] Another implementation can utilize an unbalanced ternary value with one of (0, 1, 2) values instead of one of (-1, 0, 1) values. For this implementation, a final "-1" bias step is not required.
[0049] Another implementation could utilize a vector GPU for edge devices. This implementation can be advantageously compared to ASTC decoders, which typically replace multiplications with 2-KB LUTs to achieve throughput. The arithmetic approach described above matches LUT speed while saving cache and is more edge-device-friendly.
[0050] The applicant has recognized that ternary data can often be sparse (i.e., zero values appear frequently) in many practical applications, such as those used to store neural network weights. The applicant has also recognized that encoding schemes that map ternary zeros to non-zero integers can process all data uniformly. The applicant has recognized that mapping schemes that preserve zero values can provide significant computational advantages by implementing a “fast path” for blocks of all-zero data, which can allow for enhanced compression and processing speed.
[0051] Now for reference Figure 5 , Figure 5 This is a schematic block diagram of a trit encoder 500 constructed and operated using this particularly advantageous mapping scheme according to a preferred embodiment of the invention. The trit encoder 500 may include a zero-to-zero trit mapper 520, a weighted summer 230, and a binary converter 240.
[0052] In this embodiment, the zero-to-zero trit mapper 520 can receive a set of input ternary values 510, for example, from Figure 2 The input ternary value, which comes from Figure 2 The input ternary values are (-1, 0, +1, -1, +1). Mapper 520 can map these ternary values to a set of mapped integers 525 according to the following rules: The ternary value 0 is mapped to the mapped integer 0. The ternary value +1 maps to the mapped integer 1, and The ternary value -1 is mapped to the mapped integer 2.
[0053] For an input of 510, this can produce a mapped integer of 525 (2, 0, 1, 2, 1).
[0054] As in Figure 2 In one embodiment, the weighted summer 230 may receive a mapped integer 525 and may compute a weighted sum by processing the mapped integer 525 into a number represented by a base 3, which in this embodiment may produce a weighted sum (WS) with a value of 146. The resulting weighted sum may then be converted by a binary converter 240 into an 8-bit encoded integer 550 having a binary value of 10010010.
[0055] Now for reference Figure 6 , Figure 6This is a schematic block diagram of a trit decoder 600 for decoding the encoded integer 550 generated by encoder 500. Similar to trit decoder 300, trit decoder 600 may include a core arithmetic engine 315, which includes a multiplier 320, a shifter 330, and a remainder logic block 340. However, in this embodiment, trit decoder 600 includes a zero-reserved remapping logic block 650. Decoder 600 may receive the encoded integer 146 and iteratively process the encoded integer 146 to extract the original ternary value. Core arithmetic engine 315 may generate a sequence of modulo-3 remainders R.
[0056] The zero-retention remapping logic block 650 can receive each remainder R and can apply the corresponding inverse mapping function f(R) to recover the ternary value T(i) according to the following rules: The remainder 0 is remapped to the ternary value 0; The remainder 1 is remapped to the ternary value + 1, and The remainder 2 is remapped to the ternary value -1.
[0057] Logic block 650 can also manage iterations by using the quotient q from the previous iteration as a new input for the subsequent iteration.
[0058] When the input ternary value 510 is all zeros Figure 5 and Figure 6 The advantages of this mapping scheme are perhaps most obvious. In this particular case, the encoded integer 550 is 0 (i.e., 8 zeros).
[0059] Now for a brief reference Figure 7 The diagram illustrates a trit decoder 700 for applications with sparse data, such as for storing neural network weights. The trit decoder 700 may be similar to the trit decoder 600, but may additionally include a zero-checker 710 preceding the core arithmetic engine 315.
[0060] The zero checker 710 can perform a check on the received encoded bytes; if the byte is zero, the zero checker 710 can output a trit consisting of all five zero values and can skip the remaining elements of the decoder 700.
[0061] Furthermore, the zero-checker 710 can instruct any unit operating on the output of the decoder 700 to skip an upcoming multiplication operation or an upcoming multiply-accumulate operation. For example, if the unit receiving the output of the decoder 700 is a multiplier, the multiplier can provide a zero output when the zero-checker 710 so instructs. Alternatively, if the unit receiving the output of the decoder 700 is a node of a neural network, the node can skip its operation when the zero-checker 710 so instructs.
[0062] Specific to the architecture of the APU 400, additional optimizations may be possible. The output of the zero-checker 710 can be used as a hardware trigger gate in an online comparison to skip subsequent downstream processing operations, such as MAC operations.
[0063] It should be understood that the core arithmetic engine 315 can be independent of the specific mapping scheme used during encoding. The core arithmetic engine 315 can be designed to recover base-3 numbers from weighted sums, regardless of how those numbers were originally derived. Therefore, the same arithmetic hardware can correctly process the encoded integer 183 (from...). Figure 2 ) and the encoded integer 146 (from Figure 5 ).
[0064] While certain features of the invention have been shown and described herein, many modifications, substitutions, alterations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and alterations falling within the true spirit of the invention.
Claims
1. A method for encoding a set of ternary values into encoded integers having a predefined number of bits, each ternary value being selected from a set {-1, 0, +1}, the method comprising: Map the ternary value to a set of mapped integers, where each mapped integer is a non-negative integer in the set {0, 1, 2}; as well as The weighted sum of the mapped integers is calculated using powers of 3, wherein the final result fits a predefined byte range defined by the predefined number of bits.
2. The method of claim 1, further comprising converting the final result into a binary value.
3. The method according to claim 1, wherein, The calculation includes processing the mapped integer into a number represented by a base 3.
4. The method according to claim 3, wherein, The process includes multiplying each of the mapped integers by the corresponding power of three to produce a multiplied value, and summing the multiplied values.
5. The method according to claim 1, wherein, The predefined number of bits is 8 bits, the set of ternary values has 5 values, and for the 8-bit integer, the range of the predefined byte is 0 to 256.
6. A system for encoding a set of ternary values into encoded integers having a predefined number of bits, each ternary value being selected from a set {-1, 0, +1}, the system comprising: A trit mapper is used to map each of the ternary values to a set of mapped integers, where each mapped integer is a non-negative integer in the set {0, 1, 2}. A weighted summer, the weighted summer being used to calculate a weighted sum of the mapped integers by processing the mapped integers into numbers represented in base 3; as well as A binary converter operatively connected to the weighted summer, the binary converter being configured to convert the weighted sum into the encoded integer.
7. The system according to claim 6, wherein, The weighted summer is configured to multiply each of the mapped integers by the corresponding power of three, and sum the results of the multiplication to compute the weighted sum.
8. The system according to claim 6, wherein, The predefined number of bits is 8, and the set of ternary values has five values, and for the 8-bit integer, the byte range is 0 to 256.
9. An associative processing unit (APU) for parallel encoding multiple sets of ternary values into encoded integers having a predefined number of bits, each ternary value being selected from a set {-1, 0, +1}, the APU comprising: An associative memory array having multiple bitline processors, wherein the set of ternary values is stored in columns of the associative memory array, and A controller configured to issue commands to the APU to implement, on the bitline processor, the trit mapper, the weighted summer, and the binary converter according to claim 6 via bitwise logical operations on the set of ternary values.
10. A method for decoding an encoded binary integer into a set of ternary values, the method comprising: The encoded binary integer is multiplied by a predetermined integer constant to produce a multiplied encoded integer, wherein the predetermined integer constant is the smallest constant capable of division within a predefined byte range; The encoded binary integers of the multiplication are shifted right by a fixed number of bits to produce an iterative version of the quotient; The modulo-3 remainder of the iterative version of the encoded binary integer is calculated iteratively by comparing iterative versions of the quotient with multiples of 3; and Set each ternary value as a function of each modulo-3 remainder.
11. The method according to claim 10, wherein, The byte range is 0 to 256, and the predetermined integer constant is 171.
12. The method according to claim 11, wherein, The fixed number of bits is 9.
13. The method according to claim 10, wherein, The function is to subtract 1.
14. The method of claim 10, further comprising: For the next iteration, the current iteration version of the encoded binary integer is replaced with a previous iteration version of the quotient.
15. A system for decoding encoded binary integers into a set of ternary values, the system comprising: A multiplier for multiplying the encoded binary integer by a predetermined integer constant to produce a multiplied encoded integer, wherein the predetermined integer constant is the smallest constant capable of performing division within a predetermined byte range to produce a multiplied encoded integer; A shifter for right-shifting the encoded integers of the multiplication by a fixed number of bits to produce an iterative version of the quotient; A remainder logic block, the remainder logic block being used to calculate the modulo-3 remainder of the iterative version of the encoded binary integer based on the iterative version of the quotient; and A remapping logic block is used to set a ternary value for the current iteration based on the modulo-3 remainder, and to use an iterative version of the quotient from a previous iteration as an iterative version of the encoded binary integer for subsequent iterations.
16. The system according to claim 15, wherein, The encoded binary integer is an 8-bit integer, and the predetermined integer constant is 171.
17. The system according to claim 16, wherein, The fixed number of bits used for the right shift is 9.
18. The system of claim 15, wherein the remapping logic block is configured to set the ternary value by subtracting 1 from the modulo-3 remainder.
19. An association processing unit (APU) for parallel decoding of a set of encoded binary integers into multiple sets of ternary values, the APU comprising: An associative memory array having multiple bitline processors, wherein the set of ternary values is stored in columns of the associative memory array, and A controller configured to issue commands to the APU to implement, on the bitline processor, the multiplier, shifter, remainder logic block, and remapping logic block as claimed in claim 15 via bitwise logical operations on the set of ternary values.
20. The system according to claim 19, wherein, The controller implements the shifter by activating only a subset of rows, the subset of rows corresponding to the high bits of the encoded integers being multiplied.
21. The system according to claim 15, wherein, The remapping logic block is a zero-retention remapping logic block configured to recover the ternary value according to the following rules: The remainder 0 is remapped to the ternary value 0; The remainder 1 is remapped to the ternary value + 1, and The remainder 2 is remapped to the ternary value -1.
22. The system of claim 21, further comprising a zero checker preceding the multiplier, the zero checker being configured to output a ternary value of 0 for all trits when the encoded binary integer has a value of 0.