A priori method and system for coding input information

Abstract

The application discloses a priori method and system for decoder input information, comprising: acquiring LLR values of M diversity copies in the kth information bit in real time; performing consistency detection on the signs of the LLR values of the M diversity copies in the kth information bit, and performing priori assignment on the information bit according to the detection result to obtain corresponding priori assignment values as first input information; calculating the difference between the LLR values of the kth information bit after combination and the priori assignment values as second input information; constructing the first input information and the second input information into total input information, and then sending the total input information into a decoder. The application can provide non-zero priori information for high consistency (satisfying sign consistency) bits, and can quickly converge to a stable state within the first 1-2 iterations, thereby improving decoding efficiency.

Description

Technical Field

[0001] The invention relates to the field of communication technology, and in particular to a priori method and system for decoder input information. Background Technology

[0002] In the field of power line carrier (PLC) communication technology for the State Grid Corporation of China, the transmitting end copies the same information bit to multiple different OFDM (Orthogonal Frequency Division Multiplexing) symbols and different subcarriers, forming multiple diversity copies. The receiving end combines the soft bits of these diversity copies into an LLR (log-likelihood ratio), and then sends the LLR as input information to the decoder for decoding.

[0003] In diversity copy scenarios, the receiver possesses multiple independent copies of the same bit. The LLR symbol consistency of these copies carries crucial information about the bit's reliability: complete LLR symbol consistency across all copies indicates high determinism, while symbol divergence suggests significant uncertainty. Existing schemes use a single merged LLR value as input, completely discarding this additional information about "inter-copy consistency," leaving the decoder unable to determine which bits are more reliable.

[0004] In the existing scheme, the merged LLR is directly used as the system bit input of the decoder, and all prior information is initialized to zero. This means that the decoder does not know which bits are more reliable and which bits are more ambiguous. The reliability of all bits needs to be gradually "explored" through an iterative process.

[0005] In current technology, the following methods are generally used to verify the input information of the decoder: Option A: Zero Prior Initialization – The standard practice in current State Grid dual-mode communication receivers. All prior soft information in the Turbo decoder is uniformly initialized to zero, and only the LLR after the subset is merged is used as input for Systematic Bits. This means that the decoder's "preconceived notion" for each bit is completely zero, and multiple iterations are required to gradually determine the reliability of each bit, resulting in a high average number of iterations.

[0006] In Scheme A, all priors are zero, and the Turbo decoder must start iterating from a "completely uncertain" state. For bits that are actually very certain (such as all replicas having a large LLR), this "start from zero" strategy is clearly inefficient—these bits hardly change in the first few iterations but still participate in all the computations.

[0007] Option B: Early Termination of CRC – After each iteration, a CRC (Cyclic Redundancy Check) is performed; if successful, the iteration is terminated early. This is a "passive" power optimization strategy: it does not change the decoder input, but only checks whether it has succeeded after a certain iteration. Its limitation is that at least one complete iteration must be completed before a determination can be made, and it cannot provide useful prior information at the beginning of decoding to shorten the convergence process, resulting in low decoding efficiency.

[0008] Scheme C: Prior weighting based on signal-to-noise ratio (SNR) – Different prior weights are assigned based on the estimated SNR of the subcarrier containing each bit: bits on high SNR subcarriers receive larger prior weights, while bits on low SNR subcarriers receive smaller prior weights. The drawback of this scheme is its reliance on the accuracy of SNR estimation. The time-varying nature of the PLC channel introduces errors in SNR estimation itself, and calculating SNR requires additional hardware resources. Scheme C requires SNR estimation for each subcarrier, which not only increases hardware complexity but also the error in SNR estimation under the time-varying PLC channel can distort the prior weights, negatively impacting decoding performance and resulting in lower decoding efficiency. Summary of the Invention

[0009] To address the technical problem of low decoding efficiency caused by iterative verification of input information in existing decoders, this invention proposes a priori method and system for decoder input information. By comparing the symbol consistency of each replica LLR, the input information is divided into two categories: "high confidence" and "low confidence". A non-zero prior LLR initial value is assigned to the high confidence level, thereby enabling the decoder to quickly "lock" the correct result on the high-reliability bits, reducing useless iteration consumption and improving decoding efficiency.

[0010] To achieve the above objectives, the present invention provides the following technical solution: A priori method for decoder input information specifically includes the following steps: S1: Real-time acquisition of the LLR values ​​of the M diversity replicas in the k-th information bit; S2: Perform a sign consistency check on the LLR values ​​of the M diversity replicas in the k-th information bit, and perform prior allocation on the information bit according to the check result to obtain the corresponding prior assignment as the first input information; S3: Calculate the difference between the combined LLR value of the kth information bit and the prior value, and use it as the second input information; S4: Construct the first input information and the second input information into the total input information, and then send the total input information into the decoder.

[0011] Preferably, in step S1, the LLR values ​​of the M diversity replicas are sent to the storage module for storage.

[0012] Preferably, S2 includes: S2-1: Perform a symbol consistency check on the LLR value of each diversity replica in the information bits to determine whether symbol consistency is satisfied; S2-2: Priorally allocate the information bits that satisfy symbol consistency to obtain prior assignments; S2-3: Keep the prior information bits that do not satisfy symbol consistency at zero.

[0013] Preferably, in step S2-1, the method for determining symbol consistency is as follows: The most significant bit of the LLR value of each diversity replica is operated on using a sign function; if the operation results are the same, it is determined that the sign consistency is satisfied; if the operation results are different, it is determined that the sign consistency is not satisfied.

[0014] Preferably, in step S2-2, the calculation method for the prior assignment is as follows: L_prior(k) = α · sign( ) · | | Where L_prior(k) represents the prior assignment of the k-th information bit; α∈(0,1) is the prior strength factor; sign( ) represents the result of the operation; | | represents the LLR value after merging the k-th information proportion, 1≤k≤K, where K represents the total number of information proportions.

[0015] Preferably, it also includes a hierarchical prior strategy: If all the calculation results are the same, the grade of the calculation result is determined to be level one: L_prior(k) = α_max · sign( ) · | | Where α_max represents the highest prior strength factor; When the number of any one type of operation result exceeds half of the total number, the operation result is classified as level two. L_prior(k) = α_midx · sign( ) · | | Where α_mid represents the moderate prior strength factor; When the number of any operation result is no more than half of the total number, the level of the operation result is determined to be level three, and the prior is kept to zero.

[0016] Preferably, in step S3, the method for obtaining the second input information is as follows: L_sys'(k) = | | - |L_prior(k)| Where L_sys'(k) represents the second input information of the k-th information bit; | | represents the combined LLR value corresponding to the k-th information bit; |L_prior(k)| represents the prior assignment of the k-th information bit.

[0017] The present invention also provides a priori system for decoder input information, comprising: The data acquisition module is used to acquire the LLR values ​​of M diversity replicas in real time during the information bit transmission process; The storage module is used to store the LLR values ​​and prior assignments of M diversity replicas; The symbol consistency detection module is used to detect the symbol of the LLR value of each diversity replica and determine whether it meets the symbol consistency requirement. The prior allocation module is used to perform prior allocation on information bits that satisfy symbol consistency, and obtain prior assignments as the first input information. The differential construction module is used to calculate the difference between the LLR value after combining information bits and the prior assignment, which serves as the second input information; The output module is used to construct the total input information from the first input information and the second input information, and then send the total input information to the decoder.

[0018] Preferably, the symbol consistency detection module further includes a bit calculator; the bit calculator is used to count the number of LLR value symbol operation results that are the same in the same information bit, and to determine the level of the operation result.

[0019] Preferably, the symbol consistency detection module further includes a priori adjustment unit; the priori adjustment unit is used to dynamically adjust the priori strength factor to calculate the priori assignment based on the level of the calculation result.

[0020] In summary, by adopting the above technical solution, the present invention has at least the following beneficial effects compared with the prior art: Significantly reduces the average number of decoding iterations: This invention provides non-zero prior information for highly consistent (symbolic consistency) bits, which can quickly converge to a stable state within the first 1-2 iterations, and propagates determinism to neighboring bits through the inherent constraints of Turbo coding.

[0021] Zero additional pilot overhead: The symbol consistency detection of this invention only relies on the individual LLR data that already exists in the diversity replica merging stage. This invention does not require any SNR estimation, additional pilots, or channel estimation results, and achieves significant power consumption benefits at extremely low cost.

[0022] Simple structure: This invention only requires an XOR operation on the sign bit of each replica LLR during symbol consistency detection, and the prior value calculation requires only one multiplication (or shift). The hardware increment of the entire module is far less than the power consumption of an SNR estimator or an additional Turbo iteration. This makes this solution highly practical for resource-constrained smart meter chips.

[0023] Highly practical: This solution only modifies the interface between the diversity merging module and the Turbo decoding module, without affecting other modules such as FFT, channel estimation, demodulation, and diversity merging. It can plug-and-play replace the direct path in existing receivers without requiring modifications to the transmitter or protocol frame structure. Furthermore, it can be used in conjunction with diversity replica weighted merging technology; the combined effect of the two is greater than the sum of their individual effects. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a priori method for decoder input information according to an exemplary embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of a priori system for decoder input information according to an exemplary embodiment of the present invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to embodiments and specific implementation methods. However, this should not be construed as limiting the scope of the above-described subject matter of the present invention to the following embodiments; all technologies implemented based on the content of the present invention fall within the scope of the present invention.

[0027] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0028] like Figure 1 As shown, the present invention provides a priori method for decoder input information, specifically including the following steps: S1: The LLR values ​​of M diversity replicas during the transmission of any information bit can be obtained from the server in real time.

[0029] In this embodiment, the existing time-domain diversity method can be used to copy the information bits into M diversity replicas, and then encode and transmit them. Each diversity replica will generate a corresponding LLR value (M values) after soft demodulation. The M LLR values ​​are merged and used as input information and sent to the decoder.

[0030] In this embodiment, the LLR value corresponding to each diversity replica can be stored in the storage module for easy access at any time. It can be deleted after classification is completed and will not occupy the storage module space for a long time. The modification to the existing merging module is minimal but the effect is significant. Instead of discarding the replicas directly after merging in the prior art, this additional information of "inter-replica LLR value consistency" is completely discarded, which makes it impossible for the decoder to know which bits are more reliable.

[0031] In this embodiment, the k-th information bit is copied to M diversity replicas, and the corresponding LLR values ​​form a value set. , Let L_m represent the LLR value of the m-th diversity replica; then, the m LLR values ​​are merged using existing weighting techniques to obtain the merged LLR value L_merged(k), which represents the LLR value of the k-th information bit after merging.

[0032] S2: Perform a sign consistency check on the LLR value of each diversity replica in each information bit, and perform prior assignment on the information bit according to the check result to obtain the corresponding prior assignment, which serves as the first input information of the information bit.

[0033] Specifically, such as Figure 2 As shown, S2 specifically includes the following steps.

[0034] S2-1: Check the symbol of the LLR value of each diversity replica in the information bits to determine whether symbol consistency is satisfied.

[0035] In existing technologies, the sign of the LLR value of a diversity replica itself carries important information about the reliability of that bit: complete consistency of the signs of the LLR values ​​of all diversity replicas indicates a high degree of certainty for that bit, while sign divergence indicates significant uncertainty. Current schemes use the merged single LLR value as input information, merging the LLR values ​​of each diversity replica and then discarding them, without utilizing the known signs of the LLR values ​​of the diversity replicas for further detection.

[0036] In this embodiment, the prior assignment does not require any SNR estimation, additional pilots, or channel estimation results. It only requires analyzing the sign consistency of the LLR values ​​of each diversity replica to transform this "free" information into usable prior soft information, filling this information gap and achieving significant power consumption benefits at extremely low cost.

[0037] In this embodiment, the method for determining symbol consistency is as follows: The most significant bit of the LLR value of each diversity replica is operated on using a sign function (such as the sgn function or the sign function); if the operation results are the same, it is determined that the sign consistency is satisfied; if the operation results are different, it is determined that the sign consistency is not satisfied.

[0038] For example, if the highest bit of the LLR value is greater than 0, the sign function returns 1; if the highest bit of the LLR value is equal to 0, the sign function returns 0; if the highest bit of the LLR value is less than 0, the sign function returns -1. The sign function returns 1, -1, or 0 for all LLR values ​​in the same information bit (i.e., sign(L_1) = sign(L_2) = … = sign( If the LLR values ​​of a portion of the information bit are 1 and the LLR values ​​of a portion of the information bit are 0, then the information bit is determined not to satisfy the sign consistency.

[0039] In this embodiment, a bit calculator can also be set up to count the number of LLR value sign operations with the same result in the same information bit, and to determine the grade of the operation result.

[0040] For example, the number of operations that result in 1 is The number of operations that result in 0 is The number of operations that result in 1 is , M represents the total number of LLR values ​​(or diversity copies) in the same information bit.

[0041] S2-2: Prior-allocate the information bits that satisfy symbol consistency (symbol detection result flag_k is 1) to obtain the prior assignment: L_prior(k) = α · sign( ) · | | Where L_prior(k) represents the prior assignment of the k-th information bit; α∈(0,1) is the prior strength factor, typically α=0.3-0.5; sign( ) represents the result of the operation (e.g., 1, 0, or -1); | | represents the LLR value after combining the k-th information bits, 1≤k≤K, where K represents the total number of information bits.

[0042] This embodiment also includes a hierarchical prior strategy, which can determine the prior strength factor based on the level of the computation result, so as to make full use of different levels of sign consistency information: Level I: When the signs of the LLR values ​​of all M diversity replicas are exactly the same, the level of the operation result is determined to be Level I, and the highest prior is assigned: L_prior(k) = α_max · sign( ) · | | Where α_max represents the highest prior strength factor, with a value of 0.4-0.6.

[0043] Level II: When the number of results of any operation exceeds (greater than) half of the total number (e.g., The result of the operation is assigned a level two priority, and a moderate prior is assigned. L_prior(k) = α_midx · sign( ) · | | Where α_mid represents the moderate prior strength factor, with a value of 0.15-0.35.

[0044] Level III (Severe Divergence): When the number of results of any operation is no greater than (less than or equal to) half of the total number (i.e. and and The result of the operation is set to level three, the prior is kept to zero, no prior guidance is provided, and erroneous prior bias is avoided.

[0045] This invention extends binary classification to a multi-level classification system (complete agreement / majority agreement / serious disagreement) through the aforementioned multi-level prior strategy. It utilizes symbolic agreement information with finer granularity, assigning different strengths of priors to different levels of agreement. In particular, the moderate prior assignment to "majority agreement" bits compensates for the information loss in binary classification schemes on such bits.

[0046] Furthermore, the selection criteria for the prior strength factor α are as follows: if α is too large, it may "suppress" the replica information when the conditions are not fully met (assuming that each replica is independent and identically distributed, but the probability of consistency is less than 1); if α is too small, the prior effect is not significant. Therefore, α is preferably 0.3-0.5.

[0047] In this embodiment, the prior strength factor α can be dynamically adjusted through the following adaptive mechanism to ensure the robustness of the scheme under different diversity configurations and channel conditions: A (Adaptive based on the number of diversity replicas): α = α_base · (1 - 1 / M), where α_base represents the preset basic prior strength factor; M represents the total number of diversity replicas.

[0048] When the number of diversity replicas is large (e.g., M=6), the consistency of all diversity replica symbols is a strong reliability signal, and a larger α can be used; when the number of replicas is small (e.g., M=2), the consistency of two diversity replica symbols may just be a coincidence, and a smaller α should be used to avoid overconfidence.

[0049] B (Iterative Adjustment Based on CRC Feedback): Maintain a sliding window CRC (Cyclic Redundancy Check) statistician. If multiple consecutive frames of CRC are successful and the average number of iterations is high, it indicates that α is too small (insufficient prior effect), and α is appropriately increased (e.g., by 0.1 each time). If consecutive CRC failures are accompanied by a small number of iterations, it indicates that α is too large (the prior may have introduced an error bias), and α is appropriately decreased (e.g., by 0.1 each time).

[0050] C (Long-Term Learning Based on Channel Statistics): The actual decoding accuracy of symbol-consistent bits over a long period of operation is statistically analyzed (obtained by comparing the bit values ​​after successful decoding with the original LLR symbols), and this is used as a reference value for α. For example, if the statistics show that the accuracy of all symbol-consistent bits is 95%, then α can be set to 0.95 × α_base.

[0051] In this embodiment, when α is a reasonable value (e.g., α≤0.5), even if a few consistent bits are actually erroneous (i.e., all replicas make the same mistake), the non-zero prior will not "lock up" the decoder because the prior weight is always less than the system bit weight, and the system bits still play a dominant role. In the worst case (α→0), this scheme automatically degenerates into the existing scheme A without any performance loss and without causing a performance degradation safety boundary.

[0052] S2-3: Keep the prior information bits that do not satisfy symbol consistency (symbol detection result flag_k is 0 or -1) at zero, i.e., L_prior(k)=0.

[0053] In this embodiment, in addition to symbol consistency detection, prior assignment based on LLR magnitude consistency is also included. Not only are the symbols compared, but also the magnitudes of the LLRs of each replica are compared. When all replicas are symbolically consistent and their magnitudes all exceed a certain threshold, a higher prior weight is assigned. This scheme is more accurate than pure symbol consistency, but requires an additional magnitude comparator.

[0054] This embodiment also includes prior estimation based on inter-replica mutual information (LLR). The mutual information between each replica's LLR is calculated as a continuous measure of consistency, rather than a binary judgment. Higher mutual information results in greater prior weights. This scheme can provide non-zero prior information even for partially consistent bits, but the computational complexity of mutual information is high.

[0055] This embodiment also includes a consistency weight based on time decay. Combined with a time-aware diversity replica weighted merging method, the temporal weight of each replica is considered when determining symbol consistency: earlier replicas have higher decision weights, while later replicas have lower weights. For example, when all three early replicas are consistent but one later replica is inconsistent, it can be considered "substantially consistent" and assigned a higher prior value. This scheme represents the optimal combination of this invention and diversity replica weighted merging technology.

[0056] S3: Calculate the difference between the combined LLR value of the information bits and the prior assignment, and use it as the second input information for the information bit.

[0057] In this embodiment, the prior assignment and the merged LLR value repeatedly represent the determinism of the same bit. To avoid duplicate counting and ensure that there is no information overlap between the system bits and prior bits input to the Turbo decoder, thus preventing the degradation of decoding performance caused by the repeated counting of the determinism of the same bit, this step requires removing the prior part from the merged LLR value to obtain the second input information while keeping the symbol unchanged. L_sys'(k) = | | - |L_prior(k)| Where L_sys'(k) represents the second input information of the k-th information bit; | | represents the combined LLR value corresponding to the k-th information bit; |L_prior(k)| represents the prior assignment of the k-th information bit.

[0058] Furthermore, if the prior strength factor α is small (e.g., α≤0.3), this step can be omitted to simplify the hardware design, at the cost of a small amount of information overlap.

[0059] S4: Construct the total input information from the first input information and the second input information, and then send the total input information to the decoder to complete the decoding.

[0060] In this embodiment, the input to the turbo decoder is divided into two parts: system bit input and a priori input. These two parts do not simply add, subtract, or cancel each other out; they play different roles in the turbo decoder. After the total input information is sent to the decoder, it will enter different channels for subsequent processing.

[0061] S3 subtracts the consistency prior from the system bits to ensure that the system bit port does not contain prior information, thus avoiding the duplicate inclusion of consistency information in the branch metric, which would cause the effective LLR to expand to a factor of (1+α). S4 sends the subtracted system bits (second input information) L_sys'(k) into the system bit port and the consistency prior (first input information) L_prior(k) into the prior port, and the two enter different processing channels of the decoder. The total amount of information carried by the input information remains unchanged, but the consistency prior information is correctly routed to the prior port, allowing it to participate in the decision in the first iteration, rather than being buried in the system bits and waiting to be gradually released in multiple iterations. This is the core mechanism of this scheme to accelerate convergence.

[0062] Since the information bits that satisfy symbol consistency have already obtained non-zero priors, these information bits can converge quickly in the first few iterations. Through the inherent constraints of Turbo coding, the determinism is propagated to the neighboring symbol-consistent bits that do not satisfy symbol consistency, thereby accelerating the convergence of the entire code block and increasing the decoding rate.

[0063] In this embodiment, the present invention utilizes the symbol consistency of the diversity replicas' LLR to provide non-zero prior information initialization for the Turbo decoder. This transforms the "consistency between replicas," information completely ignored in existing schemes, into usable soft prior information, thereby accelerating Turbo decoding convergence. This is a novel information utilization method, unlike any existing prior strategy based on signal-to-noise ratio or iterative feedback. The principle behind this effect is that with zero prior, Turbo decoding requires multiple iterations to determine the reliability of each bit, while this scheme informs the decoder in advance of the information for "determining" the bits, preventing it from wasting iterations on these bits. In the typical PLC operating range with a diversity replica count N_copy ≥ 4 and a signal-to-noise ratio between -5dB and +5dB, it is expected to reduce the average number of iterations from 6-8 to 4-5, i.e., reducing decoding power consumption by 25%-40%.

[0064] Meanwhile, the four-step process of this invention—"retaining a separate LLR for diversity replicas → symbol consistency detection → prior calculation → overlap removal"—ensures the correct transmission of information: no intermediate data is lost, no information is double-counted, and no additional bias is introduced. This is the key guarantee that this solution can achieve power optimization without reducing performance.

[0065] The core operations of the entire process are only sign bit XOR and multiplication, and the incremental hardware cost is far lower than the decoding power saving. This gives this solution a solid engineering foundation for implementation on resource-constrained smart meter chips.

[0066] In this embodiment, instead of allocating prior information all at once before decoding, the prior information value can be dynamically adjusted after each Turbo iteration based on the update status of each replica's LLR. This approach can utilize consistency information more accurately, but it increases the complexity within the decoder.

[0067] In this embodiment, instead of modifying the prior values, the iteration order can be adjusted within the Turbo decoder: prioritize the exchange of high-consistency (satisfying symbol consistency) bits, allowing these bits to converge first; then process the exchange of low-consistency (not satisfying symbol consistency) bits. This approach does not change the input format, but requires modification to the interleaver sorting logic within the decoder.

[0068] like Figure 2 As shown, based on the above-described prior method for decoder input information, the present invention also provides a prior system for decoder input information, including a data acquisition module, a storage module, a symbol consistency detection module, a prior allocation module, a differentiation construction module, and an output module.

[0069] In this embodiment, the input end of the data acquisition module is connected to the server, the output end of the data acquisition module is connected to the input end of the storage module, the output end of the storage module is connected to the input end of the symbol consistency detection module, the output end of the symbol consistency detection module is connected to the input end of the prior allocation module, the output end of the prior allocation module is connected to the input end of the differentiation construction module, the output end of the differentiation construction module is connected to the input end of the output module, and the output end of the output module is connected to the input end of the decoder.

[0070] The data acquisition module is used to acquire the LLR values ​​of M diversity replicas in real time during the transmission of any information bit. The storage module is used to store the LLR values ​​and prior assignments of M diversity replicas of any information bit; The symbol consistency detection module is used to detect the symbol of the LLR value of each diversity replica using a symbol function (such as the sgn function or the sign function) to determine whether the symbol consistency is satisfied. The prior allocation module is used to perform prior allocation on information bits that satisfy symbol consistency, and obtain the corresponding prior assignment as the first input information. The differential construction module is used to calculate the difference between the LLR value after the information bits are combined and the prior assignment, which serves as the second input information for the information bit. The output module is used to construct the total input information from the first input information and the second input information, and then send the total input information to the decoder.

[0071] In this embodiment, the symbol consistency detection module is also equipped with a bit calculator, which is used to count the number of LLR value symbol operation results that are the same in the same information bit, and to determine the level of the operation result.

[0072] In this embodiment, the symbol consistency detection module is further provided with a prior adjustment unit, which is used to dynamically adjust the prior strength factor calculation prior assignment according to the level of the calculation result, so as to make full use of symbol consistency information of different degrees.

[0073] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention. In practical applications of persistent media (such as server disks, NAS, and object storage), various changes in form and detail can be made without departing from the spirit and scope of the present invention.

Claims

1. A priori method for decoder input information, characterized in that, Specifically, the following steps are included: S1: Real-time acquisition of the LLR values ​​of the M diversity replicas in the k-th information bit; S2: Perform a sign consistency check on the LLR values ​​of the M diversity replicas in the k-th information bit, and perform prior allocation on the information bit according to the check result to obtain the corresponding prior assignment as the first input information; S3: Calculate the difference between the combined LLR value of the kth information bit and the prior value, and use it as the second input information; S4: Construct the first input information and the second input information into the total input information, and then send the total input information into the decoder.

2. The priori method for decoder input information as described in claim 1, characterized in that, In step S1, the LLR values ​​of the M diversity replicas are sent to the storage module for storage.

3. A priori method for decoder input information as described in claim 1 or 2, characterized in that, S2 includes: S2-1: Perform a symbol consistency check on the LLR value of each diversity replica in the information bits to determine whether symbol consistency is satisfied; S2-2: Priorally allocate the information bits that satisfy symbol consistency to obtain prior assignments; S2-3: Keep the prior information bits that do not satisfy symbol consistency at zero.

4. The priori method for decoder input information as described in claim 3, characterized in that, In S2-1, the method for determining symbol consistency is as follows: The most significant bit of the LLR value of each diversity replica is operated on using a sign function; if the operation results are the same, the symbol consistency is satisfied; if the operation results are different, the symbol consistency is not satisfied.

5. The priori method for decoder input information as described in claim 3, characterized in that, In S2-2, the calculation method for the prior assignment is as follows: L_prior(k) = α · sign( ) · | | Where L_prior(k) represents the prior assignment of the k-th information bit; α∈(0,1) is the prior strength factor; sign( ) represents the result of the operation; | | represents the LLR value after merging the k-th information proportion, 1≤k≤K, where K represents the total number of information proportions.

6. The priori method for decoder input information as described in claim 5, characterized in that, It also includes hierarchical prior strategies: If all the calculation results are the same, the grade of the calculation result is determined to be level one: L_prior(k) = α_max · sign( ) · | | Where α_max represents the highest prior strength factor; When the number of any one type of operation result exceeds half of the total number, the operation result is classified as level two. L_prior(k) = α_midx · sign( ) · | | Where α_mid represents the moderate prior strength factor; When the number of any operation result is no more than half of the total number, the level of the operation result is determined to be level three, and the prior is kept to zero.

7. A priori method for decoder input information as described in claim 1 or 2, characterized in that, In step S3, the method for obtaining the second input information is as follows: L_sys'(k) = | | - |L_prior(k)| Where L_sys'(k) represents the second input information of the k-th information bit; | | represents the combined LLR value corresponding to the k-th information bit; |L_prior(k)| represents the prior assignment of the k-th information bit.

8. A priori system for decoder input information based on the priori method according to any one of claims 1-7, characterized in that, include: The data acquisition module is used to acquire the LLR values ​​of M diversity replicas in real time during the information bit transmission process; The storage module is used to store the LLR values ​​and prior assignments of M diversity replicas; The symbol consistency detection module is used to detect the symbol of the LLR value of each diversity replica and determine whether it meets the symbol consistency requirement. The prior allocation module is used to perform prior allocation on information bits that satisfy symbol consistency, and obtain prior assignments as the first input information. The differential construction module is used to calculate the difference between the LLR value after combining information bits and the prior assignment, which serves as the second input information; The output module is used to construct the total input information from the first input information and the second input information, and then send the total input information to the decoder.

9. A priori system for decoder input information as described in claim 8, characterized in that, The symbol consistency detection module also includes a bit calculator; the bit calculator is used to count the number of LLR value symbol operations with the same result in the same information bit, and to determine the level of the operation result.

10. A priori system for decoder input information as described in claim 8 or 9, characterized in that, The symbol consistency detection module also includes a priori adjustment unit; the priori adjustment unit is used to dynamically adjust the priori strength factor and calculate the priori assignment based on the level of the calculation result.

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