A kind of support optical fiber, coaxial and bluetooth multi-source input and with built-in lithium one-to-multiple wireless audio transmitter and its receiving system

Abstract

The present application relates to wireless audio transmission device technical field, specifically to a kind of support optical fiber, coaxial and Bluetooth multi-source input and with built-in lithium battery one-to-many wireless audio transmitter and its receiving system, comprising: multi-source input arbitration module and time mark broadcast transmitting module, clock phase-locked receiving module, electrical isolation power supply module.The present application is through the hardware linkage of multi-source input arbitration architecture and asynchronous sampling rate conversion unit, realizes the intelligent gating of multi-source different native sampling rate audio signals and high-resolution unified resampling, effectively avoids the channel conflict and clock alignment disorder when multiple signals are concurrent;At the same time, using the closed-loop phase-locked loop system formed by time stamp synchronization beacon and local numerical control oscillator, with the low-delay hardware-level interrupt trigger signal of synchronous trigger controller, the analog audio synchronization output delay difference between multiple receiving slaves is constrained within 10 milliseconds, improves the time-domain phase consistency under radio frequency broadcast mode.

Description

Technical Field

[0001] This invention relates to the field of wireless audio transmission equipment technology, specifically to a wireless audio transmitter and receiver system that supports multiple input sources including fiber optic, coaxial and Bluetooth and has a built-in lithium battery. Background Technology

[0002] Wireless audio transmission technology is widely used in audio-visual entertainment, multimedia conferencing, and outdoor broadcasting. Existing wireless audio transceivers suffer from the following significant underlying technical shortcomings when dealing with scenarios involving concurrent access from multiple audio sources, simultaneous output from multiple receivers to multiple devices, and simultaneous charging and use:

[0003] First, in a wireless broadcast-style "one transmit, multiple receive" unidirectional transmission architecture, to avoid network channel congestion and storms caused by multiple receivers simultaneously replying with acknowledgment packets, the transmitter typically uses an unacknowledged mechanism for unidirectional radio frequency broadcasting. Due to multipath effects and spatial fading in wireless channels, each receiver experiences uncontrollable network jitter when receiving data. Furthermore, there is an inherent frequency difference between the local active crystal oscillator of each receiver and the transmitter's reference clock. Without a high-precision clock synchronization compensation closed loop, this frequency difference accumulates over time, forming clock drift. This causes multiple receivers to fail to trigger at the same absolute time point when performing digital-to-analog conversion on the audio stream, resulting in significant time delays and phase misalignments between the multiple outputs. In the macroscopic sound field, this manifests as noticeable acoustic phase shift or acoustic attenuation, failing to meet the stringent requirement of lossless multi-speaker simultaneous sound transmission.

[0004] Secondly, the existing power supply architecture cannot simultaneously guarantee long battery life and pure sound quality. When the wireless receiver is charging while operating, the power frequency interference current and high-frequency switching ripple introduced by the external AC charger or power bank are directly introduced into the device through the physical charging cable. In traditional non-isolated circuit designs, the external charging input ground wire and the internal audio reference ground wire are directly electrically connected, forming a closed-loop common ground circuit. These externally input high-frequency switching noises and power frequency currents generate transient potential differences in the common ground circuit, directly modulating the internal analog audio reference ground level, creating continuous and severe current background noise at the audio output. This leads to a sharp deterioration in the signal-to-noise ratio of the audio signal, severely affecting the listening experience of the audio decoding output and the steady-state operation of the system. Summary of the Invention

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] This invention provides a multi-source wireless audio receiving system supporting fiber optic, coaxial, and Bluetooth inputs and featuring a built-in lithium battery. The system includes a wireless transmitter and at least one wireless receiver.

[0007] A multi-source input arbitration module is configured in the wireless transmitter host and integrates a digital audio input interface, an analog audio input interface, a Bluetooth input module, and an OTG input module. It is used to access multiple audio signals and automatically select the target input channel according to a preset priority through an internal audio channel arbitrator.

[0008] The time-stamped broadcast transmission module, configured in the wireless transmitter host, is used to encode and package the selected audio signals, and periodically insert timestamp synchronization beacons into the audio data frames for wireless broadcasting.

[0009] A clock phase-locked receiver module, configured in the wireless receiver slave, is used to receive the audio data frame and perform clock synchronization compensation through a local phase-locked loop based on the timestamp synchronization beacon, triggering audio output at a specified absolute timestamp;

[0010] An electrically isolated power supply module is configured on the wireless receiver slave unit, including an external power supply interface and an isolation power supply circuit. The isolation power supply circuit physically and electrically isolates the charging ground wire of the external power supply interface from the audio reference ground wire inside the system, so as to support the wireless receiver slave unit to output audio without current noise when charging.

[0011] Furthermore, the analog audio input interface includes at least two 3.5mm audio input terminals, wherein at least one of the 3.5mm audio input terminals is connected in series with a hardware variable resistor type volume adjustment circuit and an analog audio operational amplifier in the physical circuit, for hardware-level lossless volume gain or attenuation adjustment of the input analog audio signal before the audio channel arbitrator selects the channel;

[0012] The digital audio input interface consists of an optical fiber input interface and a coaxial input interface;

[0013] The OTG input module is configured as a digital audio decoding interface based on the USBAudioClass protocol, which is used to directly read the underlying digital audio bitstream from an external smart terminal or storage device without the need for additional drivers.

[0014] Furthermore, the internal audio channel arbiter includes an interface detection unit, a priority register, and a multiplexing switch;

[0015] The interface detection unit is used to monitor the level transition status of each input interface or the handshake signal of the peripheral device in real time.

[0016] The preset priority order fixed in the priority register is as follows: the OTG input module, the Bluetooth input module, the digital audio input interface, and the analog audio input interface;

[0017] When the interface detection unit determines that multiple interfaces have valid audio signals at the same time, the multiplexing switch is configured to: cut off the signal data link of the low priority channel according to the highest priority instruction output by the priority register, and only keep the target input channel corresponding to the highest priority connected to the subsequent transmission module.

[0018] Furthermore, the time stamp broadcasting module includes an audio hardware encoder and a timestamp injection unit;

[0019] The audio hardware encoder is used to convert the selected audio signal into a pulse code modulation (PCM) data stream and divide and pack it into fixed-length audio payload blocks.

[0020] The timestamp injection unit includes a high-precision local reference clock, which is used to attach an absolute timestamp generated based on the local reference clock to each audio payload block, and encapsulate the absolute timestamp in the frame header of the audio data frame to form the timestamp synchronization beacon;

[0021] When the time-stamp broadcasting module transmits the audio data frame, it adopts a one-way radio frequency broadcast mode based on a non-acknowledgment mechanism to drive at least two wireless receiver slaves simultaneously.

[0022] The time-stamped broadcast transmission module integrates a forward error correction coding matrix. The forward error correction coding matrix performs matrix redundancy operation on the audio data frame encapsulated with the timestamped synchronization beacon, generates a forward error correction check block, and appends it to the end of the audio data frame so that the wireless receiving slave can perform autonomous error correction and restoration in the state of no retransmission interaction.

[0023] The time-marked broadcast transmission module and the multi-source input arbitration module are connected by a digital signal processing core.

[0024] The DSP core includes an asynchronous sampling rate conversion unit and a digital noise reduction algorithm module;

[0025] The ASRC unit is used to uniformly resample audio signals with different native sampling rates output by the multi-source input arbitration module into a fixed high-resolution target sampling rate audio data stream.

[0026] The digital noise reduction algorithm module is used to perform full-band dynamic range stabilization and background noise suppression processing on the resampled audio data stream, and then output the processed clean audio signal to the time-stamped broadcast transmission module for encoding and packaging.

[0027] Furthermore, the clock phase-locked receiver module includes an RF receiving antenna, an error correction decoder, and a flexible jitter buffer;

[0028] The radio frequency receiving antenna is used to capture the audio data frames transmitted based on the unidirectional radio frequency broadcast mode;

[0029] The error correction decoder uses the forward error correction check block to perform local autonomous error correction on the damaged data frame and stores the restored audio payload block in the elastic jitter buffer to absorb network jitter delay during wireless channel transmission.

[0030] The internal clock compensation circuit of the clock phase-locked receiver module includes a timestamp extraction unit, a phase error comparator, and a local numerically controlled oscillator.

[0031] The timestamp extraction unit is used to extract the absolute timestamp of the transmitting end from the received audio data frame;

[0032] The phase error comparator is used to calculate the clock drift error between the absolute timestamp and the local count value currently generated by the local numerically controlled oscillator, and outputs a frequency fine-tuning control word to the local numerically controlled oscillator based on the clock drift error, forcing the oscillation frequency of the local numerically controlled oscillator to maintain phase lock with the reference clock of the transmitting host.

[0033] Furthermore, the clock phase-locked receiver module also includes a synchronous trigger controller and a digital-to-analog converter;

[0034] The synchronous trigger controller continuously monitors the time count value of the local numerically controlled oscillator in phase-locked state. When the time count value reaches the preset playback timestamp associated with the audio payload block, the synchronous trigger controller outputs a hardware-level interrupt trigger signal to the digital-to-analog converter.

[0035] In response to the hardware-level interrupt trigger signal, the digital-to-analog converter instantly converts the audio payload block in the elastic jitter buffer into an analog audio signal for output, thereby constraining the audio synchronization output delay difference of multiple wireless receiver slaves to be less than 10 milliseconds.

[0036] Furthermore, the isolated power supply circuit includes an isolated DC-DC converter chip and a high-frequency miniature transformer;

[0037] The power input terminal and charging ground wire of the external power supply interface are connected to the primary side of the high-frequency micro transformer, and the secondary output terminal of the high-frequency micro transformer is connected to the audio reference ground wire and the load power supply terminal inside the system.

[0038] There is no direct DC electrical connection between the primary side and the secondary side. The power supply is configured to cross from the primary side to the secondary side through the magnetic coupling of the high-frequency micro transformer, thereby physically cutting off the power frequency interference and high-frequency noise introduced by the external power supply equipment through the common ground loop.

[0039] Furthermore, the electrically isolated power supply module also includes a power management unit (PMU) and an energy storage battery integrated on the secondary side;

[0040] The power management unit includes a power path arbitration switch configured to perform seamless power switching: when the external power supply interface detects the access of an external power source, the power path arbitration switch is activated, preferentially extracting the pure electrical energy converted by magnetic coupling from the secondary side output terminal to power the system, and bypassing to charge the energy storage battery, so as to maintain the uninterrupted operation and transmission interruption of the wireless receiver slave in the charging and use mode.

[0041] Furthermore, the electrically isolated power supply module is also coupled with a power visualization monitoring circuit;

[0042] The power visualization monitoring circuit includes a voltage detection pin and a multi-level LED indicator structure;

[0043] The voltage detection pin is connected to the output terminal of the energy storage battery to collect the battery terminal voltage change characteristics in real time. The internal master controller of the wireless receiver slave device drives the multi-level LED indicator to switch between the light colors or flashing logic corresponding to the four preset states of full charge, medium charge, low charge or charging, based on the terminal voltage change characteristics.

[0044] On the other hand, a multi-source wireless audio transmitter supporting optical fiber, coaxial cable, and Bluetooth inputs and featuring a built-in lithium battery includes:

[0045] An audio input interface array, comprising a fixed optical input interface, a coaxial input interface, at least two 3.5mm analog audio input interfaces, and a USB OTG input interface;

[0046] Bluetooth receiver chip, used to receive wireless Bluetooth audio signals from external space;

[0047] The main control chip has multiple physical input pins that are electrically connected to each interface in the audio input interface array and the signal output pin of the Bluetooth receiver chip, respectively. The main control chip integrates a digital audio multiplexer and a digital signal processor, and a high-precision crystal oscillator is electrically connected to the peripheral circuit of the main control chip.

[0048] The wireless radio frequency transmitter chip has its baseband signal input pin electrically connected to the signal output pin of the main control chip, and its radio frequency output pin electrically connected to a radio frequency transmitting antenna;

[0049] The built-in power supply circuit includes a lithium battery and a power management chip electrically connected to the output terminal of the lithium battery. Multiple power output pins of the power management chip are physically and electrically connected to the power pins of the audio input interface array, the Bluetooth receiver chip, the main control chip, and the wireless radio frequency transmitter chip, respectively.

[0050] Beneficial effects

[0051] This invention achieves intelligent gating and high-resolution unified resampling of multiple audio signals with different native sampling rates through hardware linkage of a multi-source input arbitration architecture and an asynchronous sampling rate conversion unit, effectively avoiding channel conflicts and clock alignment disorder when multiple signals are concurrent. Simultaneously, a closed-loop phase-locked loop system composed of a timestamp synchronization beacon and a local numerically controlled oscillator, combined with a low-latency hardware-level interrupt trigger signal from a synchronization trigger controller, constrains the difference in analog audio synchronization output delay between multiple receiver slaves to within 10 milliseconds, improving time-domain phase consistency in RF broadcast mode. The receiver slaves employ a physical electrical isolation power supply design based on high-frequency micro-transformer magnetic coupling, physically cutting off the common ground loop path between the external charging ground wire and the internal audio reference ground wire. This allows the system to effectively block the transmission of external power frequency and high-frequency switching ripple to the audio side in charging-while-using mode, significantly reducing system noise floor and improving the signal-to-noise ratio of analog audio output while ensuring uninterrupted steady-state audio transmission from the wireless receiver slaves. Attached Figure Description

[0052] Figure 1 This is a flowchart of the multi-source input intelligent arbitration and seamless switching control of the present invention;

[0053] Figure 2 This is a block diagram of the overall system architecture of the present invention. Detailed Implementation

[0054] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but includes other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0056] The present invention will now be described in further detail with reference to the accompanying drawings:

[0057] Example:

[0058] like Figures 1-2 As shown, a multi-source wireless audio receiving system supporting fiber optic, coaxial, and Bluetooth inputs and equipped with a built-in lithium battery includes a wireless transmitter and at least one wireless receiver slave. The system comprises:

[0059] The multi-source input arbitration module, configured in the wireless transmitter host, integrates a digital audio input interface, an analog audio input interface, a Bluetooth input module, and an OTG input module. It is used to access multiple audio signals and automatically select the target input channel according to the preset priority through the internal audio channel arbitrator.

[0060] The time-stamped broadcast transmission module, configured in the wireless transmitter host, is used to encode and package the selected audio signals and periodically insert timestamp synchronization beacons into the audio data frames for wireless broadcasting.

[0061] The clock phase-locked receiver module, configured in the wireless receiver slave, is used to receive audio data frames and perform clock synchronization compensation through the local phase-locked loop based on the timestamp synchronization beacon, triggering audio output at the specified absolute timestamp;

[0062] An electrically isolated power supply module, configured on the wireless receiver slave, includes an external power supply interface and an isolation power supply circuit. The isolation power supply circuit physically and electrically isolates the charging ground wire of the external power supply interface from the audio reference ground wire inside the system, so as to support the wireless receiver slave to output audio without current noise when charging.

[0063] Furthermore, the specific operation procedure of the multi-source input arbitration module is as follows:

[0064] The multi-source input arbitration module is entirely deployed on the front-end input side of the wireless transmitting host, and is responsible for receiving and processing multiple audio signals from different physical media and protocol layers. In terms of hardware, this module is mainly composed of a multi-source audio input array, an interface detection unit, a priority register, a multiplexing switch, and an audio channel arbiter inside the main control chip. All components are interconnected through physical wires, digital buses and control lines, forming a signal processing network with hardware-level coordinated response.

[0065] In the multi-source audio input array, the analog audio input interface is configured with two independent 3.5mm analog audio input terminals. To realize high-quality and lossless analog signal preprocessing, a hardware variable-resistor type volume adjustment circuit and an analog audio operational amplifier are connected in series on the subsequent physical circuit of at least one 3.5mm analog audio input terminal. The hardware variable-resistor type volume adjustment circuit adopts a dual-unit low-noise potentiometer, which changes the resistance value connected to the circuit through the rotation of a mechanical shaft, so as to perform stepless attenuation on the input original analog audio signal. The attenuated or non-attenuated analog signal is then directly input to the non-inverting input terminal of the analog audio operational amplifier. This operational amplifier adopts a low-noise, high-impedance peripheral feedback circuit architecture, which is mainly used to complete impedance matching and perform linear voltage gain amplification on the analog audio signal, so as to improve the signal-to-noise ratio of the signal. The amplified analog audio signal is output to the high-precision analog-to-digital conversion chip (ADC) on the board of the transmitting host, which converts it into the first digital audio pulse code modulation (PCM) bitstream conforming to the Inter-IC Sound (I2S) standard. This bitstream includes a serial data line (SDATA), a bit clock line (BCLK) and a left / right channel selection line.

[0066] The digital audio input interfaces include an optical fiber input interface and a coaxial input interface. The optical fiber input interface adopts an integrated photoelectric conversion receiving head, which is used to capture the externally introduced optical pulse signal, and uses its internal photodiode to restore the optical signal to the digital audio transmission format (SPDIF) electrical signal conforming to the TTL / CMOS level standard. The coaxial input interface is connected to the external coaxial cable through a 75-ohm characteristic impedance matching resistor network, so as to suppress the reflected superposed wave generated by the high-frequency digital signal at the end of the transmission cable. The impedance-matched SPDIF electrical signal is waveform-shaped by a high-speed differential comparator to restore the steep edge of the digital signal. These two SPDIF signals are respectively input to the digital audio receiver (DIR) inside the transmitting host, and after demodulation and phase locking, they are respectively converted into the second and third independent I2S format digital audio bitstreams.

[0067] The OTG input module is based on the USB Universal Serial Bus architecture, with its hardware core being a dedicated high-speed USB-to-I2S bridge chip supporting the USB Audio Class 2.0 (UAC2.0) protocol. When an external smart terminal or storage device is connected to the module via a Type-C interface, the bridge chip establishes an isochronous transmission endpoint directly with the external host without requiring additional driver loading. The bridge chip directly extracts the underlying digital audio raw data packets sent by the external device through the physical layer differential signal lines (D+, D-). After unpacking and removing USB frame headers and checksum redundancy within the chip, it directly converts the data into a fourth channel of clean, lossless I2S format digital audio stream. The Bluetooth input module uses an independent RF system-on-a-chip (SoC), which integrates a 2.4GHz omnidirectional antenna, a low-noise amplifier, and a hardware audio decoding core. This Bluetooth SoC receives the Advanced Audio Distribution Profile (A2DP) stream sent by an external Bluetooth transmitter via a wireless link and directly decodes it into a fifth channel of I2S format digital audio stream at the hardware level.

[0068] The physical buses of the aforementioned five I2S format digital audio streams (corresponding to the streams converted from two analog inputs, the optical fiber demodulated stream, the coaxial demodulated stream, the OTG bridged stream, and the Bluetooth decoded stream, respectively) are simultaneously connected to the various input terminals of the multiplexer. The multiplexer employs a high-bandwidth, low-on-resistance digital cross-matrix switch chip or directly utilizes the digital audio bus multiplexer selector within the DSP / MCU chip. The selection state of the multiplexer is entirely controlled by the internal audio channel arbiter.

[0069] The internal audio channel arbiter is implemented by an interface detection unit, a priority register, and a controller. The interface detection unit includes multiple parallel hardware monitoring circuits: for the 3.5mm analog interface, it uses the contact state of the mechanical spring inside the socket to generate a level transition signal sent to the GPIO pin when the external plug is inserted; for optical and coaxial interfaces, it continuously reads the phase-locked loop lock status register (LOCK bit) of the digital audio receiver (DIR), and sets the register once a valid digital carrier lock signal is detected; for the USBOTG module, it determines the connection by monitoring the rising edge of the VBUS power bus voltage and combining it with whether the USB configuration status register of the bridge chip has entered the configured state; for the Bluetooth module, it reads the level output of the Bluetooth SoC's connection status pin (CONN) or reads the status word of its internal link manager through the UART serial communication protocol.

[0070] The priority register is a set of binary codes stored in the non-volatile memory of the transmitter host or in the register file of the main control chip. The absolute priority order of each input source is predefined and fixed in this register, and is limited to the following from high to low: OTG input module (binary code 11), Bluetooth input module (binary code 10), digital audio input interface (binary code 01), and analog audio input interface (binary code 00).

[0071] When the wireless transmitter is operational, the control core of the internal audio channel arbiter continuously reads the output status of the interface detection unit via interrupt triggering or high-frequency polling. When the interface detection unit determines that only one interface has a valid signal input, the control core directly sends the selection command corresponding to that channel to the multiplexer. When the interface detection unit determines that multiple physical interfaces have valid audio signal input simultaneously, the control core immediately calls the value in the priority register for hardware-level comparison and arbitration. Based on the highest priority command output from the priority register, the control core writes the corresponding selection control word to the control pin of the multiplexer. At this time, the multiplexer immediately disconnects the I2S clock and data lines of all low-priority channels (switching them to a high-impedance state or directly grounding them), keeping only the bus connected to the target input channel corresponding to the current highest priority (e.g., the OTG input module), thereby transmitting the clean I2S digital audio stream conflict-free to the subsequent time-stamped broadcast transmission module.

[0072] Experimental scenario verification:

[0073] On the experimental test platform, a Windows 11 PC was configured as an OTG input source, connected to the Type-COTG interface of the wireless transmitter. A smartphone was configured to connect to the transmitter's Bluetooth SoC via Bluetooth and continuously play audio streams. A Blu-ray player was configured to connect to the coaxial input interface via a coaxial cable, outputting a fixed-frequency 48kHz SPDIF digital audio signal. An audio signal generator was configured to continuously inject a 1kHz, 1Vrms amplitude sine wave analog signal into the analog interface with hardware volume control via a 3.5mm audio cable. The transmitter's internal main control chip was connected to an external dual-channel digital oscilloscope and logic analyzer to monitor the gating control pin level of the multiplexer switch and the I2S bus signal ultimately output to the DSP core in real time.

[0074] In the initial state, the audio signal generator, Blu-ray player, and smartphone Bluetooth playback are turned on. At this time, the analog detection pin, coaxial phase-locked register, and Bluetooth connection pin in the interface detection unit are triggered simultaneously. The internal audio channel arbiter reads the priority register. Since the priority of Bluetooth (10) is higher than that of coaxial (01) and analog (00), the control core outputs a control word to the multiplexer. The logic analyzer observes that the selection channel of the multiplexer immediately switches to the Bluetooth I2S bus. At this time, the transmitting host correctly receives and broadcasts the Bluetooth audio signal.

[0075] During the operation of the above three signals maintaining concurrent input, the USB cable of the personal computer was manually inserted into the Type-COTG interface. The interface detection unit instantly captured the rising edge of the 5V voltage on the VBUS pin, and the configuration register of the bridge chip completed the UAC2.0 protocol handshake and set the bit within 45 milliseconds. The internal audio channel arbiter immediately triggered a high-priority hardware interrupt to read the latest concurrent status. Because the newly connected OTG input module has the highest priority (11), the control core wrote a new switching control word to the multiplexer switch within 2 milliseconds. It can be intuitively observed through a dual-channel oscilloscope that the I2S clock and data lines of the original Bluetooth channel were instantly pulled low and cut off, while the I2S data stream of the OTG channel was seamlessly connected to the main bus. There was no data pointer overshoot during the entire switching process, and no signal overlap or data collision occurred, proving the high-precision control and non-interference technical reliability of the hardware arbitration architecture in multi-source input scenarios.

[0076] Furthermore, the specific operation procedure for the time-stamped broadcast transmission module is as follows:

[0077] The I2S format digital audio stream output from the front-end multi-source input arbitration module first enters the digital signal processing (DSP) core via a high-speed digital bus. Due to significant differences in the native sampling rates of different input sources (such as 44.1kHz from Bluetooth, 48kHz from coaxial, and 96kHz from OTG), direct broadcast packaging would cause local clock alignment issues among multiple receiver slaves. Therefore, the DSP core incorporates a hardware-level asynchronous sampling rate conversion (ASRC) unit. The ASRC unit uses a polyphase fractional delay finite impulse response (FIR) filter network to calculate the precise phase difference between the input and output clocks, performing polynomial interpolation resampling on the input data. This seamlessly and forcibly converts the input data stream of any native sampling rate into a globally uniform high-resolution target sampling rate (e.g., 96kHz / 24bit) audio data stream. The data stream with the unified sampling rate then enters the DSP's internal digital noise reduction algorithm module. This module runs multi-band dynamic range compression (DRC) and spectral subtraction algorithms to perform full-band dynamic range stabilization and background noise suppression on the audio signal.

[0078] The time-domain smoothed digital audio signal, processed by the DSP core, is then imported into the audio hardware encoder. The audio hardware encoder performs frame-by-frame truncation on the continuous Pulse Code Modulation (PCM) data stream according to time windows, dividing and packaging it into audio payload blocks of fixed time length (e.g., carrying 2.5 milliseconds of audio data).

[0079] During the data frame assembly phase, the timestamp injection unit performs the crucial clock beacon synchronization operation. Internally, the timestamp injection unit is physically coupled with a temperature-compensated crystal oscillator (TCXO) with extremely low phase noise, serving as the local reference clock for the transmitting host. The timestamp injection unit also contains a 64-bit high-speed free-running hardware counter driven by this TCXO. The moment the audio hardware encoder completes packaging the current audio payload block, the hardware interrupt logic immediately latches the current absolute time count value of this 64-bit hardware counter, generating an absolute timestamp strictly bound to that specific audio payload block. Subsequently, the underlying network packet structure is directly modified to forcibly write this absolute timestamp into a custom reserved field in the audio data frame header, thus creating a "timestamp synchronization beacon" at the front end of each data frame for slave alignment.

[0080] The audio data frame, after its header encapsulation, then enters the RF baseband processing controller. To achieve true unidirectional "one transmit, multiple receive," the RF baseband processing controller's media access control layer is forcibly configured to a non-acknowledgment unidirectional RF broadcast mode. In this mode, the transmitting host neither listens for nor waits for any ACK acknowledgment packets from the receiving slaves after sending data, completely eliminating network storms and bandwidth congestion caused by multiple slaves responding simultaneously. However, the No-ACK mode is highly susceptible to packet loss due to spatial interference in the complex 2.4GHz / 5.8GHz ISM band. To address this, the RF baseband internally activates a hardware forward error correction (FEC) coding matrix. This matrix employs the Reed-Solomon block error correction algorithm to perform Galois domain matrix redundancy operations on the complete data frame, including the timestamp synchronization beacon and audio payload block, generating a corresponding redundancy check code. This redundancy check code is appended to the end of the audio data frame as a "forward error correction check block." Ultimately, the complete broadcast data frame is modulated and amplified by Gaussian Frequency Shift Keying (GFSK) by the RF front-end chip, and then transmitted to space via the transmitting antenna, supporting synchronous wireless transmission of multiple audio signals.

[0081] Experimental scenario verification:

[0082] In a microwave anechoic chamber measuring 15 meters in length and width, and in a typical office environment with multipath interference, a wireless transmitter and five wireless receivers were deployed. The transmitter's multi-source input arbitration module selected a 44.1 kHz Bluetooth input signal. A high-power Wi-Fi router operating at full capacity was artificially introduced into the space to create severe co-channel electromagnetic interference in the 2.4 GHz band. Test equipment included a high-precision logic analyzer connected to the transmitter (for capturing the transmitter's absolute timestamp) and a multi-channel audio synthesis tester (for measuring the analog audio waveforms output by multiple receivers).

[0083] After the system was powered on, the physical radio frequency frames transmitted from the baseband MAC layer were captured by a logic analyzer. It was found that the frame header of each data frame contained a 64-bit absolute timestamp beacon that increased at 2.5 millisecond intervals, and the frame tail always carried a calculated RSFEC check block. In an external environment with strong interference, the channel monitor showed that the air bit error rate (BER) once reached 5%. Because the system forcibly adopted the No-ACK broadcast mode, the transmitting host did not perform any data retransmissions, and the bandwidth utilization remained stable and linear. Simultaneously, thanks to the matrix redundancy of the frame tail forward error correction check block, all five receiving slaves achieved local autonomous error correction and restoration without triggering retransmission interactions.

[0084] By comparing the analog audio waveforms of the final output from the five slave receivers using a multi-channel audio comprehensive tester, the results show that all slave receivers can precisely trigger the DAC audio output at exactly the same absolute time point. The phase offset of the audio signal output waveforms from the five slave receivers is extremely small, and the time delay difference between any two slave receivers is strictly controlled between 2 and 4 milliseconds, far below the design redundancy target of less than 10 ms. This experiment fully demonstrates that the passive broadcast hardware architecture with timestamp injection and FEC verification in this embodiment not only solves the technical problem of achieving a time delay difference of less than 10 ms for synchronized output from multiple devices, but also fully possesses the practical value for steady-state transmission in complex scenarios such as no mains power and high-interference outdoor environments.

[0085] Furthermore, the specific operation procedure of the clock phase-locked receiver module is as follows:

[0086] The clock phase-locked receiver module is integrated within the wireless receiver slave unit, serving as the core control unit for audio signal reconstruction and multi-terminal output alignment. In terms of hardware architecture, this module comprises an RF receiving antenna, a physical layer demodulator, an error correction decoder, a flexible jitter buffer, a timestamp extraction unit, a phase error comparator, a local digitally controlled oscillator (DCO), a synchronization trigger controller, and a digital-to-analog converter (DAC). These hardware units are physically connected via onboard high-frequency signal lines, parallel / serial digital buses, and interrupt control lines, forming a closed-loop clock phase tracking and synchronous audio triggering system.

[0087] After the RF receiving antenna of the wireless receiver slave captures the GFSK modulated high-frequency signal of the space physical broadcast, it sends it to the physical layer demodulator. The demodulator strips the high-frequency carrier and restores it into a digital audio data frame containing a frame header and a frame trailer. Because the transmitter uses a one-way RF broadcast mode based on a non-acknowledgment (No-ACK) mechanism, the data frame may have bit errors during space transmission due to multipath effects or co-channel interference. The demodulated raw data frame then enters the error correction decoder. The error correction decoder extracts the forward error correction check block attached to the end of the audio data frame and calls the built-in Reed-Solomon (RS) block decoding matrix to perform algebraic geometric verification on the data frame. When a burst error is detected in the data frame, the error correction decoder, without any retransmission interaction with the transmitter host, uses the redundant computing power of the error correction matrix to autonomously calculate and correct the erroneous bits locally, recovering a clean digital audio bitstream.

[0088] The clean digital audio stream output by the error correction decoder is then split into two parallel processing paths: the first path is the audio data link, where the depacketized audio payload blocks are immediately written into the elastic jitter buffer. The elastic jitter buffer is based on a first-in-first-out (FIFO) circular queue architecture, which forms a physical buffer by dynamically adjusting the spacing between the read and write pointers to completely absorb and offset network jitter latency caused by multipath transmission and spatial fading in wireless channels.

[0089] The second path is the clock control link, where the frame header of the data frame is sent to the timestamp extraction unit. The timestamp extraction unit uses a hardware state machine to perform high-speed decoding of specific fields in the frame header, completely extracting the 64-bit absolute timestamp information injected by the transmitting host at the moment of packetization. This absolute timestamp directly reflects the absolute count value of the transmitting end's master clock at the time the corresponding audio block is generated. This value is then used as the target phase reference input to the first input of the phase error comparator.

[0090] The second input of the phase error comparator is connected to the internal free-running counter of the local numerically controlled oscillator (DCO). The DCO receives high-frequency reference pulses from a high-precision active crystal oscillator on the receiving slave's board and generates a local time count value by incrementing it via a digital accumulator. Upon a hardware interrupt triggering the extraction of the transmitter's absolute timestamp, the phase error comparator immediately latches the current count value of the local free-running counter. Subsequently, the comparator's internal subtractor calculates the algebraic difference between these two timestamps, which represents the clock drift error between the receiving slave's local clock and the transmitting master clock.

[0091] The phase error comparator inputs the clock drift error to the proportional-integral (PI) digital filter operation unit, calculates and generates a high-precision frequency fine-tuning control word, and writes this control word into the control register of the local numerically controlled oscillator (DCO). The DCO dynamically adjusts the step value of its digital accumulator or the capacitance of its external capacitor array based on the frequency fine-tuning control word, thereby fine-tuning its output oscillation frequency. This forces the increment rate of the local free-running counter to be completely locked to the clock phase of the transmitting host, forming a high-precision clock phase tracking closed loop.

[0092] During the audio trigger output phase, the synchronous trigger controller continuously reads the free-run counter value of the local numerically controlled oscillator (DCO) in phase-locked state and performs a full-bit comparison with the preset playback timestamp associated with the audio payload block currently at the head of the elastic jitter buffer queue. When the free-run counter value of the local numerically controlled oscillator increments to the clock edge that is exactly equal to the preset playback timestamp, the digital comparator inside the synchronous trigger controller immediately flips, sending a hardware-level interrupt trigger signal to the digital-to-analog converter (DAC) via a dedicated low-latency hard interrupt pin.

[0093] The hardware control core of the digital-to-analog converter (DAC) responds instantly to the hardware-level interrupt trigger signal, starting with a nanosecond-level response time. The DAC instantly retrieves the aligned audio payload block PCM data from the elastic jitter buffer via the I2S bus, feeding it into the internal current source array and multi-stage low-pass filter circuitry to complete high-fidelity digital-to-analog conversion, ultimately outputting a clean analog audio signal. Because all wireless receiver slaves in the system operate with the exact same phase-locked loop and hardware interrupt triggering logic, the time difference for synchronized analog audio output between multiple wireless receiver slaves is strictly constrained.

[0094] Experimental scenario verification:

[0095] The experimental platform consists of one wireless transmitter and three completely independent wireless receivers (labeled Slave A, Slave B, and Slave C, respectively). The transmitter receives a 48kHz sinusoidal audio signal via a coaxial interface and continuously transmits data frames encapsulated with 64-bit TCXO absolute timestamps into space in No-ACK broadcast mode. The three wireless receivers are placed at different locations 10 meters away from the transmitter.

[0096] The testing equipment included: a 4-channel, 2.5GHz bandwidth, 20GSa / s sampling rate digital storage oscilloscope (DSO); and a high-precision audio comprehensive analyzer.

[0097] During the test connection, the hardware-level interrupt trigger signal pins output by the internal synchronous trigger controllers of the three wireless receiver slaves were connected to channels 1, 2, and 3 of the digital storage oscilloscope through high-frequency coaxial probes of equal length, respectively; at the same time, the analog audio left channel signal finally output by the three wireless receiver slaves was connected to the multi-input terminal of the audio comprehensive analyzer.

[0098] After the system powers on and establishes a stable wireless link, the hardware interrupt pulse waveforms on channels 1, 2, and 3 are continuously monitored using a digital storage oscilloscope. Experimental results show that under the closed-loop control of the phase-locked loop, the timestamp extraction unit continuously extracts a 64-bit timestamp, the phase error comparator dynamically outputs a control word to fine-tune the DCO, and the clock drift of the locked local numerically controlled oscillator is minimal. It can be visually observed on the oscilloscope screen that when the audio payload reaches the playback time, the edges of the hardware-level interrupt trigger signal waveforms on the three channels almost completely overlap. By using the oscilloscope's cursor measurement tool to statistically analyze the rise time difference of the three pulses, the maximum jitter time difference between any two hardware interrupt signals is strictly locked within 4.2 microseconds (μs).

[0099] Simultaneously, the phase delay and time delay difference of the actual analog audio waveforms output by the three slave units were analyzed using an audio comprehensive analyzer (APx555). Test data showed that the three analog sine waves exhibited perfect phase consistency across the entire frequency band, with no phase shift or echo noise. Comprehensive calculations revealed that the maximum actual output time delay difference of the analog audio between slave units A, B, and C was only 3.1 milliseconds (ms), a value far below the patented technical specification of "less than 10 milliseconds."

[0100] Furthermore, the specific operating procedure for the electrical isolation power supply module is as follows:

[0101] The electrically isolated power supply module is configured on the power input and distribution side of the wireless receiver slave unit, serving as the core hardware unit for eliminating ground noise, achieving clean audio output, and ensuring stable operation while charging and using. The module's hardware architecture mainly consists of an external power supply interface (Type-C power supply interface), an isolated power supply circuit, a power management unit (PMU), an energy storage battery, and a power visualization monitoring circuit. These hardware units are physically interconnected through onboard high-conductivity copper foil traces, a power transmission path network, voltage sampling control lines, and status drive lines, constructing a power supply guarantee system within the wireless receiver slave unit that enables power transmission across obstacles, intelligent path arbitration, and physical electrical isolation of the ground wire.

[0102] In the physical implementation of electrical isolation, the core of the isolated power supply circuit consists of a high-frequency isolated DC-DC converter chip and an integrated high-frequency miniature transformer. The power input terminal (VBUS bus) of the external power supply interface and the external charging input ground (GND_IN) are directly connected to the primary side pin of the high-frequency miniature transformer and connected to the primary side power switch bridge inside the isolated DC-DC converter chip. The secondary side output pin of the high-frequency miniature transformer serves as the load power supply terminal (VCC_SYS) within the entire receiver slave system, and its secondary side ground pin serves as the independent audio reference ground (GND_AUDIO) within the system. There is no direct DC electrical connection between the physical conductors and ground plane on the primary side and the physical conductors and ground plane on the secondary side, and the physical distance between the two sides strictly meets the preset insulation withstand voltage creepage distance. When an external power source (such as an AC charger or power bank) is plugged into the external power supply interface, the isolated DC-DC converter chip on the primary side modulates the input DC power into high-frequency AC pulses of hundreds of kilohertz to several megahertz and drives the primary winding of the high-frequency miniature transformer. The electrical power is transmitted to the secondary winding entirely through magnetic coupling between the primary and secondary windings of the high-frequency miniature transformer, crossing the spatial insulation barrier. The high-frequency AC output from the secondary winding is then converted back into steady-state DC power by a high-speed synchronous rectifier and filter circuit. This architecture physically eliminates the common ground loop between the external power supply equipment and the internal audio circuitry, physically blocking the conduction path of power frequency interference current and high-frequency switching noise introduced by external power cables to the audio output side.

[0103] In power dispatch and path management, both the Power Management Unit (PMU) and the energy storage battery are deployed within the secondary-side isolation domain of a high-frequency micro-transformer. The PMU integrates a high-precision power path arbitration switch, a lithium battery charging control core, and multiple low-dropout linear regulators (LDOs). The power path arbitration switch consists of a low-on-resistance MOSFET interlocked logic array. When no external power supply is connected to the external power interface, the power path arbitration switch automatically selects the energy storage battery output link, supplying power from the energy storage battery to the slave master control module, wireless receiver module, and audio output module of the wireless receiver. When the external power interface detects external power connection and a steady-state voltage is established at the secondary-side output after magnetic coupling conversion by the high-frequency micro-transformer, the comparator inside the PMU is instantaneously triggered. The power supply path arbitration switch responds seamlessly to the trigger signal, prioritizing the supply of clean power from the secondary output to the system load (VCC_SYS) for direct system power. Simultaneously, it shuts down the power supply link to the energy storage battery and activates the built-in constant current-constant voltage (CC-CV) charging control core, diverting a portion of the remaining power from the secondary output to the energy storage battery for safe recharging. This hardware-level arbitration and seamless bypass switching of the power path ensures that the voltage drop across the system load is less than the hardware reset threshold when the wireless receiver switches from battery power to external charging power (or vice versa). This maintains uninterrupted audio decoding and steady-state output in the charging-while-using mode, achieving no audio transmission interruption or popping noises when plugging or unplugging the charging cable.

[0104] During status monitoring and feedback, the power visualization monitoring circuit is physically coupled to the output terminals of the energy storage battery and the status output pin of the power management unit (PMU). The power visualization monitoring circuit includes a high-impedance voltage detection pin, a multi-channel low-power voltage divider resistor network, and a multi-level LED indicator structure. The voltage detection pin is connected to the built-in analog-to-digital converter (ADC) input channel of the receiver slave's internal control module, continuously acquiring the real-time terminal voltage change characteristics of the energy storage battery during charging and discharging. The firmware of the wireless receiver slave's internal control module contains a battery power-voltage mapping curve library. The internal control module periodically reads the full-length digital value converted by the ADC, eliminates voltage glitches caused by transient load fluctuations through digital filtering, and compares it with the mapping curve library to determine the current remaining percentage of power or charging progress. The control module then outputs pulse-width modulation (PWM) signals or level combinations through multiple general-purpose input / output (GPIO) pins to drive the multi-level LED indicator structure. This indicator light structure uses LED light-emitting combinations in different spatial positions, different specific light colors (such as red, yellow, and green), and specific logic for constant light or flashing frequency to intuitively and in real time distinguish and provide feedback on four different device power and power supply statuses: fully charged, medium charged, low charged, or charging.

[0105] Experimental scenario verification:

[0106] The experimental test platform includes one wireless receiver slave unit operating in a steady-state wireless state. The slave unit's 3.5mm analog audio output interface is connected to the balanced input of a high-precision audio comprehensive analyzer (APx555) via a standard shielded audio cable for real-time monitoring of the total harmonic distortion plus noise (THD+N) and full-band spectral energy distribution of the slave unit's output audio. On the power supply side, a mains-powered adjustable charging power supply with severe high-frequency ripple (artificially injected 100mV, 50Hz power frequency interference, and 100kHz high-frequency noise) is configured. The output of this mains-powered adjustable charging power supply is connected to the slave unit's Type-C power supply interface via a 2-meter USB cable. Additionally, probes from a 4-channel high-speed digital oscilloscope are connected to the system power load (VCC_SYS) and audio reference ground lines within the slave unit to capture transient voltage waveforms during power supply plugging and unplugging.

[0107] In its initial state, the wireless receiver slave is powered independently by its internal energy storage battery. The audio analysis instrument (APx555) measured that the background noise of the analog output audio of the receiver slave at this time is extremely pure, with no obvious discrete spectral lines in the entire frequency band, and the THD+N index reaches -96dB.

[0108] During continuous audio output, a hot-plugged AC power cable with severe ripple interference was manually connected to the Type-C interface. At this moment, the oscilloscope detected a momentary high-frequency excitation applied to the primary side of the high-frequency miniature transformer, with electrical energy being transferred to the secondary side via magnetic coupling across the physical insulation layer. The power path arbitration switch within the power management unit (PMU) quickly completed the switching action within 1.5 milliseconds. Observing the waveform at the system power load terminal (VCC_SYS) on the secondary side using the oscilloscope, the voltage only experienced a tiny dip of 45 millivolts at the moment of switching, far below the chip reset threshold. The operation of the wireless receiving module and the main control module was not affected in any way, and the audio bus transmission remained completely continuous, confirming the technical authenticity of seamless power switching.

[0109] Meanwhile, after the steady-state of simultaneous charging and use was established, the full-band spectrum and noise floor were continuously observed using an audio comprehensive analyzer. Test data showed that even with severe power frequency and high-frequency noise from the external input power supply, the external ground noise was completely physically isolated on the primary side due to the lack of a direct DC electrical connection between the primary and secondary sides of the high-frequency miniature transformer, preventing backflow to the audio reference ground. The APx555 display showed that the THD+N of the audio output channel remained stable between -95.8dB and -96dB, with no power frequency noise lines representing AC hum appearing at 50Hz and its harmonics, and no perceptible current noise or background noise.

[0110] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-source wireless audio receiving system supporting fiber optic, coaxial, and Bluetooth inputs and equipped with a built-in lithium battery, comprising a wireless transmitter and at least one wireless receiver slave, characterized in that, The system includes: A multi-source input arbitration module is configured in the wireless transmitter host and integrates a digital audio input interface, an analog audio input interface, a Bluetooth input module, and an OTG input module. It is used to access multiple audio signals and automatically select the target input channel according to a preset priority through an internal audio channel arbitrator. The time-stamped broadcast transmission module, configured in the wireless transmitter host, is used to encode and package the selected audio signals, and periodically insert timestamp synchronization beacons into the audio data frames for wireless broadcasting. A clock phase-locked receiver module, configured in the wireless receiver slave, is used to receive the audio data frame and perform clock synchronization compensation through a local phase-locked loop based on the timestamp synchronization beacon, triggering audio output at a specified absolute timestamp; An electrically isolated power supply module is configured on the wireless receiver slave unit, including an external power supply interface and an isolation power supply circuit. The isolation power supply circuit physically and electrically isolates the charging ground wire of the external power supply interface from the audio reference ground wire inside the system, so as to support the wireless receiver slave unit to output audio without current noise when charging.

2. The wireless audio receiving system for multiple sources, including fiber optic, coaxial, and Bluetooth inputs, and equipped with a built-in lithium battery, as described in claim 1, is characterized in that... The analog audio input interface includes at least two 3.5mm audio input terminals, wherein at least one of the 3.5mm audio input terminals is connected in series with a hardware variable resistor type volume adjustment circuit and an analog audio operational amplifier in the physical circuit, which is used to perform hardware-level lossless volume gain or attenuation adjustment on the input analog audio signal before the audio channel arbitrator selects the channel; The digital audio input interface consists of an optical fiber input interface and a coaxial input interface; The OTG input module is configured as a digital audio decoding interface based on the USBAudioClass protocol, which is used to directly read the underlying digital audio bitstream from an external smart terminal or storage device without the need for additional drivers.

3. The wireless audio receiving system for multiple sources, including fiber optic, coaxial, and Bluetooth inputs, and equipped with a built-in lithium battery, as described in claim 2, is characterized in that... The internal audio channel arbiter includes an interface detection unit, a priority register, and a multiplexing switch; The interface detection unit is used to monitor the level transition status of each input interface or the handshake signal of the peripheral device in real time. The preset priority order fixed in the priority register is as follows: the OTG input module, the Bluetooth input module, the digital audio input interface, and the analog audio input interface; When the interface detection unit determines that multiple interfaces have valid audio signals at the same time, the multiplexing switch is configured to: cut off the signal data link of the low priority channel according to the highest priority instruction output by the priority register, and only keep the target input channel corresponding to the highest priority connected to the subsequent transmission module.

4. The wireless audio receiving system for multiple sources, including fiber optic, coaxial, and Bluetooth inputs, and equipped with a built-in lithium battery, as described in claim 3, is characterized in that... The time stamp broadcast transmission module includes an audio hardware encoder and a timestamp injection unit; The audio hardware encoder is used to convert the selected audio signal into a pulse code modulation (PCM) data stream and divide and pack it into fixed-length audio payload blocks. The timestamp injection unit includes a high-precision local reference clock, which is used to attach an absolute timestamp generated based on the local reference clock to each audio payload block, and encapsulate the absolute timestamp in the frame header of the audio data frame to form the timestamp synchronization beacon; When the time-stamp broadcasting module transmits the audio data frame, it adopts a one-way radio frequency broadcast mode based on a non-acknowledgment mechanism to drive at least two wireless receiver slaves simultaneously. The time-stamped broadcast transmission module integrates a forward error correction coding matrix. The forward error correction coding matrix performs matrix redundancy operation on the audio data frame encapsulated with the timestamped synchronization beacon, generates a forward error correction check block, and appends it to the end of the audio data frame so that the wireless receiving slave can perform autonomous error correction and restoration in the state of no retransmission interaction. The time-marked broadcast transmission module and the multi-source input arbitration module are connected by a digital signal processing core. The DSP core includes an asynchronous sampling rate conversion unit and a digital noise reduction algorithm module; The ASRC unit is used to uniformly resample audio signals with different native sampling rates output by the multi-source input arbitration module into a fixed high-resolution target sampling rate audio data stream. The digital noise reduction algorithm module is used to perform full-band dynamic range stabilization and background noise suppression processing on the resampled audio data stream, and then output the processed clean audio signal to the time-marked broadcast transmission module for encoding and packaging.

5. A single-transmitter, multiple-receiver wireless audio receiver system supporting fiber optic, coaxial, and Bluetooth multi-source inputs and equipped with a built-in lithium battery, as described in claim 4, is characterized in that... The clock phase-locked receiver module includes an RF receiving antenna, an error correction decoder, and a flexible jitter buffer; The radio frequency receiving antenna is used to capture the audio data frames transmitted based on the unidirectional radio frequency broadcast mode; The error correction decoder uses the forward error correction check block to perform local autonomous error correction on the damaged data frame and stores the restored audio payload block in the elastic jitter buffer to absorb network jitter delay during wireless channel transmission. The internal clock compensation circuit of the clock phase-locked receiver module includes a timestamp extraction unit, a phase error comparator, and a local numerically controlled oscillator. The timestamp extraction unit is used to extract the absolute timestamp of the transmitting end from the received audio data frame; The phase error comparator is used to calculate the clock drift error between the absolute timestamp and the local count value currently generated by the local numerically controlled oscillator, and outputs a frequency fine-tuning control word to the local numerically controlled oscillator based on the clock drift error, forcing the oscillation frequency of the local numerically controlled oscillator to maintain phase lock with the reference clock of the transmitting host.

6. A single-transmitter, multiple-receiver wireless audio receiving system supporting fiber optic, coaxial, and Bluetooth multi-source inputs and equipped with a built-in lithium battery, as described in claim 5, is characterized in that... The clock phase-locked receiver module also includes a synchronous trigger controller and a digital-to-analog converter; The synchronous trigger controller continuously monitors the time count value of the local numerically controlled oscillator in phase-locked state. When the time count value reaches the preset playback timestamp associated with the audio payload block, the synchronous trigger controller outputs a hardware-level interrupt trigger signal to the digital-to-analog converter. In response to the hardware-level interrupt trigger signal, the digital-to-analog converter instantly converts the audio payload block in the elastic jitter buffer into an analog audio signal output, thereby constraining the audio synchronization output delay difference of multiple wireless receiver slaves to be less than 10 milliseconds.

7. A wireless audio receiving system supporting fiber optic, coaxial, and Bluetooth multi-source inputs and equipped with a built-in lithium battery, as described in claim 6, is characterized in that... The isolated power supply circuit includes an isolated DC-DC converter chip and a high-frequency miniature transformer; The power input terminal and charging ground wire of the external power supply interface are connected to the primary side of the high-frequency micro transformer, and the secondary output terminal of the high-frequency micro transformer is connected to the audio reference ground wire and the load power supply terminal inside the system. There is no direct DC electrical connection between the primary side and the secondary side. The power supply is configured to cross from the primary side to the secondary side through the magnetic coupling of the high-frequency micro transformer, thereby physically cutting off the power frequency interference and high-frequency noise introduced by the external power supply equipment through the common ground loop.

8. A single-transmitter, multiple-receiver wireless audio receiving system supporting fiber optic, coaxial, and Bluetooth multi-source inputs and equipped with a built-in lithium battery, as described in claim 7, is characterized in that... The electrically isolated power supply module also includes a power management unit (PMU) and an energy storage battery integrated on the secondary side; The power management unit includes a power path arbitration switch configured to perform seamless power switching: when the external power supply interface detects the access of an external power source, the power path arbitration switch is activated, preferentially extracting the pure electrical energy converted by magnetic coupling from the secondary side output terminal to power the system, and bypassing to charge the energy storage battery, so as to maintain the uninterrupted operation and transmission interruption of the wireless receiver slave in the charging and use mode.

9. A single-transmitter, multiple-receiver wireless audio receiving system supporting fiber optic, coaxial, and Bluetooth multi-source inputs and equipped with a built-in lithium battery, as described in claim 8, is characterized in that... The electrically isolated power supply module is also coupled with a power visualization monitoring circuit; The power visualization monitoring circuit includes a voltage detection pin and a multi-level LED indicator structure; The voltage detection pin is connected to the output terminal of the energy storage battery and is used to collect the battery terminal voltage change characteristics in real time. The internal main controller of the wireless receiver slave device drives the multi-level LED indicator to switch between the light colors or flashing logic corresponding to four preset states: full charge, medium charge, low charge, or charging, based on the terminal voltage change characteristics.

10. A multi-source wireless audio transmitter supporting fiber optic, coaxial, and Bluetooth inputs and equipped with a built-in lithium battery, applied to the multi-source wireless audio receiver system supporting fiber optic, coaxial, and Bluetooth inputs and equipped with a built-in lithium battery as described in any one of claims 1-9, characterized in that... include: An audio input interface array, comprising a fixed optical input interface, a coaxial input interface, at least two 3.5mm analog audio input interfaces, and a USB OTG input interface; Bluetooth receiver chip, used to receive wireless Bluetooth audio signals from external space; The main control chip has multiple physical input pins that are electrically connected to each interface in the audio input interface array and the signal output pin of the Bluetooth receiver chip, respectively. The main control chip integrates a digital audio multiplexer and a digital signal processor, and a high-precision crystal oscillator is electrically connected to the peripheral circuit of the main control chip. A wireless radio frequency transmitter chip, wherein its baseband signal input pin is electrically connected to the signal output pin of the main control chip, and its radio frequency output pin is electrically connected to a radio frequency transmitting antenna; The built-in power supply circuit includes a lithium battery and a power management chip electrically connected to the output terminal of the lithium battery. Multiple power output pins of the power management chip are physically and electrically connected to the power pins of the audio input interface array, the Bluetooth receiver chip, the main control chip, and the wireless radio frequency transmitter chip, respectively.

Images