Special integrated chip, ris phase optimal configuration solving method and related device

Abstract

Embodiments of the present application disclose a special integrated chip, a RIS phase optimal configuration solving method and related devices. A gradient generator utilizes 1-bit binary characteristics to simplify multiplication into a sign selection operation of a multiplexer and an inverter, to complete gradient and Hessian matrix calculation required by second-order Taylor approximation with extremely low area and power consumption; a coefficient generator combines Lagrange multipliers, relaxation variables and penalty factors to completely map a discrete optimization problem into an Ising model, to complete information transmission target of SWIPT and process energy collection constraints; a dSB solver configures parallel MMTE modules according to the number of RIS units, to realize Ising ground state solving with high parallelism and strong escape local optimal capability on a classical hardware; the gradient generator, the coefficient generator and the dSB solver constitute an on-chip iterative closed loop without CPU intervention, supplemented by a hot-startable initialization mechanism, to output RIS phase configuration close to global optimization within lower delay, which has low power consumption, low delay, high solution quality and scale scalability.

Description

Technical Field

[0001] This invention relates to the field of logic chip technology, and in particular to a dedicated integrated chip, a method for solving the optimal phase configuration of RIS, and related apparatus. Background Technology

[0002] The 1-bit intelligent reflective surface (RIS)-assisted Simultaneous Wireless Information and Power Transfer (SWIPT) system is a key technology for providing high-efficiency and sustainable communication for energy-constrained networks such as the future large-scale Internet of Things. It integrates two key technologies: SWIPT and RIS. SWIPT allows wireless signals to be collected by terminal devices and converted into electrical energy while transmitting information, thus powering low-power devices and solving the problems of high maintenance costs and difficulty in large-scale deployment caused by traditional devices relying on batteries. RIS is a plane composed of a large number of low-cost, low-power passive reflective units that can intelligently control the phase of incident electromagnetic waves and improve the signal propagation environment.

[0003] Each unit in a 1-bit RIS has only two states, transforming the RIS phase configuration optimization problem into a combinatorial optimization problem, which can be well solved using Ising machines. Existing methods for solving the 1-bit phase optimization problem in practical RIS-SWIPT systems using Ising machines mainly focus on software algorithms, lacking dedicated hardware implementations. This makes it difficult to meet the requirements of practical RIS-SWIPT systems for low latency, low power consumption, and real-time deployment at the edge. Summary of the Invention

[0004] This application provides a dedicated integrated chip, a method for solving the optimal RIS phase configuration, and related devices. It can provide a dedicated Ising hardware accelerator for the 1-bit RIS-SWIPT phase optimization problem, thereby meeting the requirements of practical RIS-SWIPT systems for low latency, low power consumption, and real-time deployment at the edge.

[0005] The first aspect of this application provides a dedicated integrated chip for use in a 1-bit RIS-assisted SWIPT system, the dedicated integrated chip comprising: A gradient generator is configured to control a matrix reader to sequentially read elements of an externally input channel matrix via a row counter and / or column counter and an address generator; to perform multiplication operations between the elements of the channel matrix and the corresponding elements in the RIS phase configuration of the current iteration round via a multiplexer and an inverter; and to accumulate the product of the multiplication operations between each element of the channel matrix and the corresponding element in the RIS phase configuration of the current iteration round via an accumulator to obtain a first-order gradient and a second-order Hessian matrix, which are used to construct a local second-order Taylor approximation function. The coefficient generator is configured to read the Lagrange multipliers, slack variables, and penalty factors of the current iteration round through the parameter weight unit; and to map the first-order gradient in the second-order Taylor approximation function to a bias term and the second-order Hessian matrix in the second-order Taylor approximation function to an Ising coupling matrix by combining the Lagrange multipliers, slack variables, and penalty factors of the current iteration round through the multiplier and accumulator. The discrete simulation bifurcation dSB solver is configured to configure the number of matrix multiplication-time evolution (MMTE) modules according to the number of elements in the RIS phase configuration, and to obtain the RIS candidate phase configuration by solving the corresponding Ising ground state problem in parallel through the configured multiple MMTE modules based on the Ising coupling matrix and bias terms. When the current iteration round is the initial iteration round, the RIS phase is configured as the initial solution input from the outside, and the values ​​of the Lagrange multipliers, relaxation variables, and penalty factors are preset values.

[0006] Optionally, the dedicated integrated chip further includes: The candidate solution evaluation module is configured to calculate the augmented Lagrange values ​​corresponding to the RIS phase configuration and the RIS candidate phase configuration respectively using an augmented Lagrange function calculator, and to calculate the constraint residual values ​​based on the RIS phase configuration and the RIS candidate phase configuration using a constraint residual calculator; to compare the magnitudes of the augmented Lagrange values ​​corresponding to the RIS phase configuration and the RIS candidate phase configuration using an augmented Lagrange comparator, and to compare whether the constraint residual values ​​are greater than 0 using a constraint residual comparator.

[0007] Optionally, the dedicated integrated chip further includes: The results management module is configured to write the RIS candidate phase configuration as the RIS phase configuration into the second current solution register when the augmented Lagrange value corresponding to the RIS phase configuration is less than the augmented Lagrange value corresponding to the RIS phase configuration and the constraint residual value is not greater than 0; compare the RIS phase configuration stored in the second current solution register with the optimal RIS phase configuration stored in the optimal solution register through a solution comparator; if the RIS phase configuration is better than the optimal RIS phase configuration, update the optimal RIS phase configuration stored in the optimal solution register to the RIS phase configuration; if the RIS phase configuration is not better than the optimal RIS phase configuration, keep the optimal RIS phase configuration stored in the optimal solution register unchanged.

[0008] Optionally, the dedicated integrated chip further includes: The bit-by-bit correction module is configured to flip the RIS candidate phase configuration bit-by-bit to obtain a new RIS candidate phase configuration when the augmented Lagrange value corresponding to the RIS candidate phase configuration is not less than the augmented Lagrange value corresponding to the RIS phase configuration and / or the constraint residual value is greater than 0. The top-level controller is configured to control the RIS candidate phase configuration evaluation module to continue execution based on the new RIS candidate phase configuration.

[0009] Optionally, the top-level controller is further configured to write the RIS candidate phase configuration as the RIS phase configuration into the first current solution register and control the gradient generator to continue execution when the augmented Lagrangian value corresponding to the RIS candidate phase configuration is less than the augmented Lagrangian value corresponding to the RIS phase configuration and the constraint residual value is not greater than 0.

[0010] Optionally, the dedicated integrated chip further includes: The parameter update module is configured to update the Lagrange multipliers and relaxation variables through the Lagrange multiplier and relaxation variable module, and update the penalty factor through the adaptive penalty factor update module when the augmented Lagrange value corresponding to all new RIS candidate phase configurations is not less than the augmented Lagrange value corresponding to the RIS phase configuration and / or the constraint residual value is greater than 0. The top-level controller is also configured to control the gradient generator to continue execution based on the updated Lagrange multipliers, slack variables, and penalty factors.

[0011] Optionally, regarding the updating of the penalty factor via the adaptive penalty factor update module: The parameter update module is configured to determine whether the RIS phase configuration of the current iteration round and the previous iteration round are the same through a stability checker; if they are the same, the stability count is incremented by 1 through the stability counter; if they are different, the stability count is cleared to zero through the stability counter; if the stability count does not reach the preset threshold, the penalty factor is increased according to the growth coefficient; if the stability count reaches the preset threshold, the penalty factor remains unchanged.

[0012] A second aspect of this application provides a method for solving the optimal RIS phase configuration, applied to a 1-bit RIS-assisted SWIPT system, the method comprising: The row counter and / or column counter, along with the address generator, control the matrix reader to sequentially read the elements of the externally input channel matrix; the multiplexer, in conjunction with the inverter, performs multiplication operations between the elements of the channel matrix and the corresponding elements in the RIS phase configuration of the current iteration round; the accumulator accumulates the product of the multiplication operations between each element of the channel matrix and the corresponding element in the RIS phase configuration of the current iteration round to obtain the first-order gradient and the second-order Hessian matrix, which are used to construct a local second-order Taylor approximation function; The Lagrange multipliers, relaxation variables, and penalty factors of the current iteration round are read through the parameter weight unit; through the multiplier and accumulator, combined with the Lagrange multipliers, relaxation variables, and penalty factors of the current iteration round, the first-order gradient in the second-order Taylor approximation function is mapped to the bias term, and the second-order Hessian matrix in the second-order Taylor approximation function is mapped to the Ising coupling matrix. The number of matrix multiplication-time evolution (MMTE) modules is configured according to the number of elements in the RIS phase configuration, and the corresponding Ising ground state problem is solved in parallel by the configured multiple MMTE modules based on the Ising coupling matrix and bias terms to obtain the RIS candidate phase configuration. When the current iteration round is the initial iteration round, the RIS phase is configured as the initial solution input from the outside, and the values ​​of the Lagrange multipliers, relaxation variables, and penalty factors are preset values.

[0013] A third aspect of this application provides an electronic device, including: a processor and a memory; The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the second aspect of the embodiments of this application.

[0014] The fourth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the second aspect of this application.

[0015] As can be seen, in this embodiment, the gradient generator simplifies multiplication to a sign selection operation of "multiplexer and inverter" using the 1-bit binary characteristic, completing the gradient and Hessian matrix calculations required for the second-order Taylor approximation with extremely low area and power consumption; the coefficient generator combines Lagrange multipliers, slack variables, and penalty factors to completely map the discrete optimization problem to the Ising model, completing the information transmission objective of SWIPT and handling the dual constraints of energy harvesting; the dSB solver configures parallel MMTE modules according to the number of RIS units, realizing the Ising ground state solution with high parallelism and strong escape from local optima on classical hardware; the gradient generator, coefficient generator, and dSB solver constitute an on-chip iterative closed loop without CPU intervention, supplemented by a hot-start initialization mechanism, thereby outputting a near-globally optimal RIS phase configuration with low latency, which combines low power consumption, low latency, high solution quality, and scalability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the architecture of a dedicated integrated chip provided in one embodiment of this application is shown; Figure 2 A flowchart illustrating a method for solving the optimal RIS phase configuration according to an embodiment of this application is shown. Figure 3 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] Please refer to Figure 1 This illustration shows a schematic diagram of the architecture of a dedicated integrated chip provided in one embodiment of this application. The dedicated integrated chip is applied to a 1-bit smart reflective surface RIS-assisted wireless power-carrying communication (SWIPT) system, and the dedicated integrated chip includes: A gradient generator is configured to control a matrix reader to sequentially read elements of an externally input channel matrix via a row counter and / or column counter and an address generator; to perform multiplication operations between the elements of the channel matrix and the corresponding elements in the RIS phase configuration of the current iteration round via a multiplexer and an inverter; and to accumulate the product of the multiplication operations between each element of the channel matrix and the corresponding element in the RIS phase configuration of the current iteration round via an accumulator to obtain a first-order gradient and a second-order Hessian matrix, which are used to construct a local second-order Taylor approximation function. The coefficient generator is configured to read the Lagrange multipliers, slack variables, and penalty factors of the current iteration round through the parameter weight unit; and to map the first-order gradient in the second-order Taylor approximation function to a bias term and the second-order Hessian matrix in the second-order Taylor approximation function to an Ising coupling matrix by combining the Lagrange multipliers, slack variables, and penalty factors of the current iteration round through the multiplier and accumulator. The discrete simulated bifurcation (dSB) solver is configured to configure the number of matrix multiplication-time evolution (MMTE) modules according to the number of elements in the RIS phase configuration, and to use the configured multiple MMTE modules to solve the corresponding Ising ground state problem in parallel according to the Ising coupling matrix and bias terms to obtain the RIS candidate phase configuration. When the current iteration round is the initial iteration round, the RIS phase is configured as the initial solution input from the outside, and the values ​​of the Lagrange multipliers, relaxation variables, and penalty factors are preset values.

[0020] like Figure 1 As shown, the gradient generator and coefficient generator together constitute the Ising coefficient generation module. The Ising coefficient generation module is configured to transform the optimization objective of the 1-bit RIS-assisted SWIPT system into Ising model parameters recognizable by the dSB solver. These Ising model parameters include the Ising coupling matrix and bias terms. Wherein: The gradient generator consists of a column counter, a row counter, an address generator, a matrix reader, a multiplexer, an inverter, and an accumulator (ACC).

[0021] Column counters and row counters can work together to generate a coordinate pair, allowing the reading of elements in the channel matrix row by row or column by column. Alternatively, either a row counter or a column counter can be used to import elements into the channel matrix in batches, row by row or column by column; this is not a limitation. The channel matrix includes information about the signal power at the information receiving end. Corresponding information channel matrix and the signal power at the energy receiver Corresponding energy receiving channel matrix , , , The RIS phase configuration for the current iteration round, i.e. the current solution, is an N×1 dimensional coefficient vector, where N is the number of RIS units. Since it is 1-bit quantization, each element has a binary value, so its conjugate transpose is equal to the transpose. It can be used to construct the objective function. For example, the information rate is proportional to The logarithm of , therefore we can directly let . .same, It can be used to construct constraint functions ,example like The collected energy E at the energy receiver can be expressed as: , in, , , These are the parameters for the energy harvesting model. The system constraint requires that E exceed the minimum harvested energy threshold. ,Right now Transform it into a constraint function and write it as follows: An address generator is essentially a multiply-accumulate unit used to generate a target address based on the base address and the elements in the coordinate pair.

[0022] The matrix reader is an enabled memory interface controller that sends the address output by the address generator to the address bus of external memory, issues a read enable signal, and then captures the return value on the data bus. External memory may include, for example, input registers, which the top-level controller can control to read the channel matrix stored in the matrix register. and and read its stored information from the first current solution register. .

[0023] For 1-bit Its value is either +1 or -1. The elements of the channel matrix are related to the RIS phase configuration. Corresponding element The multiplication operation degenerates into sign selection: if the sign is +1, the result of the multiplication is an element of the channel matrix; if the sign is -1, the result is the inverse of an element of the channel matrix. Therefore, it can be implemented using a multiplexer and an inverter. A typical floating-point multiplier requires 4-5 stages of pipeline and thousands of logic gates to implement the multiplication. This embodiment only requires one inverter and one MUX, resulting in a 2-3 order of magnitude difference in area and power consumption. Finally, the first-order gradient is obtained by accumulating the product of the multiplication operations of each element of the channel matrix with the corresponding element in the RIS phase configuration of the current iteration. And the second-order Hessian matrix M.

[0024] The augmented Lagrangian function is: , For RIS phase configuration, These are Lagrange multipliers used to adjust the optimization direction based on constraint violations. As slack variables, the inequality constraints are transformed into The form; The penalty factor controls the weight of the constraint penalty term in the overall objective. The initial values ​​of all three can be preset values. The augmented Lagrangian function unifies the information receiver objective and the energy receiver constraint into a single function, transforming the constrained problem into an unconstrained optimization problem.

[0025] Since the function may still contain higher-order terms, it cannot be directly solved by the standard Ising machine. In this embodiment, a two-layer iteration is constructed. The outer iteration is the augmented Lagrangian function described above. The inner iteration uses... As the starting point, for Performing a second-order Taylor expansion yields a local second-order Taylor approximation function near the current point: , This approximation function only preserves the first-order gradient near the current point. and second-order Hessian matrix This transforms the original high-order optimization structure locally into a quadratic form. The gradient generator can calculate the first-order gradient. And the second-order Hessian matrix M.

[0026] The coefficient generator includes a parameter weighting unit, a multiplexer, a multiplier, and an accumulator. At the beginning of each iteration, the parameter weighting unit reads the Lagrange multipliers for the current iteration. slack variables and penalty factor The multiplexer will select the Lagrange multiplier. slack variables and penalty factor Operands are distributed to the operand ports of the multipliers and accumulators. The multiplier array performs independent outer product / scalar multiplication operations in parallel, and the accumulator multiplies the output of the multipliers with the first-order gradient. The elements of the second-order Hessian matrix M are added together by matrix or vector addition, and finally mapped to the bias term h and the Ising coupling matrix J through the Ising mapping.

[0027] Furthermore, the application-specific integrated circuit (ASIC) may also include a normalization unit and a cache. The normalization unit can adjust the numerical range of the bias term h and the Ising coupling matrix J, and then cache them in the cache.

[0028] The core idea of ​​dSB is to replace the continuous evolution of N nonlinear oscillators with... Discrete exhaustive search. The dSB solver is centered around a parallel Matrix Multiplication-Time Evolution (MMTE) module, which supports various spin-scale configurations, such as 64, 128, and 256 spin scales. The number of data processed per cycle by a single MAC remains constant across different hardware scales. The number of parallel MMTEs and the number of MACs within each MMTE can be adjusted to adapt to different problem scales. The MMTE module includes matrix multiplication (MM) units and time evolution (TE) units. The MM units calculate the Ising coupling terms based on the Ising coupling matrix J, and the TE units update the position and momentum of the oscillator. The phase variable of each RIS reflection unit... This corresponds to a virtual oscillator.

[0029] For example, when there are enough MMTE modules, one MMTE can correspond to one reflection unit in the RIS. When there are not enough MMTE modules, they can be processed in batches.

[0030] As can be seen, in this embodiment, the gradient generator simplifies multiplication to a sign selection operation of "multiplexer and inverter" using the 1-bit binary characteristic, completing the gradient and Hessian matrix calculations required for the second-order Taylor approximation with extremely low area and power consumption; the coefficient generator combines Lagrange multipliers, slack variables, and penalty factors to completely map the discrete optimization problem to the Ising model, completing the information transmission objective of SWIPT and handling energy harvesting constraints; the dSB solver configures parallel MMTE modules according to the number of RIS units, realizing the Ising ground state solution with high parallelism and strong escape from local optima on classical hardware; the gradient generator, coefficient generator, and dSB solver constitute an on-chip iterative closed loop without CPU intervention, supplemented by a hot-start initialization mechanism, thereby outputting a near-globally optimal RIS phase configuration with low latency, which combines low power consumption, low latency, high solution quality, and scalability.

[0031] Furthermore, the dedicated integrated chip also includes: The candidate solution evaluation module is configured to calculate the augmented Lagrange values ​​corresponding to the RIS phase configuration and the RIS candidate phase configuration respectively using an augmented Lagrange function calculator, and to calculate the constraint residual values ​​based on the RIS phase configuration and the RIS candidate phase configuration using a constraint residual calculator; to compare the magnitudes of the augmented Lagrange values ​​corresponding to the RIS phase configuration and the RIS candidate phase configuration using an augmented Lagrange comparator, and to compare whether the constraint residual values ​​are greater than 0 using a constraint residual comparator.

[0032] The multipliers in the augmented Lagrange function calculator and the constrained residual calculator can also be implemented using a multiplexer and an inverter. The specific solution for the augmented Lagrange value involves substituting the values ​​into the augmented Lagrange function, and the specific solution for the constrained residual involves substituting the values ​​into the constraint function, then subtracting the two. The augmented Lagrange comparator can be implemented using a subtractor and a sign bit extractor, while the constrained residual comparator can be implemented using a sign bit extractor, determining the sign of the constrained residual.

[0033] Furthermore, the dedicated integrated chip also includes: The results management module is configured to write the RIS candidate phase configuration as the RIS phase configuration into the second current solution register when the augmented Lagrange value corresponding to the RIS phase configuration is less than the augmented Lagrange value corresponding to the RIS phase configuration and the constraint residual value is not greater than 0; compare the RIS phase configuration stored in the second current solution register with the optimal RIS phase configuration stored in the optimal solution register through a solution comparator; if the RIS phase configuration is better than the optimal RIS phase configuration, update the optimal RIS phase configuration stored in the optimal solution register to the RIS phase configuration; if the RIS phase configuration is not better than the optimal RIS phase configuration, keep the optimal RIS phase configuration stored in the optimal solution register unchanged.

[0034] Furthermore, the dedicated integrated chip also includes: The bit-by-bit correction module is configured to flip the RIS candidate phase configuration bit-by-bit to obtain a new RIS candidate phase configuration when the augmented Lagrange value corresponding to the RIS candidate phase configuration is not less than the augmented Lagrange value corresponding to the RIS phase configuration and / or the constraint residual value is greater than 0. The top-level controller is configured to control the RIS candidate phase configuration evaluation module to continue execution based on the new RIS candidate phase configuration.

[0035] Furthermore, the top-level controller is also configured to write the RIS candidate phase configuration as the RIS phase configuration into the first current solution register when the augmented Lagrangian value corresponding to the RIS phase configuration is less than the augmented Lagrangian value corresponding to the RIS phase configuration and the constraint residual value is not greater than 0, and to control the gradient generator to continue execution.

[0036] Bit-by-bit flipping refers to flipping only one bit at a time in a binary vector, evaluating the effect of the flip, deciding whether to retain the flip, and then moving to the next bit to continue. For example, for a 3-bit RIS candidate phase configuration... The first element is flipped while the rest remain unchanged, resulting in a new RIS candidate phase configuration. Then, the top-level controller controls the candidate solution evaluation module to continue execution to evaluate the effect of the flip and decide whether to retain the flip; the second element is flipped a second time, while the remaining elements remain unchanged, resulting in a new RIS candidate phase configuration. Then, the top-level controller controls the candidate solution evaluation module to continue execution to evaluate the effect of the flip and decide whether to retain the flip; the third element is flipped a third time, while the remaining elements remain unchanged, resulting in a new RIS candidate phase configuration. Then, the top-level controller controls the candidate solution evaluation module to continue execution to evaluate the effect of the flip and decide whether to retain the flip. The essence of bit-by-bit flipping is a greedy local search: it does not guarantee global optimality, but makes fine adjustments around the RIS candidate phase configuration given by dSB with extremely low computational cost.

[0037] Furthermore, the dedicated integrated chip also includes: The parameter update module is configured to update the Lagrange multipliers and relaxation variables through the Lagrange multiplier and relaxation variable module, and update the penalty factor through the adaptive penalty factor update module when the augmented Lagrange value corresponding to all new RIS candidate phase configurations is not less than the augmented Lagrange value corresponding to the RIS phase configuration and / or the constraint residual value is greater than 0. The top-level controller is also configured to control the gradient generator to continue execution based on the updated Lagrange multipliers, slack variables, and penalty factors.

[0038] If all bit-by-bit corrections fail, it means that under the current Lagrange multipliers, slack variables, and penalty factor, no matter how they are flipped, a better solution cannot be obtained, therefore parameter adjustment is required. The updates to the Lagrange multipliers and slack variables can be, for example, dual increasing, or other adjustment methods, which are not limited here. The penalty factor is updated adaptively.

[0039] Specifically, regarding the updating of the penalty factor through the adaptive penalty factor update module: The parameter update module is configured to determine whether the RIS phase configuration of the current iteration round and the previous iteration round are the same through a stability checker; if they are the same, the stability count is incremented by 1 through the stability counter; if they are different, the stability count is cleared to zero through the stability counter; if the stability count does not reach the preset threshold, the penalty factor is increased according to the growth coefficient; if the stability count reaches the preset threshold, the penalty factor remains unchanged.

[0040] In SWIPT's binary discrete optimization, the changes in constraint residuals may be discontinuous, as flipping a single bit can cause a jump. The stability of the solution vector is a more robust convergence metric—in discrete problems, an invariant solution means the optimizer is "stuck" on a local structure, and increasing the penalty factor will not help; it may even lead to an ill-conditioned Hessian matrix. For example, in the k-th iteration, the update formula for the penalty factor is: ,in This is the growth coefficient.

[0041] Please refer to Figure 2 This document illustrates a flowchart of a RIS phase optimal configuration solution method provided in one embodiment of this application. This method can be applied to the aforementioned application-specific integrated circuit (ASIC). The method may include the following steps: Step 201: Control the matrix reader to sequentially read the elements of the externally input channel matrix using a row counter and / or column counter and an address generator; use a multiplexer and an inverter to perform multiplication operations between the elements of the channel matrix and the corresponding elements in the RIS phase configuration of the current iteration round; use an accumulator to accumulate the product of the multiplication operations between each element of the channel matrix and the corresponding element in the RIS phase configuration of the current iteration round to obtain the first-order gradient and the second-order Hessian matrix, which are used to construct a local second-order Taylor approximation function; Step 202: Read the Lagrange multipliers, slack variables, and penalty factors of the current iteration round through the parameter weight unit; through the multiplier and accumulator, combined with the Lagrange multipliers, slack variables, and penalty factors of the current iteration round, map the first-order gradient in the second-order Taylor approximation function to the bias term, and map the second-order Hessian matrix in the second-order Taylor approximation function to the Ising coupling matrix; Step 203: Configure the number of matrix multiplication-time evolution (MMTE) modules according to the number of elements in the RIS phase configuration, and use the configured multiple MMTE modules to solve the corresponding Ising ground state problem in parallel according to the Ising coupling matrix and bias terms to obtain the RIS candidate phase configuration; When the current iteration round is the initial iteration round, the RIS phase is configured as the initial solution input from the outside, and the values ​​of the Lagrange multipliers, relaxation variables, and penalty factors are preset values.

[0042] It should be noted that the specific implementation process on the method side can be found in the hardware side description above, and will not be repeated here.

[0043] Figure 3 The diagram illustrates the structure of a computer device according to an embodiment of this application, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system of the RIS phase optimal configuration solution method in any of the above embodiments.

[0044] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system of the RIS phase optimal configuration solution method in any of the above embodiments.

[0045] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system of the RIS phase optimal configuration solution method in any of the above embodiments.

[0046] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0047] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0048] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0049] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0050] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0051] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0052] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0053] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0054] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0055] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0056] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0057] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0058] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A dedicated integrated chip, characterized in that, The dedicated integrated chip used in the RIS-assisted wireless power-carrying communication SWIPT system with a 1-bit smart reflective surface includes: A gradient generator is configured to control a matrix reader to sequentially read elements of an externally input channel matrix via a row counter and / or column counter and an address generator; to perform multiplication operations between the elements of the channel matrix and the corresponding elements in the RIS phase configuration of the current iteration round via a multiplexer and an inverter; and to accumulate the product of the multiplication operations between each element of the channel matrix and the corresponding element in the RIS phase configuration of the current iteration round via an accumulator to obtain a first-order gradient and a second-order Hessian matrix, which are used to construct a local second-order Taylor approximation function. The coefficient generator is configured to read the Lagrange multipliers, slack variables, and penalty factors of the current iteration round through the parameter weight unit; and to map the first-order gradient in the second-order Taylor approximation function to a bias term and the second-order Hessian matrix in the second-order Taylor approximation function to an Ising coupling matrix by combining the Lagrange multipliers, slack variables, and penalty factors of the current iteration round through the multiplier and accumulator. The discrete simulation bifurcation dSB solver is configured to configure the number of matrix multiplication-time evolution (MMTE) modules according to the number of elements in the RIS phase configuration, and to use the configured multiple MMTE modules to solve the corresponding Ising ground state problem in parallel according to the Ising coupling matrix and bias terms to obtain the RIS candidate phase configuration. When the current iteration round is the initial iteration round, the RIS phase is configured as the initial solution input from the outside, and the values ​​of the Lagrange multipliers, relaxation variables, and penalty factors are preset values.

2. The dedicated integrated chip according to claim 1, characterized in that, The dedicated integrated chip also includes: The candidate solution evaluation module is configured to calculate the augmented Lagrange values ​​corresponding to the RIS phase configuration and the RIS candidate phase configuration respectively using an augmented Lagrange function calculator, and to calculate the constraint residual values ​​based on the RIS phase configuration and the RIS candidate phase configuration using a constraint residual calculator; to compare the magnitudes of the augmented Lagrange values ​​corresponding to the RIS phase configuration and the RIS candidate phase configuration using an augmented Lagrange comparator, and to compare whether the constraint residual values ​​are greater than 0 using a constraint residual comparator.

3. The dedicated integrated chip according to claim 2, characterized in that, The dedicated integrated chip also includes: The results management module is configured to write the RIS candidate phase configuration as the RIS phase configuration into the second current solution register when the augmented Lagrange value corresponding to the RIS phase configuration is less than the augmented Lagrange value corresponding to the RIS phase configuration and the constraint residual value is not greater than 0; compare the RIS phase configuration stored in the second current solution register with the optimal RIS phase configuration stored in the optimal solution register through a solution comparator; if the RIS phase configuration is better than the optimal RIS phase configuration, update the optimal RIS phase configuration stored in the optimal solution register to the RIS phase configuration; if the RIS phase configuration is not better than the optimal RIS phase configuration, keep the optimal RIS phase configuration stored in the optimal solution register unchanged.

4. The dedicated integrated chip according to claim 3, characterized in that, The dedicated integrated chip also includes: The bit-by-bit correction module is configured to flip the RIS candidate phase configuration bit-by-bit to obtain a new RIS candidate phase configuration when the augmented Lagrange value corresponding to the RIS candidate phase configuration is not less than the augmented Lagrange value corresponding to the RIS phase configuration and / or the constraint residual value is greater than 0. The top-level controller is configured to control the RIS candidate phase configuration evaluation module to continue execution based on the new RIS candidate phase configuration.

5. The dedicated integrated chip according to claim 4, characterized in that, The top-level controller is further configured to write the RIS candidate phase configuration as the RIS phase configuration into the first current solution register when the augmented Lagrangian value corresponding to the RIS phase configuration is less than the augmented Lagrangian value corresponding to the RIS phase configuration and the constraint residual value is not greater than 0, and to control the gradient generator to continue execution.

6. The dedicated integrated chip according to claim 4, characterized in that, The dedicated integrated chip also includes: The parameter update module is configured to update the Lagrange multipliers and relaxation variables through the Lagrange multiplier and relaxation variable module, and update the penalty factor through the adaptive penalty factor update module when the augmented Lagrange value corresponding to all new RIS candidate phase configurations is not less than the augmented Lagrange value corresponding to the RIS phase configuration and / or the constraint residual value is greater than 0. The top-level controller is also configured to control the gradient generator to continue execution based on the updated Lagrange multipliers, slack variables, and penalty factors.

7. The dedicated integrated chip according to claim 6, characterized in that, Regarding the updating of the penalty factor via the adaptive penalty factor update module: The parameter update module is configured to determine whether the RIS phase configuration of the current iteration round and the previous iteration round are the same through a stability checker; if they are the same, the stability count is incremented by 1 through the stability counter; if they are different, the stability count is cleared to zero through the stability counter; if the stability count does not reach the preset threshold, the penalty factor is increased according to the growth coefficient; if the stability count reaches the preset threshold, the penalty factor remains unchanged.

8. A method for solving the optimal phase configuration of RIS, characterized in that, The method for a RIS-assisted wireless power-carrying communication SWIPT system applied to a 1-bit smart reflective surface (RIS) wireless power-carrying communication system includes: The row counter and / or column counter, along with the address generator, control the matrix reader to sequentially read the elements of the externally input channel matrix; the multiplexer, in conjunction with the inverter, performs multiplication operations between the elements of the channel matrix and the corresponding elements in the RIS phase configuration of the current iteration round; the accumulator accumulates the product of the multiplication operations between each element of the channel matrix and the corresponding element in the RIS phase configuration of the current iteration round to obtain the first-order gradient and the second-order Hessian matrix, which are used to construct a local second-order Taylor approximation function; The Lagrange multipliers, relaxation variables, and penalty factors of the current iteration round are read through the parameter weight unit; through the multiplier and accumulator, combined with the Lagrange multipliers, relaxation variables, and penalty factors of the current iteration round, the first-order gradient in the second-order Taylor approximation function is mapped to the bias term, and the second-order Hessian matrix in the second-order Taylor approximation function is mapped to the Ising coupling matrix. The number of matrix multiplication-time evolution (MMTE) modules is configured according to the number of elements in the RIS phase configuration, and the corresponding Ising ground state problem is solved in parallel using the configured multiple MMTE modules based on the Ising coupling matrix and bias terms to obtain the RIS candidate phase configuration. When the current iteration round is the initial iteration round, the RIS phase is configured as the initial solution input from the outside, and the values ​​of the Lagrange multipliers, relaxation variables, and penalty factors are preset values.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claim 8.

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