Multi-rate compatible QSFP112 optical transmission system based on domestic DSP and implementation method

Abstract

The application discloses a multi-rate compatible QSFP112 optical transmission system based on a domestic DSP and an implementation method, and relates to the technical field of optical transmission. The multi-rate compatible QSFP112 optical transmission system based on the domestic DSP comprises the following units: an optical transmission link configuration unit configured to estimate channel quality and acquire a rate mode to configure the domestic DSP; a multi-channel optical emission processing unit configured to perform frequency reduction and expansion rate remapping on input electrical signals after equalization and retiming and distribute the input electrical signals to a plurality of channel optical signal compensation emission units; the channel optical signal compensation emission units are configured to apply digital pre-emphasis compensation to the electrical signals and modulate the electrical signals to generate optical signals; and an optical transmission link time delay compensation unit configured to insert a composite alignment training sequence and perform coarse-grained time delay adjustment. According to the application, independent clock recovery and cross-channel phase alignment are performed on the recovered and spliced unit, and then the output is inversely spliced according to a demapping table, so that the rate of the DSP output signal is matched with the appropriate bandwidth, and reliable optical transmission of multi-rate compatibility is realized in the QSFP112.

Description

Technical Field

[0001] This invention relates to the field of optical transmission technology, specifically to a multi-rate compatible QSFP112 optical transmission system and its implementation method based on a domestically produced DSP. Background Technology

[0002] With the continued growth of data center traffic driven by cloud computing and artificial intelligence, 400G Ethernet has become the mainstream speed standard for short-distance optical interconnects. The QSFP112 package, with its compact size and high-density port layout, is widely used in 400G optical modules.

[0003] In the 400GQSFP112 short-distance optical module, multimode fiber is used in conjunction with a VCSEL array to achieve parallel optical transmission. Inside the optical module, a DSP chip completes the processing and rate conversion of high-speed electrical signals, and then the VCSEL array converts the electrical signals into optical signals for transmission. At the same time, with the advancement of the domestic substitution process, the demand for optical module solutions based on domestic DSP and other devices is increasing.

[0004] The limitations of existing technologies include at least the following issues: the domestic VCSEL devices that domestic DSPs need to be adapted to typically have lower available modulation bandwidth than imported devices of the same rate level. If domestic DSPs continue to use conventional processing architectures, the main lobe of their high-speed electrical signal spectrum will exceed the linear operating range of domestic VCSELs, leading to modulation distortion and eye diagram closure, making it difficult to meet the system bit error rate requirements. Furthermore, this mismatch between the electrical signal rate and the bandwidth of the optical devices is due to the fact that existing DSP architectures do not consider scenarios where the bandwidth of back-end optical devices is limited, and lack an adaptation mechanism that actively rearranges the signal rate and number of channels within the DSP. This makes it difficult for the signal rate output by domestic DSPs to match the bandwidth capability of domestic VCSELs, directly restricting the collaborative application of domestic DSPs and domestic VCSELs on the QSFP112 platform. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a multi-rate compatible QSFP112 optical transmission system and implementation method based on domestically produced DSPs, solving the problem that existing DSP architectures lack an active rate orchestration mechanism and are difficult to match the bandwidth of domestically produced VCSELs.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution: a multi-rate compatible QSFP112 optical transmission system based on a domestic DSP, comprising: an optical transmission link configuration unit, used by the domestic DSP to receive training sequences sent by the host to estimate the channel quality of the local electrical port receiver and obtain the nominal rate mode of the electrical port, and to select a DSP parameter set from the firmware configuration table to configure the domestic DSP; and a multi-channel optical transmission processing unit, used by the configured domestic DSP to perform equalization and retiming on the input electrical signal from the host within the compact space of the QSFP112 package, then to perform frequency reduction, capacity expansion, and rate remapping, deserialize the input electrical signal and reassemble it into multiple lower modulation rate electrical signals, denoted as second rate electrical signals, and to allocate the multiple second rate electrical signals to multiple VCSEL channels according to a dynamically updated round-robin mapping relationship; The optical signal compensation transmitting unit is used to independently apply digital pre-emphasis compensation, which is inversely proportional to the nonlinear distortion of the corresponding VCSEL channel, to each second-rate electrical signal based on a pre-calibrated nonlinear characteristic mapping table of each VCSEL channel, and modulate it onto the corresponding VCSEL channel to generate an optical signal. The optical transmission link delay compensation unit is used to insert a composite alignment training sequence carrying channel identifiers and delay measurement information into each optical signal, and perform photoelectric conversion at the receiving end to obtain each electrical signal. The channel identifier is extracted to establish a receiving end demapping table, and the delay measurement information is extracted to obtain the delay difference between channels, and coarse-grained delay adjustment is performed. The recovery and splicing unit is used to perform independent clock data recovery on each delayed electrical signal to clear jitter, and perform cross-channel phase alignment on each signal based on one of them. Then, it performs reverse Gearbox splicing according to the receiving end demapping table to restore the output electrical signal.

[0007] Further, the specific steps for configuring the domestic DSP by selecting the DSP parameter set from the firmware configuration table are as follows: The domestic DSP performs amplitude histogram accumulation on the training sequence received from the host side, and obtains the vertical eye opening and channel insertion loss values ​​through the internal eye diagram estimation circuit; the vertical eye opening and channel insertion loss values ​​are comprehensively processed to generate loss level parameters; the corresponding DSP parameter set record is located in the two-dimensional lookup structure of the firmware configuration table using the nominal rate mode of the electrical port as the row index and the loss level parameters as the column index. The DSP parameter set includes the coordinated values ​​of the Gearbox division ratio, the initial coefficient of the electrical port equalizer, and the initial value of the optical side pre-emphasis compensation preload; the DSP parameter set obtained from the lookup table is written to the corresponding register group of the domestic DSP in an atomic configuration transaction.

[0008] Further, the specific steps for deserializing and reassembling the input electrical signal into multiple lower-modulation-rate electrical signals, denoted as the second-rate electrical signal, are as follows: The configured domestic DSP receives the input electrical signal and performs channel equalization on the input electrical signal based on the initial coefficients of the electrical port equalizer, adapting it to the loss level parameters; and performs clock data recovery and retiming on the channel-equalized input electrical signal; the domestic DSP, based on the Gearbox frequency division ratio, deserializes and remaps the channels of the retimed input electrical signal, deserializing and reassembling the input electrical signal into a second-rate electrical signal with a multiplied number of channels and a proportionally reduced single-channel modulation rate.

[0009] Furthermore, the specific steps for allocating multiple second-rate electrical signals to multiple VCSEL channels according to a dynamically updated round-robin mapping relationship are as follows: A full-temperature scan is performed on each VCSEL channel to obtain the photoelectric conversion efficiency, 3dB bandwidth, and linearity indicators of each channel, forming a VCSEL channel performance ranking table; the threshold current drift rate and slope efficiency decay rate of each VCSEL channel are monitored to evaluate the degradation rate differences of each channel; based on the degradation rate differences of each channel and combined with the performance ranking table, the preset round-robin mapping relationship is updated, and the domestic DSP allocates signals according to the updated round-robin mapping relationship; when the round-robin mapping relationship changes, the domestic DSP embeds an orthogonal identifier uniquely corresponding to the allocated VCSEL channel into each second-rate electrical signal.

[0010] Furthermore, the specific steps for applying digital pre-emphasis compensation are as follows: The initial operating point is set to the optical-side pre-emphasis compensation preload value in the DSP parameter set; for each second-rate electrical signal, the PI curve inflection point deviation, frequency response roll-off characteristic, and linearity deviation of the corresponding VCSEL channel are extracted from the nonlinear feature mapping table; a frequency domain inverse function filter is constructed based on the frequency response roll-off characteristic and the initial operating point; an amplitude domain anti-nonlinear pre-distortion lookup table is constructed based on the linearity deviation; and the PI curve inflection point deviation is converted into a DC bias correction amount, together forming a joint compensation model; based on the joint compensation model, each second-rate electrical signal is processed through the frequency domain inverse function filter, the anti-nonlinear pre-distortion lookup table, and the DC bias correction amount to obtain the compensated second-rate electrical signals.

[0011] Furthermore, the specific steps of coarse-grained delay adjustment are as follows: The domestic DSP performs orthogonal decoding on each electrical signal, establishes a receiver demapping table based on the channel identifier obtained from the decoding, and determines the VCSEL channel of the transmitter corresponding to each electrical signal; the domestic DSP extracts the delay measurement information of the composite aligned training sequence in each electrical signal, compares the arrival time differences of the delay measurement information in each electrical signal, obtains the relative delay difference between each channel, and determines the maximum relative delay difference; the domestic DSP compares the maximum relative delay difference with a preset threshold; when the maximum relative delay difference exceeds the preset threshold, the corresponding coarse-grained digital delay compensation amount is applied to each digital signal based on the electrical signal with the earliest arrival time.

[0012] Furthermore, the specific steps for independently restoring clock data for each delayed electrical signal to eliminate jitter are as follows: The domestic DSP identifies the VCSEL channel corresponding to each delayed electrical signal and reads the temperature drift coefficient of the relaxation oscillation frequency calibrated for each VCSEL channel; the domestic DSP extracts the clock reference from each electrical signal and sets the phase tracking response speed for clock data recovery based on the temperature drift coefficient; the domestic DSP tracks the extracted clock reference at the set phase tracking response speed and re-timing samples each electrical signal to obtain the jitter-free electrical signal.

[0013] Further, the specific steps for restoring the output electrical signal are as follows: After the domestic DSP completes the independent clock data recovery for each channel, it selects one of the jitter-free electrical signals as a reference. The domestic DSP measures the time deviation between the remaining channels and the reference reference at the corresponding data symbol transition edge position to obtain the residual phase difference of each channel relative to the reference reference. The domestic DSP inserts a digital delay corresponding to the measured residual phase difference into each signal to align each signal with the reference reference before entering the reverse Gearbox assembly. Based on the receiver's demapping table, the domestic DSP determines the data word position corresponding to each electrical signal during reverse Gearbox assembly and assembles the aligned electrical signals into an output electrical signal according to the demapping table.

[0014] Furthermore, it also includes specific degradation monitoring, with the following specific steps: extracting the threshold current drift rate, slope efficiency decay rate, and PD dark current growth trend of each VCSEL channel as specific degradation characteristic parameters; continuously tracking the temporal changes of specific degradation characteristic parameters in a sliding window manner, and generating compensation control commands when preset compensation constraints are met; adjusting the compensation strategy of the corresponding channel based on the compensation control commands; and using the temporal changes of specific degradation characteristic parameters as the degradation trend of each VCSEL channel to update the rotation mapping relationship.

[0015] The method for implementing multi-rate compatible QSFP112 optical transmission based on domestic DSP includes the following steps: the domestic DSP receives the training sequence sent by the host to estimate the channel quality of the local electrical port receiver and obtains the nominal rate mode of the electrical port. The DSP parameter set is selected from the firmware configuration table to configure the domestic DSP. After configuration, the domestic DSP performs equalization and retiming on the input electrical signal from the host within the compact space of the QSFP112 package. Then, it performs frequency reduction, capacity expansion and rate remapping. The input electrical signal is deserialized and reassembled into multiple lower modulation rate electrical signals, which are denoted as second rate electrical signals. The multiple second rate electrical signals are allocated to multiple VCSEL channels according to the dynamically updated round-robin mapping relationship. Based on a pre-calibrated nonlinear characteristic mapping table for each VCSEL channel, the domestic DSP independently applies digital pre-emphasis compensation, which is inversely proportional to the nonlinear distortion of the corresponding VCSEL channel, to each second-rate electrical signal and modulates it onto the corresponding VCSEL channel to generate optical signals. A composite alignment training sequence carrying channel identifiers and time delay measurement information is inserted into each optical signal. At the receiving end, photoelectric conversion is performed to obtain each electrical signal. The channel identifier is extracted to establish a receiving end demapping table, and the time delay measurement information is extracted to obtain the time delay difference between channels. Coarse-grained time delay adjustment is then performed. Independent clock data recovery is performed on each of the time delay-adjusted electrical signals to eliminate jitter. After cross-channel phase alignment of each signal with one of them as a reference, reverse Gearbox assembly is performed according to the receiving end demapping table to recover the output electrical signal.

[0016] The present invention has the following beneficial effects: (1) The multi-rate compatible QSFP112 optical transmission system based on domestic DSP introduces a Gearbox frequency reduction and capacity expansion mechanism in the multi-channel optical transmission processing unit. By deserializing and reassembling the signal, the original electrical signal with fewer channels but higher single-channel rate is actively arranged into a second-rate electrical signal with doubled channel number but proportionally reduced single-channel rate. This reduces the baud rate of each signal to within the available modulation bandwidth of the domestic VCSEL. Based on the electrical port rate mode and channel quality parameters obtained during the link establishment phase, the corresponding Gearbox frequency division ratio is found from the firmware configuration table to achieve adaptation under different electrical port rate conditions. This makes the signal rate output by the DSP no longer passively follow the electrical port setting, but actively match the actual bandwidth capability of the back-end domestic VCSEL, thus solving the rate mismatch problem. Moreover, the reduction of single-channel rate directly reduces the power consumption of the corresponding driving circuit. The increase in the number of channels is exchanged for the reduction in single-channel power consumption. Thermal control under the condition of constant total throughput is achieved within the compact QSFP112 package space.

[0017] (2) This multi-rate compatible QSFP112 optical transmission system based on domestic DSP obtains photoelectric conversion efficiency, bandwidth and linearity indicators by performing full-temperature scanning on each VCSEL channel and establishes a performance ranking table as a reference benchmark for initial rotation mapping. During operation, it continuously monitors degradation characteristic parameters such as threshold current drift rate and slope efficiency attenuation rate of each channel and dynamically adjusts the rotation mapping relationship based on the degradation rate difference, so that each signal evenly shares the channels with different degradation levels throughout the entire life cycle, avoiding a certain signal from occupying the fast degradation channel for a long time and failing prematurely. When the channel degradation triggers the preset condition, a compensation control command is generated and the corresponding channel is adjusted. The compensated degradation trend is fed back to the rotation mapping link, forming a complete closed loop from monitoring, compensation to scheduling adjustment, which extends the overall usable life of the module.

[0018] (3) The multi-rate compatible QSFP112 optical transmission system based on domestic DSP periodically inserts a composite alignment training sequence carrying channel identifiers and time delay measurement information into each optical signal at the transmitter. After the receiver completes photoelectric conversion, the DSP extracts the channel identifier by performing orthogonal decoding on the sequence, establishes the correspondence between each electrical signal and the VCSEL channel of the transmitter, and obtains the relative time delay difference between channels by comparing the arrival time difference of the time delay measurement information in each signal. When the maximum time delay difference exceeds the preset threshold, the corresponding coarse-grained digital delay compensation is applied to the other channels based on the channel with the earliest arrival time, so that the remaining time delay difference falls within the processing range of the subsequent fine alignment circuit. Thus, the time delay measurement, channel identification and coarse-grained compensation are integrated into the same sequence. The receiver can obtain the time delay information and perform compensation at the same time as decoding the channel identifier, providing an accurate timing basis for independent clock recovery and cross-channel phase alignment, and ensuring that multiple signals can be accurately recovered into the original electrical signal when the reverse Gearbox is assembled.

[0019] (4) The multi-rate compatible QSFP112 optical transmission implementation method based on domestic DSP obtains the electrical port channel quality and rate mode by receiving the training sequence sent by the host during the link establishment stage. Based on this, the corresponding DSP parameter set is selected from the firmware configuration table to complete the initial configuration, so that the parameters of each link are matched with the current channel conditions and rate mode. After entering the transmission stage, the allocation is carried out according to the dynamically updated round-robin mapping relationship, and a composite alignment training sequence is embedded in each optical signal. This enables the receiver to complete the channel identification and delay measurement synchronously after completing the photoelectric conversion, thereby transmitting the channel mapping status of the transmitter to the receiver in real time. The receiver performs reverse Gearbox assembly according to the decoded demapping table, ensuring that the multiple signals under dynamic round-robin conditions can still be accurately restored to the original output electrical signal, thus ensuring the collaborative effect of domestic DSP and domestic VCSEL under dynamic working conditions.

[0020] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0021] Figure 1 This is a block diagram of the multi-rate compatible QSFP112 optical transmission system based on a domestically produced DSP, according to the present invention.

[0022] Figure 2 This is a flowchart illustrating the specific steps involved in configuring the domestic DSP by selecting a DSP parameter set from the firmware configuration table in the multi-rate compatible QSFP112 optical transmission system based on a domestically produced DSP, as described in this invention.

[0023] Figure 3 This is a flowchart of the multi-rate compatible QSFP112 optical transmission implementation method based on domestic DSP of the present invention. Detailed Implementation

[0024] Please see Figure 1 This invention provides a technical solution: a multi-rate compatible QSFP112 optical transmission system based on a domestically produced DSP, comprising: The optical transmission link configuration unit is used to estimate the channel quality of the local electrical interface receiver by receiving the training sequence sent by the domestic DSP receiver host, and to obtain the nominal rate mode of the electrical interface, and to select the DSP parameter set from the firmware configuration table to configure the domestic DSP. The multi-channel optical emission processing unit is used by the configured domestic DSP in the compact space of QSFP112 package to equalize and retime the input electrical signal from the host, then perform frequency reduction, capacity expansion and rate remapping, deserialize the input electrical signal and reassemble it into multiple PAM4 electrical signals with lower modulation rate, denoted as the second rate PAM4 electrical signal, and distribute the multiple second rate PAM4 electrical signals to multiple (domestic) VCSEL channels according to the dynamically updated round-robin mapping relationship. The optical signal compensation transmitting unit is used to independently apply digital pre-emphasis compensation, which is inversely proportional to the nonlinear distortion of the corresponding VCSEL channel, to each second-rate PAM4 electrical signal based on a pre-calibrated nonlinear characteristic mapping table of each VCSEL channel, and modulate it onto the corresponding VCSEL channel to generate an optical signal. The optical transmission link delay compensation unit is used to insert a composite alignment training sequence carrying channel identifier and delay measurement information into each optical signal, and perform photoelectric conversion at the receiving end to obtain each electrical signal, extract the channel identifier to establish the receiving end demapping table, extract the delay measurement information to obtain the delay difference between channels, and perform coarse-grained delay adjustment. The recovery and splicing unit is used to independently recover the clock data of each electrical signal after the time delay adjustment to eliminate jitter. After aligning the phase of each channel with one of them as a reference, it performs reverse Gearbox splicing according to the receiver's demapping table to restore the output electrical signal.

[0025] Specifically, such as Figure 2 As shown, the specific steps for configuring a domestic DSP by selecting the DSP parameter set from the firmware configuration table are as follows: The domestically produced DSP performs amplitude histogram accumulation on the training sequence received from the host side, and obtains the vertical eye opening and channel insertion loss values ​​(at the local electrical interface receiver) through an internal eye diagram estimation circuit. Specifically: The domestic DSP integrates an eye diagram estimation circuit. This circuit does not directly draw a complete eye diagram. Instead, it performs high-speed sampling of the received composite alignment training sequence from the host side, accumulates and statistically analyzes the amplitude values ​​of the sampling points according to their time positions, and forms an amplitude histogram. It should be noted that in the early stage of link establishment, the optical path has not yet been activated. At this time, the composite alignment training sequence is sent by the host and is mainly used for electrical interface channel quality assessment. Its channel identification field and delay measurement field do not carry valid information. By analyzing the sample distribution density of different amplitude intervals in the histogram, the vertical opening of the eye diagram is calculated, which is the minimum distance between the signal "1" and "0" level distributions in the central region of the eye diagram. Meanwhile, the nominal power of the composite alignment training sequence transmitted by the host side through internal storage is compared with the average power calculated after analog-to-digital conversion of the received signal to calculate the channel attenuation value, and this attenuation value is used as an approximation of the channel insertion loss. A larger vertical eye opening and a smaller insertion loss indicate better current electrical channel quality. After optical path activation, the composite alignment training sequence periodically generated and inserted by the transmitter DSP uses the same sequence format. Its channel identification field and delay measurement field carry valid information. The receiver can use the same sequence format to complete three functions: channel quality tracking, channel mapping identification, and inter-channel delay measurement. The vertical eye diagram opening and channel insertion loss values ​​are combined to generate (link quality) loss level parameters, specifically: After the main control unit inside the domestic DSP obtains the calculated vertical eye diagram opening and channel insertion loss values, it maps these two parameters into a discrete loss level. In one implementation, the firmware two-dimensional configuration lookup table stored in the domestic DSP firmware has a preset two-dimensional loss level partitioning rule: if the insertion loss is less than or equal to 5dB and the eye opening is greater than or equal to 150mV, it is defined as "low loss level" with a corresponding loss level parameter value of 1. If the insertion loss is greater than or equal to 10dB, or the eye opening is less than or equal to 100mV, it is defined as "high loss level" with a corresponding loss level parameter value of 3. All other parameter combinations that do not fall into the above two categories are defined as "medium loss level", with a corresponding loss level parameter value of 2; Critical classification rule supplement: an eye opening of 100mV is classified as high loss; an eye opening of 150mV and an insertion loss of 5dB are classified as low loss. When a single parameter falls on the boundary and another parameter crosses the interval, the high-loss judgment rule is prioritized. Using the nominal rate mode of the electrical port as the row index and the loss level parameter as the column index, the corresponding DSP parameter set record is located in the two-dimensional lookup structure of the firmware configuration table. The DSP parameter set record pre-calibrates the coordinated values ​​of the Gearbox division ratio, the initial coefficient of the electrical port equalizer, and the initial value of the optical side pre-emphasis compensation preload for different combinations of rate modes and different link loss levels. Specifically: The firmware of the main control unit inside the domestic DSP stores a firmware two-dimensional configuration lookup table. The rows of the table correspond to different nominal electrical port rate modes such as "400G mode" and "200G mode", and the columns correspond to different loss levels such as "low loss", "medium loss" and "high loss" as currently evaluated. Each cell stores a set of DSP parameters that are calibrated together. In one implementation, in the cell [400G mode, medium loss level], the stored DSP parameter set is as follows: the Gearbox division ratio is set to 4:8, the initial coefficients of the electrical equalizer are a set of CTLE gain values ​​and FFE tap weights pre-trained for 10dB channel loss, and the initial value of the optical side pre-emphasis compensation preload is a moderate frequency compensation gain. Specifically, the initial value of the optical-side pre-emphasis compensation preload is pre-calibrated to be complementary to the high-frequency attenuation characteristics of the electrical interface channel under the corresponding loss level. This ensures that the optical-side pre-emphasis pre-compensates for the superposition effect of residual distortion of the electrical interface channel and VCSEL nonlinearity in the open-loop state. During the factory calibration phase, for each loss level, the optimal initial value of the optical-side pre-emphasis compensation preload is found through traversal testing. The calibration principle for this initial value is that its frequency response curve is complementary to the high-frequency attenuation curve of the electrical port channel under the corresponding loss level in the frequency domain, and the superposition of the two tends to result in a flat amplitude-frequency response. In one implementation, for the "medium loss level," the channel attenuation at 15 GHz is approximately 6 dB, and the corresponding initial value of the optical-side pre-emphasis compensation preload provides a gain boost of approximately 6 dB at 15 GHz. Thus, when the DSP parameter set is loaded, the optical-side digital pre-emphasis compensation path can compensate for most of the high-frequency signal attenuation remaining after power-down equalization, even in an open-loop state without real-time feedback. The DSP parameter set obtained from the lookup table is written to the corresponding register group of the domestic DSP in an atomic configuration transaction manner. This ensures that the Gearbox frequency division link, the electrical port signal equalization path, and the optical pre-emphasis path complete parameter updates within the same configuration cycle, avoiding instantaneous link lock-up or sudden bit error caused by step-by-step configuration. This supports fast adaptive parameter loading based on real-time channel conditions in multi-rate modes. Specifically: The main control unit inside the domestic DSP packages a complete set of DSP parameter data through the internal bus and generates a single "atomic write" instruction. After receiving this instruction, the configuration management module inside the domestic DSP will first temporarily store all new parameters in the shadow register; Upon receiving the "update effective" trigger signal, the new parameter values ​​in all shadow registers will be synchronously and atomically updated to the Gearbox configuration register, CTLE / FFE equalizer parameter register, and optical-side digital pre-emphasis FIR filter coefficient register within the same clock cycle. The domestic DSP uses multiple parallel configuration buses to separate the address fields of Gearbox, equalizer, and pre-emphasis register, and writes them to the shadow register in parallel, refreshing all parameters synchronously in a single clock cycle. Furthermore, atomic configuration transactions and VCSEL round-robin mapping updates are isolated using bidirectional mutex locks: round-robin mapping updates are prohibited from starting until the atomic configuration transaction has completely ended; during the execution of round-robin mapping updates, all atomic configuration transaction requests are blocked; the round-robin mapping update operation can only be executed after the atomic configuration has completed the synchronization update of all path parameters; the round-robin mapping update only modifies the non-linear feature index corresponding to each channel and does not cover the global parameter set of Gearbox and electrical port equalizer. The bidirectional mutex lock is set with a 1.5μs timeout threshold. When the timeout threshold is reached, the lock is automatically released and a local configuration anomaly alarm is reported to prevent hardware logic deadlock. In one implementation, the entire atomic configuration transaction takes no more than 1 microsecond to complete. During this period, the link experiences only one brief and predictable momentary interruption, and the receiver's CDR can be quickly relocked, thereby effectively preventing the link from losing its lock for a long time or generating sudden bit errors due to the time difference of step-by-step configuration.

[0026] The specific steps for deserializing the input electrical signal and reassembling it into a multi-channel PAM4 electrical signal with a lower modulation rate, denoted as the second-rate PAM4 electrical signal, are as follows: The configured domestic DSP receives the input electrical signal and performs channel equalization on the input electrical signal based on the initial coefficients of the electrical port equalizer, adapting it to the loss level parameters. Specifically: The configured domestic DSP internal CTLE and FFE equalizers load and apply the initial coefficients of the electrical equalizer obtained from step 2. CTLE provides a frequency-related gain to compensate for the skin effect loss of the channel; FFE performs finite impulse response filtering on the signal through multiple taps to eliminate inter-symbol interference. In one implementation, for the "medium loss level," the DC gain of the CTLE is set to 0 dB, increasing to 6 dB at 12 GHz; the FFE is configured as a 3-tap filter with a pre-index tap factor of -0.15, a main tap factor of 0.85, and a post-index tap factor of -0.05. These initial factors are optimized for the currently assessed loss level, enabling rapid initial opening of the eye diagram, which is severely distorted due to transmission link attenuation. And perform clock data recovery and retiming on the input electrical signal after channel equalization, specifically as follows: The equalized signal enters the CDR circuit. The CDR circuit extracts the implicit clock signal from the signal's transition edge, and then uses this recovered clock to perform precise retiming sampling of the data signal. In one implementation, the CDR employs a dual-loop structure based on a phase interpolator, wherein the frequency-locked loop is used to capture the frequency, and the phase-locked loop is used to finely track the phase. The signal jitter after retiming is controlled within 1psRMS, and a high-speed electrical signal with regular timing is output. The domestically produced DSP, based on the Gearbox frequency division ratio, performs deserialization and channel remapping on the retiming input electrical signal. It deserializes and reassembles the input electrical signal into a second-rate PAM4 electrical signal with a multiplied number of channels and a proportionally reduced single-channel modulation rate. Specifically: The Gearbox inside the domestic DSP operates according to the Gearbox frequency division ratio obtained by looking up the table. It deserializes the high-speed serial data stream after retiming to obtain the internal parallel data bus. The digital logic circuit inside the Gearbox rearranges and distributes the deserialized data bits according to the new mapping rules, and finally combines them into multiple independent parallel data streams with reduced rates, namely second-rate PAM4 electrical signals. In one implementation, for example, when the Gearbox frequency division ratio is 4:8, the four input 100GPAM4 signals (each with a baud rate of 53.125 GBaud) can be deserialized and reassembled into eight 50GPAM4 signals, with the baud rate of each signal reduced to 26.5625 GBaud. It should be noted that the value of the Gearbox division ratio reduces the fundamental frequency of the second-rate PAM4 electrical signal to within the available modulation bandwidth of the optical transmission channel. Thus, under the bandwidth-constrained condition of the optical transmission channel, the optical transmission channel operates in the linear modulation region by actively reducing the single-channel rate. Specifically: The Nyquist frequency of a single-channel 100GPAM4 signal is approximately 26.56 GHz, which is close to the 3 dB bandwidth of a typical domestic VCSEL of approximately 28 GHz. The high-frequency components of the signal are significantly attenuated, resulting in insufficient eye diagram margin and difficulty in meeting the system bit error rate requirements. By looking up a table to select an appropriate Gearbox division ratio, the single-channel signal rate can be reduced to an even lower level, and its Nyquist frequency will decrease accordingly. In one implementation, for example, when using a 4:8 frequency division ratio, the single-channel 100GPAM4 signal rate can be reduced to 50GPAM4, and its Nyquist frequency is reduced to about 13.28GHz. At this time, the 3dB bandwidth of a domestic VCSEL is 28GHz, and its response attenuation at 13.28GHz is only 1.5dB, which is far better than the situation at 26.56GHz. This provides sufficient bandwidth margin, avoids the serious inter-symbol interference introduced by the VCSEL channel bandwidth limitation, and ensures the signal quality of each VCSEL channel. The reduction in single-channel rate simultaneously decreases the transient power consumption of the corresponding channel, offsetting the additional heat dissipation introduced by the increase in the number of channels. This achieves controllable power consumption and heat dissipation while maintaining the same total throughput within the compact space of the QSFP112 package. Specifically: For VCSEL drive circuits, power consumption is proportional to modulation rate. Reducing the modulation rate from 100GPAM4 to 50GPAM4 almost halves the power consumption of a single-channel drive circuit. It should be noted that the drive power consumption is not ideally halved linearly. Under 50GPAM4, the DC bias power consumption of the VCSEL still needs to be maintained, so the single-channel power consumption has not been reduced to 60mW. In one implementation, the measured power consumption of a single-channel 100GPAM4 driver circuit at room temperature of 25°C is about 120mW. After the speed is reduced to 50GPAM4, the measured power consumption at room temperature of 25°C is reduced to about 70mW. The number of channels doubled from 4 to 8, but the total power consumption of 8 channels was 8 × 70mW = 560mW. Compared with the solution of using 4 channels to directly drive 100GPAM4 signals to achieve the same total throughput, the total power consumption was 4 × 120mW = 480mW, which only increased by about 16.7%. The power consumption did not increase proportionally with the number of channels. Under high-temperature conditions, the DSP synchronously fine-tunes the drive bias current to maintain the total power consumption fluctuation range of ≤±5%. This change in power consumption structure allows for control of total heat dissipation within the compact physical space of the QSFP112, preventing excessive local hot spots from affecting the stability and lifespan of the module.

[0027] Specifically, the steps for allocating multiple second-rate PAM4 electrical signals to multiple VCSEL channels according to a dynamically updated round-robin mapping relationship are as follows: A full-temperature scan was performed on each VCSEL channel to obtain the photoelectric conversion efficiency, 3dB bandwidth, and linearity of each channel, forming a VCSEL channel performance ranking table as the basis for the initial round-robin mapping. Specifically: On the automated test bench before the module leaves the factory, the eight VCSEL channels in the module are scanned for a full temperature range from 0°C to 70°C. At each temperature point, the relationship between the output optical power and the input current of each channel is measured by sending a known test signal, thereby calculating the photoelectric conversion efficiency; at the same time, its small signal frequency response curve is measured to obtain the 3dB bandwidth. The linearity index is quantified by analyzing the slope changes of the PI curve at various points. In one implementation, a weighted scoring method is used to rank the performance of the eight channels: photoelectric conversion efficiency accounts for 40%, 3dB bandwidth accounts for 35%, and linearity index accounts for 25%. After comprehensive scoring, a permanent "VCSEL channel performance ranking table" is generated and stored in the non-volatile memory of the main control unit inside the domestic DSP. When the module is powered on for the first time, the DSP will establish a default rotation mapping relationship based on this table, prioritizing the use of the channel with the best performance. The threshold current drift rate and slope efficiency decay rate of each VCSEL channel were monitored to evaluate the differences in degradation rate among the channels. Specifically: During module operation, the main control unit inside the domestic DSP will periodically trigger a monitoring of the degradation parameters of each VCSEL channel; By observing the small changes in output optical power under the same bias current, or the small increase in bias current while maintaining constant optical power, the two key degradation indicators, threshold current drift rate and slope efficiency attenuation rate, can be indirectly calculated. In one implementation, the monitoring cycle is set to once every 24 hours. The main control unit records the change in bias current for each channel. When the bias current of a certain channel increases by 1.5mA after 1000 hours of operation, while the average increase of other channels is only 0.5mA, it is determined that the threshold current drift rate of that channel is 1.5mA / thousand hours, and the degradation rate is significantly faster than that of other channels. Based on the degradation rate differences of each channel and combined with the performance ranking table, the preset rotation mapping relationship is updated. The domestic DSP then allocates signals according to the updated rotation mapping relationship, specifically as follows: The built-in rotation management algorithm of the main control unit of the domestic DSP comprehensively evaluates the initial performance and degradation rate of each channel. The algorithm aims to achieve signal quality balance throughout the entire life cycle. In one implementation, the algorithm directly uses the real-time health score of each channel as its rotation weight. The formula for calculating the real-time health score is: Real-time health score = Overall performance score × (1 - Normalized degradation rate) - Deep degradation penalty score; Among them, the overall factory performance score is the overall score in the VCSEL channel performance ranking table; the normalized degradation rate is calculated as follows: collect the maximum and minimum current degradation rates of all 8 VCSEL channels, and the normalized degradation rate r of a single channel = (current channel degradation rate) / (current channel degradation rate). (maximum value) / (maximum value) Minimum value), with a range of 0 ≤ r ≤ 1, and all r = 0 when there is no channel degradation; When a deep degradation channel is marked, its penalty is 0.4; otherwise, it is 0. The score range is 0 to 1. If the real-time health score calculated by the formula is less than 0, it is forcibly truncated to 0. If the calculation result is greater than 1, it is forcibly truncated to 1 to ensure that the score always falls within the valid range of 0 to 1. The higher the score of a channel, the higher its rotation weight and the longer its time slice in the rotation sequence. Channels with good initial performance and slow degradation naturally receive high weights, while channels marked as deeply degraded will have their weights significantly reduced due to penalty points, thus achieving the goal of reducing their occupied time. The rotation mapping table is updated according to the final determined rotation weights, and the new mapping instructions are sent to the signal allocation logic of the domestic DSP. The digital cross switch inside the DSP immediately allocates signals according to the updated mapping relationship, and the signal allocation can be completed in nanoseconds. Rotational allocation with additional thermal balance constraints: High-weight channels are not allowed to be continuously occupied for three consecutive rotational cycles. Low-degradation or low-temperature channels are automatically interspersed to share the heat load, avoiding the accumulation of local hot spots in the VCSEL array. In one implementation, the base duration of a single rotation cycle is 120 seconds, and the same high-weight channel is prohibited from working continuously for three consecutive cycles, or 360 consecutive seconds. When the rotation mapping relationship changes, the domestic DSP embeds an orthogonal identifier code, uniquely corresponding to the assigned VCSEL channel, into each second-rate PAM4 electrical signal. The orthogonal identifier code corresponds one-to-one with the channel number in the VCSEL channel performance ranking table. The receiving end obtains the current rotation mapping relationship by decoding the orthogonal identifier code. Specifically: After each rotation mapping relationship is updated, the domestic DSP will not immediately insert a new identifier into the data stream. Instead, it will wait for the current composite alignment training sequence frame period to end, and in the next frame of the composite alignment training sequence to be sent, it will replace the orthogonal identifier code field inside it with a new codeword corresponding to the newly allocated VCSEL channel. In one implementation, the VCSEL channel number 1 is identified by the Gold sequence 1; the channel number 2 is identified by the Gold sequence 2 which is orthogonal to it, and so on, strictly corresponding to the channel number at the factory. Each of the eight Gold sequences has a code length of 127 bits and a chip rate of 1 Gbps. The composite alignment training sequence is continuously transmitted at a fixed period. In one implementation, the frame period of the composite alignment training sequence is 128 UI. The receiver decodes each frame sequence and immediately updates the receiver's demapping table based on the new identifier code after detecting a change in the orthogonal identifier code to obtain the current channel mapping relationship. It should be noted that when the nominal speed mode of the electrical port is in reduced speed mode, the domestic DSP only activates the Gearbox output channels corresponding to the number of channels required after speed reduction, and statically selects the corresponding number of channels with the best performance from multiple domestic VCSEL channels according to the performance ranking table to carry the effective signal. The remaining channels are placed in standby mode. Specifically: When the main control unit inside the domestic DSP recognizes that the host sends a rate negotiation command through the high-speed electrical port link and the negotiation result is 200G mode, including three trigger scenarios: power-on initialization negotiation, link real-time rate switching, and host port reconfiguration, the Gearbox only needs to provide 4 channels of 50GPAM4 signal output. At this time, the DSP shuts down the other 4 outputs. At the same time, a comprehensive evaluation of the current real-time health score of each channel is conducted. This score is continuously updated through subsequent degradation monitoring, reflecting the complete performance evolution of each channel from the factory to the present. The four channels with the highest real-time health scores out of the eight channels are selected as working channels, and the signals are allocated to them, rather than simply based on the performance ranking at the factory. In one implementation, although channels 1 and 2 were ordered earlier at the factory, they have degraded severely due to long-term operation in high-temperature environments, and their current real-time health scores have dropped to 0.6 and 0.55, respectively. Channels 6 and 7, having been in standby mode for an extended period due to the reduced speed, have experienced only minor degradation, with their current real-time health scores remaining at 0.9 and 0.85, respectively. At this point, the system will select channels 6, 7, 3, and 5 with the highest real-time health scores to carry valid signals. This dynamic selection method based on real-time health scores ensures that the module always uses the optoelectronic device with the best current physical state when switching any working mode.

[0028] Specifically, the steps for applying digital pre-emphasis compensation are as follows: The initial operating point is set to the initial value of the optical pre-emphasis compensation preload in the DSP parameter set, specifically as follows: After completing the parameter configuration, the optical-side digital pre-emphasis module of the DSP loads and applies the initial values ​​of the optical-side pre-emphasis compensation obtained from the above steps. This set of initial values ​​constitutes a basic optical-side digital pre-emphasis FIR filter. In one implementation, the preloaded initial value corresponding to the "medium loss level" is a 3-tap FIR filter with tap coefficients of [-0.12, 1.0, -0.08], which provides a gain boost of about 6dB at 15GHz. This set of initial values ​​provides a starting point that is basically matched with the current channel characteristics for subsequent fine compensation. For each second-rate PAM4 electrical signal, the inflection point deviation, frequency response roll-off characteristic, and linearity deviation of the corresponding VCSEL channel are extracted from the nonlinear characteristic mapping table. Specifically: After each second-rate PAM4 electrical signal is assigned to a specific physical VCSEL channel, the optical-side digital pre-emphasis module of the domestic DSP will retrieve the record corresponding to the physical channel from the "VCSEL nonlinear feature mapping table" in the internal main control unit memory according to the current rotation mapping relationship. The VCSEL nonlinear characteristic mapping table stores the PI curve inflection point deviation, frequency response roll-off characteristics, linearity deviation, and CDR loop bandwidth parameters that match the channel noise characteristics for each VCSEL channel. The CDR loop bandwidth parameter is used for receiver clock recovery and is not called in the transmitter pre-emphasis processing. In one implementation, the mapping table of VCSEL channel 3 records: PI curve inflection point deviation of +0.3mA (i.e., threshold current is 0.3mA higher than nominal value), frequency response roll-off characteristic of an additional 2.5dB attenuation at 20GHz, and linearity deviation of 3% gain compression at the midpoint of rated operating current. A frequency domain inverse function filter is constructed based on the frequency response roll-off characteristics and the initial operating point. An amplitude domain inverse nonlinear predistortion lookup table is constructed based on the linearity deviation. The inflection point deviation of the PI curve is converted into a DC bias correction. Together, these constitute a joint compensation model for comprehensively inverting the nonlinear distortion of the VCSEL channel. Specifically: Based on the obtained frequency response roll-off characteristics, linearity deviation, and PI curve inflection point deviation of the VCSEL channel, a joint compensation model for the channel is constructed. In one implementation, the core of the joint compensation model is a digital predistortion engine, which adopts a memory polynomial model structure and includes a first-order linear fundamental term, a second-order nonlinear distortion compensation term, and a DC bias correction term. The steps for determining the coefficients of each term are as follows: Read the frequency response roll-off characteristic curve of the channel from the VCSEL nonlinear characteristic map table. The curve records the gain attenuation of the VCSEL at different frequencies. The target equalization curve is obtained by inverting the frequency response roll-off characteristic curve over the entire modulation frequency range. The least squares fitting algorithm is used to fit the target equalization curve into a 3-tap FIR filter. The tap coefficients are the linear term coefficients of the memory polynomial model. These linear term coefficients minimize the error between the amplitude frequency response of the FIR filter and H_inv(f) within the 3dB bandwidth of the VCSEL, thereby pre-compensating for the high-frequency roll-off of the VCSEL. Read the linearity deviation curve of the channel from the VCSEL nonlinear characteristic map table. The curve records the percentage deviation of the VCSEL output optical power from the ideal linear response under different drive currents. Invert the deviation curve to obtain the target predistortion curve, that is, the opposite nonlinear predistortion variable that needs to be applied for each input signal amplitude. A polynomial fitting algorithm is used to fit the target pre-distortion curve into a second-order polynomial function. The coefficients of the first and second terms are the nonlinear coefficients of the memory polynomial model. This second-order polynomial function enables the output optical power to recover the linear relationship with the input signal amplitude after the pre-distorted driving signal passes through the nonlinear PI characteristics of VCSEL. Read the inflection point deviation value of the PI curve of the channel from the VCSEL nonlinear feature mapping table, that is, the difference between the measured threshold current and the nominal threshold current. Convert the inflection point deviation value into the corresponding drive voltage compensation amount. This conversion is performed by the transconductance gain of the drive circuit of the channel measured during factory calibration: drive voltage compensation amount = inflection point deviation value / drive circuit transconductance gain. The drive voltage compensation amount is the DC bias correction term of the memory polynomial model. The above-mentioned linear term coefficients, nonlinear term coefficients, and DC bias correction term together constitute a comprehensive inversion model for the nonlinear distortion of the VCSEL channel; Based on the joint compensation model, the second-rate PAM4 electrical signals of each channel are processed through a frequency domain inverse function filter, an inverse nonlinear pre-distortion lookup table, and a DC bias correction to obtain the compensated second-rate PAM4 electrical signals of each channel, specifically as follows: When the 50GPAM4 electrical signal flows through the optical side digital pre-emphasis, the high-frequency components of the signal are specifically enhanced as it passes through the linear equalization section of the digital predistortion engine to pre-compensate for the high-frequency roll-off of the VCSEL. The signal passes through a nonlinear predistortion section, and its amplitude value is mapped point by point according to the nonlinear term of the memory polynomial model; In one implementation, a PAM4 level signal point that should generate 10mW optical power is pre-adjusted to an amplitude of 9.7mW optical power corresponding to the driving voltage after model calculation, in order to counteract the gain compression of VCSEL in this region. Before converting the signal into an analog voltage, a DC bias correction amount derived from the inflection point deviation of the PI curve is superimposed. The electrical signal processed by the joint compensation model already carries a "pre-distortion" that is exactly the opposite of the physical defects of the target VCSEL. When this signal drives the VCSEL, the two opposite distortions cancel each other out, ultimately producing a high-quality optical signal. It should be noted that the nonlinear characteristic mapping table is obtained at the factory by performing a full-temperature scan on each VCSEL channel, recording the PI curve inflection point deviation, small-signal frequency response roll-off characteristics, and linearity deviation of each VCSEL. Specifically: The data source for this mapping table is the automated calibration process before the module leaves the factory. This process controls the module temperature to go through 0℃, 25℃, and 70℃. After each temperature stabilizes, a high-precision source table scans each VCSEL channel. By sending a DC scanning signal, the PI curve is recorded and the inflection point deviation and linearity deviation are calculated; by sending a small signal sweep frequency signal and measuring the optical power, the response amplitude at different frequencies is recorded, thereby obtaining the frequency response roll-off characteristics; by measuring the relative intensity noise under different bias currents, the relative intensity noise of the transmitting VCSEL, the receiving TIA noise, and the total PCB transmission jitter are combined to jointly configure the CDR loop bandwidth parameters. The clock data recovery loop bandwidth parameter is used for subsequent adaptive clock recovery at the receiver and is not used in the optical-side digital pre-emphasis processing at the transmitter. When the actual operating temperature of the module changes continuously, the DSP's built-in linear interpolation algorithm retrieves the VCSEL characteristic parameters of two adjacent calibration temperature points and calculates the PI, frequency response, and linearity compensation parameters corresponding to the current temperature through linear interpolation of the temperature difference. When the module's operating temperature is below 0℃, the 0℃ calibration parameters are used uniformly; when it is above 70℃, the 70℃ calibration parameters are used uniformly. Temperature linear interpolation calculation is only enabled within the 0℃~70℃ range to ensure that accurate nonlinear compensation parameters can be obtained at any operating temperature. In one implementation, the scan current ranges from 0mA to 10mA with a step size of 0.1mA; the sweep frequency ranges from 1GHz to 35GHz with a step size of 0.5GHz. All data is stored in a structured manner in the flash memory of the main control unit inside the domestic DSP, indexed by channel number and temperature.

[0029] Specifically, the steps for coarse-grained delay adjustment are as follows: The domestically produced DSP performs orthogonal decoding on the orthogonal identifier code in each electrical signal, establishes a receiver demapping table based on the decoded channel identifier, and determines the corresponding transmitter VCSEL channel for each electrical signal. Specifically: At the receiving end, the eight electrical signals after photoelectric conversion are first sampled by their respective ADCs and converted into digital signals. The digital logic inside the DSP performs orthogonal decoding operations independently for each digital signal. For each signal, the DSP performs sliding correlation operations within a preset maximum time delay search window. In one implementation, the sliding correlation window length is uniformly set to 120ps to cover the maximum 80ps relative time delay difference between channels in this module. The received code sequence is correlated with 8 mutually orthogonal Gold sequence templates stored locally. For each signal, the channel identifier carried by the signal is determined by the correlation peak with the template that is highest and exceeds a preset threshold. In one implementation, a preset correlation peak threshold of 0.7 is set. If the correlation peak value is below 0.7, the frame is determined to have no valid orthogonal identifier code, and the current frame is discarded while waiting for the next frame of the composite alignment training sequence to be decoded again. This process is independent of the absolute arrival time of each signal, so channel identification can be completed before delay adjustment. In one implementation, the correlation peak value between the receiver physical channel 1 and the Gold sequence 5 is 0.92, which is much higher than the correlation peak values ​​of the other 7 templates (all below 0.15). Therefore, it is determined that the signal comes from the VCSEL channel 5 on the transmitting side of this module. After all 8 signals are decoded, the DSP can establish a "receiver demapping table". This table clearly records the correspondence between "receiver physical channel 1 and VCSEL channel 5 on the transmitting side of this module". The domestically produced DSP extracts the time delay measurement information of the composite aligned training sequence from each electrical signal, compares the arrival time differences of the time delay measurement information in each electrical signal, obtains the relative time delay difference between each signal, and determines the maximum relative time delay difference, specifically as follows: The time delay measurement field in the composite aligned training sequence is a known sequence with sharp autocorrelation characteristics. The receiving DSP uses a locally generated, identical code pattern to perform sliding correlation operation on each received digital signal. The time when the correlation peak appears is defined as the precise arrival time of that signal. In one implementation, the delay measurement field uses a 127-bit Barker code. The receiving DSP performs sliding correlation with an accuracy of 1 / 64 UI. By comparing the arrival times of eight different channels, the relative delay difference between each pair of channels is calculated, and the maximum value is found. For example, if the third channel arrives earliest and the seventh channel arrives latest, and the difference between them is 80 ps, ​​then the "maximum relative delay difference" is 80 ps. It should be noted that the relative delay difference between channels refers to the original time difference between the arrival of each signal at the receiving ADC; the maximum relative delay difference is the extreme value of the relative delay difference between all channels; the residual phase difference is the sub-picosecond timing deviation between the clocks of each CDR after coarse-grained delay compensation. The domestically produced DSP compares the maximum relative delay difference with a preset threshold, specifically as follows: The main control unit of the domestic DSP has a preset threshold. This threshold is set based on the statistical results of the measured inter-channel delay dispersion of the domestic VCSEL array and TIA, and in combination with the processing capability range of the subsequent digital domain fine alignment circuit. In one implementation, the preset threshold is 50 ps. This value is determined based on the measured skew distribution of a batch of domestically produced VCSEL arrays (average 25 ps, maximum approximately 80 ps) and the maximum compensation capability of the digital domain fine alignment circuit (approximately ±10 ps). The DSP compares the maximum relative delay difference (80 ps) calculated in the previous step with this preset threshold (50 ps). When the maximum relative time delay difference exceeds a preset threshold, the earliest arriving electrical signal is used as a reference, and corresponding coarse-grained digital delay compensation is applied to each digital signal to ensure that the remaining time delay difference between the signals falls within the processable range of subsequent fine alignment in the digital domain. Specifically: If the comparison result exceeds the threshold, the coarse-grained compensation process is initiated, taking the earliest arriving digital signal as the time reference, and calculating the delay value of each other digital signal relative to the reference. In one implementation, the 7th channel is 80 ps behind the reference. The DSP controls a 5-bit programmable digital delay line on that channel's signal path to apply a coarse-grained digital delay of 80 ps. All other channels are processed in the same way, and the eight digital signals are coarsely aligned in time, with the remaining delay difference between them controlled within 5 ps. When the maximum relative time delay difference does not exceed the preset threshold, no coarse-grained compensation is performed, and the process is directly handed over to the subsequent fine-grained alignment and unification in the digital domain. Specifically: If the maximum relative delay difference is 30ps, which is less than the 50ps threshold, it indicates that the inter-channel skew of the current link is within an acceptable range. The DSP does not perform any coarse-grained delay processing on the signals; each digital signal directly enters the subsequent fine-grained digital domain alignment process.

[0030] Specifically, the steps for independently restoring the clock data of each delayed electrical signal to eliminate jitter are as follows: The domestically produced DSP identifies the VCSEL channels corresponding to each electrical signal after time delay adjustment, and reads the relaxation oscillation frequency temperature drift coefficient calibrated during the factory full-temperature scan of each VCSEL channel, specifically: After the delay adjustment is completed, each digital signal enters an independent clock recovery stage. The DSP identifies which specific VCSEL channel on the transmitting side of this module the signal being processed comes from, based on the receiver's demapping table. The DSP retrieves the clock data recovery loop bandwidth parameter preset for this channel in the VCSEL nonlinear feature mapping table from memory. This parameter is configured by comprehensively matching the relative intensity noise of the transmitting VCSEL, the receiving TIA noise, and the total amount of PCB transmission jitter during factory calibration. In one implementation, for VCSEL channels with higher relative noise due to manufacturing processes, the recovered clock jitter is greater. Therefore, a narrower loop bandwidth value (e.g., 2MHz) is preset for them during factory calibration to better filter out noise and provide a cleaner recovered clock. For channels with lower relative noise, a wider loop bandwidth value (e.g., 5MHz) is preset to provide faster phase tracking speed. The domestically produced DSP extracts the clock reference from the data transition edges of each electrical signal, and sets the phase tracking response speed for clock data recovery based on the temperature drift coefficient, so that the phase tracking response speed matches the slow phase drift characteristics of the VCSEL channel caused by temperature changes. Specifically: A fully digital CDR circuit extracts the clock frequency and phase from the data transition edges of the signal. The CDR loop includes a low-pass filter to set the tracking bandwidth of the loop. In this scheme, the tracking bandwidth is not a fixed value, but is set according to the clock data recovery loop bandwidth parameter preset for this channel in the VCSEL nonlinear feature mapping table that was read earlier; In one implementation, for channel 5 with relatively high noise intensity, the preset loop bandwidth is 2MHz. This narrower bandwidth can effectively filter out high-frequency clock jitter caused by VCSEL noise. For channel 2 with relatively low noise intensity, the preset loop bandwidth is 5MHz to provide faster phase tracking speed. After configuration, the total jitter tolerance of CDR is checked to ensure that the input jitter tolerance index under 1e-12 bit error specified in the QSFP112 protocol is met. The domestically produced DSP tracks the extracted clock reference using the set phase tracking response speed and re-timing samples each electrical signal to obtain a jitter-free electrical signal, specifically as follows: The phase-locked loop or delay-locked loop inside the CDR circuit continuously tracks and locks the extracted clock reference according to the set dynamic response characteristics, regenerating a clean clock with low jitter that is synchronized with the data. This clean clock is used as a sampling trigger signal to "re-timing" the original data signal for sampling; In one implementation, the CDR of channel 5 continuously tracks the extracted clock reference with a loop bandwidth of 2MHz, and the jitter of the regenerated pure clock is less than 800fsRMS. After re-timing the signal using this clean clock, the jitter of the output signal is reduced from 3.5psRMS of the input to 0.8psRMS, eliminating various jitter components accumulated in long-distance PCB traces, connectors, optoelectronic devices and optical fibers. After re-timing, the output is a clean electrical signal with regular waveform and clear timing.

[0031] 8. The multi-rate compatible QSFP112 optical transmission system based on a domestically produced DSP according to claim 1, characterized in that the specific steps for restoring the output electrical signal are as follows: After completing the independent clock data recovery for each channel, the domestically produced DSP selects one of the jitter-free electrical signals as a reference, specifically as follows: After all 8 signals have undergone independent clock cleaning, the DSP will designate one of the channels as the reference for cross-channel alignment. In one implementation, the receiver physical channel 1 is selected as the reference by default. This selection is arbitrary, as long as all channels are aligned with it. Once selected, the clock and data timing of this signal become the target for alignment of the other 7 signals. The domestically produced DSP measures the time deviation between each of the remaining channels and the reference reference at the corresponding data symbol transition edge positions, obtaining the residual phase difference of each channel relative to the reference reference, specifically as follows: The phase detection circuit inside the DSP accurately compares the time position difference between a specific transition edge of the reference signal and the transition edge of the corresponding data symbol in another signal. In one implementation, this measurement employs digital phase interpolation technology with an accuracy of up to 200 fs. Through this comparison, it is precisely measured that the second path is 1.5 ps behind the reference reference, the third path is 0.8 ps ahead, and so on. These small, directional time differences are the residual phase differences. The domestically produced DSP inserts a digital delay corresponding to the measured residual phase difference into each signal, ensuring that each signal is aligned with the reference before entering the reverse Gearbox for assembly. Specifically: Provided that the clocks recovered by each CDR are at the same frequency, the DSP uses a fractional delay filter in the digital domain to finely adjust the time delay of each non-reference signal based on the measured residual phase difference. In one implementation, a 64th-order Farrow fractional delay filter is used to provide fine-grained delay adjustment with a resolution of 0.2 ps. For example, for channel 2, which arrives 1.5 ps later, the filter precisely inserts a delay of 1.5 ps; for channel 3, which arrives 0.8 ps earlier, the filter effectively advances it by 0.8 ps using an interpolation algorithm. After this processing, the timing of the data streams of all 8 signals is highly consistent when they enter the reverse Gearbox. The domestically produced DSP determines the data word position of each electrical signal during reverse Gearbox assembly based on the receiver's demapping table. It then assembles the strictly aligned electrical signals into an output signal according to the demapping table. Specifically: Eight strictly aligned electrical signals are sent into a reverse Gearbox, which reads the receiver's demapping table. In one implementation, the demapping table states that "receive channel 1 corresponds to VCSEL channel 5 on the transmitting side of this module". Then, the reverse Gearbox knows that the data on the current receive channel 1 should be placed in the 5th time slot of the final output data word. By following a mapping rule that is completely opposite to the splitting logic of the transmitter Gearbox and dynamically adjusting according to the demapping table, the 8 50GPAM4 data streams are combined into 4 100GPAM4 output electrical signals, thus completing signal reconstruction.

[0032] Among them, the receiver demapping table is obtained by the domestic DSP from the orthogonal identifier code in the composite alignment training sequence. When the transmitter performs channel rotation, after the rotation mapping change takes effect, the DSP updates the orthogonal identifier code synchronously in the next frame of the composite alignment training sequence after the current frame period of the composite alignment training sequence ends. The receiver decodes the updated orthogonal identifier frame and refreshes the receiver demapping table in real time. The switching delay does not exceed the period of a single composite aligned training sequence frame. There is no cross-frame misalignment, which makes the channel correspondence of the reverse Gearbox concatenation consistent with the current rotation mapping relationship of the transmitter. In one implementation, the frame period of the composite alignment training sequence is short enough that the latency of the entire round-robin switching is less than the interruption threshold that the service link can tolerate, making it transparent to the upper-layer service link and not causing bit errors.

[0033] Specifically, it also includes specific degradation monitoring, with the following steps: The threshold current drift rate, slope efficiency decay rate, and PD dark current growth trend of each VCSEL channel are extracted as specific degradation characteristic parameters, specifically: The domestic DSP continuously collects data from each channel. For VCSEL, it calculates the threshold current drift rate by monitoring the change in bias current adjusted to maintain constant average optical power; and it calculates the slope efficiency attenuation rate by monitoring the change in optical modulation amplitude under the same modulation current. For the PD, the main control unit periodically completely shuts down the VCSEL transmitter, measures the PD's output current at this time, thereby obtaining the PD's dark current and tracking its growth trend over time; In one implementation, the main control unit records the bias current value and modulation amplitude value of each channel every 24 hours. After 2000 hours of operation, the bias current of channel 3 increased from 3.0mA to 3.8mA, and the threshold current drift rate was calculated to be 0.4mA / thousand hours. The optical modulation amplitude of channel 3 decreased from 2.5mW to 2.3mW, and the calculated slope efficiency attenuation rate was 4% / kWh; the dark current of the PD corresponding to channel 3 increased from 50nA to 120nA. These three parameters directly reflect the physical aging process of optoelectronic devices and are defined as specific degradation characteristic parameters. The temporal changes of specific degradation characteristic parameters are continuously tracked using a sliding window method. When preset compensation constraints are met, a compensation control command is generated, specifically as follows: The domestic DSP runs a lightweight timing analysis algorithm that maintains a sliding window with a time length of 100 hours and analyzes the change trajectory of the above three parameters within the window. When the algorithm predicts that the cumulative slope efficiency attenuation rate of a certain channel will cause the optical modulation amplitude of that channel to fall below the lower limit specified in the protocol, the preset compensation constraint condition is met. In one implementation, the lower limit of the protocol optical modulation amplitude is 2.2mW; the sliding window size is 100 hours, and the window slides once every 10 hours. The linear extrapolation method is used to predict the modulation amplitude change in the next 50 hours. At the time point of 2000 hours, the algorithm analyzes the data of the previous 100 hours and finds that the slope efficiency decay trend of channel 3 is -0.02mW / 100 hours. It is predicted that in the next 50 hours, its optical modulation amplitude will fall below the preset threshold of 2.2mW. At this time, a compensation control command for channel 3 is generated. Based on the compensation control command, the compensation strategy for the corresponding channel is adjusted, specifically as follows: Upon receiving the compensation instruction, the domestically produced DSP adjusts the compensation strategy for the corresponding channel; In one implementation, the average optical power change caused by threshold current drift is compensated by finely adjusting the DC bias current of the VCSEL of the channel. For example, the DC bias current of the VCSEL of channel 3 is increased from 3.8mA to 4.1mA to maintain stable average optical power. When the slope efficiency decreases and the optical modulation amplitude is insufficient, the gain coefficient of the optical-side digital pre-emphasis FIR filter in the joint compensation model is adjusted to enhance the high-frequency components of the signal and compensate for the bandwidth limitation exacerbated by aging. For example, in the case of channel 3 slope efficiency attenuation of 4% / thousand hours, the high frequency gain of the optical-side digital pre-emphasis FIR filter is increased by 1.5dB, the bias current is used to solve the average power problem, and the optical-side digital pre-emphasis FIR filter is used to solve the bandwidth and modulation amplitude problems. This avoids the instability factors introduced by compensation overlap. After compensation is performed, the monitoring threshold corresponding to the channel is updated synchronously to avoid false alarms caused by compensation action. The temporal variation trend of specific degradation feature parameters is used as the degradation trend of each VCSEL channel to update the rotation mapping relationship and adjust the rotation cycle. Specifically: After the compensation is performed, the main control unit will assess the reason for the compensation, the amount of compensation, and the current degradation rate of the channel, and integrate them into a "health report". When the compensation amount in the compensation control command exceeds the preset upper limit, or when the output signal quality of the channel after compensation still fails to meet the preset requirements, the channel is marked as a deeply degraded channel. Among them, the upper limit of the compensation amount is 3dB increase of the maximum gain of the optical digital pre-emphasis FIR filter, the signal quality threshold is the bit error rate of the receiver 1e-12, the deep degradation mark is a dynamic mark, and the channel degradation rate is recalculated every 24 hours of degradation monitoring cycle. The normal range threshold for degradation rate is: threshold current drift rate ≤ 0.2mA / kWh, slope efficiency decay rate ≤ 2% / kWh. When a channel is marked as deeply degraded, the deep degradation penalty in its real-time health score is set to 0.4, and the score is significantly reduced accordingly. After the degradation rate falls back to the normal range for two consecutive monitoring cycles, the deep degradation marker is removed, the penalty score is reset to zero, the original real-time health score calculation method is restored, and the rotation weight is restored synchronously. Immediately after the completion of this monitoring cycle, the rotation weights of all channels are recalculated and the rotation mapping table is refreshed. Since the real-time health score of this channel has been significantly reduced, its rotation weight is immediately shortened after the refresh, and the time occupied is reduced accordingly. At the same time, the rotation weights and time occupied of other channels with higher real-time health scores are extended accordingly. In one implementation, channel 3 is marked as a deeply degraded channel because its compensation amount is close to the upper limit and its signal quality is still below the threshold. Its real-time health score is significantly reduced from 0.75 to 0.35 (penalty score of 0.4 takes effect), and the corresponding single occupation time is shortened from 120 seconds to 55 seconds. Meanwhile, the real-time health scores of channels 1 and 2 are good, at 0.95 and 0.90 respectively, and their occupation time is extended accordingly. At the same time, the main control unit updates the real-time health score of each channel. This score will be used for channel selection in the aforementioned speed-down mode. As a result, the load distribution strategy of the entire module dynamically tilts towards healthier channels, reducing the rate at which overall performance deteriorates due to the rapid degradation of a few channels. All degradation monitoring data, compensation events, real-time health scores, and rotation strategy change records are reported to the host through the CMIS4.0 interface. The reported parameters include time-series data of degradation characteristics for each channel, compensation adjustment records, rotation mapping change logs, and real-time health scores. Reports are submitted in batches every 24 hours. When events such as compensation adjustment, deep degradation marking, or rotation mapping change occur, a single active report is immediately triggered. All monitoring data and event data are locally cached for 7 days. When the cache overflows, the oldest record is automatically overwritten. If a report fails, it is retried every 30 seconds. If it fails 3 times in a row, the current report is terminated and a local alarm log is recorded.

[0034] Please see Figure 3 This invention provides a technical solution: a method for implementing multi-rate compatible QSFP112 optical transmission based on domestically produced DSP, comprising the following steps: The domestic DSP receives the training sequence sent by the host to estimate the channel quality of the local electrical port receiver and obtain the nominal rate mode of the electrical port. It selects the DSP parameter set from the firmware configuration table to configure the domestic DSP. After configuration, the domestic DSP performs equalization and retiming on the input electrical signal from the host in the compact space of the QSFP112 package. Then, it performs down-frequency expansion and rate remapping, deserializes the input electrical signal and reassembles it into multiple electrical signals with lower modulation rates, which are denoted as second rate electrical signals. The multiple second rate electrical signals are then distributed to multiple VCSEL channels according to the dynamically updated round-robin mapping relationship. Based on a pre-calibrated nonlinear characteristic mapping table for each VCSEL channel, the domestic DSP independently applies digital pre-emphasis compensation that is inverse to the nonlinear distortion of the corresponding VCSEL channel to each second-rate electrical signal, and modulates it onto the corresponding VCSEL channel to generate optical signals. A composite alignment training sequence carrying channel identifiers and time delay measurement information is inserted into each optical signal, and photoelectric conversion is performed at the receiving end to obtain each electrical signal. The channel identifiers are extracted to establish a receiving end demapping table, and the time delay measurement information is extracted to obtain the time delay difference between channels, and coarse-grained time delay adjustment is performed. Each electrical signal after time delay adjustment is independently clocked to eliminate jitter. Then, one of the signals is used as a reference to perform cross-channel phase alignment. Finally, the signal is reconstructed using the receiver's demapping table and reassembled into the output electrical signal.

[0035] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0036] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP, characterized in that, include: The optical transmission link configuration unit is used to estimate the channel quality of the local electrical interface receiver by receiving the training sequence sent by the domestic DSP receiver host, and to obtain the nominal rate mode of the electrical interface, and to select the DSP parameter set from the firmware configuration table to configure the domestic DSP. The multi-channel optical emission processing unit is used by the configured domestic DSP in the compact space of QSFP112 package to equalize and retime the input electrical signal from the host, then perform frequency reduction, capacity expansion and rate remapping, deserialize the input electrical signal and reassemble it into multiple electrical signals with lower modulation rates, which are denoted as second rate electrical signals, and distribute the multiple second rate electrical signals to multiple VCSEL channels according to the dynamically updated round-robin mapping relationship. The optical signal compensation transmitting unit is used to independently apply digital pre-emphasis compensation, which is inversely proportional to the nonlinear distortion of the corresponding VCSEL channel, to each second-rate electrical signal based on a pre-calibrated nonlinear characteristic mapping table of each VCSEL channel, and modulate it onto the corresponding VCSEL channel to generate an optical signal. The optical transmission link delay compensation unit is used to insert a composite alignment training sequence carrying channel identifier and delay measurement information into each optical signal, and perform photoelectric conversion at the receiving end to obtain each electrical signal, extract the channel identifier to establish the receiving end demapping table, extract the delay measurement information to obtain the delay difference between channels, and perform coarse-grained delay adjustment. The recovery and splicing unit is used to independently recover the clock data of each electrical signal after time delay adjustment to eliminate jitter. After aligning the phase of each channel with one of them as a reference, it performs reverse Gearbox splicing according to the receiver's demapping table to restore the output electrical signal.

2. The multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP according to claim 1, characterized in that, The specific steps for configuring a domestic DSP by selecting the DSP parameter set from the firmware configuration table are as follows: The domestic DSP performs amplitude histogram accumulation on the training sequence received from the host side, and obtains the vertical eye opening and channel insertion loss values ​​through the internal eye diagram estimation circuit. The vertical eye diagram opening and the channel insertion loss value are processed together to generate loss level parameters; Using the nominal rate mode of the electrical port as the row index and the loss level parameter as the column index, the corresponding DSP parameter set record is located in the two-dimensional lookup structure of the firmware configuration table. The DSP parameter set includes the coordinated values ​​of the Gearbox division ratio, the initial coefficient of the electrical port equalizer, and the initial value of the optical side pre-emphasis compensation preload. The DSP parameter set obtained from the lookup table is written to the corresponding register group of the domestic DSP in an atomic configuration transaction.

3. The multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP according to claim 2, characterized in that, The specific steps for deserializing the input electrical signal and reassembling it into a multi-channel electrical signal with a lower modulation rate, denoted as the second-rate electrical signal, are as follows: The configured domestic DSP receives the input electrical signal and performs channel equalization on the input electrical signal based on the initial coefficients of the electrical port equalizer, which is adapted to the loss level parameters. And perform clock data recovery and retiming on the input electrical signal after channel equalization; The domestic DSP is based on the Gearbox frequency division ratio. It deserializes and remaps the input electrical signal after retiming, and reassembles the input electrical signal into a second-rate electrical signal with a multiplied number of channels and a proportionally reduced single-channel modulation rate.

4. The multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP according to claim 1, characterized in that, The specific steps for distributing multiple second-rate electrical signals to multiple VCSEL channels according to a dynamically updated round-robin mapping relationship are as follows: A full-temperature scan was performed on each VCSEL channel to obtain the photoelectric conversion efficiency, 3dB bandwidth, and linearity of each channel, forming a VCSEL channel performance ranking table. Monitor the threshold current drift rate and slope efficiency decay rate of each VCSEL channel to evaluate the differences in degradation rate among the channels; Based on the difference in degradation rate of each channel and combined with the performance ranking table, the preset rotation mapping relationship is updated, and the domestic DSP allocates signals according to the updated rotation mapping relationship. When the rotation mapping relationship changes, the domestic DSP embeds an orthogonal identifier code that uniquely corresponds to the assigned VCSEL channel into each second-rate electrical signal.

5. The multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP according to claim 2, characterized in that, The specific steps for applying digital pre-emphasis compensation are as follows: The initial operating point is set to the optical-side pre-emphasis compensation preload initial value in the DSP parameter set. For each second-rate electrical signal, extract the inflection point deviation of the PI curve, the frequency response roll-off characteristic, and the linearity deviation of the corresponding VCSEL channel from the nonlinear feature mapping table. A frequency domain inverse function filter is constructed based on the frequency response roll-off characteristics and the initial operating point. An amplitude domain anti-nonlinear pre-distortion lookup table is constructed based on the linearity deviation. The inflection point deviation of the PI curve is converted into a DC bias correction amount, which together constitute a joint compensation model. Based on the joint compensation model, each second-rate electrical signal is processed by a frequency domain inverse function filter, an inverse nonlinear predistortion lookup table, and a DC bias correction to obtain the compensated second-rate electrical signals.

6. The multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP according to claim 1, characterized in that, The specific steps for coarse-grained delay adjustment are as follows: The domestic DSP performs orthogonal decoding on each electrical signal, establishes a receiver demapping table based on the channel identifier obtained from the decoding, and determines the VCSEL channel of the transmitter corresponding to each electrical signal. The domestic DSP extracts the time delay measurement information of the composite aligned training sequence in each electrical signal, compares the arrival time difference of the time delay measurement information in each electrical signal, obtains the relative time delay difference between each signal, and determines the maximum relative time delay difference. The domestic DSP compares the maximum relative delay difference with a preset threshold; When the maximum relative time delay difference exceeds the preset threshold, the earliest arriving electrical signal is used as the reference, and corresponding coarse-grained digital delay compensation is applied to each digital signal.

7. The multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP according to claim 1, characterized in that, The specific steps for independently restoring the clock data of each delayed electrical signal to eliminate jitter are as follows: The domestic DSP identifies the VCSEL channels corresponding to each electrical signal after time delay adjustment, and reads the temperature drift coefficient of the relaxation oscillation frequency calibrated for each VCSEL channel. The domestic DSP extracts the clock reference from various electrical signals and sets the phase tracking response speed of clock data recovery based on the temperature drift coefficient; The domestic DSP tracks the extracted clock reference at the set phase tracking response speed and re-timing samples each electrical signal to obtain an electrical signal with jitter cleared.

8. The multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP according to claim 1, characterized in that, The specific steps to restore the output electrical signal are as follows: After completing the independent clock data recovery of each channel, the domestic DSP selects one of the jitter-free electrical signals as a reference. The domestic DSP measures the time deviation between each of the other channels and the reference reference at the corresponding data symbol transition edge position, and obtains the residual phase difference of each channel relative to the reference reference. The domestic DSP inserts a digital delay corresponding to the measured residual phase difference into each signal, so that each signal is aligned with the reference before entering the reverse Gearbox assembly. The domestic DSP determines the data word position of each electrical signal during reverse Gearbox assembly based on the receiver's demapping table, and then assembles the aligned electrical signals into an output electrical signal according to the demapping table.

9. The multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP according to claim 1, characterized in that, It also includes specific degradation monitoring, the specific steps of which are as follows: The threshold current drift rate, slope efficiency decay rate, and PD dark current growth trend of each VCSEL channel are extracted as specific degradation characteristic parameters. The system continuously tracks the temporal changes of specific degradation characteristic parameters using a sliding window approach, and generates compensation control commands when preset compensation constraints are met. Based on the compensation control command, adjust the compensation strategy of the corresponding channel; The temporal changes of specific degradation feature parameters are used as the degradation trend of each VCSEL channel to update the rotation mapping relationship.

10. A method for implementing multi-rate compatible QSFP112 optical transmission based on domestically produced DSP, using the multi-rate compatible QSFP112 optical transmission system based on domestically produced DSP as described in any one of claims 1-9, characterized in that, Includes the following steps: The training sequence sent by the domestic DSP receiver host is used to estimate the channel quality of the local electrical port receiver and obtain the nominal rate mode of the electrical port. The DSP parameter set is selected from the firmware configuration table to configure the domestic DSP. The configured domestic DSP, within the compact space of the QSFP112 package, performs equalization and retiming on the input electrical signal from the host, then performs frequency reduction, capacity expansion, and rate remapping. It deserializes the input electrical signal and reassembles it into multiple electrical signals with lower modulation rates, denoted as the second rate electrical signals. The multiple second rate electrical signals are then distributed to multiple VCSEL channels according to a dynamically updated round-robin mapping relationship. Based on the pre-calibrated nonlinear characteristic mapping table of each VCSEL channel, the domestic DSP independently applies digital pre-emphasis compensation that is inverse to the nonlinear distortion of the corresponding VCSEL channel to each second-rate electrical signal, and modulates it onto the corresponding VCSEL channel to generate optical signals. A composite alignment training sequence carrying channel identifiers and time delay measurement information is inserted into each optical signal. At the receiving end, photoelectric conversion is performed to obtain each electrical signal. The channel identifier is extracted to establish a receiving end demapping table. The time delay measurement information is extracted to obtain the time delay difference between channels, and coarse-grained time delay adjustment is performed. Each electrical signal after time delay adjustment is independently clocked to eliminate jitter. Then, one of the signals is used as a reference to perform cross-channel phase alignment. Finally, the signal is reverse-gearboxed according to the receiver's demapping table to restore the output electrical signal.

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