Photon clock synchronization chip and photon clock synchronization method

Abstract

The application is suitable for the field of clock synchronization technology, and provides a photonic clock synchronization chip and a photonic clock synchronization method. The transmitting end of the chip is used for generating an optical frequency comb optical signal, converting part of the optical frequency comb optical signal into an optical frequency comb electrical signal, performing frequency division processing and first phase-locked loop processing on the optical frequency comb electrical signal, locking a local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb optical signal, obtaining a first clock signal, and outputting a synchronization signal to the receiving end according to the SEUL-693 cyclic sequence based on the first clock signal; the receiving end of the chip is used for receiving the synchronization signal, generating a second clock signal which is homologous to the optical frequency comb optical signal based on the synchronization signal, and generating a synchronization pulse based on the second clock signal; the synchronization pulse is used for ensuring that the clock of the receiving end is synchronized with the clock of the transmitting end. The scheme realizes clock synchronization without an external reference clock, thereby reducing the cost of clock synchronization.

Description

Technical Field

[0001] This application belongs to the field of clock synchronization technology, and in particular relates to a photonic clock synchronization chip and a photonic clock synchronization method. Background Technology

[0002] High-precision clock synchronization plays a fundamental role in fields such as deep space communication, phased array radar, distributed sensing, and quantum key distribution. Although photonic clock technology has made progress, such as chip solutions integrating microcavity optical combs that have optimized frequency output and jitter control, the synchronization mechanism still has inherent drawbacks: existing methods require continuous transmission of synchronization sequences or rely on external reference clock sources, which not only excessively consumes communication bandwidth resources but also significantly increases the difficulty of system integration and the burden of operation and maintenance. It can be seen that the clock synchronization cost in existing technologies is relatively high. Summary of the Invention

[0003] In view of this, embodiments of this application provide a photonic clock synchronization chip to solve the technical problem of high clock synchronization cost in the prior art.

[0004] In a first aspect, embodiments of this application provide a photonic clock synchronization chip, which includes a transmitter and a receiver; The transmitting end is used to generate an optical frequency comb signal, convert a portion of the optical frequency comb signal into an optical frequency comb electrical signal, and perform frequency division and first phase-locked loop processing on the optical frequency comb electrical signal to lock the local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal to obtain a first clock signal. Based on the first clock signal, a synchronization signal is output to the receiving end according to the SEUL-693 cyclic sequence. The SEUL-693 cyclic sequence includes several identical SEUL-693 cyclic sub-sequences, and the frequency corresponding to each state in the SEUL-693 cyclic sub-sequence is determined according to a reference frequency. The receiving end is used to receive the synchronization signal, generate a second clock signal that is of the same origin as the optical frequency comb signal according to the synchronization signal, and generate a synchronization pulse according to the second clock signal; the synchronization pulse is used to ensure that the clock of the receiving end is synchronized with the clock of the transmitting end.

[0005] Optionally, the SEUL-693 cyclic subsequence includes six states, wherein the frequency corresponding to the first state is the reference frequency, the frequency corresponding to the second state is a nine-fold harmonic of the reference frequency, the frequency corresponding to the third state is a three-fold harmonic of the reference frequency, the frequency corresponding to the fourth state is the reference frequency, the frequency corresponding to the fifth state is a nine-fold harmonic of the reference frequency, and the frequency corresponding to the sixth state is a three-fold harmonic of the reference frequency.

[0006] Optionally, the transmitting end includes a loop generator, an optical frequency comb driver, and a micro-ring resonator; the transmitting end generates the optical frequency comb signal in the following manner: The loop generator generates a baseband electrical signal of the reference frequency and sends the baseband electrical signal to the optical frequency comb driver. The optical frequency comb driver receives the baseband electrical signal and generates a drive signal based on the baseband electrical signal. The driving signal is received through the micro-ring resonant cavity, and the optical frequency comb signal corresponding to the reference frequency is generated according to the driving signal.

[0007] Optionally, the transmitter may further include a frequency divider, a first photodetector, and a first phase-locked loop; The transmitting end converts a portion of the optical frequency comb signal into an optical frequency comb electrical signal in the following manner, and performs frequency division processing and a first phase-locked loop processing on the optical frequency comb electrical signal: The first photodetector extracts a portion of the optical frequency comb signal from the micro-ring resonant cavity, converts the extracted optical frequency comb signal into an optical frequency comb electrical signal, and sends the optical frequency comb electrical signal to the frequency divider. The optical frequency comb signal is received through the frequency divider, and the optical frequency comb signal is divided to match the input frequency band of the first phase-locked loop. The optical frequency comb signal after frequency division is then sent to the first phase-locked loop. The first phase-locked loop receives the optical frequency comb signal after frequency division processing, locks the local voltage-controlled oscillator in the first phase-locked loop to the optical frequency comb tooth spacing of the optical frequency comb signal, and then outputs the first clock signal.

[0008] Optionally, the transmitter further includes a clock modulator; the transmitter outputs a synchronization signal to the receiver according to a SEUL-693 cyclic sequence based on a first clock signal in the following manner: The loop generator generates the SEUL-693 loop sequence and sends the SEUL-693 loop sequence to the clock modulator. The clock modulator receives the first clock signal and the SEUL-693 cyclic sequence, modulates the synchronization signal corresponding to the SEUL-693 cyclic sequence according to the first clock signal and the SEUL-693 cyclic sequence, and sends the synchronization signal to the receiving end.

[0009] Optionally, the receiving end includes a second photodetector, a loop detector, a second phase-locked loop, and a clock generator; the receiving end receives the synchronization signal in the following manner, and generates a second clock signal that is of the same origin as the optical frequency comb signal based on the synchronization signal: The second photodetector receives the synchronization signal, restores the synchronization signal to the optical frequency comb signal, and sends the optical frequency comb signal to the loop detector. The optical frequency comb signal is received by the cyclic detector and matched with the SEUL-693 cyclic sequence in real time to obtain a detection identification signal, which is then sent to the second phase-locked loop. The detection identification signal is received through the second phase-locked loop, and a clock sourced from the same origin as the optical frequency comb signal is identified based on the detection identification signal. The clock generator generates the second clock signal based on the clock source identified by the second phase-locked loop as being from the same origin as the optical frequency comb signal.

[0010] Optionally, the receiving end further includes a counter; the receiving end generates a synchronization pulse based on the second clock signal in the following manner: The counter receives the second clock signal output by the clock generator and outputs a synchronization pulse once for each preset number of complete cycles based on the second clock signal; the preset number is determined according to the SEUL-693 cycle sequence.

[0011] Optionally, the counter is a modulo-7 counter, and the preset quantity is seven.

[0012] Optionally, the reference frequency is within a preset reference frequency range; the reference frequency range is 693MHz ±5%.

[0013] Secondly, embodiments of this application provide a photonic clock synchronization method applied to a photonic clock synchronization chip, the photonic clock synchronization chip including a transmitter and a receiver; the method includes: The transmitter generates an optical frequency comb signal and converts a portion of the optical frequency comb signal into an optical frequency comb electrical signal. The optical frequency comb electrical signal is then subjected to frequency division and a first phase-locked loop (PLL) process to lock the local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal, resulting in a first clock signal. Based on the first clock signal, a synchronization signal is output to the receiver according to a SEUL-693 cyclic sequence. The SEUL-693 cyclic sequence includes several identical SEUL-693 cyclic sub-sequences, and the frequency corresponding to each state in the SEUL-693 cyclic sub-sequence is determined based on a reference frequency. The receiving end receives the synchronization signal and generates a second clock signal that is of the same origin as the optical frequency comb signal based on the synchronization signal. A synchronization pulse is generated based on the second clock signal. The synchronization pulse is used to ensure that the clock of the receiving end is synchronized with the clock of the transmitting end.

[0014] The photonic clock synchronization chip provided in this application has the following beneficial effects: This application provides a photonic clock synchronization chip comprising a transmitter and a receiver. The transmitter generates an optical frequency comb signal, converts a portion of the optical frequency comb signal into an optical frequency comb electrical signal, and performs frequency division and a first phase-locked loop (PLL) process on the optical frequency comb electrical signal to lock a local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal, thereby obtaining a first clock signal. Based on the first clock signal, a synchronization signal is output to the receiver according to a SEUL-693 cyclic sequence. The SEUL-693 cyclic sequence includes several identical SEUL-693 cyclic sub-sequences, and the frequencies corresponding to each state in the SEUL-693 cyclic sub-sequences are determined according to a reference frequency. The receiver receives the synchronization signal and generates a second clock signal that is of the same origin as the optical frequency comb signal based on the synchronization signal. Based on the second clock signal, a synchronization pulse is generated. The synchronization pulse is used to ensure that the clock of the receiver is synchronized with the clock of the transmitter. As can be seen, the photonic clock synchronization chip provided in this application effectively avoids the need to continuously send synchronization sequences or rely on external reference clock sources by adopting the SEUL-693 cyclic sequence and the same source clock generation mechanism. This significantly reduces communication bandwidth usage and system integration complexity, provides high-precision clock synchronization capability, and significantly reduces system complexity and bandwidth usage, ultimately reducing the cost of clock synchronization. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a photonic clock synchronization chip provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a photonic clock synchronization method provided in an embodiment of this application. Detailed Implementation

[0017] It should be noted that the terminology used in the embodiments of this application is only for explaining specific embodiments of this application and is not intended to limit this application. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, "at least one" or "one or more" means one, two or more. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0018] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0019] Traditional high-precision clock synchronization schemes, such as hydrogen clocks and rubidium clocks in deep space communication, and high-precision cable and phase-locked loop schemes in phased array radar, suffer from problems such as large size, high power consumption, high cost, system complexity, and susceptibility to environmental interference. In addition, existing synchronization schemes require continuous transmission of synchronization sequences or rely on external reference clocks, resulting in large synchronization overhead, bandwidth consumption, and increased system complexity.

[0020] To address this, this application proposes a photonic clock synchronization chip. Please refer to... Figure 1 , Figure 1 This is a schematic diagram of the structure of a photonic clock synchronization chip provided in an embodiment of this application.

[0021] like Figure 1 As shown in the embodiment of this application, the photonic clock synchronization chip includes a transmitter and a receiver.

[0022] The transmitter generates an optical frequency comb signal, converts a portion of the optical frequency comb signal into an optical frequency comb electrical signal, and performs frequency division and a first phase-locked loop (PLL) process on the optical frequency comb electrical signal to lock the local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal, thereby obtaining a first clock signal. Based on the first clock signal, a synchronization signal is output to the receiver according to the SEUL-693 cyclic sequence. The SEUL-693 cyclic sequence includes several identical SEUL-693 cyclic sub-sequences, and the frequency corresponding to each state in the SEUL-693 cyclic sub-sequence is determined according to a reference frequency. The receiver is used to receive the synchronization signal, generate a second clock signal that is of the same origin as the optical frequency comb signal based on the synchronization signal, and generate a synchronization pulse based on the second clock signal; the synchronization pulse is used to ensure that the clock of the receiver is synchronized with the clock of the transmitter.

[0023] For ease of understanding, the following explains some key terms in this embodiment: Optical frequency comb signals refer to optical signals with a series of equally spaced, narrow-linewidth frequency components in the optical spectrum. These frequency components are like the teeth of a comb, and the spacing between them is called the optical frequency comb tooth spacing. This signal has applications in precision measurement and clock synchronization.

[0024] The spacing between optical frequency comb teeth refers to the frequency difference between adjacent frequency components in the optical frequency comb signal. This spacing is usually determined by the equipment that generates the optical frequency comb and serves as a reference for clock synchronization.

[0025] The SEUL-693 cyclic sequence refers to a pre-defined, periodically repeating signal pattern. This sequence consists of multiple SEUL-693 cyclic subsequences, each containing a series of signals with specific frequency states.

[0026] A SEUL-693 cyclic subsequence is a basic repeating unit in a SEUL-693 cyclic sequence. Each SEUL-693 cyclic subsequence consists of multiple states, each state corresponding to a specific frequency, which are determined based on a reference frequency.

[0027] The reference frequency is the fundamental frequency used to determine the frequencies of each state in the SEUL-693 cyclic subsequence. By multiplying or dividing this reference frequency, the frequencies required for different states in the SEUL-693 cyclic subsequence can be generated.

[0028] A synchronization pulse is a periodic electrical pulse signal generated by the receiver. This pulse is used to calibrate the receiver's local clock, ensuring it is synchronized with the transmitter's clock.

[0029] This embodiment provides a photonic clock synchronization chip, the structure of which includes a transmitter and a receiver. The chip can be designed to contain two independent physical modules, respectively implementing transmission and reception functions, and connected via an optical fiber or wireless link. Alternatively, the chip can be integrated on the same chip substrate, achieving communication through internal interconnects.

[0030] The transmitter is configured to generate an optical frequency comb signal. The generation of the optical frequency comb signal can be achieved in several ways. For example, light can be generated using a continuous-wave laser and then modulated by an external modulator (e.g., an electro-optic modulator) to produce an optical signal with multiple equally spaced frequency components. Another approach is to use a mode-locked laser, which can directly generate the optical frequency comb.

[0031] The transmitter is further configured to convert a portion of the optical frequency comb signal into an optical frequency comb electrical signal. This conversion can be achieved using a photodetector. For example, a portion of the optical frequency comb signal can be directly incident on a photodiode, which then converts the optical signal into a corresponding electrical signal.

[0032] The transmitter is also configured to perform frequency division and a first phase-locked loop (PLL) process on the optical frequency comb signal to lock the local voltage-controlled oscillator (VCO) to the optical frequency comb tooth spacing of the optical frequency comb signal, thereby obtaining a first clock signal. The frequency division can be implemented using a digital frequency divider or an analog frequency divider circuit to reduce the frequency of the electrical signal. The first PLL process can employ a standard analog PLL or digital PLL circuit. This PLL receives the frequency-divided electrical signal as a reference input and adjusts the frequency of its internal voltage-controlled oscillator (VCO) to match the comb tooth spacing of the optical frequency comb signal, thereby outputting a stable first clock signal.

[0033] The transmitting end outputs a synchronization signal to the receiving end according to a SEUL-693 cyclic sequence based on a first clock signal. The output synchronization signal can be generated by a timing controller based on the first clock signal. This timing controller can preset a cyclic timing pattern, for example, by changing the frequency or phase of the output signal to encode specific timing information. This timing sequence can be a simple periodic pulse sequence or a more complex frequency-jumping sequence.

[0034] The SEUL-693 cyclic sequence comprises several identical SEUL-693 cyclic subsequences, where the frequency corresponding to each state is determined based on a reference frequency. The SEUL-693 cyclic sequence can be constructed based on a reference frequency. For example, a fundamental frequency can be set, and then different states within the SEUL-693 cyclic subsequence can be defined by multiplying, dividing, or directly outputting this fundamental frequency. Each SEUL-693 cyclic subsequence can contain multiple different frequency states, and combinations of these frequency states form a cyclic pattern.

[0035] The receiver is configured to receive the synchronization signal. The receiver can receive the synchronization signal via a photoelectric conversion module. For example, when the synchronization signal is transmitted in optical form, the receiver can use a photodetector to convert it into an electrical signal.

[0036] The receiver is further configured to generate a second clock signal that is of the same origin as the optical frequency comb signal, based on the synchronization signal. The receiver can utilize a phase-locked loop or frequency synthesizer to extract clock information from the received synchronization signal. For example, a second clock signal of the same origin as the transmitting optical frequency comb signal can be generated by detecting frequency or phase changes in the synchronization signal and comparing them with an internal oscillator.

[0037] The receiver is also configured to generate a synchronization pulse based on the second clock signal. The synchronization pulse can be generated using a counter or timing generator. For example, a counting threshold can be set, and a synchronization pulse is output when the number of cycles of the second clock signal reaches that threshold.

[0038] The synchronization pulse is used to ensure that the clock at the receiver is synchronized with the clock at the transmitter. The synchronization pulse can also serve as a reference for internal clock calibration at the receiver. For example, the receiver's local oscillator can be phased or frequency-adjusted based on the synchronization pulse to eliminate any discrepancies with the transmitter's clock.

[0039] The photonic clock synchronization chip of this application generates an optical frequency comb signal at the transmitter and outputs a synchronization signal using a SEUL-693 cyclic sequence. The receiver then generates a synchronous clock and synchronization pulse based on this signal. This effectively solves the problems of large size, high power consumption, high cost, system complexity, and high synchronization overhead in existing high-precision clock synchronization solutions in fields such as deep space communication and phased array radar. This solution achieves high-precision, low-overhead clock synchronization, improving system integration and environmental adaptability.

[0040] In some embodiments described above in this application, clock synchronization is proposed using a SEUL-693 cyclic sequence. This sequence contains several identical SEUL-693 cyclic subsequences, and the frequency of each state in the SEUL-693 cyclic subsequence is determined based on a reference frequency. However, in practical applications, designing a SEUL-693 cyclic subsequence with good recognition characteristics and anti-interference capabilities to ensure that the receiver can quickly and accurately identify and lock onto the synchronization signal is a key challenge in achieving efficient and reliable clock synchronization.

[0041] In practical applications, the mathematical basis of the SEUL-693 cycle is the sequence of roots of energy levels in discrete spacetime geometry, defined as: 6, 9, 3, 6, 9, 3. This cycle has the following mathematical characteristics: 1. Periodicity is 2. 2. The sum is 36. 3. Its relationship with modulo 7 is: 6 ≡ 6 mod 7, 9 ≡ 2 mod 7, 3 ≡ 3 mod 7, thus recursively resonating with modulo 7. 4. It has the same structure in both the time and frequency domains.

[0042] Furthermore, the corresponding optical frequency comb of the SEUL-693 cycle and the optical frequency comb is a spectrum composed of equally spaced frequency peaks, and its tooth pitch (FSR) determines the clock accuracy. In practical applications, it has been found that the periodic structure of the SEUL-693 cycle (6,9,3,6,9,3) naturally corresponds to the tooth pitch design of the optical frequency comb.

[0043] In this regard, this application further proposes that the SEUL-693 cyclic subsequence includes six states, wherein the frequency corresponding to the first state is the reference frequency, the frequency corresponding to the second state is the ninth harmonic of the reference frequency, the frequency corresponding to the third state is the third harmonic of the reference frequency, the frequency corresponding to the fourth state is the reference frequency, the frequency corresponding to the fifth state is the ninth harmonic of the reference frequency, and the frequency corresponding to the sixth state is the third harmonic of the reference frequency.

[0044] The SEUL-693 cyclic subsequence is the basic building block of the SEUL-693 cyclic sequence. Its length and number of states directly affect the coding efficiency and recognition complexity of the synchronization signal. A SEUL-693 cyclic subsequence containing six states means that the sequence has sufficient length and information carrying capacity to form a unique and highly distinguishable frequency pattern. Each state corresponds to a specific time window within which the synchronization signal will exhibit a preset frequency. This design helps improve the uniqueness of the synchronization signal and reduces the probability of misidentification in complex environments.

[0045] The reference frequency is the fundamental reference frequency for the entire photonic clock synchronization chip system, typically provided by a highly stable oscillator. Setting the first state of the SEUL-693 cyclic subsequence as the reference frequency provides a clear starting reference point for the receiver, facilitating initial frequency acquisition and sequence boundary identification. This helps simplify the initial locking process of the receiver to the synchronization signal.

[0046] In this regard, this application further proposes that the reference frequency is within a preset reference frequency range, and the reference frequency range is 693MHz±5%.

[0047] The reference frequency is the core frequency in the photonic clock synchronization chip used to define the SEUL-693 cyclic sequence and drive the generation of the optical frequency comb. Limiting it to a preset range ensures the stability and accuracy of this critical frequency, thus providing a fundamental guarantee for the reliable operation of the entire synchronization system. This preset range is typically determined based on a comprehensive consideration of the chip's internal circuit characteristics, optical device response, and overall system performance optimization requirements. In practical applications, this reference frequency can be precisely generated and maintained by integrating a high-precision frequency source, such as a crystal oscillator or an on-chip phase-locked loop circuit, ensuring it remains within the set range. Specifically limiting the reference frequency range to 693MHz ± 5% provides clear engineering implementation parameters. This specific frequency value and its allowable deviation range are carefully selected, possibly matching the free spectral range of the chip's internal microring resonator, the optimal operating point of the voltage-controlled oscillator (VCO), or the clock frequency requirements of a specific communication standard. By precisely controlling the reference frequency within this range, system noise can be effectively reduced, power consumption optimized, and the generation quality of the optical frequency comb signal improved. During the chip manufacturing and testing phases, high-precision frequency measurement equipment can be used to rigorously test and calibrate the actual generated reference frequency to ensure that it meets the specified range, thereby guaranteeing the performance consistency and reliability of the chip under various operating conditions.

[0048] By limiting the reference frequency to a preset range of 693MHz ± 5%, the performance and stability of the photonic clock synchronization chip can be significantly improved. Specifically, this precise frequency limitation ensures that the micro-ring resonator operates at its optimal resonance state when the transmitter generates the optical frequency comb signal, thereby producing a high-quality, low-noise optical frequency comb signal. This high-quality optical frequency comb signal is the foundation for generating a stable first clock signal. Simultaneously, the precise reference frequency also guarantees the accuracy and predictability of the SEUL-693 cyclic sequence, enabling the receiver to more reliably identify the synchronization signal and lock onto its second clock signal. This precise frequency control not only optimizes the efficiency and stability of the chip's internal circuitry (such as the phase-locked loop and voltage-controlled oscillator) but also reduces the system's sensitivity to changes in the external environment, thus ensuring the long-term accuracy and robustness of clock synchronization between the transmitter and receiver.

[0049] It should be noted that the reference frequency can also be limited to a preset range of 693*n MHz ± 5%, where n is an integer (e.g., 2) or a whole fraction (e.g., one-third). A ninth harmonic refers to a frequency obtained by processing a reference frequency through a frequency multiplication circuit (e.g., a frequency multiplier or a phase-locked loop). Introducing a ninth harmonic of the reference frequency into the SEUL-693 cyclic subsequence significantly increases the frequency jump amplitude within the sequence, thereby enhancing the sequence's spectral characteristics and distinctiveness. The presence of this high-frequency state makes it easier for the receiver to distinguish this state from other states during frequency detection.

[0050] Three-way division refers to the frequency obtained by processing the reference frequency through a frequency division circuit (e.g., a frequency divider or phase-locked loop). Introducing three-way division of the reference frequency into the sequence further enriches the frequency diversity of the sequence, forming a unique frequency pattern that includes high frequency, fundamental frequency, and low frequency. This frequency combination helps improve the anti-interference capability of the synchronization signal in noisy environments, enabling the receiver to accurately identify the various states of the sequence through more complex pattern matching algorithms.

[0051] This repetitive frequency pattern (e.g., base frequency, ninth harmonic, third harmonic, base frequency, ninth harmonic, third harmonic) provides a structured encoding method for the SEUL-693 cyclic subsequence. This repetition not only increases the overall length of the sequence but also provides redundant information during pattern recognition at the receiver, thus significantly improving the robustness and reliability of synchronization. Even in the event of partial data loss or interference, the receiver can still recover synchronization information by recognizing the repetitive pattern.

[0052] By employing a six-state SEUL-693 cyclic subsequence and carefully designing its frequency pattern as the reference frequency, its ninth harmonic, its third harmonic, the reference frequency, its ninth harmonic, and its third harmonic, this application provides a synchronization signal with high distinguishability and strong anti-interference capability. This unique frequency combination and repetition pattern allows the receiver to quickly and unambiguously identify the start and end of the SEUL-693 cyclic subsequence using pattern matching or correlation detection algorithms, thereby significantly improving the accuracy and robustness of clock synchronization. In particular, the introduction of harmonic and division frequency transitions increases the spectral width and complexity of the sequence, enabling the synchronization signal to be effectively distinguished and captured even in complex channel environments, effectively solving the problems of ambiguity or low synchronization efficiency that may exist in traditional synchronization sequences. This repetitive frequency pattern also provides redundant information to the receiver, further enhancing the reliability of synchronization and ensuring stable and accurate synchronization between the receiver's clock and the transmitter's clock.

[0053] In some embodiments described above in this application, the transmitting end needs to generate an optical frequency comb signal as a reference for clock synchronization. However, how to efficiently, stably, and accurately generate an optical frequency comb signal that is highly correlated with the reference frequency is a key challenge in achieving high-precision clock synchronization. If the generation process of the optical frequency comb signal is unstable or lacks precision, it will directly affect the accuracy and synchronization performance of subsequent clock signals.

[0054] In this regard, this application further proposes that the transmitter includes a cyclic generator, an optical frequency comb driver, and a micro-ring resonator. The transmitter generates the optical frequency comb signal in the following manner: the cyclic generator generates a baseband electrical signal of a reference frequency and sends the baseband electrical signal to the optical frequency comb driver; the optical frequency comb driver receives the baseband electrical signal and generates a drive signal based on the baseband electrical signal; the micro-ring resonator receives the drive signal and generates an optical frequency comb signal corresponding to the reference frequency based on the drive signal.

[0055] Specifically, a loop generator is used to generate the fundamental frequency electrical signal for the reference frequency. This fundamental frequency electrical signal is the source of the frequency reference for the entire photonic clock synchronization system. The loop generator can be a highly stable crystal oscillator, such as a quartz crystal oscillator or an atomic clock, to provide an extremely accurate and stable reference frequency. Alternatively, a frequency synthesizer can be used to generate the desired reference frequency from a lower-frequency reference source using phase-locked loop (PLL) technology. Its output fundamental frequency electrical signal is typically a sine wave or square wave with well-defined frequency and phase characteristics. The purpose of generating the fundamental frequency electrical signal is to provide a high-precision, highly stable electrical frequency reference. The loop generator ensures that the frequency characteristics of subsequent optical frequency comb signals are traceable and highly accurate.

[0056] The optical frequency comb driver receives a fundamental frequency electrical signal from a loop generator and generates a drive signal based on this signal. This drive signal is used to modulate the microring resonator, causing it to generate an optical frequency comb signal. The optical frequency comb driver may include components such as amplifiers, filters, and modulators. For example, it can amplify the fundamental frequency electrical signal and convert it into a radio frequency or microwave signal suitable for driving the microring resonator to excite nonlinear effects within it. Generating the drive signal is the bridge connecting the electrical reference and the optical signal generation. The optical frequency comb driver converts the electrical fundamental frequency signal into a driving form suitable for exciting the microring resonator to generate an optical frequency comb, ensuring energy and frequency matching, thereby effectively initiating the nonlinear optical process.

[0057] The microring resonator receives a drive signal from an optical frequency comb driver and generates an optical frequency comb signal corresponding to a reference frequency based on this drive signal. The microring resonator is a compact optical resonator, typically made of high-Q materials, capable of generating a series of equally spaced frequency comb teeth under the action of pump light through nonlinear optical effects such as the Kerr effect or four-wave mixing. The frequency and power of the drive signal affect the comb tooth spacing, bandwidth, and stability of the generated optical frequency comb signal. By precisely controlling the drive signal, it can be ensured that the comb tooth spacing of the generated optical frequency comb signal highly corresponds to the reference frequency. Generating an optical frequency comb signal corresponding to the reference frequency is the core of achieving photonic clock synchronization. Under the action of the drive signal, the microring resonator converts electrical frequency information into an optical frequency comb, whose comb tooth spacing precisely corresponds to the reference frequency. This optical frequency comb signal has high coherence and wide spectral characteristics, providing a high-quality optical source for subsequent clock extraction and synchronization.

[0058] Through the above technical solution, this application provides a compact, efficient, and reliable optical frequency comb signal generation method. A cyclic generator provides a stable reference frequency electrical signal, which the optical frequency comb driver effectively converts into the driving signal required by the micro-ring resonator. The micro-ring resonator then efficiently generates an optical frequency comb signal that precisely corresponds to the reference frequency. This integrated generation mechanism avoids the complex optical path and bulky size of traditional optical frequency comb systems, significantly improving the generation stability, accuracy, and integration of the optical frequency comb signal. It provides a high-quality, high-reliability optical frequency reference for photonic clock synchronization chips, thereby ensuring the performance of the entire clock synchronization system.

[0059] In some embodiments described above in this application, the transmitting end generates an optical frequency comb signal through a micro-ring resonant cavity. A portion of this optical frequency comb signal needs to be converted into an optical frequency comb electrical signal, followed by frequency division and a first phase-locked loop (PLL) process to lock the local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal, thus obtaining a first clock signal. However, optical frequency comb signals typically have extremely high repetition frequencies. Directly converting them into electrical signals and performing subsequent precise processing may face technical challenges such as bandwidth limitations of electrical devices, decreased signal integrity, and difficulties in stable PLL locking, thereby affecting the accuracy and stability of the first clock signal.

[0060] In this regard, this application further proposes that the transmitter also includes a frequency divider, a first photodetector, and a first phase-locked loop (PLL). The transmitter converts a portion of the optical frequency comb signal into an optical frequency comb electrical signal in the following manner, and performs frequency division and first PLL processing on the optical frequency comb electrical signal: A portion of the optical frequency comb signal is extracted from the micro-ring resonant cavity through the first photodetector, and the extracted optical frequency comb signal is converted into an optical frequency comb electrical signal, which is then sent to the frequency divider; the optical frequency comb electrical signal is received through the frequency divider, and frequency division processing is performed on the optical frequency comb electrical signal to match the input frequency band of the first PLL, and the frequency-divided optical frequency comb electrical signal is sent to the first PLL; the frequency-divided optical frequency comb electrical signal is received through the first PLL, and the local voltage-controlled oscillator in the first PLL is locked to the optical frequency comb tooth spacing of the optical frequency comb electrical signal, and then a first clock signal is output.

[0061] The first photodetector is a device that converts optical signals into electrical signals. Its function is to extract a portion of the optical frequency comb optical signal from the micro-ring resonant cavity and efficiently and accurately convert it into an optical frequency comb electrical signal. This conversion process is a crucial step in realizing the optoelectronic domain interface, ensuring that the timing information of the optical frequency comb can be accurately introduced into the electrical processing link. In practical applications, the first photodetector can employ a high-bandwidth PIN photodiode or an avalanche photodiode (APD) to ensure good response speed and conversion efficiency even under high-speed optical frequency comb signals.

[0062] A frequency divider is a circuit used to reduce the frequency of an input signal to a preset ratio. Its function is to receive the optical frequency comb signal from a first photodetector and divide it. Since the repetition frequency of the optical frequency comb can be very high, directly inputting it to the first phase-locked loop (PLL) may exceed its operating frequency range or cause performance degradation. Therefore, the frequency divider reduces the frequency so that the frequency of the divided optical frequency comb signal matches the input frequency band of the first PLL, thus ensuring the stable and efficient operation of the first PLL. The frequency divider can be a digital frequency divider (such as a trigger-based counter) or an analog frequency divider (such as an injection-locked oscillator), the specific choice depending on the required division ratio and operating frequency.

[0063] The first phase-locked loop (PLL) is a feedback control system used to lock the output frequency and phase of a local voltage-controlled oscillator (VCO) to the frequency and phase of a reference signal. In this scheme, the first PLL receives the frequency-divided optical frequency comb signal as a reference input. Its core function is to lock the local VCO to the optical frequency comb tooth spacing of the optical frequency comb signal through phase comparison, filtering, and VCO control. Once locked, the first PLL outputs a highly stable first clock signal that is homologous to the optical frequency comb signal. This first clock signal has low jitter and high precision, providing a reliable reference for the subsequent generation of synchronization signals. The first PLL can be an integer N-division PLL or a fractional N-division PLL to meet different frequency accuracy and phase noise requirements.

[0064] Through the above technical solution, the transmitting end can effectively convert high-frequency optical frequency comb signals into processable electrical signals and extract a high-precision, high-stability first clock signal. Specifically, the first photodetector is responsible for accurately converting a portion of the optical frequency comb signal into an optical frequency comb electrical signal, achieving seamless integration of the photoelectric domain. Subsequently, the frequency divider performs frequency division processing on the high-frequency optical frequency comb electrical signal, reducing its frequency to an input frequency band acceptable to the first phase-locked loop (PLL), thereby overcoming the bandwidth limitations and stability challenges of directly processing high-frequency signals. Based on this, the first PLL can stably lock the local voltage-controlled oscillator to the optical frequency comb tooth spacing of the frequency-divided optical frequency comb electrical signal, ensuring that the output first clock signal has a strict phase and frequency synchronization relationship with the original optical frequency comb signal. This step-by-step processing method—first performing photoelectric conversion, then frequency division to adapt to the PLL, and finally achieving precise locking through the PLL—effectively solves the problem of directly extracting a stable electrical clock from high-frequency optical signals, significantly improving the accuracy, stability, and anti-interference capability of the first clock signal, and laying a solid foundation for subsequently generating a highly reliable synchronization signal according to the SEUL-693 cyclic sequence.

[0065] To address this, this application further proposes a transmitter for a photonic clock synchronization chip, which generates a first clock signal highly synchronized with the optical frequency comb signal and outputs a synchronization signal to the receiver according to a preset SEUL-693 cyclic sequence. However, effectively combining the first clock signal with the SEUL-693 cyclic sequence to generate a synchronization signal that accurately carries timing information and is suitable for long-distance transmission is a key challenge in achieving precise clock synchronization.

[0066] To address the aforementioned issues, the transmitting end of this application further includes a clock modulator. The transmitting end generates a SEUL-693 cyclic sequence via a loop generator and sends the SEUL-693 cyclic sequence to the clock modulator. The clock modulator receives a first clock signal and the SEUL-693 cyclic sequence, and modulates a synchronization signal corresponding to the SEUL-693 cyclic sequence based on the first clock signal and the SEUL-693 cyclic sequence, then sends the synchronization signal to the receiving end.

[0067] The loop generator is responsible for generating the SEUL-693 cyclic sequence. This sequence is a pre-defined series of states, each corresponding to a specific frequency, which is determined based on a reference frequency. The loop generator can be a digital logic circuit, such as a state machine or a programmable sequence generator, which periodically outputs control signals or data representing the various states in the SEUL-693 cyclic sequence according to a preset program or configuration. These control signals are then sent to a clock modulator as the basis for modulating the first clock signal.

[0068] The clock modulator is a key component that receives the SEUL-693 cyclic sequence from the loop generator and the first clock signal from the first phase-locked loop (PLL), and modulates these signals to generate the final synchronization signal. Specifically, the clock modulator can employ various modulation techniques. For example, it can switch or encode the frequency, phase, or amplitude of the first clock signal based on the state of the SEUL-693 cyclic sequence. For instance, when the SEUL-693 cyclic sequence indicates a specific frequency, the clock modulator adjusts the first clock signal to that frequency or modulates it based on that frequency; when the SEUL-693 cyclic sequence indicates another frequency, it makes corresponding adjustments. In this way, the clock modulator accurately loads the frequency information contained in the SEUL-693 cyclic sequence onto the synchronization signal based on the first clock signal, ensuring that the synchronization signal accurately reflects the preset timing pattern.

[0069] The core of this embodiment is the process of modulating a synchronization signal based on a first clock signal and a SEUL-693 cyclic sequence. In this process, the clock modulator uses the first clock signal as a carrier or base clock and utilizes the SEUL-693 cyclic sequence provided by the cyclic generator as modulation information. For example, the clock modulator can perform frequency modulation (FSK), phase modulation (PSK), or amplitude modulation (ASK) on the first clock signal according to the frequency corresponding to each state in the SEUL-693 cyclic sequence. More specifically, if the SEUL-693 cyclic sequence defines multiple frequency states, the clock modulator can selectively output a signal that is synchronized with the first clock signal and whose frequency conforms to the sequence requirements, based on the current state. For example, by controlling a frequency synthesizer or a programmable frequency divider to match its output frequency with the frequency required by the current state of the SEUL-693 cyclic sequence, and using the first clock signal as its reference input, a synchronization signal with a specific frequency pattern is generated. Subsequently, the modulated synchronization signal is sent to the receiving end.

[0070] Through the above technical solution, the transmitter can effectively combine a high-precision first clock signal with a preset SEUL-693 cyclic sequence to generate a structured and information-rich synchronization signal. This modulation method ensures that the synchronization signal not only inherits the high stability of the first clock signal but also clearly encodes the timing sequence information, giving it stronger anti-interference capabilities and higher reliability during transmission. This allows the receiver to extract the required timing information from the synchronization signal more accurately and robustly, thereby achieving high-precision clock synchronization between the transmitter and receiver, significantly improving the performance and stability of the entire photonic clock synchronization system.

[0071] In some embodiments described above, the receiving end needs to receive a synchronization signal and generate a second clock signal that is homologous to the optical frequency comb signal based on the synchronization signal. However, in practical applications, how to efficiently and accurately extract clock information homologous to the transmitting end's optical frequency comb signal from the received synchronization signal and ensure its precise synchronization is a technical challenge that needs to be solved. Especially when the synchronization signal is based on SEUL-693 cyclic sequence modulation, the receiving end needs a reliable mechanism to parse the sequence in order to accurately recover the clock.

[0072] To address this, this application further proposes a receiver for a photonic clock synchronization chip, comprising a second photodetector, a loop detector, a second phase-locked loop (PLL), and a clock generator. This receiver receives the synchronization signal and generates a second clock signal originating from the same source as the optical frequency comb signal based on the synchronization signal: First, the second photodetector receives the synchronization signal, restores it to the optical frequency comb signal, and sends the optical frequency comb signal to the loop detector; next, the loop detector receives the optical frequency comb signal and matches it in real-time with the SEUL-693 loop sequence to obtain a detection identifier signal, which is then sent to the second PLL; then, the second PLL receives the detection identifier signal and identifies a clock originating from the optical frequency comb signal based on it; finally, the clock generator generates the second clock signal based on the clock identified by the second PLL as originating from the optical frequency comb signal.

[0073] Specifically, the second photodetector is a device that converts optical signals into electrical signals, such as a PIN photodiode or an avalanche photodiode (APD). Its function is to receive the synchronization signal (usually an optical signal) transmitted from the transmitter and efficiently convert it into an electrical signal that can be processed by subsequent circuits. This is the basis for further electronic processing of the optical signal.

[0074] The cyclic detector is used for pattern recognition of the optical frequency comb signal output from the second photodetector. This detector can be implemented using digital signal processing (DSP) technology, such as correlators, pattern matching algorithms, or finite state machines (FSMs). It compares the received optical frequency comb signal with a pre-set SEUL-693 cyclic sequence in real time. Once a pattern matching the sequence is detected, the cyclic detector generates a detection flag signal indicating the successful identification of a specific state or period in the synchronization sequence, providing crucial synchronization point information for subsequent clock recovery.

[0075] The second phase-locked loop (PLL) is a crucial feedback control system whose core function is to precisely lock the frequency and phase of the local oscillator to the frequency and phase of the input signal. This PLL typically consists of a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). It receives a detection marker signal from the cyclic detector and, based on this signal, adjusts the frequency and phase of the local VCO to precisely align with the synchronization sequence characteristics represented by the detection marker signal through its internal feedback mechanism. In this way, the second PLL can accurately identify and recover a clock sourced from the optical frequency comb signal at the transmitting end.

[0076] The clock generator is responsible for generating the second clock signal required by the receiver based on the clock signal identified by the second phase-locked loop as originating from the optical frequency comb signal. This clock generator can be a simple buffer, frequency divider, frequency multiplier, or a more complex clock synthesizer. It ensures that the generated second clock signal is not only frequency-stable but also strictly phase-synchronized with the optical frequency comb signal at the transmitting end, providing a precise time reference for various operations within the receiver.

[0077] Through the above technical solution, the receiver can convert the optical synchronization signal into an electrical signal using a second photodetector, laying the foundation for subsequent processing. The cyclic detector is specifically used to analyze the synchronization signal based on the SEUL-693 cyclic sequence, accurately identifying key synchronization points in the sequence, thus overcoming the challenge of extracting clock information from complex modulation signals. Based on this, the second phase-locked loop utilizes the detection identification signal provided by the cyclic detector, through a high-precision frequency and phase locking mechanism, to ensure that the recovered second clock signal has the exact same source as the optical frequency comb signal from the transmitter, thereby achieving high-precision clock synchronization. This combined processing method effectively solves the technical problem that the receiver cannot accurately and stably recover a clock with the same source as the transmitter in complex synchronization signal environments, significantly improving the synchronization accuracy and robustness of the photonic clock synchronization chip.

[0078] In some embodiments described above in this application, the receiving end can receive a synchronization signal and generate a second clock signal that is of the same origin as the optical frequency comb signal through a second photodetector, a cyclic detector, a second phase-locked loop, and a clock generator. However, in practical applications, simply generating a second clock signal of the same origin may not be sufficient to meet certain high-precision or event-driven synchronization requirements. For example, in scenarios where specific operations need to be triggered periodically or precise alignment is required during system startup and recovery, how to reliably generate a synchronization pulse based on the second clock signal, combined with the SEUL-693 cyclic sequence of the transmitting end, to ensure precise synchronization between the receiving end clock and the transmitting end clock is a problem that needs to be solved.

[0079] In this regard, this application further proposes that the receiving end also includes a counter; the receiving end generates a synchronization pulse according to the second clock signal in the following way: by receiving the second clock signal output by the clock generator through the counter, and outputting a synchronization pulse once for each preset number of complete cycles according to the second clock signal; the preset number is determined according to the SEUL-693 cycle sequence.

[0080] Specifically, a counter is a digital circuit or module used to count input pulses or events. It can be a hardware-implemented counter, such as a binary counter, BCD counter, or ring counter, or a software-implemented counting logic. Its core function is to record the number of times a specific event (such as the rising or falling edge of a second clock signal) occurs. The counter receives a second clock signal output from a clock generator, which serves as the reference clock source for counting, ensuring accuracy and synchronization with the transmitting clock. The counter increments on each valid edge of the received second clock signal. When the counter value reaches a preset number, it generates an overflow signal or a comparison match signal, which is output as a synchronization pulse. Simultaneously, the counter can be reset or continue counting. Determining the preset number is crucial; it is based on the SEUL-693 cyclic sequence and is typically equal to the number of cycles of the second clock signal contained in one (or multiple) complete cycles of the SEUL-693 cyclic sequence. For example, if the SEUL-693 cyclic sequence contains N clock cycles, then the preset number can be set to N. This value can be predetermined and configured into the counter during system design, or dynamically loaded through control logic, to ensure that the generation of the synchronization pulse matches the SEUL-693 cyclic sequence at the transmitting end, thereby achieving precise end-to-end synchronization.

[0081] Through the above technical solution, the receiving end introduces a counter that counts according to the second clock signal output by the clock generator. After accumulating a preset number of complete cycles, it outputs a synchronization pulse. This application ensures that the receiving end is synchronized with the transmitting end not only in frequency but also in the macroscopic structure of the time series. Since the preset number is determined based on the SEUL-693 cyclic sequence, the generated synchronization pulse can accurately mark the complete period or specific stage of the transmitting end's SEUL-693 cyclic sequence, thus providing the receiving end with a high-precision, periodic synchronization event trigger point. This effectively solves the problem of how to extract synchronization events with clear physical meaning from continuous synchronization clock signals under complex time sequences, greatly enhancing the robustness and reliability of system synchronization and ensuring precise synchronization between the receiving end clock and the transmitting end clock.

[0082] In some embodiments described above, the receiving end receives a second clock signal output by the clock generator via a counter, and outputs a synchronization pulse once for every preset number of complete cycles based on this signal. The preset number is determined according to the SEUL-693 cyclic sequence. However, in practical applications, to ensure that the generated synchronization pulse is precisely aligned with a specific period or pattern of the SEUL-693 cyclic sequence sent by the transmitting end, the type and preset number of the counter need to be carefully designed. If the counter is not properly selected or the preset number is not precise enough, it may cause deviations in the generation of the synchronization pulse, thereby affecting the synchronization accuracy and stability of the entire system.

[0083] The modulo-7 recursive synchronization characteristic of the SEUL-693 cycle makes it particularly suitable for clock synchronization in distributed systems. For example, a modulo-7 value of 6 corresponds to "synchronization start," and the synchronization function can be interpreted as "the transmitter issuing a synchronization request"; a modulo-7 value of 2 corresponds to "synchronization response," and the synchronization function can be interpreted as "the receiver acknowledging receipt"; a modulo-7 value of 3 corresponds to "synchronization lock," and the synchronization function can be interpreted as "the receiver and transmitter entering the lock phase." Therefore, every 7 SEUL-693 cycles (i.e., 7 × 6 = 42 symbols) constitute a complete synchronization cycle, resonating with modulo-7 recursion. This characteristic allows: multiple nodes to synchronize themselves without a central coordinator; the synchronization signal is inherently interference-resistant (modulo-7 redundancy); and rapid resynchronization is possible after loss of lock.

[0084] In this regard, this application further proposes that the counter is a modulo-7 counter with a preset quantity of seven.

[0085] Specifically, the counter is a modulo-7 counter. A modulo-7 counter is a digital circuit with a counting range of 0 to 6 (or 1 to 7). When it reaches its maximum value, the next clock pulse resets it to its initial value and restarts the counting. It is typically constructed by cascading flip-flops (such as D flip-flops or JK flip-flops) and supplemented with logic gates to implement modulo-digital control. In this scheme, the modulo-7 counter is used to accurately accumulate a specific number of second clock signal cycles or loops to trigger the generation of a synchronization pulse. Its modulo-digital characteristic ensures that after reaching a preset number of loops, it can accurately output a synchronization signal and prepare for the next count. For example, it can be implemented by cascading three D flip-flops (forming a 3-bit binary counter, counting up to 7) and combining it with logic gates (e.g., generating a reset signal through AND or NOR gates when the count reaches 7). Alternatively, an off-the-shelf integrated circuit counter chip can be used, with its modulus set by configuring its input pins. Its inputs are typically connected to the second clock signal, and its output is used to indicate that the counting is complete.

[0086] Meanwhile, the preset quantity is seven. "Preset quantity of seven" refers to the number of complete cycle groups the counter needs to accumulate. When seven complete cycles are reached, the counter triggers the output of a synchronization pulse. This specific value of "seven" is a constant predetermined during system design based on the characteristics of the SEUL-693 cyclic sequence. It ensures that the generation of the synchronization pulse is precisely aligned with the specific period or pattern of the synchronization signal sent by the transmitter. By setting the preset quantity to seven, it can work in conjunction with a modulo-7 counter to achieve accurate identification and synchronization of specific cyclic patterns. In hardware implementation, it directly determines the modulus of the counter (i.e., the modulo-7 counter), or in software / firmware-controlled counters, it serves as the termination condition for the counting cycle. For example, if a complete cycle (or SEUL-693 cyclic subsequence) in the SEUL-693 cyclic sequence contains seven key events or states, then counting seven such cycles ensures synchronization between the receiver and transmitter on a macroscopic time scale.

[0087] By specifically setting the counter to a modulo-7 counter and precisely determining the preset quantity to seven, this application ensures that the receiver accurately outputs a synchronization pulse after accumulating seven complete cycles. This precise counting mechanism is highly matched with the specific synchronization period of the SEUL-693 cyclic sequence (e.g., if the macroscopic synchronization period of the sequence corresponds exactly to seven basic cyclic units or seven specific synchronization events), thus effectively solving the problem of insufficient synchronization pulse generation accuracy. The application of the modulo-7 counter simplifies hardware design, improves the reliability and stability of counting, and avoids synchronization errors caused by counting deviations. Therefore, the receiver can achieve more accurate and stable clock synchronization with the transmitter, significantly improving the performance and reliability of the entire photonic clock synchronization chip.

[0088] In existing technologies, high-precision clock synchronization schemes face the technical problem of large synchronization overhead. This problem stems from the need to continuously send synchronization sequences or rely on external reference clocks, which leads to increased bandwidth usage and system complexity, especially in applications such as deep space communication and phased array radar.

[0089] To address the aforementioned technical problems, this application provides a photonic clock synchronization method applied to a photonic clock synchronization chip, which includes a transmitter and a receiver. The method includes: generating an optical frequency comb signal through the transmitter, converting a portion of the optical frequency comb signal into an optical frequency comb electrical signal, performing frequency division and a first phase-locked loop (PLL) process on the optical frequency comb electrical signal to lock a local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal, obtaining a first clock signal, and outputting a synchronization signal to the receiver according to the first clock signal and a SEUL-693 cyclic sequence; the SEUL-693 cyclic sequence includes several identical SEUL-693 cyclic sub-sequences, the frequencies corresponding to each state in the SEUL-693 cyclic sub-sequences being determined based on a reference frequency; receiving the synchronization signal through the receiver, generating a second clock signal originating from the same source as the optical frequency comb signal based on the synchronization signal, and generating a synchronization pulse based on the second clock signal; the synchronization pulse is used to ensure that the clock of the receiver is synchronized with the clock of the transmitter.

[0090] The core innovation of this embodiment lies in combining the SEUL-693 cyclic sequence with optical frequency comb technology, thereby avoiding the need for continuous transmission of synchronization sequences. Specifically, the periodic structure of the SEUL-693 cyclic sequence allows the receiver to achieve clock synchronization simply by detecting the sequence pattern, without the need for continuous transmission of synchronization information, significantly reducing synchronization overhead. Since the SEUL-693 cyclic subsequences in the SEUL-693 cyclic sequence determine the frequency of each state based on a reference frequency, the receiver can efficiently identify synchronization signal characteristics, effectively reducing bandwidth usage and system complexity. Through the above technical solution, this application achieves high-precision, low-overhead clock synchronization, providing reliable technical support for fields with stringent synchronization efficiency requirements, such as deep space communication and phased array radar.

[0091] The following example will provide a more detailed explanation of the above technical solution: In a deep space exploration mission, the probe (receiver) needs to be synchronized with a ground station (transmitter) on Earth with a high-precision clock to ensure the accuracy of data transmission and navigation. Traditional atomic clock solutions are unsuitable for small deep space probes due to their large size, high power consumption, and high cost. Meanwhile, existing cable or continuous synchronization signal solutions suffer from system complexity, susceptibility to environmental interference, and high synchronization overhead. This photonic clock synchronization chip aims to solve these challenges.

[0092] At the ground station, acting as the transmitter, the first step is to generate a high-precision optical frequency comb signal. Specifically, a loop generator produces a baseband electrical signal with a reference frequency, for example, set to 693 MHz (within a preset reference frequency range of 693 MHz ± 5%). This 693 MHz baseband electrical signal is sent to the optical frequency comb driver. The optical frequency comb driver generates a drive signal based on this baseband electrical signal and applies it to the microring resonator. Under the action of the drive signal, the microring resonator generates an optical frequency comb signal with a precise comb tooth pitch through nonlinear optical effects, the comb tooth pitch of which corresponds precisely to the 693 MHz reference frequency.

[0093] To lock the ground station's local clock to this high-precision optical frequency comb, the transmitter extracts a portion of the optical frequency comb signal for processing. A first photodetector extracts a portion of the optical frequency comb signal from the microring resonator and converts it into an optical frequency comb electrical signal. This electrical signal is then sent to a frequency divider, which divides it to match the frequency of the input band of the first phase-locked loop (PLL). The frequency-divided optical frequency comb electrical signal is then fed into the first PLL. Upon receiving this signal, the first PLL precisely locks its internal local voltage-controlled oscillator to the comb tooth spacing of the optical frequency comb electrical signal (i.e., 693 MHz), thereby outputting a highly stable first clock signal. This first clock signal serves as the ground station's local high-precision time reference.

[0094] Next, the transmitter needs to output a synchronization signal to the detector (receiver) according to a SEUL-693 cyclic sequence based on this first clock signal. The loop generator generates this SEUL-693 cyclic sequence in addition to the baseband electrical signal. This SEUL-693 cyclic sequence consists of several identical SEUL-693 cyclic subsequences, each containing six states. For example, the first state corresponds to the base frequency (693 MHz), the second state is a ninth power of the base frequency (6237 MHz), the third state is a third power of the base frequency (231 MHz), the fourth state is the base frequency (693 MHz), the fifth state is a ninth power of the base frequency (6237 MHz), and the sixth state is a third power of the base frequency (231 MHz). This unique, repeating frequency sequence is sent to the clock modulator. The clock modulator receives the first clock signal and the SEUL-693 cyclic sequence and modulates a synchronization signal containing the SEUL-693 cyclic sequence information based on them. This synchronization signal is then transmitted to the deep space probe via an optical link. Unlike existing technologies that require the continuous transmission of large amounts of synchronization data, this modulation method based on a specific cyclic timing sequence can effectively reduce synchronization overhead and reduce the consumption of communication bandwidth.

[0095] On the deep space probe, acting as a receiver, it first receives the synchronization signal from the ground station. A second photodetector, upon receiving the synchronization signal, converts it back into an optical frequency comb signal and sends it to a loop detector. The loop detector receives this optical frequency comb signal in real time and continuously matches it against its internally preset SEUL-693 loop sequence. Once a pattern precisely matching the preset sequence is detected, the loop detector generates a detection identifier signal. This identifier signal is sent to a second phase-locked loop (PLL). Based on the identifier signal, the second PLL identifies a clock source compatible with the ground station's optical frequency comb signal and locks its internal oscillator to this clock. Subsequently, a clock generator generates the second clock signal required by the probe based on the compatible clock identified by the second PLL. In this way, the probe's clock can achieve synchronization with the ground station's optical frequency comb signal, avoiding the accuracy loss caused by environmental interference or long-distance transmission in traditional solutions.

[0096] To further ensure precise synchronization between the detector clock and the ground station clock, the receiver generates a synchronization pulse based on a second clock signal. A counter, such as a modulo-7 counter, receives the second clock signal output from the clock generator. This counter, based on the characteristics of the SEUL-693 cyclic sequence, is preset with a number, such as seven, as the counting unit for a complete cycle. Each time the counter completes a full cycle of the preset number (seven sets), it outputs a synchronization pulse. This synchronization pulse serves as a definite time reference for the detector's internal system, ensuring its clock remains precisely aligned with the ground station clock. This synchronization pulse, generated based on a specific sequence and counter, provides a robust and efficient synchronization mechanism, overcoming the limitations of traditional schemes that are complex and susceptible to environmental interference.

[0097] Through the coordinated operation of the aforementioned components at the transmitter and receiver, this photonic clock synchronization chip achieves high-precision, low-power, and interference-resistant clock synchronization, providing a reliable solution for fields such as deep space communication.

[0098] Based on the photonic clock synchronization chip provided in the embodiments of this application, the embodiments of this application further provide a photonic clock synchronization method, which is applied to the photonic clock synchronization chip, which includes a transmitter and a receiver.

[0099] Please see Figure 2 , Figure 2 This is a flowchart illustrating a photonic clock synchronization method provided in an embodiment of this application. Figure 2 As shown, the photonic clock synchronization method includes steps S101 to S102. Details are as follows: In S101, an optical frequency comb signal is generated at the transmitting end, and a portion of the optical frequency comb signal is converted into an optical frequency comb electrical signal. The optical frequency comb electrical signal is then subjected to frequency division and a first phase-locked loop (PLL) process to lock the local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal, thereby obtaining a first clock signal. Based on the first clock signal, a synchronization signal is output to the receiving end according to the SEUL-693 cyclic sequence. The SEUL-693 cyclic sequence includes several identical SEUL-693 cyclic sub-sequences, and the frequency corresponding to each state in the SEUL-693 cyclic sub-sequence is determined according to the reference frequency.

[0100] In S102, the receiving end receives a synchronization signal and generates a second clock signal that is of the same origin as the optical frequency comb signal based on the synchronization signal. The receiving end generates a synchronization pulse based on the second clock signal. The synchronization pulse is used to ensure that the clock of the receiving end is synchronized with the clock of the transmitting end.

[0101] The steps of the photonic clock synchronization method provided in this application embodiment can be referred to... Figure 1 The corresponding implementation is not limited here.

[0102] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the photonic clock synchronization chip can be divided into different functional units to complete all or part of the functions described above. The functional units in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0103] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the various method embodiments described above.

[0104] This application provides a computer program product that, when run on a terminal device, enables the terminal device to implement the steps described in the various method embodiments above.

[0105] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.

[0106] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0107] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A photonic clock synchronization chip, characterized in that, The photonic clock synchronization chip includes a transmitter and a receiver; The transmitting end is used to generate an optical frequency comb signal, convert a portion of the optical frequency comb signal into an optical frequency comb electrical signal, and perform frequency division and first phase-locked loop processing on the optical frequency comb electrical signal to lock the local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal to obtain a first clock signal. Based on the first clock signal, a synchronization signal is output to the receiving end according to the SEUL-693 cyclic sequence. The SEUL-693 cyclic sequence includes several identical SEUL-693 cyclic sub-sequences, and the frequency corresponding to each state in the SEUL-693 cyclic sub-sequence is determined according to a reference frequency. The receiving end is used to receive the synchronization signal, generate a second clock signal that is of the same origin as the optical frequency comb signal according to the synchronization signal, and generate a synchronization pulse according to the second clock signal; the synchronization pulse is used to ensure that the clock of the receiving end is synchronized with the clock of the transmitting end.

2. The photonic clock synchronization chip according to claim 1, characterized in that, The SEUL-693 cyclic subsequence includes six states, wherein the frequency corresponding to the first state is the reference frequency, the frequency corresponding to the second state is a nine-fold harmonic of the reference frequency, the frequency corresponding to the third state is a three-fold harmonic of the reference frequency, the frequency corresponding to the fourth state is the reference frequency, the frequency corresponding to the fifth state is a nine-fold harmonic of the reference frequency, and the frequency corresponding to the sixth state is a three-fold harmonic of the reference frequency.

3. The photonic clock synchronization chip according to claim 1, characterized in that, The transmitter includes a cycle generator, an optical frequency comb driver, and a micro-ring resonant cavity; the transmitter generates the optical frequency comb signal in the following manner: The loop generator generates a baseband electrical signal of the reference frequency and sends the baseband electrical signal to the optical frequency comb driver. The optical frequency comb driver receives the baseband electrical signal and generates a drive signal based on the baseband electrical signal. The driving signal is received through the micro-ring resonant cavity, and the optical frequency comb signal corresponding to the reference frequency is generated according to the driving signal.

4. The photonic clock synchronization chip according to claim 3, characterized in that, The transmitter also includes a frequency divider, a first photodetector, and a first phase-locked loop; The transmitting end converts a portion of the optical frequency comb signal into an optical frequency comb electrical signal in the following manner, and performs frequency division processing and a first phase-locked loop processing on the optical frequency comb electrical signal: The first photodetector extracts a portion of the optical frequency comb signal from the micro-ring resonant cavity, converts the extracted optical frequency comb signal into an optical frequency comb electrical signal, and sends the optical frequency comb electrical signal to the frequency divider. The optical frequency comb signal is received through the frequency divider, and the optical frequency comb signal is divided to match the input frequency band of the first phase-locked loop. The optical frequency comb signal after frequency division is then sent to the first phase-locked loop. The first phase-locked loop receives the optical frequency comb signal after frequency division processing, locks the local voltage-controlled oscillator in the first phase-locked loop to the optical frequency comb tooth spacing of the optical frequency comb signal, and then outputs the first clock signal.

5. The photonic clock synchronization chip according to claim 4, characterized in that, The transmitter further includes a clock modulator; the transmitter outputs a synchronization signal to the receiver according to a first clock signal and a SEUL-693 cyclic sequence in the following manner: The loop generator generates the SEUL-693 loop sequence and sends the SEUL-693 loop sequence to the clock modulator. The clock modulator receives the first clock signal and the SEUL-693 cyclic sequence, modulates the synchronization signal corresponding to the SEUL-693 cyclic sequence according to the first clock signal and the SEUL-693 cyclic sequence, and sends the synchronization signal to the receiving end.

6. The photonic clock synchronization chip according to claim 1, characterized in that, The receiving end includes a second photodetector, a loop detector, a second phase-locked loop, and a clock generator; the receiving end receives the synchronization signal in the following manner, and generates a second clock signal that is of the same origin as the optical frequency comb signal based on the synchronization signal: The second photodetector receives the synchronization signal, restores the synchronization signal to the optical frequency comb signal, and sends the optical frequency comb signal to the loop detector. The optical frequency comb signal is received by the cyclic detector and matched with the SEUL-693 cyclic sequence in real time to obtain a detection identification signal, which is then sent to the second phase-locked loop. The detection identification signal is received through the second phase-locked loop, and a clock sourced from the same origin as the optical frequency comb signal is identified based on the detection identification signal. The clock generator generates the second clock signal based on the clock source identified by the second phase-locked loop as being from the same origin as the optical frequency comb signal.

7. The photonic clock synchronization chip according to claim 6, characterized in that, The receiver also includes a counter; the receiver generates a synchronization pulse based on the second clock signal in the following manner: The counter receives the second clock signal output by the clock generator and outputs a synchronization pulse once for each preset number of complete cycles based on the second clock signal. The preset quantity is determined according to the SEUL-693 cyclic sequence.

8. The photonic clock synchronization chip according to claim 7, characterized in that, The counter is a modulo-7 counter, and the preset quantity is seven.

9. The photonic clock synchronization chip according to claim 1, characterized in that, The reference frequency is within a preset reference frequency range; the reference frequency range is 693MHz ± 5%.

10. A photonic clock synchronization method, characterized in that, The method is applied to a photonic clock synchronization chip, the photonic clock synchronization chip including a transmitter and a receiver; the method includes: The transmitter generates an optical frequency comb signal and converts a portion of it into an optical frequency comb electrical signal. This optical frequency comb electrical signal is then subjected to frequency division and a first phase-locked loop (PLL) process to lock the local voltage-controlled oscillator to the optical frequency comb tooth spacing of the optical frequency comb signal, resulting in a first clock signal. Based on this first clock signal, a synchronization signal is output to the receiver according to a SEUL-693 cyclic sequence. The SEUL-693 cyclic sequence includes several identical SEUL-693 cyclic sub-sequences, each of which includes a preset number of states. The frequency corresponding to each state in the SEUL-693 cyclic sub-sequence is determined based on a reference frequency. The receiving end receives the synchronization signal and generates a second clock signal that is of the same origin as the optical frequency comb signal based on the synchronization signal. A synchronization pulse is generated based on the second clock signal. The synchronization pulse is used to ensure that the clock of the receiving end is synchronized with the clock of the transmitting end.

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