Domain controller and vehicle-mounted device

Abstract

The application discloses a domain controller and a vehicle-mounted device, and relates to the technical field of time synchronization of vehicle-mounted devices. The domain controller comprises a second pulse component, a microprocessor, a baseband processor and an application processor. The second pulse component receives a first second pulse signal of an external time source component. The microprocessor performs frequency division processing on the first second pulse signal of the second pulse component to obtain a second second pulse signal and sends the second second pulse signal to the application processor. The baseband processor receives a time synchronization message, analyzes the time synchronization message to obtain second time information, and sends the second time information to the application processor. The application processor generates first time information according to the second second pulse signal, corrects the second time information according to the first time information to obtain third time information, and sends the third time information to the baseband processor. The baseband processor updates time information in the time synchronization message according to the third time information to obtain an updated time synchronization message and sends the updated time synchronization message. The application achieves the effects of reducing hardware cost and realizing high-precision time synchronization.

Description

Technical Field

[0001] This application relates to the field of time synchronization technology for in-vehicle equipment, and more particularly to a domain controller and in-vehicle equipment. Background Technology

[0002] In the context of vehicle-to-everything (V2X) scenarios, different ECUs (Electronic Control Units) on the vehicle need to cooperate with each other to complete advanced intelligent driving services. User plane data and control plane messages are transmitted between different ECUs, requiring time synchronization with sufficiently high accuracy.

[0003] In related technologies, time synchronization is mainly achieved through a pure hardware solution at the MAC / PHY layer of the automotive communication domain controller, or through a pure software solution at the AP layer. The problems with these solutions are: the pure hardware implementation requires the hardware chip to support the AS protocol at the MAC / PHY layer, which places high demands on the hardware and leads to high hardware costs; compared to the pure hardware implementation, the pure software implementation has lower time synchronization accuracy and makes it difficult to ensure real-time time synchronization. Summary of the Invention

[0004] The main purpose of this application is to provide a domain controller and vehicle-mounted equipment, which aims to solve the technical problems of high hardware cost and limited synchronization accuracy in the time synchronization scheme of vehicle-mounted equipment in related technologies.

[0005] To at least achieve the above objectives, embodiments of this application propose a domain controller, including a second pulse component, a microprocessor, a baseband processor, and an application processor; The second pulse component is used to receive the first second pulse signal from an external time source component; The microprocessor is used to receive the first second pulse signal sent by the second pulse component, perform frequency division processing on the first second pulse signal to obtain the second second pulse signal, and send it to the application processor; The baseband processor is used to receive time synchronization messages and parse the time synchronization messages to obtain second time information, and then send the second time information to the application processor. The application processor is used to generate first time information based on the second second pulse signal, correct the second time information based on the first time information to obtain third time information, and send the third time information to the baseband processor; The baseband processor is also used to obtain an updated time synchronization message based on the time information in the time synchronization message updated by the third time information, and to send the updated time synchronization message.

[0006] In addition, to at least achieve the above objectives, embodiments of this application also propose an in-vehicle device, including the domain controller as described above.

[0007] This application discloses a domain controller, including a second pulse component, a microprocessor, a baseband processor, and an application processor. For each hardware component in this domain controller, support for the AS protocol is not mandatory, reducing the hardware requirements and thus lowering hardware costs. On one hand, the microprocessor performs frequency division processing on the first second pulse signal sent by the second pulse component and sends a second second pulse signal to the application processor, enabling the application processor to generate first time information based on the second second pulse signal, forming a high-precision hardware time stamp. On the other hand, the baseband processor receives and parses the time synchronization message and sends the second time information to the application processor. The application processor corrects the second time information based on the first time information to obtain third time information and sends it to the baseband processor, enabling the baseband processor to update the time information in the time synchronization message based on the third time information, obtaining an updated time synchronization message and sending it out. This update of the time information in the message is achieved by executing a software program. In this domain controller, a software-hardware collaborative processing approach is used to achieve high-precision time synchronization, reaching the synchronization accuracy of pure hardware solutions in related technologies, but without being limited by the high requirements of hardware chips. This greatly expands the scope of application of this method and facilitates subsequent business iteration updates and reuse. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a connection diagram of the first embodiment of the domain controller in this application; Figure 2 This is a schematic diagram of signal flow provided in the first embodiment of the domain controller of this application; Figure 3 This is a schematic flowchart illustrating the method for time synchronization in the first embodiment of the domain controller of this application; Figure 4 A schematic diagram of a system architecture for a domain controller provided in an embodiment of this application; Figure 5 A schematic diagram of the time synchronization method involved in the domain controller application example provided in the embodiments of this application; Figure 6 The diagram illustrates a specific interaction example of time synchronization implemented in the domain controller application example provided in this application embodiment.

[0011] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0012] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application. To better understand the technical solutions of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0013] In the context of vehicle-to-everything (V2X) scenarios, different ECUs (Electronic Control Units) on the vehicle need to cooperate to complete advanced intelligent driving services. User plane data and control plane messages are transmitted between different ECUs, requiring time synchronization with sufficiently high accuracy to ensure the effectiveness of the data and messages for service execution.

[0014] In related technologies, time synchronization is mainly achieved through a pure hardware solution at the MAC (Media Access Control) layer / PHY (Physical) layer of the vehicle's communication domain controller, or through a pure software solution at the AP (Application Layer). The problems with these solutions are: The pure hardware implementation at the MAC / PHY layer requires the hardware chip to support the AS (Ethernet Frame Format) protocol at that layer, resulting in high hardware requirements and costs. Furthermore, when such a chip is used in a product, it binds the product to that chip throughout its entire lifecycle, leading to a strong binding and high coupling between the entire system and a single component, thus failing to meet the decoupling design requirements of certain components in practical applications. Additionally, the protocols supported by this hardware chip are locked, preventing continuous iteration based on different usage scenarios. If a new time synchronization protocol is added later, business updates will be limited by the hardware chip, thus restricting its applicability. The pure software implementation at the AP layer can only achieve millisecond-level synchronization. Compared to the pure hardware implementation, the software implementation has lower time synchronization accuracy and struggles to ensure real-time time synchronization. It is evident that current time synchronization solutions for in-vehicle devices in related technologies cannot yet achieve a balance between hardware cost and time synchronization accuracy.

[0015] To address the issues of high hardware cost and limited synchronization accuracy in existing time synchronization solutions for in-vehicle devices, this application provides a solution, specifically proposing a domain controller and an in-vehicle device containing the domain controller. The following provides a detailed description of this embodiment and subsequent embodiments.

[0016] This application provides a domain controller.

[0017] It should be noted that a domain controller is a high-performance computing platform that centrally manages the previously dispersed and independent ECUs in a vehicle according to their functional areas. It is the core hardware that supports functions such as in-vehicle network communication, time synchronization, and V2X (Vehicle to Everything). In the embodiments of this application, the domain controller can be a communication domain controller, intelligent driving domain controller, in-vehicle communication module, OBU (On-Board Unit), etc., in the context of vehicle networking.

[0018] In the first embodiment of the domain controller of this application, reference is made to Figure 1 , Figure 1 This is a connection diagram of this embodiment. The domain controller may include a second pulse component, a microprocessor, a baseband processor, and an application processor. The second pulse component is connected to an external timing source component, the microprocessor is connected to the second pulse component, and the application processor is connected to both the microprocessor and the baseband processor.

[0019] The system includes a second pulse component for receiving the first second pulse signal from an external time synchronization source component; a microprocessor for receiving the first second pulse signal from the second pulse component and performing frequency division processing on the first second pulse signal to obtain a second second pulse signal, which is then sent to the application processor; a baseband processor for receiving and parsing a time synchronization message to obtain second time information, which is then sent to the application processor; an application processor for generating first time information based on the second second pulse signal, correcting the second time information based on the first time information to obtain third time information, and sending the third time information to the baseband processor; and a baseband processor for updating the time information in the time synchronization message based on the third time information to obtain an updated time synchronization message, which is then sent to the baseband processor.

[0020] It should be noted that the second pulse component refers to the component used to carry the external input PPS (Pulse Per Second) signal. Specifically, it can be a hardware module used to receive and forward the PPS signal, such as a dedicated pulse shaping circuit, buffer, or optocoupler. An external time synchronization source component refers to a component used to carry external time synchronization sources. Specifically, it can be a hardware module that acquires time information from different external time synchronization sources. An external time synchronization source is an external device or system that can provide a standard time reference, such as GNSS (Global Navigation Satellite System), NITZ (Network Identity and Time Zone), NTP (Network Time Protocol), SNTP (Simple Network Time Protocol), PTP (Precision Time Protocol), high-precision RTC (Real-Time Clock) systems, IRIG-B code systems, etc. Correspondingly, the external time synchronization source component can be a GNSS receiver, NITZ server, NTP server, SNTP server, PTP server, high-precision RTC or IRIG-B code time synchronization device, etc. The first-second pulse signal refers to the pulse signal generated once per second by the external time synchronization source component, used to represent precise second boundary times.

[0021] When the second pulse component receives the first-second pulse signal from an external time synchronization source component, it can directly connect to the pulse output terminal of the external time synchronization source component via a hardware interface to receive the PPS signal in level form as the first-second pulse signal. Alternatively, it can first perform level conversion, isolation, or shaping on the signal output from the external time synchronization source component to enhance the signal's anti-interference and driving capabilities, and then receive the processed PPS signal as the first-second pulse signal. After receiving the first-second pulse signal, the second pulse component can directly forward the signal to the microprocessor, or it can buffer, amplify, or perform other processing on the signal as needed to adapt to the microprocessor's signal quality requirements before sending it to the microprocessor.

[0022] Understandably, by using a dedicated second pulse component to receive the first second pulse signal output by an external time synchronization source component, direct coupling between the external time synchronization source component and other modules within the domain controller can be avoided, thus improving signal stability and reliability. This design eliminates the need for all hardware components of the domain controller to support the AS protocol, reducing the hardware requirements of the domain controller and thereby lowering hardware costs. It also provides a pulse source for subsequent high-precision hardware time stamping.

[0023] It should also be noted that a microprocessor refers to a controller that provides frequency division processing logic, such as a MCU (Microcontroller Unit), FPGA (Field Programmable Gate Array), or PLC (Programmable Logic Controller). Frequency division processing refers to the process of reducing or increasing the frequency of an input signal by a certain ratio to obtain a signal of the desired frequency. This can be implemented using hardware logic such as counters, phase-locked loops, or timers. The second-second pulse signal refers to a pulse signal with a shorter period than the first-second pulse signal obtained after frequency division processing. For example, a pulse signal that occurs once per second is divided into pulse signals that occur once every x milliseconds (ms). Here, x can be set according to the data update rate requirements in the time synchronization protocol and is not specifically limited here.

[0024] For example, the microprocessor can be an ARM Cortex-M core processor (M-Core for short). The OS (Operating System) carried by the M-Core can be an RTOS (Real-Time Operating System) to ensure the real-time performance and non-preemptive nature of the frequency division operation. The M-Core can divide the pulse signal once per second, i.e., the first pulse signal, into a pulse signal of 125ms / time, i.e., the second pulse signal. In a further example, in order to improve accuracy, the frequency can be further divided, for example, into a pulse signal of 50ms / time.

[0025] After receiving the first second pulse signal sent by the second pulse component, the microprocessor can use an internal timer or counter to divide the first second pulse signal. For example, by configuring the counter overflow value, the 1Hz (Hertz) second pulse signal can be converted into an 8Hz pulse signal, that is, a pulse is generated every 125ms. The second second pulse signal obtained after frequency division can be output by the microprocessor's general-purpose input / output pins, or it can be sent to the application processor through a dedicated timer output channel.

[0026] Understandably, by dividing the first-second pulse signal by a microprocessor to provide a higher-frequency second-second pulse signal to the application processor, the application processor can generate time information with finer time granularity. This design utilizes the programmability of the microprocessor, making it easy to flexibly adjust the frequency division parameters according to the data update rate requirements of different time synchronization protocols. On the other hand, the second-second pulse signal obtained by the microprocessor's frequency division serves as the trigger source for hardware time stamping, forming the basis for high-precision hardware time stamping.

[0027] It should also be noted that BP (Baseband Processor) refers to the component used for handling the input and output of time synchronization messages. Specifically, it can be a hardware module used to process baseband signals in the communication protocol stack, such as a cellular communication module, a vehicle-to-everything (V2X) communication unit, or an ASIC (Application Specific Integrated Circuit). Time synchronization messages are network messages carrying time synchronization information, such as the sync message and follow-up message in the IEEE 802.1as protocol. Secondary time information refers to the time-synchronization related field data parsed from the time synchronization message, such as correction fields and precise origin timestamp fields, which can be obtained by parsing the message header or payload.

[0028] When the baseband processor receives a time synchronization message, it can obtain it from the external network through the physical layer interface. When the baseband processor parses the time synchronization message, it can extract the time-related fields carried in the message, such as the correction field field and the precise origin timestamp field. The time information contained in these fields is the second time information. When the baseband processor sends the second time information to the application processor, it can transmit it through the internal high-speed bus, shared memory, or message queue to ensure the real-time nature of information transmission.

[0029] Understandably, by receiving time synchronization messages and parsing the second time information through the baseband processor, key data related to time calculation can be extracted from the time synchronization messages, providing input for the application processor to perform subsequent correction calculations. This design allows the baseband processor to only receive messages and parse fields without participating in complex time synchronization algorithms, reducing the functional complexity of the baseband processor while ensuring the accuracy and timeliness of time information extraction.

[0030] It should also be noted that the AP (Application Processor) refers to the main component that carries the high-precision time synchronization processing software program. Specifically, it can be a hardware module with strong computing power and a robust software operating environment, such as a processor based on the ARM Cortex-A series core or an x86 architecture processor. The application processor's operating system can be an embedded Linux system to provide powerful computing capabilities. The first time information refers to the high-precision timestamp information generated by the application processor based on the second-second pulse signal, such as the local hardware time obtained by latching the arrival time of the second-second pulse signal using a timer. The third time information refers to the updated time information obtained by the application processor after correcting the second time information based on the first time information, such as an updated correction threshold value.

[0031] When the application processor generates the first time information based on the second-second pulse signal, it can read the current time value latched by the internal timer as the first time information after the second-second pulse signal triggers an interrupt. When the application processor corrects the second time information based on the first time information, it can perform a preset time synchronization algorithm, such as calculating the correction field value in the second time information based on the first time information, to obtain the updated correction field value, which is the third time information. When the application processor sends the third time information to the baseband processor, it can transmit the updated time information to the baseband processor through the internal communication interface so that the baseband processor can encapsulate and send the message.

[0032] Understandably, by generating the first time information based on the second-second pulse signal through the application processor, high-precision hardware time stamping is achieved, ensuring the accuracy of the timestamp. At the same time, the application processor corrects the second time information through software to obtain the third time information. This allows for time information updates without relying on dedicated hardware chips, reducing the hardware requirements of the domain controller and facilitating subsequent business iteration updates and reuse.

[0033] Additionally, it should be noted that updating the time information in the time synchronization message refers to replacing the original time-related fields in the parsed time synchronization message with the corrected parameter values. For example, updating the correction field value of the correction field to the correction field value in the third time information. The third time information can be the entire field containing the time information in the time synchronization message. After the application processor sends the third time information to the baseband processor, the baseband processor updates the entire field of the time information in the time synchronization message based on the third time information. The updated time synchronization message refers to a complete message that conforms to the time synchronization protocol format after the field replacement is completed, and it can continue to be transmitted in the time synchronization network.

[0034] After receiving the third time information sent by the application processor, the baseband processor can update the previously parsed time synchronization message according to the third time information. For example, it can write the correction field value in the third time information into the corresponding field position of the original message. When the baseband processor sends out the updated time synchronization message, it can send the message to the external network through the physical layer interface, such as to other ECUs in the vehicle or network-side time synchronization conversion devices such as NW-TT (Network-Side TSN Translator).

[0035] Understandably, by updating the time information in the time synchronization message based on the third-party time information and sending the updated time synchronization message through the baseband processor, the correction and forwarding functions of the time synchronization message are realized. The domain controller adopts a software and hardware collaborative processing method to achieve high-precision time synchronization, which can achieve the synchronization accuracy of pure hardware solutions in related technologies, but is not limited by the high requirements of hardware chips. This greatly expands the scope of application of the method and facilitates subsequent business iteration updates and reuse.

[0036] like Figure 2 The diagram shown is a schematic representation of the signal flow provided in this embodiment. Figure 3 The diagram shown is a flowchart illustrating the method for implementing time synchronization using a domain controller in this embodiment. Figure 2 and Figure 3 The specific working process of the domain controller implementing time synchronization in this embodiment, i.e., the time synchronization method, may include steps S1 to S7: Step S1: The external timing source component sends the first second pulse signal to the second pulse component; Step S2: After receiving the first second pulse signal, the second pulse component forwards the first second pulse signal to the microprocessor. Step S3: The microprocessor receives the first second pulse signal sent by the second pulse component, performs frequency division processing on the first second pulse signal to obtain the second second pulse signal, and sends it to the application processor. Step S4: After receiving the time synchronization message, the baseband processor parses the time synchronization message to obtain the second time information and sends it to the application processor. Step S5: The application processor generates first time information based on the second second pulse signal; Step S6: The application processor corrects the second time information based on the first time information to obtain the third time information, and sends the third time information to the baseband processor. Step S7: The baseband processor updates the time information in the time synchronization message according to the third time information, obtains the updated time synchronization message, and sends the updated time synchronization message to the outside.

[0037] This embodiment provides a domain controller, including a second pulse component, a microprocessor, a baseband processor, and an application processor. Support for the AS protocol is not mandatory for any of the hardware components in this domain controller, reducing hardware requirements and thus lowering hardware costs. On one hand, the microprocessor performs frequency division processing on the first second pulse signal sent by the second pulse component and sends a second second pulse signal to the application processor. The application processor then generates first time information based on the second second pulse signal, forming a high-precision hardware time stamp. On the other hand, the baseband processor receives and parses the time synchronization message and sends the second time information to the application processor. The application processor corrects the second time information based on the first time information to obtain third time information and sends it to the baseband processor. The baseband processor then updates the time information in the time synchronization message based on the third time information, obtaining an updated time synchronization message and sending it out. This software program execution achieves the update of time information in the message, thus realizing time synchronization. This domain controller employs a hardware-software collaborative processing approach to achieve high-precision time synchronization, reaching the synchronization accuracy of pure hardware solutions in related technologies, but without being limited by the high demands of hardware chips. This greatly expands the scope of application of this method and facilitates subsequent business iteration updates and reuse.

[0038] In one feasible implementation, refer to Figure 4 , Figure 4 This is a schematic diagram of a system architecture for a domain controller provided in this embodiment. The microprocessor can specifically set up a software module, which is a frequency division processing module.

[0039] The frequency division processing module is configured to receive the first second pulse signal sent by the second pulse component, perform frequency division processing on the first second pulse signal to obtain the second second pulse signal, and send it to the application processor.

[0040] It should be noted that the frequency division processing module refers to the software logic unit inside the microprocessor used to perform frequency division processing. For example, it can be an independent software task, an interrupt service subroutine, or a firmware module running on the microprocessor. The frequency division processing module is responsible for frequency conversion of the input first-second pulse signal and outputting a higher-frequency second-second pulse signal to meet the application processor's requirement for a shorter time interval trigger signal.

[0041] In an exemplary implementation, after receiving the first-second pulse signal sent by the second pulse component, the frequency division processing module can count and divide the pulse signal using a timer or counter inside the microprocessor. For example, the counter can be set to generate an output pulse every time it accumulates to a preset value, thereby converting the 1s / time first-second pulse signal into a 125ms / time second-second pulse signal. The frequency division processing module can also adjust the frequency division coefficient according to actual needs to change the period of the second-second pulse signal, and send the generated second-second pulse signal to the application processor through the output pin or internal channel of the microprocessor.

[0042] In this embodiment, by setting up a frequency division processing module inside the microprocessor and implementing pulse frequency division in software, the frequency division coefficient can be flexibly configured according to the requirements of different time synchronization protocols, thereby improving flexibility and scalability. At the same time, the frequency division processing module provides the second-second pulse signal after frequency division to the application processor, providing a reliable trigger source for the application processor to generate a high-precision hardware timestamp, thus ensuring the accuracy of subsequent time synchronization calculations.

[0043] In one feasible implementation, continue to refer to Figure 4 The baseband processor can be configured with two software modules: a push message processing module and a pop message processing module.

[0044] The push message processing module is configured to receive time synchronization messages, parse the time synchronization messages to obtain second time information, and send the second time information to the application processor; the pop message processing module is configured to update the time information in the time synchronization message according to the third time information to obtain the updated time synchronization message, and send the updated time synchronization message.

[0045] It should be noted that the push message processing module and the pop message processing module can be understood as software functional units running inside the baseband processor, such as independent software tasks, threads, interrupt service routines, or firmware logic modules. The push message processing module is mainly responsible for processing time synchronization messages entering the baseband processor from the external network, while the pop message processing module is mainly responsible for processing updated time synchronization messages returned from the application processor that need to be sent out.

[0046] In the exemplary implementation, after receiving a time synchronization message from an external source, the push message processing module can disassemble the message according to a preset protocol format, extract the time synchronization-related field data (i.e., the second time information), and then send the second time information to the application processor through the internal communication interface. After receiving the third time information sent by the application processor, the pop message processing module can locate the field that needs to be modified in the previously stored time synchronization message, write the updated value from the third time information into the message, obtain the updated time synchronization message, and send the updated time synchronization message to the external network through the physical layer interface.

[0047] In this implementation, by setting up a push message processing module and a pop message processing module inside the baseband processor, the functions of receiving, parsing, updating, and sending messages are modularly divided, making the software structure of the baseband processor clearer and facilitating individual debugging and later maintenance. At the same time, the baseband processor is only responsible for pushing and parsing messages and popping and updating messages, and does not participate in the specific time synchronization algorithm calculation. This reduces the software complexity of the baseband processor and also makes it easier to iterate only the application processor software during subsequent service upgrades, while the basic processing flow of the baseband processor remains unchanged, thus improving the scalability and reusability of the entire domain controller.

[0048] In one feasible implementation, continue to refer to Figure 4 Application processors can have built-in timers.

[0049] The timer is used to generate first time information based on the second second pulse signal. The first time information is hardware timestamp information and may include the message entry hardware time Tse. The application processor is also used to trigger an interrupt and latch the time through the timer when the application processor receives the second time information, and generate the message entry hardware time Tse.

[0050] It should be noted that a timer refers to a hardware module located within the application processor that provides precise timing and latching functions. This can be a timer peripheral, counter circuit, or dedicated timestamp unit integrated within the application processor. Hardware timestamp information refers to the precise time value latched by the timer when it receives the second-second pulse signal, which can be obtained by reading the timer's register. The message entry hardware time Tse refers to the time when the message arrives at the application processor's entry point; that is, the moment the time synchronization message is transmitted from the baseband processor to the application processor, and the moment the application processor actually receives the message, the local hardware time latched by the timer's register during the instantaneous time latch triggered by the second-second pulse signal.

[0051] For example, the timer may include two hardware timers: a Tod Timer (Time of Day Timer) and a HW Timer (Hardware Timer). The Tod Timer consists of 78 bits, with a timing structure of 48 bits for seconds and 30 bits for nanoseconds, and a minimum timing unit of 1 ns. Its time value can be absolutely adjusted, relatively adjusted, or latched through configuration registers. The Tod Timer can be used by the software portion of the application processor for time acquisition and maintenance, allowing the software to read and correct the current absolute time, such as UTC time. The HW Timer consists of 32 bits, with a timing structure of 29 bits for nanoseconds and 3 bits for sub-nanoseconds, and a minimum timing unit of 1 ns. Like the Tod Timer, its time value can be absolutely adjusted, relatively adjusted, or latched through configuration registers. The HW Timer can receive the second-second pulse signal output by the microprocessor for hardware time stamping and time delay calculation in the application processor. The calculation results are reported to the software portion of the application processor. The Tod Timer focuses on the readability and maintenance of absolute time, while the HW Timer focuses on high-resolution short-time measurement. The two work together to acquire time information of the timer and record hardware timestamps during the time synchronization process.

[0052] When the second-second pulse signal arrives, the application processor's built-in timer can trigger an interrupt and latch the current count value of the timer into a register. The application processor can then read this register to obtain the first time information. When the application processor receives the second time information sent by the baseband processor, it can trigger the timer to perform the interrupt and latch operation again through hardware signals or software instructions, recording the timer value at this moment as the message entry hardware time Tse. The application processor can also read the timer's register through the interrupt service routine and pass the Tse value to the subsequent delay calculation process, such as for calculation with the correction field field in the second time information.

[0053] In this implementation, by using a built-in timer in the application processor and triggering an interrupt and latching the time when the second time information is received, a high-precision message entry hardware time can be obtained. This avoids scheduling delays and jitter caused by software involvement in reading the time, thereby improving the accuracy of the timestamp. This hardware-software co-operation approach allows the application processor to obtain a hardware timestamp that meets the time synchronization requirements without the need for external dedicated stamping hardware, reducing the hardware cost of the domain controller while maintaining the flexibility to optimize the time synchronization algorithm through subsequent software upgrades.

[0054] In one feasible implementation, the second time information may include a clock frequency ratio, a correction field time Tsi, and a first correction field value correctionField(i-1); the application processor is further configured to calculate and obtain the second correction field value correctionField(i1) based on the message ingress hardware time Tse, the correction field time Tsi, the clock frequency ratio rateratio, and the first correction field value correctionField(i-1).

[0055] The third time information includes the second correction field value correctionField(i1); the application processor is also used to send the second correction field value correctionField(i1) to the baseband processor, and the baseband processor is used to update the first correction field value correctionField(i-1) in the time synchronization message to the second correction field value correctionField(i1) to obtain the updated time synchronization message.

[0056] It should be noted that the clock frequency ratio (rateratio) refers to the frequency ratio between the local clock and the grandmaster clock. It is used to convert time differences between different clock domains to the same time scale. It is obtained by the baseband processor from the time synchronization message, or it can be calculated based on the synchronization status of the local clock and the grandmaster clock. The local clock can be the DS-TT (Device-Side TSN Translator) clock. The correction field time (Tsi) is the time value read from the correction field field of the time synchronization message, representing the accumulated delay correction amount before the message reaches the application processor. The first correction field value (correctionField(i-1)) is the current value of the correction field field before this update. It can be the correction field value provided by the NW-TT (Network-Side TSN Translator), and its value can be the same as the correction field time (Tsi). The second correction field value (correctionField(i-1)) is the updated correction field value calculated by the application processor based on the above information, used to replace the original first correction field value (correctionField(i-1)).

[0057] For example, the specific process by which the baseband processor receives and parses the time synchronization message to obtain the second time information can be as follows: After receiving the time synchronization message from an external NW-TT or DS-TT, the baseband processor parses the fields according to a time synchronization protocol such as the IEEE 802.3as protocol. The parsed fields may include: Cumulative Scaled Rate Offset: This field represents the frequency deviation between the local clock and the grandmaster clock. The domain controller can use this field to calculate the clock frequency ratio. Correction Field: This field is used to record the cumulative time such as processing time and link delay when the Sync message is sent from the master clock and forwarded by the relay instance. When the domain controller forwards and processes the message, it mainly recalculates and updates this field to correct the delay error in the message transmission process and ensure the time synchronization accuracy. Precise Origin Timestamp: Used to record the precise time when the master clock sends the Sync message. In one-step mode, it is carried by the Sync message, and in two-step mode, it is carried by the subsequent Follow_Up message.

[0058] In practical applications, besides parsing the fields that decisively affect time synchronization accuracy, other necessary fields can also be parsed, such as: message type (used to quickly identify the message as a synchronization event message); sequence ID (used to identify the sending order of Sync messages and establish the association between Sync messages and Follow_Up messages in two-step mode, avoiding order errors during message processing and ensuring that timestamps and other information match); flags (used to indicate whether the Sync message carries the precise Origin Timestamp field); source port ID (used to uniquely identify the sending port of the Sync message); logMessage Interval (used to indicate the average sending interval of Sync messages, so that the domain controller can adapt to its own synchronization rhythm); and so on. In practical applications, when the baseband processor parses the time synchronization message, it can extract the above fields, and when the baseband processor generates the updated time synchronization message, it fills in the above fields accordingly.

[0059] After parsing the above fields, the baseband processor can extract the time information contained in the fields, i.e., the second time information, and then send it to the application processor. After receiving the second time information sent by the baseband processor, the application processor can obtain the clock frequency ratio rateratio, the correction domain time Tsi, and the first correction domain value correctionField(i-1) from it. Then, it calculates the correction domain value by combining it with the packet entry hardware time Tse that it has latched. For example, it subtracts the correction domain time Tsi from the packet entry hardware time Tse to obtain the time difference (Tse-Tsi) to characterize the link transmission delay of the packet. Then, it multiplies the time difference by the clock frequency ratio rateratio to perform time scale conversion. Finally, it adds the conversion result to the first correction domain value correctionField(i-1) to obtain the second correction domain value correctionField(i1). The specific calculation formula is as follows: correctionField(i1)=correctionField(i-1)+(Tse-Tsi) rateratio(i); After the calculation is completed, the application processor sends the second correction field value, correctionField(i1), as the third time information to the baseband processor. After receiving the third time information, the baseband processor can locate the position of the correction field in the time synchronization message, replace the original first correction field value, correctionField(i-1), with the second correction field value, correctionField(i1), realize the first update of the correction field value, and encapsulate the message into data conforming to the time synchronization protocol format as needed and send it to the external NW-TT.

[0060] In this implementation, the application processor calculates the second correction domain value based on the message entry hardware time, correction domain time, clock frequency ratio, and the first correction domain value. This enables the software program to update the correction domain value in the message, eliminating the need for dedicated hardware chips to correct time information and reducing the hardware requirements of the domain controller, thereby lowering hardware costs. Simultaneously, since the message entry hardware time is a hardware timestamp latched by a timer based on the second-second pulse signal, the accuracy of the calculated time base is guaranteed, allowing the entire time synchronization process to achieve the synchronization accuracy of pure hardware solutions in related technologies. The baseband processor, besides sending and receiving messages, is only responsible for replacing fields in the message based on the updated values ​​provided by the application processor. Its simple function, without complex algorithms, facilitates subsequent service iteration updates and reuse.

[0061] In one feasible implementation, the application processor is further configured to generate fourth time information based on the first time information, the second time information, and the third time information, and send the fourth time information to the baseband processor; the baseband processor is further configured to encapsulate the fourth time information into a follow-up message and send the follow-up message.

[0062] It should be noted that the fourth time information refers to the final time synchronization data that the application processor calculates based on the first, second, and third time information obtained previously, and that needs to be sent in the follow-up message. For example, it may include fields such as the final correction threshold, clock frequency ratio, and precise origin timestamp. The follow-up message refers to the supplementary message used in the time synchronization protocol to carry the precise transmission timestamp or final correction threshold of the synchronization message, such as the Follow_Up message in the IEEE 802.1as protocol. The follow-up message can be encapsulated and generated by the baseband processor according to the time synchronization protocol format.

[0063] After receiving the first, second, and third time information, the application processor can calculate the final correction field value based on the correction field value in the third time information and the hardware timestamp in the first time information. The final correction field value, along with fields such as clock frequency ratio and precise origin timestamp, is then sent to the baseband processor as the fourth time information. Upon receiving the fourth time information, the baseband processor can fill these fields according to the format of the follow-up message. For example, the final correction field value is written into the correction field field of the follow-up message, and the precise origin timestamp is written into the corresponding timestamp field, thereby encapsulating a complete Follow_Up message. The Follow_Up message is then sent to the external network through the physical layer interface.

[0064] In this implementation, the application processor generates fourth time information, which is then encapsulated into a follow-up message by the baseband processor and sent out. This allows for more accurate correction information to be transmitted to downstream nodes during time synchronization, thereby improving the overall accuracy of time synchronization. At the same time, this process is entirely performed by the application processor in software, without relying on dedicated hardware. This reduces the hardware requirements of the domain controller and facilitates flexible adjustment of the content and format of the follow-up message according to different time synchronization protocols, thus improving versatility and scalability.

[0065] In one feasible implementation, the first time information may further include the message exit hardware time TR; the application processor is also used to generate the message exit hardware time TR by triggering an interrupt and latching the time through a timer when the application processor sends the third time information.

[0066] It should be noted that the message exit hardware time (TR) refers to the time when the message arrives at the application processor exit point. Specifically, it is the local hardware time latched by the timer register during the instantaneous time latching triggered by the second-second pulse signal when the application processor sends the third time information to the baseband processor. The message exit hardware time (TR) can be used to calculate the message's dwell time within the device, or as one of the bases for correction calculations when generating follow-up messages.

[0067] When the application processor is about to send the third time information to the baseband processor, the application processor can trigger a timer to perform interrupt and latch operations through hardware signals or software instructions, and record the timer value at this moment as the message exit hardware time TR. After the transmission is completed, the application processor can also read the timer register through the interrupt service routine and pass the TR value to the subsequent delay calculation process. For example, it can be used to cooperate with previously latched message entry hardware time Tse and other data to calculate the dwell time of the third time information inside the application processor, and then used for subsequent correction of the threshold value calculation or follow-up message generation.

[0068] In this implementation, by triggering an interrupt and latching the time when the application processor sends the third time information, a high-precision message exit hardware time can be obtained, representing the precise moment when the third time information leaves the application processor. This provides a reliable hardware time reference for calculating the internal processing latency of the application processor or further correcting the time information, thereby improving the overall time synchronization accuracy. At the same time, this scheme can be implemented using only the timer built into the application processor, without the need for external dedicated hardware chips, reducing the hardware cost of the domain controller and maintaining the flexibility of software implementation of time synchronization logic.

[0069] In one feasible implementation, the second time information also includes the high-precision time domain time TS; the application processor is also used to calculate the third correction field value correctionField(i2) based on the message exit hardware time TR, the high-precision time domain time TS, the clock frequency ratio rateratio, and the second correction field value correctionField(i1).

[0070] The fourth timing information includes the third correction field value, correctionField(i2); the application processor sends the third correction field value, correctionField(i2), to the baseband processor, which encapsulates the third correction field value, correctionField(i2), into a follow-up message and sends the follow-up message.

[0071] It should be noted that the high-precision time domain time TS refers to the high-precision timestamp carried in the time synchronization message, which indicates the time of message origin. It is usually generated by the master clock and written into the message field, such as the precise origin timestamp field. The third correction field value, correctionField(i2), is the final correction field value obtained by further compensating for the internal dwell time of the device based on the second correction field value. It is used to be passed to the downstream node in the message.

[0072] After obtaining the message exit hardware time TR, high-precision time domain time TS, clock frequency ratio rateratio, and the second correction field value correctionField(i1), the application processor can calculate the third correction field value correctionField(i2) according to a preset algorithm. For example, subtracting the high-precision time domain time TS from the message exit hardware time TR yields the time difference (TR-TS), which represents the message's dwell time within the device. This difference is then multiplied by the clock frequency ratio rateratio for time scale conversion. Finally, the conversion result is added to the second correction field value correctionField(i1) to obtain the third correction field value correctionField(i2). The specific calculation formula is as follows: correctionField(i2)=correctionField(i1)+(TR-TS) rateratio(i); After the calculation is completed, the application processor sends the third correction field value, correctionField(i2), as the fourth time information to the baseband processor to realize the second update of the correction field value. After receiving it, the baseband processor fills the third correction field value, correctionField(i2), into the corresponding field of the follow-up message, encapsulates it into a complete follow-up message, and sends it to the external NW-TT.

[0073] In this implementation, the application processor calculates the third correction threshold value based on parameters such as the message exit hardware time and the high-precision time domain time, and then encapsulates it into a follow-up message by the baseband processor. This can more accurately compensate for the message's dwell time in the domain controller, enabling downstream nodes to obtain more accurate correction information and thus improving the overall time synchronization accuracy. At the same time, this calculation process is completed entirely in the application processor software, without relying on dedicated hardware, which reduces hardware costs and allows for flexible adjustment of the calculation logic according to different time synchronization protocols, improving versatility and scalability.

[0074] In one feasible implementation, such as Figure 1 As shown, the domain controller is connected to an external timing source component, which is connected to both the second pulse component and the baseband processor.

[0075] like Figure 2 As shown, the external time source component is used to receive the time source signal, decompose the first second pulse signal and UTC time data from the time source signal, and send the first second pulse signal to the second pulse component and the UTC time data to the baseband processor; the baseband processor is also used to receive UTC time data to operate based on an absolute time reference.

[0076] It should be noted that a time source signal refers to an input signal that can provide standard time information, such as GNSS signals, NITZ signals, NTP signals, SNTP signals, PTP signals, high-precision RTC or IRIG-B code signals, etc.; UTC time data refers to Coordinated Universal Time (UTC) time information, which is used to represent the current absolute time and includes year, month, day, hour, minute, second, etc., and can be parsed from the time source signal.

[0077] External time source components can receive time source signals through dedicated receiving modules or devices, such as receiving GNSS signals through a GNSS receiver. Then, they can extract the first-second pulse signal and UTC time data from the time source signal, send the first-second pulse signal to the second pulse component, and send the UTC time data to the baseband processor. After receiving the UTC time data, the baseband processor can use the data to calibrate the local time reference, such as updating the internal real-time clock or adjusting the initial value of the timestamp counter, so that the baseband processor has an absolute time reference when working, i.e., when transmitting and receiving messages, parsing messages, and encapsulating messages.

[0078] In this implementation, the first second pulse signal and UTC time data are provided to the second pulse component and the baseband processor respectively by the external time source component. This enables the domain controller to obtain both a high-precision pulse reference for hardware time stamping and UTC time data for absolute time synchronization. This design allows the baseband processor to work based on the absolute time reference, ensuring that the time information in the time synchronization message is aligned with Coordinated Universal Time, thereby improving the accuracy and reliability of the time synchronization of the entire domain controller.

[0079] Based on the first embodiment of the domain controller in this application, the same or similar content as the above embodiment in the second embodiment of the domain controller in this application can be referred to the above description, and will not be repeated hereafter. Continuing on this basis, refer to... Figure 4 In this domain controller, the application processor includes an IP layer (Internet Protocol Layer: network layer), which contains an algorithm module.

[0080] The algorithm module is used to correct the second time information based on the first time information to obtain the third time information; and / or to generate the fourth time information based on the first time information, the second time information and the third time information.

[0081] like Figure 4 As shown, the application processor's hierarchical order from bottom to top is the physical layer, MAC layer (Media Access Control layer), IP layer, and application layer. The algorithm module refers to the software functional unit running in the IP layer, used to execute time synchronization-related calculations and processing logic. In this embodiment, the algorithm module in the IP layer specifically comprises three software modules: a time latch module, a delay calculation module, and a time stamping module. The time latch module is configured to acquire and save the first time information, such as the packet ingress hardware time Tse and the packet egress hardware time TR, which can be obtained by reading the timer register, and to acquire the second time information, such as the correction domain time Tsi and the high-precision time domain time TS, sent by the baseband processor for delay calculation. The delay calculation module is configured to calculate the link transmission delay or the device internal dwell time based on the latched timestamp information. The time stamp module is configured to add, replace, or update the timestamp field of the packet. For example, the packet ingress hardware time Tse and the packet egress hardware time TR provided by the time latch module can be written into the packet for subsequent delay calculation by the TSN (Time-Sensitive Networking) entity. Alternatively, the calculation result obtained by the delay calculation module can be written back into the packet to form an updated time synchronization packet for subsequent packet transmission by the TSN entity.

[0082] For example, the time latching module can latch first time information, such as hardware timestamps like the message ingress hardware time Tse and message egress hardware time TR, by calling a timer. It can also latch second time information, such as the correction field time Tsi and the high-precision time field time TS, by receiving the output from the baseband processor. The delay calculation module can calculate third time information, such as the second correction field value correctionField(i-1), correction field time Tsi, and clock frequency ratio rateratio, based on the first time information provided by the time latching module and the parameters in the second time information sent by the baseband processor. The time stamping module can update the time information fields of the message to be sent or generate the field content of the fourth time information based on the calculation results of the delay calculation module.

[0083] In this implementation, by setting an algorithm module in the IP layer of the application processor and further subdividing the algorithm module into a time latch module, a latency calculation module, and a time stamping module, a modular division of labor for the time synchronization process is achieved, facilitating independent development, testing, and maintenance. Simultaneously, since the IP layer sits above the physical and MAC layers, it can directly utilize the hardware capabilities provided by the underlying layers and output processed time information to the application layer, improving the efficiency of software and hardware collaboration. Furthermore, since the algorithm module is implemented in software, when the time synchronization protocol is updated or added, only the logic of the corresponding module in the IP layer needs to be adjusted, without modifying the underlying hardware, which is beneficial for business iteration updates and function reuse.

[0084] In one feasible implementation, the application processor's timer is set at the IP layer.

[0085] Understandably, the timer is located in the IP layer, on the same layer as the algorithm module within the IP layer. When a message arrives or is sent, the IP layer can directly trigger the timer to latch the time, without needing to call across layers or add extra software transmission. This reduces the delay and jitter in the timestamp acquisition process and helps to obtain more accurate hardware timestamps.

[0086] In this embodiment, the algorithm module is set in the IP layer of the application processor, and the timer for receiving the second-second pulse signal is also set in the IP layer. The time synchronization algorithm processing and hardware timestamp latching are both in the IP layer of the application processor. Software and a small amount of hardware are involved to achieve software-hardware collaboration. In this scheme of achieving time synchronization by executing software algorithms in the IP layer through software-hardware collaboration, high-precision time synchronization can be achieved. Implementing it in the IP layer can reduce the requirements for hardware. The software algorithm can be dynamically updated and can be expanded to support more new time synchronization protocols without hardware modifications, meeting more practical application needs.

[0087] In one feasible implementation, the application processor further includes an application layer, which has a TSN entity; the TSN entity is used to call the algorithm module to perform business processing according to a preset time synchronization protocol.

[0088] It should be noted that a TSN entity refers to a software module in the application layer of the application processor that is responsible for executing time synchronization business logic. It can call the corresponding algorithm module to perform business processing according to the pre-set time synchronization protocol, such as message content generation and latency calculation.

[0089] For example, when the baseband processor parses the time synchronization message, in addition to extracting time-related fields, it can also parse the payload (effective payload data) and package the payload data to send to the application processor. The application processor's TSN entity receives the payload data packet from the IP layer for subsequent information extraction, latency calculation, and message content generation. The TSN entity can unpack / repackage the received payload data packet according to the TSN protocol.

[0090] The baseband processor can encapsulate payload data into a data packet format suitable for internal transmission and send it to the application processor through the internal communication interface. After receiving the payload data packet, the application processor's TSN entity can call the corresponding algorithm module to perform business processing on the payload data according to the type of time synchronization protocol currently in use. This includes parsing the business information carried in the payload, maintaining the time synchronization state machine, and generating business data that needs to be replied to the baseband processor. After processing, the TSN entity can send the processing result to the baseband processor through the relevant interface of the application processor so that the baseband processor can perform subsequent message encapsulation and transmission.

[0091] Understandably, by setting up a TSN entity at the application layer of the application processor to receive payload data packets and call the algorithm module for business processing according to the preset time synchronization protocol, the problem of rigid and singular time synchronization protocols that can be supported in related technologies and the inability to dynamically iterate and update is solved. This decouples the time synchronization business logic from the underlying hardware chip, allowing the domain controller to support different time synchronization protocols or business requirements simply by updating the software without changing the hardware structure, thus improving the flexibility and scalability of the solution.

[0092] In an alternative implementation, to reduce communication overhead between different hardware components within the domain controller, the microprocessor and baseband processor can be integrated into a single hardware component, such as a BP component, which can be connected to the second pulse component and the application processor, respectively.

[0093] The BP component can be used to receive the first second pulse signal sent by the second pulse component and perform frequency division processing on the first second pulse signal to obtain the second second pulse signal and send it to the application processor; it can also be used to receive the time synchronization message and parse the time synchronization message to obtain the second time information and send the second time information to the application processor; and it can be used to update the time information in the time synchronization message according to the third time information to obtain the updated time synchronization message and send the updated time synchronization message.

[0094] For example, to help understand the specific process of time synchronization of the domain controller obtained by combining this embodiment with the first embodiment described above, refer to... Figure 5 and Figure 6 , Figure 5 A flowchart illustrating the time synchronization method used in a domain controller application example is provided. Figure 6 The document provides a detailed interactive example diagram of a domain controller application implementing time synchronization. This domain controller application example demonstrates the specific process of achieving high-precision time synchronization based on software and hardware integration, and may include the following steps: Step A00: The second pulse component receives the first second pulse signal sent by the external timing source component and sends the first second pulse signal to the microprocessor. Figure 6 (Not shown in the image).

[0095] In step A10, the microprocessor receives the first second pulse signal and performs frequency division processing on the first second pulse signal to obtain the second second pulse signal, which is then sent to the application processor.

[0096] like Figure 6 As shown, step A10 specifically includes steps A11 to A12: Step A11: The frequency division processing module of the microprocessor receives the first second pulse signal sent by the second pulse component and performs frequency division processing on the first second pulse signal to obtain the second second pulse signal; Step A12: The frequency division processing module outputs the second-second pulse signal to trigger the application processor's timer; After receiving the first second pulse signal from the second pulse component, the frequency division processing module divides it by frequency, defaulting to a 1:8 ratio. The output after frequency division is the second second pulse signal of 125ms. The frequency division processing module notifies the timer via an interrupt, thus triggering the timer's interrupt.

[0097] In step A20, the microprocessor receives the first second pulse signal and performs frequency division processing on the first second pulse signal to obtain the second second pulse signal, which is then sent to the application processor.

[0098] like Figure 6 As shown, step A20 specifically includes steps A21 to A23: Step A21: The stack message processing module of the baseband processor receives the time synchronization message and parses the time synchronization message to obtain the second time information; After receiving a time synchronization message sent by an external NW-TT, the in-stack message processing module parses it according to a preset time synchronization protocol and extracts key fields. It then obtains the second time information by acquiring the time information inherent in the key fields, and finally parses the core data from the key fields to obtain the payload data. The payload data can be the core time data fields contained in the frame of the time synchronization message, or the timestamp, sequence number, and correction parameters from an NTP / PTP message.

[0099] Step A22: The push message processing module sends the second time information to the application processor's time latch module; The push message processing module sends the second time information to the time latching module for latching, which is used by the subsequent delay calculation module, such as latching the clock frequency ratio, correction domain time, and first correction domain value.

[0100] Step A23: The stack message processing module sends the payload data packet to the time latch module; The push message processing module also packages the payload data and sends it to the time latch module.

[0101] In step A30, when the application processor receives the second time information, it triggers an interrupt through a timer and latches the time to generate the first time information.

[0102] like Figure 6 As shown, step A30 specifically includes steps A31 to A34: In step A31, while executing step A22, the application processor's time stamp module triggers an interrupt via a timer and latches the time. While the push message processing module sends the second time information to the time latch module, the time stamp module provides an interrupt signal and latches the hardware timestamp when triggered by the second second pulse signal through a timer.

[0103] Step A32: The time stamp module generates the message entry hardware time; The time stamping module generates the message entry hardware time, i.e., the first time information, based on the hardware timestamp.

[0104] Step A33: The time stamp module latches the hardware time of the message entry point through the time latch module; The time stamping module sends the message entry hardware time to the time latching module for latching, which is then used by the subsequent delay calculation module.

[0105] Step A34: The time latching module sends the latched time information to the TSN entity; The time latch module sends the latched time information, including clock frequency ratio, correction domain time, first correction domain value, and message entry hardware time, to the TSN entity.

[0106] In step A40, the application processor corrects the second time information based on the first time information to obtain the third time information, and sends the third time information to the baseband processor.

[0107] like Figure 6 As shown, step A40 specifically includes steps A41 to A43: Step A41: The TSN entity updates the correction domain value for the first time through the delay calculation module; The TSN entity can initiate the first correction domain update operation based on the acquired time information. Specifically, it calls the delay calculation module to calculate the second correction domain value based on the clock frequency ratio, correction domain time, first correction domain value, and message entry hardware time.

[0108] Step A42, the TSN entity generates third-time information; The delay calculation module returns the calculation result, i.e. the second correction threshold value, to the TSN entity, and the TSN entity obtains the third time information accordingly.

[0109] Step A43: The TSN entity sends third time information to the pop message processing module of the baseband processor; The TSN entity sends the third time information, including the second modified field value, to the pop message processing module.

[0110] In step A50, the baseband processor obtains the updated time synchronization message based on the time information in the updated time synchronization message according to the third time information, and sends the updated time synchronization message.

[0111] like Figure 6 As shown, step A50 specifically includes steps A51 to A52: Step A51: The pop message processing module updates the time information to obtain the updated time synchronization message; The pop message processing module updates the time information in the time synchronization message based on the received third time information. Specifically, it can update the first correction field value to the second correction field value to obtain the updated time synchronization message.

[0112] Step A52: The pop message processing module sends the updated time synchronization message; The pop message processing module sends the updated time synchronization message to the external network.

[0113] In step A60, when the application processor sends the third time information, it triggers an interrupt through a timer and latches the time to generate the first time information.

[0114] like Figure 6 As shown, step A60 specifically includes steps A61 to A64: In step A61, while executing step A43, the time stamping module triggers an interrupt via a timer and latches the time. While the TSN entity sends the third time information to the pop message processing module, the time stamp module provides an interrupt signal and latches the hardware timestamp when triggered by the second second pulse signal through a timer.

[0115] Step A62: The time stamp module generates the message exit hardware time; The time stamping module generates the message exit hardware time, i.e., the first time information, based on the hardware timestamp.

[0116] Step A63: The time stamp module latches the message exit hardware time through the time latch module; The time stamping module sends the message exit hardware time to the time latching module for latching, which is then used by the subsequent delay calculation module.

[0117] Step A64: The time latching module sends the latched time information to the TSN entity; The time latch module sends the latched time information, including the message exit hardware time, high-precision time domain time, clock frequency ratio, and second correction domain value, to the TSN entity.

[0118] In step A70, the application processor generates fourth time information based on the first time information, the second time information, and the third time information, and sends the fourth time information to the baseband processor.

[0119] like Figure 6 As shown, step A70 specifically includes steps A71 to A73: Step A71: The TSN entity updates and corrects the domain value a second time through the delay calculation module; The TSN entity initiates a secondary correction domain update operation based on the acquired time information. Specifically, it calls the delay calculation module to calculate the third correction domain value based on the message exit hardware time, high-precision time domain time, clock frequency ratio, and the second correction domain value.

[0120] Step A72, the TSN entity generates fourth time information; The delay calculation module returns the calculation result, i.e. the third correction threshold, to the TSN entity, and the TSN entity obtains the fourth time information accordingly.

[0121] Step A73: The TSN entity sends the fourth time information to the stack message processing module; The TSN entity sends fourth time information, including the third correction field value, to the pop message processing module.

[0122] In step A80, the baseband processor encapsulates the fourth time information into a follow-up message and sends the follow-up message.

[0123] like Figure 6 As shown, step A80 specifically includes steps A81 to A82: Step A81: The pop message processing module encapsulates the follow-up message; The pop message processing module encapsulates a follow-up message based on the received fourth time information. Specifically, the third correction field value, clock frequency ratio, high-precision time field time, and other information can be encapsulated together into a follow-up message.

[0124] Step A82: The pop message processing module sends a follow-up message.

[0125] The pop message processing module will send the message to the external network.

[0126] It should be noted that the above examples are only for understanding the embodiments of this application and do not constitute a limitation on the domain controller of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0127] It should also be noted that all actions to acquire signals, information or data in the embodiments of this application are carried out in compliance with the relevant data protection laws and policies of the country where the location is located, and with authorization from the owner of the corresponding device, terminal or equipment.

[0128] It should be understood that the various parts disclosed in the embodiments of this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0129] This application also provides an in-vehicle device, which includes the domain controller described in the above embodiments.

[0130] For example, the in-vehicle device can be a communication device, an in-vehicle network device, an intelligent driving device, etc., in a vehicle-to-everything (V2X) scenario.

[0131] The vehicle-mounted device provided in this application adopts a domain controller under any of the above embodiments. Therefore, the beneficial effects of the vehicle-mounted device are the same as those of the domain controller provided in the above embodiments, and other technical features of the vehicle-mounted device are the same as those of the domain controller disclosed in the above embodiments, and will not be described in detail here.

[0132] It should be noted that the above are only some embodiments of this application and do not limit the scope of protection of this application. All equivalent structural transformations made under the technical concept of this application and using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included in the scope of protection of this application.

Claims

1. A domain controller, characterized in that, Includes a second pulse component, a microprocessor, a baseband processor, and an application processor; The second pulse component is used to receive the first second pulse signal from an external timing source component; The microprocessor is used to receive the first second pulse signal sent by the second pulse component and perform frequency division processing on the first second pulse signal to obtain the second second pulse signal and send it to the application processor; The baseband processor is used to receive time synchronization messages and parse the time synchronization messages to obtain second time information, and send the second time information to the application processor; The application processor is used to generate first time information based on the second second pulse signal, correct the second time information based on the first time information to obtain third time information, and send the third time information to the baseband processor; The baseband processor is further configured to update the time information in the time synchronization message according to the third time information to obtain an updated time synchronization message, and send the updated time synchronization message.

2. The domain controller as described in claim 1, characterized in that, The application processor has a built-in timer, which is used to generate first time information based on the second second pulse signal. The first time information is hardware timestamp information and includes the message entry hardware time. The application processor is also configured to, at the moment when the application processor receives the second time information, trigger an interrupt through the timer and latch the time to generate the message entry hardware time.

3. The domain controller as described in claim 2, characterized in that, The second time information includes clock frequency ratio, correction domain time, and first correction domain value; The application processor is also configured to calculate a second correction domain value based on the message ingress hardware time, the correction domain time, the clock frequency ratio, and the first correction domain value. The third time information includes a second correction field value. The application processor is further configured to send the second correction field value to the baseband processor. The baseband processor is configured to update the first correction field value in the time synchronization message to the second correction field value, thereby obtaining an updated time synchronization message.

4. The domain controller as described in claim 3, characterized in that, The application processor is further configured to generate fourth time information based on the first time information, the second time information, and the third time information, and send the fourth time information to the baseband processor; The baseband processor is also used to encapsulate the fourth time information into a follow-up message and send the follow-up message.

5. The domain controller as described in claim 4, characterized in that, The first time information also includes the message exit hardware time; The application processor is also configured to trigger an interrupt and latch the time through the timer at the moment when the application processor sends the third time information, and generate the message exit hardware time.

6. The domain controller as described in claim 5, characterized in that, The second time information also includes high-precision time domain time; The application processor is also configured to calculate a third correction domain value based on the message exit hardware time, the high-precision time domain time, the clock frequency ratio, and the second correction domain value. The fourth time information includes a third correction field value. The application processor sends the third correction field value to the baseband processor. The baseband processor encapsulates the third correction field value into a follow-up message and sends the follow-up message.

7. The domain controller as described in any one of claims 1 to 6, characterized in that, The application processor includes an IP layer, and the IP layer is equipped with an algorithm module; The algorithm module is used to correct the second time information based on the first time information to obtain third time information; and / or The algorithm module is used to generate fourth time information based on the first time information, the second time information, and the third time information.

8. The domain controller as claimed in claim 7, characterized in that, The application processor's timer is set in the IP layer.

9. The domain controller as described in any one of claims 1 to 6, characterized in that, The domain controller is connected to an external time synchronization source component; The external time synchronization source component is used to receive a time source signal, decompose the first second pulse signal and UTC time data from the time source signal, send the first second pulse signal to the second pulse component, and send the UTC time data to the baseband processor; The baseband processor is also used to receive the UTC time data to operate based on an absolute time reference.

10. A vehicle-mounted device, characterized in that, Includes the domain controller as described in any one of claims 1 to 9.

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