A clock synchronization circuit, apparatus and system in a PON

Abstract

A clock synchronization circuit, device and system in a PON, relating to the field of optical communication technology, the circuit comprising: a first timing module maintaining the system time of the OLT based on the clock signal output by the first local clock and the current frequency reference value; a latch module latching the current count value of the nanosecond counter at the active edge of the 1PPS signal; a frequency measurement module calculating the difference between the count values of the nanosecond counter latched at the active edges of every two adjacent 1PPS signals to obtain a single frequency measurement value; generating the real-time frequency value of the first local clock according to the single frequency measurement values in the preset calibration period; if the deviation between the real-time frequency value and the nominal frequency value of the first local clock does not exceed the preset safety threshold, updating the current frequency reference value in the first timing module to the real-time frequency value; otherwise, keeping the current frequency reference value in the first timing module unchanged, thereby solving the problem of timing inaccuracy caused by frequency deviation of ordinary crystal oscillators.

Description

Technical Field

[0001] This application relates to optical communication technology, and more particularly to a clock synchronization circuit, device, and system in a PON. Background Technology

[0002] Figure 1 This is a schematic diagram of the time synchronization system in a Passive Optical Network (PON). Figure 1 As shown, the system includes an upstream time source device, an optical line terminal (OLT), and an optical network unit (ONU). The OLT's uplink interface connects to the upstream time source device, receiving its output 1 Pulse Per Second (1PPS) signal and Time of Day (TOD) messages. The OLT's downlink direction connects to one or more ONUs via passive optical splitters, forming a typical point-to-multipoint PON network. Each ONU can further provide a standard time reference for downstream base stations, edge computing nodes, or industrial terminals.

[0003] In existing technologies, the OLT needs to synchronize with an upstream time source to obtain accurate system time, serving as the time root node for the entire PON network. There are two main common implementation methods: One approach is a high-precision phase-locked loop (PLL) synchronization scheme. This scheme uses a high-precision PLL chip on the OLT side to lock the local voltage-controlled oscillator (VCO) to an external 1PPS signal, ensuring that the OLT's local operating clock is in phase and frequency with the upstream clock source. In this architecture, the OLT's local time is directly aligned to the 1PPS edge, the TOD message provides the absolute time value, and the sub-second portion is precisely filled by the synchronized local clock. This scheme offers excellent synchronization performance, but the PLL chip is expensive, the peripheral circuit design is complex, and the overall power consumption is high, which is not conducive to the large-scale deployment of PON equipment.

[0004] The second approach is a simplified synchronization scheme using a common crystal oscillator. In this scheme, the OLT uses only a low-cost common crystal oscillator as the system clock and does not perform frequency locking. The OLT reads the absolute time from the TOD message on the rising edge of the 1PPS signal and directly sets the local system time to that value. The sub-second portion is generated by a free counter based on the nominal frequency of the local crystal oscillator. However, due to inherent frequency offset, temperature drift, and aging issues of common crystal oscillators, there is a deviation between the actual frequency and the nominal frequency of the first local clock, causing the sub-second timing error to accumulate continuously and failing to meet the requirements for high-precision time synchronization. Summary of the Invention

[0005] This application provides a clock synchronization circuit, device, and system for a PON.

[0006] A clock synchronization circuit in a PON (Positioning Network) is applied to an OLT (Optical Linear Transmission Unit). The OLT further includes a first CPU, a first FPGA (Optical FPGA), and a first local clock. The first local clock uses a standard crystal oscillator without a phase-locked loop (PLL) to generate the system operating clock. The circuit includes a first timing module and a latching module located in the first FPGA, and a frequency measurement module located in the first CPU. The first timing module, including a nanosecond counter and a second counter, is configured to maintain the system time of the OLT based on the clock signal output by the first local clock and the current frequency reference value. The nanosecond counter is configured to accumulate the number of oscillations of the first local clock; each time the first local clock oscillates, the nanosecond counter increments by one. When the accumulated value of the nanosecond counter reaches the current frequency reference value, the second counter increments by one, and simultaneously, the nanosecond counter is reset to zero and begins accumulating again. The latching module is configured to latch the current count value of the nanosecond counter at the effective edge of the received external 1PPS signal in response to the external pulse-per-second (PPS) signal. The frequency measurement module is configured as follows: The difference between the count values ​​latched by the nanosecond counter at the effective edge of every two adjacent 1PPS signals is calculated to obtain the single frequency measurement value. Generate real-time frequency values ​​based on at least two single frequency measurements obtained within a preset calibration period; The real-time frequency value is compared with the nominal frequency value of the first local clock. If the deviation does not exceed a preset safety threshold, the current frequency reference value in the first timing module is updated to the real-time frequency value. If the deviation exceeds the safety threshold, the current frequency reference value in the first timing module remains unchanged.

[0007] A clock synchronization device in a PON, applied to an OLT, the device comprising: The clock synchronization circuit mentioned earlier; The first frequency synchronization circuit is used to send the current frequency reference value determined by the clock synchronization circuit to the ONU after the ONU and the OLT have completed clock synchronization, so that the ONU can perform local time calculation based on the current frequency reference value.

[0008] A clock synchronization system in a PON includes at least one ONU and an OLT as described above. The ONU includes a second local clock for generating the system operating clock, comprising a phase-locked loop (PLL). The PLL tracks a reference clock signal sent by the OLT, synchronizing the local clock frequency of the ONU with that of the OLT. The ONU further includes: The second frequency synchronization circuit is configured to receive an updated frequency reference value sent by the OLT after the ONU and the OLT have completed clock synchronization, or to periodically obtain the frequency reference value used by the first local clock in the OLT; when a change in the frequency reference value is detected, the updated frequency reference value is provided to the second timing module. The second timing module is configured to maintain the system time of the ONU based on the clock signal output by the second local clock and the updated frequency reference value.

[0009] In this embodiment, the timing mechanism of the first timing module allows the system timing rate to be flexibly adjusted by modifying the reference value, achieving timing accuracy calibration without relying on a phase-locked loop (PLL). The latch module captures the instantaneous value of the nanosecond counter at the effective edge of the external 1PPS signal, providing a nanosecond-level precision sampling anchor point for frequency measurement and avoiding the time uncertainty introduced by software sampling. The frequency measurement module calculates the true frequency of the crystal oscillator using the difference between the nanosecond counters of adjacent 1PPS signals and writes the effective frequency into the first timing module through a safety threshold decision mechanism, eliminating the cumulative timing error caused by crystal oscillator frequency deviation and ensuring the continuity and stability of system timing when the external 1PPS signal is abnormal. The synergistic effect of these features allows the measurement and calibration of the first local clock frequency to be independent of a PLL, solving the technical problem of timing inaccuracies caused by frequency deviation of ordinary crystal oscillators.

[0010] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0012] Figure 1 This is a schematic diagram of the time synchronization system in a PON (Positioning Network). Figure 2 A schematic diagram of the time synchronization circuit provided in the embodiments of this application; Figure 3Another schematic diagram of the time synchronization device provided in the embodiments of this application; Figure 4 This is a schematic diagram of the time synchronization system provided in an embodiment of this application. Detailed Implementation

[0013] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0014] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0015] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0016] In PON protocols such as Gigabit-Capable Passive Optical Network (GPONG Gigabit-Capable PON) and 10-Gigabit Symmetric Passive Optical Network (XGS-PON), time synchronization between the OLT and ONU is achieved based on a fixed 125 microsecond (μs) downlink frame period. The standard synchronization process specified in existing technologies mainly includes the following steps: Step 1: The PON system uses the local clock as the timing reference and fixes the single frame transmission duration at 125 microseconds.

[0017] Step 2: The OLT measures the transmission time TSend,N of the Nth downlink frame, and calculates the time T for the ONU to receive the Nth frame by combining the optical transmission delay between itself and the ONU and the ONU response time. R,N .

[0018] Step 3: The OLT uses formula T R,K = T R,N + (KN) × 125 recursively calculates the theoretical reception time T of the ONU for the Kth future frame. R,K .

[0019] Step 4: The OLT sets the frame number of the Kth transmitted frame and the theoretical reception time T. R,K It is encapsulated as a synchronous message and sent to the corresponding ONU.

[0020] Step 5: The ONU continuously detects the received frame number through the downlink frame counter. When the received frame number equals K, it updates the local system time to T. R,K This completes a time synchronization with the OLT.

[0021] In a system using a simple synchronization scheme with a common crystal oscillator, the 125-microsecond frame period in step 1 is directly generated by the nominal frequency of the local crystal oscillator. Due to the presence of crystal oscillator frequency offset, timing inaccuracies will occur, resulting in a slight deviation in the actual duration of each 125-microsecond frame period. In addition, (KN)×125 in step 3 will also introduce cumulative timing errors, and as KN increases, the synchronization accuracy gradually deteriorates.

[0022] To address the problem of balancing high cost and low accuracy in existing technologies, this application proposes the following solutions, including: Figure 2 This is a schematic diagram of the clock synchronization circuit in a PON provided in an embodiment of this application. Figure 2As shown, this circuit is applied to the OLT in a PON. The OLT includes a first CPU, a first FPGA, and a first local clock. The first local clock uses a standard crystal oscillator without a phase-locked loop (PLL) to generate the OLT's system operating clock, providing the basic clock cycle for the first FPGA and the first CPU. The first FPGA carries logic function units requiring real-time hardware response, including the first timing module and latch module of this circuit; the first CPU carries function units requiring software processing and decision-making, including the frequency measurement module of this circuit.

[0023] Under the aforementioned hardware architecture, there is an inherent deviation between the actual oscillation frequency generated by the first local clock and the nominal frequency. Without calibration, the structure where the first timing module directly performs system timing based on the nominal frequency will result in errors.

[0024] The circuit provided in this application embodiment accurately measures the true frequency of a first local clock under ordinary crystal oscillator conditions without a phase-locked loop. The circuit includes three functional units: a first timing module and a latch module located in a first FPGA, and a frequency measurement module located in a first CPU.

[0025] The following is a description of each module: 1. First timing module: The first timing module is responsible for continuously generating and maintaining the system time of the OLT using the first local clock as the beat, and providing count values ​​for frequency measurement. Specifically, the first timing module includes a nanosecond counter and a second counter. The nanosecond counter is fixedly connected to the output of the first local clock, receiving the oscillation signal of the first local clock as a counting pulse. The nanosecond counter increments by one for each oscillation of the first local clock. The second counter is fixedly connected to the carry output of the nanosecond counter. When the accumulated value of the nanosecond counter reaches the current frequency reference value, the second counter increments by one, and the nanosecond counter is reset to zero and restarts its accumulation.

[0026] The frequency reference value is stored in the register of the first timing module and is used to indicate the number of oscillations that the first local clock should produce within a standard second. The initial value of the frequency reference value is the nominal frequency value of the first local clock. During the initial power-on phase of the device, the first timing module starts timing based on this initial value; as the frequency measurement module completes the measurement of the actual frequency of the first local clock, the frequency reference value is dynamically updated to the measured value, thereby enabling the timing rate of the first timing module to gradually approach and eventually match the actual frequency of the first local clock.

[0027] The count value output terminal of the first timing module is fixedly connected to the input terminal of the latch module, so that the latch module can latch the external 1PPS signal at the effective edge.

[0028] The timing rate of the first timing module is determined by a frequency reference value. When the frequency reference value changes, the timing rate of the first timing module changes accordingly. If the new reference value is greater than the old reference value, more oscillations per second are required to trigger the second carry, and the system time advances at a slower rate; if the new reference value is less than the old value, the system time advances at a faster rate. In this way, the timing rate of the first timing module can be dynamically calibrated based on the frequency measurement results, ensuring that the system time advances at a rate that matches the true frequency of the first local clock.

[0029] 2. Latch module: A latch module, in response to a received external 1PPS signal, latches the current count value of the nanosecond counter at the valid edge of the 1PPS signal, providing time-aligned sampling data to the frequency measurement module. Specifically, the data input terminal of the latch module is fixedly connected to the nanosecond counter output terminal of the first timing module to receive the real-time nanosecond count value. Its trigger input terminal is fixedly connected to the external 1PPS signal input terminal of the OLT to receive the second pulse signal provided by the upstream clock source device. Its data output terminal is fixedly connected to the frequency measurement module of the first CPU to read the latched count value.

[0030] In this scheme, the latch module performs a hardware latch operation on each valid edge (e.g., rising edge) of the external 1PPS signal. When a valid edge of the 1PPS signal arrives, the latch module reads the current count value of the nanosecond counter and saves it to the internal register, while simultaneously triggering an interrupt to the first CPU to notify the first CPU to read the latched count value.

[0031] Since the latching action is performed in hardware, the delay between the latching moment and the 1PPS valid edge is extremely small and can be ignored. Therefore, the count value recorded by the latching module accurately reflects the value accumulated by the nanosecond counter at the moment the external 1PPS valid edge arrives. The time interval between two adjacent 1PPS valid edges is a standard 1 second. Therefore, the difference between the two latched count values ​​is the actual number of oscillations of the first local clock within a standard 1 second, thus obtaining the single frequency measurement value.

[0032] 3. Frequency Measurement Module: The frequency measurement module calculates the true frequency of the first local clock based on the sampling data provided by the latch module, and updates the valid result to the first timing module after a security check. Specifically, the data input terminal of the frequency measurement module is fixedly connected to the data output terminal of the latch module to read the latched nanosecond count value. Its configuration output terminal is fixedly connected to the register interface of the first timing module to write the updated frequency reference value.

[0033] The frequency measurement module reads the nanosecond counter count values ​​latched by the latch module at two adjacent 1PPS effective edges, calculates the difference between the two, and obtains the single frequency measurement value. This difference is directly equal to the actual number of oscillations of the first local clock within a standard 1 second.

[0034] To improve the stability of the measurement results, the frequency measurement module acquires at least two single frequency measurement values ​​within a preset calibration period, and generates a real-time frequency value representing the true frequency of the first local clock within the calibration period based on the obtained single frequency measurement values.

[0035] Before writing the real-time frequency value into the first timing module, the frequency measurement module also performs a safety threshold judgment: it compares the real-time frequency value with the nominal frequency value of the first local clock and calculates the deviation between the two. If the deviation does not exceed the preset safety threshold, it indicates that the measurement result is valid, and the frequency reference value in the first timing module is updated to the real-time frequency value; if the deviation exceeds the safety threshold, it indicates that the crystal oscillator frequency has deviated abnormally by a large margin or that there may be serious interference from the external 1PPS signal (such as excessive jitter, signal interruption causing latch value errors, etc.), then the current frequency reference value in the first timing module remains unchanged to avoid introducing erroneous frequency values ​​into the system.

[0036] Optionally, if the crystal oscillator frequency deviation exceeds the safety threshold during emergency calibration, an alarm message is reported to the upper-level management system via the network management interface to prompt maintenance personnel to conduct an inspection.

[0037] As a comparative example, assume the nominal frequency of the first local clock is 155.52 MHz, and the crystal oscillator actually has a frequency offset of +4.6 ppm, meaning the true frequency is 155,520,715 Hz. During the initial power-up phase, the initial value of the frequency reference is the nominal frequency of 155,520,000 Hz, and the first timing module uses this initial value for timing. If the nominal frequency of 155,520,000 Hz is used directly for system timing, the nanosecond counter will trigger a second carry-over when it accumulates to 155,520,000. However, the physical duration of 155,520,000 oscillations of the crystal oscillator is only 155,520,000 ÷ 155,520,715 ≈ 0.9999954 seconds, which is about 4.6 microseconds shorter than the standard 1 second. This error accumulates every second, reaching 276 microseconds after one minute, severely affecting time synchronization accuracy. After the frequency measurement module completes the measurement of the actual frequency of the first local clock, it updates the clock frequency reference value to the measured value of 155,520,715 Hz, so that the second carry occurs at the physical moment when the crystal oscillator oscillates for 1 second, thus eliminating the accumulated error.

[0038] The clock synchronization circuit in the PON provided in this embodiment, and the timing mechanism of the first timing module, allow the system timing rate to be flexibly adjusted by modifying the reference value, achieving timing accuracy calibration without relying on a phase-locked loop (PLL). The latch module captures the instantaneous value of the nanosecond counter at the effective edge of the external 1PPS signal, providing a nanosecond-level precision sampling anchor point for frequency measurement and avoiding the time uncertainty introduced by software sampling. The frequency measurement module calculates the true frequency of the crystal oscillator using the difference in nanosecond counters between adjacent 1PPS signals and writes the effective frequency into the first timing module through a safety threshold decision mechanism, eliminating the cumulative timing error caused by crystal oscillator frequency deviation, while ensuring the continuity and stability of system timing when the external 1PPS signal is abnormal. The synergistic effect of these features allows the measurement and calibration of the first local clock frequency to be independent of a PLL, solving the technical problem of timing inaccuracies caused by frequency deviation of ordinary crystal oscillators.

[0039] In one alternative implementation, the duration of the calibration period is not fixed, but is dynamically determined based on the operating environment of the first local clock.

[0040] Specifically, the calibration cycle and the operating environment of the first local clock have the following correspondence: when the first local clock is in an operating environment with temperature changes, a shorter first calibration cycle is used; when the first local clock is in an operating environment with no temperature changes or negligible temperature changes, a longer second calibration cycle is used. The first calibration cycle is shorter than the second calibration cycle.

[0041] In practical applications, the frequency stability of ordinary crystal oscillators is affected by temperature. Specifically, in scenarios where ambient temperature changes (e.g., when equipment is first powered on, when the server room air conditioning malfunctions, or when outdoor server racks heat up from direct sunlight), the crystal oscillator frequency will drift, and the faster the temperature change, the greater the frequency drift rate. If a long calibration cycle is used in such situations, the crystal oscillator frequency may have deviated significantly between calibrations, causing a continuous degradation in system timing accuracy over a period of time. Therefore, in environments with fluctuating temperatures, the calibration cycle needs to be shortened to track frequency changes more quickly. Conversely, in relatively stable temperature environments, the crystal oscillator frequency changes slowly, and an excessively short calibration cycle would incur unnecessary processing overhead.

[0042] In one exemplary implementation, when the system detects a sudden change in ambient temperature through a temperature sensor, or determines that the crystal oscillator frequency deviation is experiencing a small but rapid drift by monitoring the fluctuation amplitude of several consecutive frequency measurements, the calibration period is automatically switched to 1 second. A single frequency measurement value can be generated between every two adjacent 1PPS signals. The frequency measurement module tracks frequency changes with the highest response speed and quickly corrects the frequency reference value.

[0043] In another exemplary implementation, under steady-state operating conditions with normal temperature and signal, the crystal oscillator frequency is relatively stable. Calibration with a calibration period of 30 to 60 seconds can effectively compensate for minor temperature drift and aging effects, maintaining long-term timing accuracy.

[0044] Through the above dynamic adjustment mechanism, a sufficiently fast frequency tracking response is provided when the temperature changes, avoiding instantaneous degradation of synchronization accuracy due to crystal oscillator temperature drift. At the same time, unnecessary frequency measurement and calibration operations are reduced when the temperature is stable, thereby reducing system processing overhead and power consumption, and achieving an adaptive balance between response speed and resource consumption.

[0045] In one optional implementation, the method for obtaining the real-time frequency value after the OLT is initially powered on is explained.

[0046] When the device is first powered on, the system is in a startup transient state, and the external 1PPS signal may not yet be fully stable. For example, the clock source device may have just completed its own locking, and the signal quality on the transmission link may experience brief fluctuations. Furthermore, the interrupt response of the first FPGA's internal logic and the first CPU in the OLT is also in the initialization phase, which may result in occasional latch jitter or interrupt response delays. If only a single or small number of unprocessed frequency samples are collected at this time, these occasional abnormal data will cause the calculated initial frequency value to deviate significantly from the crystal oscillator's true frequency, thus setting the frequency reference value of the first timing module to an incorrect parameter and affecting the accuracy of all subsequent time synchronization operations.

[0047] Therefore, in this embodiment, after the OLT is initially powered on, the frequency measurement module obtains a more reliable real-time value of the clock frequency in the following manner, including steps A1 to A3.

[0048] Step A1: Multiple sampling. The frequency measurement module continuously acquires at least two single frequency measurements from a preset calibration period to form an initial sampling set. Typically, 5 to 10 sets of count values ​​corresponding to 1 PPS are continuously acquired to obtain sufficient data samples for subsequent statistical processing. For example, 8 sets are acquired.

[0049] Step A2: Abnormal Data Removal. The frequency measurement module performs anomaly detection on each individual frequency measurement value in the initial sampling set, identifying and deleting abnormal data caused by signal disturbances, glitches, or latch jitter. A typical method of anomaly detection is to calculate the median or preliminary average of all sampled values, and determine that sampled values ​​deviating from this center value by more than a preset deviation range are abnormal and removed. The remaining valid sampled values ​​after removal constitute the candidate measurement value set. For example, 2 sets are removed from 8 sets of count values.

[0050] Step A3: Averaging. The frequency measurement module takes the arithmetic mean of all valid data in the candidate measurement set and uses the average result as the initial real-time value of the clock frequency of the first local clock. Averaging smooths out residual random noise and minor jitter in a single sampling, making the final result closer to the true oscillation frequency of the crystal oscillator.

[0051] During the initial power-on phase, the frequency measurement module can effectively eliminate abnormal frequency measurement values ​​and obtain stable and accurate real-time frequency values ​​by executing the above processing procedure.

[0052] See Figure 2 This embodiment provides a clock synchronization device in a PON, applied to an OLT. The device first obtains a precise frequency reference value for a first local clock from the clock synchronization circuit of the aforementioned embodiment. Subsequently, the device sends the frequency reference value to the ONU, enabling the ONU to perform local time calculation based on a frequency reference value consistent with that of the OLT.

[0053] The above-mentioned device includes two functional units: a clock synchronization circuit and a first frequency synchronization circuit, as described in the foregoing embodiments.

[0054] The clock synchronization circuit accurately measures the true frequency of the first local clock, generating and maintaining the current frequency reference value. This frequency reference value is stored in the register of the first timing module, with an initial value of the nominal frequency of the first local clock, and is dynamically updated to the measured value by the frequency measurement module during operation.

[0055] After the ONU and OLT complete clock synchronization, the first frequency synchronization circuit sends the current frequency reference value determined by the clock synchronization circuit to the ONU. "Clock synchronization" here refers to the ONU's local clock tracking the reference clock signal sent by the OLT through a phase-locked loop (PLL), achieving physical frequency synchronization between the ONU's local clock and the OLT's local clock. This frequency reference value is sent based on physical frequency synchronization, providing the ONU with the frequency parameters required for time calculations.

[0056] With physical frequency synchronization achieved between the ONU and OLT, the ONU's local clock and the OLT's local clock oscillate at the same frequency. The TOD timing function in both the ONU and OLT requires knowledge of this oscillation frequency to correctly convert the number of oscillations counted by the local counter into physical time. The conversion relationship is as follows: t = t0 + N / F; Where t0 is the time base value, N is the number of oscillations counted by the ONU local counter starting from the time base value, and F is the frequency base value.

[0057] If the ONU uses its own crystal oscillator's nominal frequency for the above conversion, the inherent frequency offset of a common crystal oscillator will cause a discrepancy between its nominal frequency and the actual oscillation frequency, leading to a continuous accumulation of timing errors in the ONU. The OLT, however, uses the aforementioned clock synchronization circuit to accurately measure the true frequency of its local clock using an external 1PPS signal, and uses this true frequency as a frequency reference value. After the OLT sends this frequency reference value to the ONU, the ONU can use frequency parameters that are completely identical to those of the OLT and have been measured and calibrated to perform time calculations, thereby eliminating timing errors caused by crystal oscillator frequency offset.

[0058] It is important to note that sending the frequency reference value does not change the physical frequency of the ONU's local clock. The physical frequency of the ONU's local clock is determined by the PLL tracking the reference clock signal sent by the OLT. The frequency reference value only updates the frequency parameters used by the TOD timing operation in the ONU for time calculation, ensuring that the time conversion scale is consistent with the physical reality.

[0059] During the operation of the aforementioned device, the clock synchronization circuit continuously measures the true frequency of the first local clock according to a preset calibration cycle. When the measured real-time frequency value differs from the current frequency reference value, and the deviation does not exceed a preset safety threshold, the clock synchronization circuit updates the current frequency reference value to the real-time frequency value.

[0060] Whenever the frequency reference value is updated, the first frequency synchronization circuit sends the updated frequency reference value to the ONU to ensure that the time calculation parameters on the ONU side are always consistent with those on the OLT. This sending method includes: sending immediately each time the frequency reference value is updated; sending it along with a synchronization message within a preset synchronization message period; or periodically providing the current frequency reference value in response to a request from the ONU; this embodiment does not limit this method.

[0061] Taking the nominal frequency of the first local clock as 155.52 MHz as an example, during the initial power-up phase of the device, the initial value of the frequency reference is the nominal value of 155,520,000 Hz.

[0062] After the clock synchronization circuit is running, the actual frequency of the first local clock is measured to be 155,520,715 Hz based on the external 1PPS signal (i.e., there is a frequency deviation of +4.6 ppm). After the safety threshold decision confirms its validity, the frequency reference value in the first timing module is updated to 155,520,715 Hz.

[0063] The first frequency synchronization circuit detects a change in the frequency reference value and sends the updated frequency reference value of 155,520,715 Hz to the ONU.

[0064] On the ONU side, its local clock has achieved physical frequency synchronization with the OLT's local clock via the PLL, and both oscillate at the same frequency. Previously, the ONU's TOD timing operation used a nominal frequency of 155,520,000 Hz for time calculation, resulting in a timing error of approximately 4.6 microseconds per second. Upon receiving the updated frequency reference value of 155,520,715 Hz from the OLT, the ONU's TOD timing function configures this value as the new time calculation parameter, triggering a carry-over only when the nanosecond counter accumulates to 155,520,715. Since the actual physical duration of the ONU's local clock oscillating 155,520,715 times is exactly 1 second, the ONU's timing error is eliminated, and its maintained system time remains precisely consistent with the OLT's.

[0065] With the aforementioned device, the OLT accurately measures the frequency of its own first local clock and transmits the measured frequency reference value to the ONU through the first frequency synchronization circuit. This allows the ONU to obtain time calculation parameters consistent with the OLT based on physical frequency synchronization. This mechanism extends the frequency measurement results from the OLT to the ONU, unifying the time calculation reference for the entire system and eliminating the cumulative timing errors introduced by the ONU using the nominal frequency for time calculation. Furthermore, since the frequency reference value is only used for updating time calculation parameters and does not change the physical frequency of the ONU's local clock, it is independent of and does not interfere with the physical frequency synchronization function of the PLL, resulting in a clear system architecture and stable operation.

[0066] Figure 3 Another schematic diagram of the time synchronization device provided in the embodiments of this application. For example... Figure 3 As shown, the OLT also includes a first CPU and a first FPGA; the first frequency synchronization circuit includes a downstream synchronization module located in the first CPU and a first PON MAC module located in the first FPGA. In this OLT, a first local clock signal provides clock signals for the first timing module and the first PON MAC module.

[0067] The first timing module is responsible for generating 125-microsecond transmission frame boundaries based on the frequency reference value, and the latching module is responsible for latching the transmission time of the Nth transmission frame; the downstream synchronization module is responsible for executing the core calculation logic for time synchronization; the first PON MAC module is responsible for encapsulating the calculation results into a synchronization message and sending it to the ONU. Among these: The first timing module is also configured to generate 125-microsecond transmission frame boundaries based on the frequency reference value. In hardware implementation, the first timing module determines the number of local clock cycles M corresponding to 125 microseconds (M = F / 8000, where 8000 is the number of 125-microsecond transmission frames per second) based on the current frequency reference value F stored in its register, and uses M as the threshold value for triggering the frame boundary. When the frame cycle counter inside the first timing module accumulates to M, a frame boundary signal is generated, indicating the end of the current 125-microsecond frame and the start of the next frame.

[0068] The latch module is further configured to latch the transmission time of the Nth transmission frame when the first timing module generates the frame boundary of the Nth transmission frame. The latch module can save the transmission time to an internal register and notify the first CPU to read it.

[0069] The downstream synchronization module is configured as follows: Obtain the transmission time of the Nth transmission frame latched by the latch module; Based on the transmission time of the Nth transmission frame, determine the reception time T of the target optical network unit (ONU) for receiving the Nth transmission frame. R,N ; According to the reception time T of the Nth transmission frame R,N And the frame number difference between the Kth transmission frame and the Nth transmission frame, calculate the theoretical reception time T of the ONU receiving the Kth transmission frame. R,K ; The frame number of the Kth transmitted frame and the theoretical reception time T R,K The frequency reference value is sent to the first PON MAC module.

[0070] The first PON MAC module is configured to send to the ONU the frame number of the Kth transmission frame and the theoretical reception time T. R,K The synchronization message with the frequency reference value enables the ONU to utilize the theoretical reception time T when it detects that the received transmission frame number is the frame number of the Kth transmission frame. R,K Perform a local time synchronization operation on the ONU; Where N is less than K, and both N and K are positive integers.

[0071] For example, the synchronization message can be a PLOAM message or an OMCI message.

[0072] The time synchronization process executed by this device is consistent with the time synchronization mechanism specified in PON standard protocols such as GPON and XGS-PON, namely: a fixed frame period of 125 microseconds, selection of reference frame N and determination of its reception time, recursive calculation of the theoretical reception time of target frame K, issuance of synchronization message, and ONU update at the trigger time of frame K.

[0073] Compared to the standard process, the difference of this device is that the 125-microsecond frame period in the above process is no longer based on the nominal frequency of the first local clock, but on the frequency reference value F obtained by the clock synchronization circuit. The number of local clock cycles M is obtained through the conversion relationship M = F / 8000 inside the first timing module. Then, the first timing module generates the 125-microsecond transmission frame boundary based on M. The downstream synchronization module performs time recursion based on the transmission time obtained by latching the precise frame boundary.

[0074] The following explains the specific manifestations of this distinguishing feature.

[0075] 1. Identification of 125-microsecond transmission frame boundaries: The PON system specifies that each frame transmission duration is 125 microseconds, with a total of 8000 frame cycles per second. In terms of hardware implementation, the frame boundary is identified by counting the oscillation cycles of the first local clock. When the count value reaches the preset number of oscillations per frame, a frame boundary signal is triggered, indicating the end of the current frame and the start of the next frame.

[0076] In existing technology, the number of oscillations per frame is calculated based on the nominal frequency of the first local clock. For example, when the nominal frequency is 155.52 MHz, the number of oscillations per frame = 155,520,000 ÷ 8,000 = 19,440. If the actual frequency of the crystal oscillator deviates from the nominal value, the physical duration of each frame period will no longer be 125 microseconds, resulting in a single-frame timing error.

[0077] In this device, the first timing module calculates the number of oscillations M per frame based on the frequency reference value F provided by the clock synchronization circuit, according to M = F / 8000. When the frequency reference value F is updated to the actual frequency of the crystal oscillator, the first timing module uses M as the threshold for triggering the frame boundary, so that the deviation of the physical duration of each 125-microsecond frame period from the standard value is controlled within a very small range of the crystal oscillator frequency measurement error, thus eliminating frame period timing error at its source.

[0078] 2: Determine T R,N and recursive calculation of T R,K : Based on accurate frame boundary identification, the downstream synchronization module determines the reception time T of the Nth transmission frame by combining the optical transmission delay and ONU response time obtained from the PON standard ranging procedure, according to the transmission time of the Nth transmission frame. R,N .

[0079] The downstream synchronization module calculates the theoretical reception time T of the ONU for the Kth future transmission frame using the recursive formula specified in the PON standard protocol. R,K : T R,K = T R,N + (K - N) × 125; in: T R,N The theoretical reception time for the ONU to receive the reference frame N; K is the frame number of the target synchronization frame, N is the frame number of the reference frame, both K and N are positive integers, and N is less than K; (K - N) represents the number of frame cycles from the reference frame N to the target frame K; 125 is the single-frame transmission duration specified by the PON system, in μs.

[0080] Among them, T R,N The distance was obtained through the PON standard ranging procedure, which measures the optical round-trip time (RTT) between the OLT and ONU, determines the equalization delay (EqD) of the ONU, and the response time of the ONU. Based on the above information, the theoretical reception time T is obtained. R,N .

[0081] In the prior art, since the physical duration of each frame period deviates by 125 microseconds due to the crystal oscillator frequency offset, the cumulative physical time corresponding to (K - N) frame periods will have an error, and this error will accumulate linearly as KN increases.

[0082] In this device, since the 125-microsecond frame period is timed based on a precise frequency reference value F, the deviation of the physical duration of each frame period from the standard 125 microseconds is extremely small, and the cumulative physical time error corresponding to (K - N) frame periods is effectively suppressed. Therefore, the T calculated based on the above recursive formula is... R,K It can accurately reflect the actual physical time when the ONU receives the target frame K.

[0083] The clock synchronization device in the PON provided in this embodiment uses the measured frequency reference value instead of the nominal frequency as the timing reference for the 125 microsecond frame period in the standard protocol process of time synchronization from OLT to ONU. This makes the physical accuracy of frame boundary identification no longer constrained by the crystal oscillator frequency offset, eliminates the cumulative timing error in the recursive calculation, and enables high-precision OLT to ONU time synchronization under a low-cost ordinary crystal oscillator hardware architecture.

[0084] In one optional implementation, a time synchronization method between the OLT and the upstream clock source device is given.

[0085] In the traditional 1PPS+TOD synchronization method, the OLT directly updates the local system time to the absolute time value carried in the TOD message the instant the effective edge of the external 1PPS signal arrives. In this method, if a common crystal oscillator is used, the sub-second timing is inaccurate, and directly updating the system time may introduce time jumps.

[0086] To solve the above problems, the implementation method of this embodiment is as follows: The latch module is further configured to latch and record the absolute time information in the TOD signal from the upstream clock source device at the current moment in response to a 1PPS pulse signal sent by the upstream clock source device, and simultaneously latch the count value of the nanosecond counter at the current moment as the current count value. For example, when the valid edge of the 1PPS pulse signal sent by the upstream clock source device arrives, the latch module simultaneously performs two hardware latch operations: first, it latches and records the absolute time information in the TOD signal from the upstream clock source device at the current moment; second, it latches the count value of the nanosecond counter at the current moment as the current count value. Thus, the system obtains a pair of anchor point data: (current count value C0, absolute time value T0). After the latch operation is completed, the OLT's system time has not yet been modified, and the synchronization action has not yet been performed. The 1PPS edge serves only as a trigger signal for the latch operation, not a synchronization trigger signal.

[0087] The upstream synchronization module is configured to determine the counter increment value based on the frequency reference value and a preset waiting time; to determine the target count value by summing the current count value and the counter increment value; and to determine the target time value by summing the absolute time information and the waiting time. For example, the upstream synchronization module reads the anchor point data (C0, T0) obtained by the latch module and calculates the target count value and target time value corresponding to the waiting time Δt based on the obtained frequency reference value F, for example, Δt is 0.5 seconds. The counter increment value ΔC = Δt × F, meaning that within the preset time Δt, the nanosecond counter will increment forward ΔC times. Therefore, the target count value = C0 + ΔC, and the target time value = T0 + Δt. The waiting time Δt is a preset parameter whose function is to postpone the synchronization action to a future, predetermined moment, rather than executing it instantaneously at the edge of 1PPS.

[0088] The first timing module is further configured to receive a target count value and a target time value configured by the first CPU; and to update the system time of the OLT to the target time value when the nanosecond counter accumulates to the target count value. In this embodiment, the synchronization action is not triggered at the 1PPS edge, but rather when the counter freely runs to a preset target count value determined by anchor data and a frequency reference value F. The entire synchronization process does not require resetting the counter or interrupting its continuous operation, resulting in a smooth update of the system time.

[0089] This embodiment uses a frequency reference value to calculate the counter increment value and the target time value. When the counter accumulates to the target count value, the corresponding physical time is exactly equal to the target time value, which reduces the probability of time jumps and ensures a smooth transition of the OLT system time.

[0090] In one alternative implementation, the theoretical reception time T R,K Further restrictions on the calculation method.

[0091] In this implementation, the downstream synchronization module calculates the theoretical reception time T for the ONU to receive the Kth transmission frame. R,K When the calculation is performed, the following expression is used: T R,K = T R,N + (K - N) × 125 + T d ; Among them, T d The total hardware processing latency of the ONU is determined based on the MAC layer hardware processing latency between the OLT and the ONU.

[0092] In a PON system, downlink frames sent from the OLT to the ONU require multiple levels of hardware processing. On the OLT side, after the PON MAC processing module generates the downlink frame, it needs to go through electro-optical conversion, optical module driving, and other stages before it can be transmitted through the optical fiber. On the ONU side, after the optical signal undergoes photoelectric conversion, it needs to be parsed by the ONU's PON MAC processing module before it can be recognized and received by the ONU.

[0093] The hardware processing of each of the above steps requires a certain amount of time. This time is a fixed hardware processing delay, which is superimposed on the optical transmission delay. This results in a fixed offset between the actual time when the ONU receives frame K and the theoretical time calculated by considering only the optical transmission delay and the 125-microsecond frame period.

[0094] In the standard formula T of existing technology R,K = T R,N In + (KN) × 125, the OLT calculates T based on this. R,N However, the ranging process primarily compensates for the transmission delay of the fiber optic link, without separately accounting for the additional fixed delay introduced by the MAC layer hardware processing. Therefore, if the standard formula is used directly, T R,K There is a systematic deviation introduced by hardware processing between the calculation result and the physical time when the ONU actually receives frame K.

[0095] In this implementation, T d The parameter introduced to compensate for this systematic bias makes T R,K The calculation results can more accurately reflect the physical time of the actual received frame K by the ONU.

[0096] Through T R,K The total hardware processing delay T is introduced into the calculation. d This implementation incorporates the MAC layer hardware processing latency, which is not accounted for in the standard formula, into the compensation, eliminating the systematic bias introduced by hardware processing and improving the theoretical reception time T. R,K The calculated value is closer to the physical time when the ONU actually receives the target frame, further improving the time synchronization accuracy from OLT to ONU.

[0097] See Figure 4 , Figure 4 This is a schematic diagram of the time synchronization system provided in an embodiment of this application. The system includes at least one ONU and an OLT as described in the foregoing embodiment. Based on the OLT's accurate frequency measurement, this embodiment further provides an implementation scheme on the ONU side, enabling the ONU to perform local time calculation based on a frequency reference value consistent with the OLT, thereby achieving high-precision time synchronization for the entire system.

[0098] The OLT is equipped with a clock synchronization device as described in the foregoing embodiments, including a first local clock (a common crystal oscillator without a phase-locked loop), a clock synchronization circuit, and a first frequency synchronization circuit. The OLT measures the actual frequency of the first local clock through an external 1PPS signal to obtain a frequency reference value F, and sends the updated frequency reference value to the ONU when the frequency reference value is updated.

[0099] On the ONU side, the second local clock includes a phase-locked loop (PLL) used to generate the system operating clock. This PLL tracks the reference clock signal issued by the OLT, synchronizing the ONU's local clock frequency with the OLT's local clock frequency. The reference clock signal is the local oscillator signal generated by the OLT's first local clock, which is transmitted to the ONU through the clock recovery mechanism of the PON physical layer. The PLL automatically tracks the frequency and phase of this reference clock signal, ensuring that the ONU's local clock output frequency remains consistent with the OLT's first local clock, thus achieving physical layer clock frequency synchronization.

[0100] The clock frequency synchronization mentioned here refers to the physical oscillation frequency of the ONU's second local clock being consistent with the OLT's first local clock. This is achieved by the phase-locked loop tracking the reference clock signal and is independent of the value of the frequency reference value F. The frequency reference value F is used to provide the required frequency parameters for the ONU's TOD timing and is independent of the PLL's locking function.

[0101] The ONU also includes a second frequency synchronization circuit, which obtains the frequency reference value F used by the OLT after the ONU and OLT complete clock synchronization.

[0102] The second frequency synchronization circuit obtains the frequency reference value in two ways, which can be selected according to the system design: In one acquisition method, after the clock synchronization circuit of the OLT updates the frequency reference value F through frequency measurement, the first frequency synchronization circuit actively sends the updated frequency reference value to the ONU, and the second frequency synchronization circuit of the ONU receives the updated frequency reference value.

[0103] In another acquisition method, the second frequency synchronization circuit of the ONU queries the OLT through the PON management channel for the frequency reference value currently used by the first local clock according to a preset period. The OLT responds to the query request and returns the current frequency reference value to the ONU.

[0104] Regardless of the acquisition method, after obtaining the frequency reference value, the second frequency synchronization circuit compares it with the currently used local frequency reference value. When it detects a change in the value of the frequency reference value, it provides the updated frequency reference value to the second timing module.

[0105] The second timing module maintains the ONU's system time based on the clock signal output from the second local clock and the updated frequency reference value.

[0106] For example, the second local clock is synchronized with the OLT clock frequency via the PLL to generate a periodic clock signal. The second timing module counts the number of oscillations of this clock signal, incrementing the internal nanosecond counter by one for each oscillation. The second timing module also maintains a second carry threshold based on the frequency reference value F. When the nanosecond counter accumulates to the frequency reference value F, the second counter increments by one, the nanosecond counter is cleared, and the accumulation restarts.

[0107] Since the physical frequency of the ONU's local clock is synchronized with that of the OLT via the PLL, and the frequency parameter F used for time calculation is the same as that of the OLT, the ONU's system time can maintain precise consistency with the OLT. Therefore, the PLL is responsible for solving the physical frequency synchronization problem, while the frequency reference value F is responsible for solving the accuracy problem of the time conversion parameter. Each performs its own function independently, working together to ensure that the ONU maintains high-precision time calculation between two synchronization messages.

[0108] The clock synchronization system in the PON provided in this embodiment extends the frequency measurement capability of the OLT side to the ONU side through the distribution of the frequency reference value. Based on the physical frequency synchronization completed by the PLL, the ONU uses the frequency reference value F obtained from the actual measurement by the OLT for time calculation, unifying the time calculation reference of the entire system to the frequency measurement results of the OLT, eliminating the accumulated timing error introduced by the ONU using its own crystal oscillator's nominal frequency. Simultaneously, the frequency synchronization function of the PLL and the time calculation parameter update function of the frequency reference value F are independent of each other, with a clear architecture and no interference, providing a reliable guarantee for high-precision time synchronization of the system under low-cost hardware conditions.

[0109] In an optional embodiment, this embodiment further defines the ONU-side structure in the system, and provides the specific process for the division, connection relationship and execution time synchronization operation of the functional modules inside the ONU.

[0110] In this embodiment, the ONU also includes a second CPU and a second FPGA. The second frequency synchronization circuit specifically includes a local synchronization module located in the second CPU, and a second PON MAC module and a downlink frame counter located in the second FPGA. In the ONU, the second PON MAC recovers the clock frequency information of the OLT from the optical signal and uses it as a reference input for the ONU-side PLL, so that the ONU local clock and the OLT local clock are physically synchronized.

[0111] In this scheme, the second local clock outputs a clock signal based on the reference signal recovered by the second PON MAC module, providing a clock reference for the second PON MAC module and the second timing module.

[0112] The second PON MAC module, located in the second FPGA, serves as the hardware interface for PON protocol data interaction between the ONU and OLT. It receives and parses synchronization messages sent by the OLT via the PON downlink. The local synchronization module, located in the second CPU, is the control and processing unit for the ONU-side time synchronization process. It verifies or corrects the parameters parsed by the second PON MAC module, generates the synchronization time, and configures the relevant parameters to the second timing module. The downlink frame counter, located in the second FPGA and independent of the second timing module, counts the received downlink frame numbers in real time and generates a trigger signal when the frame number reaches a preset target value. The second timing module, also located in the second FPGA, maintains the ONU's local system time, receives parameters configured by the local synchronization module, responds to the downlink frame counter's trigger execution time update, and continuously keeps time based on the frequency reference value.

[0113] The module division principle is as follows: functions requiring real-time hardware response are deployed on the second FPGA, including synchronous message reception and parsing, frame number statistics and matching, time update triggering, and continuous timing; functions requiring software processing and judgment are deployed on the second CPU, including parameter verification, synchronous time generation, and parameter configuration. This division method is consistent with the functional division principle of the first FPGA and first CPU on the OLT side.

[0114] The second PON MAC module receives a synchronization message from the OLT. This message carries at least three parameters: the frame number K of the Kth transmission frame, the theoretical reception time TR,K, and the current effective frequency reference value F of the OLT. The second PON MAC module parses these parameters from the synchronization message and reports the parsing result to the local synchronization module located in the second CPU. The parsing action is performed by the internal hardware logic of the second PON MAC module, and the parsing result is transmitted via the bus interface between the second FPGA and the second CPU.

[0115] After receiving the frame number K, theoretical reception time TR,K, and frequency reference value F reported by the second PON MAC module, the local synchronization module verifies the theoretical reception time TR,K and generates a synchronization time. The verification method can employ the expected value comparison and limiting correction mechanism described in the previous embodiments, or other verification methods can be selected based on the actual application scenario. After verification, the local synchronization module obtains the actual synchronization time value used in this synchronization operation. Subsequently, the local synchronization module configures the frame number of the Kth transmission frame, the verified synchronization time, and the updated frequency reference value F into the configuration register of the second timing module. These three parameters are written via the bus interface between the second CPU and the second FPGA.

[0116] The configuration path of the frequency reference value F is exactly the same as that of the frame number K and the synchronization time. All of these originate from the synchronization message sent by the OLT, are parsed by the second PON MAC module, processed by the local synchronization module, and then written to the second timing module. The frequency reference value F is used to update the second timing module's carry-over threshold, ensuring that the ONU's timing rate is consistent with the OLT's. This parameter does not participate in the downlink frame counter's statistics and matching process for frame numbers.

[0117] The downlink frame counter operates independently within the second FPGA. After the second PON MAC module completes downlink frame boundary identification at the physical layer, the downlink frame counter increments once for each complete downlink frame identified, maintaining the currently received frame number in real time. The downlink frame counter internally incorporates comparison logic that compares the continuously updated current frame number with the preset target frame number K in the configuration register. When the currently received frame number is detected to be equal to the frame number of the Kth transmitted frame, the downlink frame counter generates a trigger signal and sends it to the second timing module. This trigger signal is a hardware signal and does not undergo software processing by the second CPU, ensuring the real-time nature and accuracy of the trigger.

[0118] The second timing module responds to the trigger signal of the downlink frame counter. Upon receiving the trigger signal, it updates the ONU's local system time to the synchronization time stored in the configuration register. This update time is the physical time when the Kth transmitted frame arrives at the ONU, which is consistent with the time corresponding to the theoretical reception time TR,K calculated by the OLT, thus ensuring the alignment accuracy between the ONU's local time and the OLT's system time. After the time update, the second timing module uses the synchronization time as a new starting point and continuously maintains the ONU's system time based on the frequency reference value F stored in the configuration register and the clock signal output by the second local clock. The nanosecond counter inside the second timing module accumulates the number of oscillations of the second local clock. When the accumulated value reaches the frequency reference value F, the second counter increments by one and the nanosecond counter is reset to zero, achieving a timing rate synchronized with the OLT. The physical frequency of the second local clock is synchronized with the OLT's first local clock through a phase-locked loop. Based on this, the second timing module uses the same frequency reference value F as the OLT for time conversion, further eliminating timing errors that may be introduced due to inconsistent frequency parameters.

[0119] This embodiment clearly defines the division and coordination of functional modules on the ONU side, fully realizing the entire process from synchronization message reception, parameter parsing and verification, parameter configuration, frame number matching triggering to time update and continuous timing. The data flow and trigger flow are clearly separated at the module level: synchronization message parsing, CPU processing, and parameter configuration constitute the data flow, while frame number statistics and hardware triggering constitute the trigger flow. Triggering and timing operations requiring precise timing are completed by hardware modules within the FPGA, while verification and configuration operations requiring flexible handling are completed by the CPU. The frequency reference value F arrives at the ONU with the synchronization message and is configured to the second timing module via the local synchronization module, ensuring that the ONU's timing parameters remain consistent with the OLT, providing a reliable guarantee for high-precision time synchronization.

[0120] In one optional implementation, the method for determining the synchronization time of the local synchronization module on the ONU side is explained.

[0121] In a PON system, synchronization messages sent from the OLT to the ONU need to be transmitted through the PON downlink. Although the PON physical layer has certain error protection mechanisms, in actual operation, the encapsulation and parsing of synchronization messages involves multiple layers of software and hardware logic on both the OLT and ONU sides. An occasional error in any of these links can cause individual bits to flip, resulting in a significant deviation between the time value parsed by the ONU and the actual time value sent by the OLT. If the ONU directly transmits the time without verification... R,K As a new value for the local system time, this will cause a significant jump in the ONU's local TOD time.

[0122] To address the aforementioned issues, in this implementation, the synchronization message carries, in addition to the frame number of the Kth transmitted frame and the theoretical reception time T, R,K In addition, it carries the frequency reference value F obtained from measurements on the OLT side. The ONU's local synchronization module does not use the theoretical reception time T. R,K Instead of directly writing the synchronization time into the second timing module, the theoretical reception time T is first calculated using the frequency reference value. R,K Perform a validity check and decide whether to use the original value or the corrected value based on the check results.

[0123] In this implementation, the steps of the local synchronization module include steps B1 to B3.

[0124] Step B1: Calculate the local expected reception time T R,e The local synchronization module obtains the current local system time T of the ONU. c and the frame number K of the downlink frame currently being received. c Based on the frame number difference (K - K) cBased on a 125-microsecond frame period and a frequency reference value F, the local system time should reach the value when the target frame K arrives, i.e., the local expected reception time T. R,e .

[0125] Step B2: Deviation Comparison. The local synchronization module will compare the theoretical reception time T sent by the OLT. R,K The calculated local expected reception time T R,e Compare the two and calculate the absolute value of the difference as the deviation.

[0126] Step B3: Judgment and Correction. If the deviation does not exceed the preset threshold, it indicates that T... R,K T is basically in line with local expectations. R,K Trustworthy, the local synchronization module sets the synchronization time to T. R,K If the deviation exceeds the preset threshold, it indicates that T... R,K There may be an anomaly; the local synchronization module may be malfunctioning with T. R,K The correction is made, and the corrected time is T. R,e ± Preset threshold, and set the corrected time as the synchronization time.

[0127] Subsequently, the local synchronization module will assign the frame number and synchronization time (possibly the original T) to the Kth transmitted frame. R,K The time value (or the corrected time value) is configured to the second timing module. When the received frame number equals K, the second timing module updates the ONU's local system time to this synchronization time.

[0128] In one alternative implementation, the synchronization message also carries the frequency reference value; This frequency reference value provides the ONU with a frame period timing reference that is of the same origin as the OLT. When the ONU uses the F value issued by the OLT to calculate the 125-microsecond frame period, the frame period timing reference on the ONU side and the OLT side are both established on the same physical time scale.

[0129] By introducing a verification and correction mechanism based on the frequency reference value F on the ONU side, this implementation method enables the ONU to no longer passively receive the T sent by the OLT. R,K It doesn't just measure the value, but rather proactively judges its rationality and corrects errors. When an anomaly occurs during the transmission or processing of a synchronization message, causing T... R,K When the time deviates from a reasonable range, the ONU can effectively identify and limit it, avoiding significant jumps in local TOD time and significantly improving the fault tolerance and long-term operational stability of the time synchronization system.

[0130] In one alternative implementation, the local expected reception time T is given. R,e One specific calculation method.

[0131] In this implementation, the local synchronization module obtains the current local system time T of the ONU. c and the frame number K of the downlink frame currently being received. c Among them, T c This is the ONU's local system time, continuously maintained by the second timing module; K c The data is obtained in real time from the downlink frame counter in the second PON MAC module.

[0132] The local synchronization module calculates the expected local reception time T using the following formula. R,e : T R,e = T c + (K - K c ) × 125; Where K is the frame number of the target synchronization frame carried in the synchronization message, K c The value is a positive integer less than K, and the 125-microsecond frame period is timed based on the frequency reference value F issued by the OLT.

[0133] In the above expression, starting from the current moment (when the ONU is receiving frame K)... c From the time when the target frame K arrives to the time when the target frame K arrives, it is necessary to pass through (K - K) in between. c (125 microsecond frame cycles) Therefore, the current local system time T c Add this (K - K) c The cumulative physical time corresponding to each frame period is the value that the local system time should reach when the target frame K arrives.

[0134] Since the timing of the 125-microsecond frame period is based on the frequency reference value F issued by the OLT, and the T is recursively calculated by the OLT side... R,K The frame period timing reference used is from the same source, therefore the T calculated by the ONU is the same. R,e T calculated by OLT R,K They are consistent on a physical timescale and are comparable.

[0135] Optional, T d The value can also be sent to the corresponding ONU along with the synchronization message, so that the ONU can perform more precise time verification or delay compensation.

[0136] The local synchronization module calculates the expected local reception time T using the following formula. R,e : T R,e = T c + (K - K c ) × 125 +T d .

[0137] In another alternative implementation, the expected value of the historical synchronization anchor point can be calculated.

[0138] In this implementation, after each successful time synchronization, the ONU's local synchronization module saves the frame number and corresponding synchronization time used for that synchronization as a historical synchronization anchor record. When a new synchronization message is received, the local synchronization module extracts the frame number K_prev and its corresponding synchronization time T_prev from the historical record and calculates the local expected reception time using the following formula: T R,e = T_prev + (K - K_prev) × 125.

[0139] In this method, the expected value is calculated based on the frame number and synchronization time of the last successful synchronization. Since T_prev itself is a reliable time value that has been corrected and verified by the OLT, the expected value calculated based on this has a smaller error and the verification result is more reliable. However, this method requires the ONU to maintain historical synchronization anchor point records, which consumes a small amount of storage resources.

[0140] It should be noted that the above-described method for calculating the expected value is merely an illustrative example. Those skilled in the art should understand that in practical applications, a suitable method can be selected to calculate the local expected reception time, or a combination or variation of the above methods can be used, depending on the ONU's hardware resources, synchronization accuracy requirements, and operating scenario. As long as the calculation process relies on the frequency reference value F issued by the OLT to ensure that the time scale of the expected value is consistent with that of the OLT, it falls within the scope of protection of this solution.

[0141] In one alternative implementation, the local synchronization module does not compare T in each received synchronization message. R,K With T R,e Instead, it determines whether to enable the verification mechanism based on whether the current synchronization is the first synchronization.

[0142] When the ONU first receives the synchronization message from the OLT, its local system time has not yet been synchronized with the OLT, and the deviation between them may be significant. At this time, if the ONU still follows the normal verification process, calculating the expected local reception time T based on the current local system time Tc and the frequency reference value F... R,e This expected value will inherit the initial deviation of the local system time, and the T value issued by the OLT. R,K They are no longer comparable. Therefore, T R,K With T R,e The deviation will inevitably far exceed the preset threshold, and the verification mechanism will misjudge T. R,KThe outlier value and its incorrect limiting correction caused the ONU to fail to obtain the correct system time during its first synchronization, or even fail to complete the first time alignment.

[0143] Therefore, when the ONU receives the OLT synchronization message for the first time, the local synchronization module compares it with the theoretical reception time T sent by the OLT. R,K With local expected reception time T R,e .

[0144] The local synchronization module maintains a synchronization status flag to record whether the ONU has completed time synchronization with the OLT at least once. This flag is initialized to an unsynchronized state when the ONU is powered on.

[0145] After receiving the synchronization message from the OLT, the local synchronization module first checks the synchronization status flag. If the flag is in an unsynchronized state, it indicates that this is the first synchronization, and the local synchronization module does not compare T. R,K With T R,e Directly put T R,K As the synchronization time, it is configured in the second timing module along with the frame number of the Kth transmitted frame; after the second timing module completes the time update, the local synchronization module updates the flag to the synchronized state. If the flag is already synchronized, it indicates that this is not the first synchronization, and the local synchronization module compares the theoretical reception time T sent by the OLT according to the normal verification process. R,K With local expected reception time T R,e The original value or the corrected value is used depending on whether the deviation exceeds the preset threshold. Then, the synchronization time and the frame number of the Kth transmission frame are configured to the second timing module.

[0146] By detecting the initial synchronization, the T data issued by the OLT is directly trusted during the initial synchronization. R,K This enables the ONU to quickly establish an initial time base aligned with the OLT. From the second synchronization onwards, a verification and clipping correction mechanism is enabled, ensuring the ONU's local time remains stable and interference-resistant during subsequent operation. This allows for smooth initiation of the synchronization process while continuously receiving verification protection.

[0147] After the ONU completes time synchronization with the OLT, its second timing module continuously keeps time based on the synchronized system time. Based on this time reference, the ONU has the ability to provide external time synchronization, providing a standard 1PPS+TOD time synchronization signal to connected downstream terminal devices (such as base stations, edge computing nodes, industrial controllers, etc.).

[0148] During the maintenance of the ONU's local system time, the second timing module uses the synchronized system time as a reference and generates a level transition (usually a rising edge) at the boundary of the whole second as a boundary marker for the 1PPS second pulse signal. This rising edge precisely corresponds to the start time of the current second. At the same time, it latches the TOD time value after the current second counter carries over (including year, month, day, hour, minute, and second information) as absolute time information bound to the edge of the 1PPS pulse.

[0149] The ONU outputs the latched TOD time value along with a 1PPS second pulse signal in a preset serial message format, forming a complete 1PPS+TOD time synchronization signal. The rising edge of the 1PPS pulse indicates the precise effective time of the time value in the TOD message. When downstream devices detect the effective edge of the 1PPS pulse, they latch the TOD message content to obtain a precise absolute time reference.

[0150] During the interval between two synchronization messages, the ONU relies on its second local clock for timing. Since the ONU's second local clock is also a standard crystal oscillator, it is subject to frequency drift, and the output 1PPS signal may gradually deviate from the correct timing during the interval. The ONU can take the following measures to suppress 1PPS drift.

[0151] The following methods are optional implementations provided in this embodiment. In actual applications, they can be selected according to the hardware resources of the ONU and the application scenario.

[0152] One possible drift suppression method is to increase the frequency of OLT sending synchronization messages and shorten the time interval between two synchronizations. Errors accumulate during the interval; the shorter the interval, the smaller the accumulated error. If the synchronization period is shortened from 1 second to 0.1 seconds, the 1PPS drift accumulation caused by crystal oscillator frequency offset is reduced by an order of magnitude, and the ONU can request the OLT to adjust the synchronization message sending period.

[0153] In addition, when the OLT sends a synchronization message, it can set the interval between the Kth transmission frame and the Nth transmission frame to a smaller value, so that each synchronization only calibrates the reception time of the nearest future frame, thereby reducing time error through high-frequency frame-by-frame or near-frame calibration.

[0154] The ONU can also estimate the actual operating frequency of its own crystal oscillator based on the difference between the theoretical reception time carried in two or more consecutive synchronization messages and the oscillation count of the second local clock in the corresponding period; and use the actual operating frequency to keep time during the interval to eliminate the influence of its own crystal oscillator frequency offset.

[0155] In actual operation, the PON time synchronization system may encounter various abnormal conditions. To ensure that the 1PPS+TOD signal output by the ONU does not jump, misalign, or interrupt due to abnormalities, this embodiment provides the following fault-tolerant processing mechanism.

[0156] When the upstream 1PPS / TOD signal is disconnected, for example, due to a failure of the upstream clock source device or a cable break between the OLT and the upstream clock source device, the OLT may not be able to receive the 1PPS signal or TOD message sent by the upstream time source device in a timely manner. The frequency measurement module on the OLT side detects the abnormal frequency measurement value through a safety threshold decision mechanism, automatically discards the measurement result, maintains the clock frequency reference value unchanged, and enters timekeeping mode. Based on the last valid frequency reference value, it continues timing and frame boundary identification, and continuously sends synchronization messages to the ONU. In this mode, the OLT's system time is maintained by the measured frequency F, and the timing accuracy is only affected by the short-term stability of the crystal oscillator, maintaining high accuracy for a relatively long period of time. At this time, the ONU continues to receive synchronization messages and execute the normal time update process, and its output 1PPS+TOD signal remains continuous and stable. After the upstream 1PPS / TOD signal is restored, the frequency measurement module detects that the 1PPS signal has stabilized again, re-executes the frequency measurement process, obtains a new valid frequency value, and updates the clock frequency reference value. The OLT automatically exits timekeeping mode and returns to normal calibration state. During the recovery process, the OLT smoothly transitions the system time to a state that is re-aligned with the upstream clock source, without causing time jumps.

[0157] If a synchronization message is lost or fails verification, for example due to a momentary interruption of the PON link or fluctuations in optical power, the ONU may fail to receive a synchronization message successfully, or the received synchronization message may contain a verification error. In this case, the ONU's local synchronization module does not forcibly refresh the local system time, but continues to count based on the currently synchronized system time and outputs a 1PPS+TOD signal, waiting for the next valid synchronization message. Synchronization messages are usually sent periodically, and the loss of a single message has a limited impact on the overall synchronization accuracy.

[0158] If the TOD and 1PPS do not match, meaning the downstream device detects an abnormal correspondence between the TOD message content output by the ONU and the 1PPS pulse boundary (e.g., the second value in the TOD message is not aligned with the second boundary of the 1PPS pulse), the ONU's local synchronization module can use the clock frequency reference value F issued by the OLT and the local expected time T. R,e Perform verification. If a deviation is found, correct it by limiting the amplitude or wait for the next valid synchronization message to restore the system, thus preventing downstream devices from using incorrect time information.

[0159] When a single ONU in the system fails to receive synchronization messages due to hardware failure, fiber optic cable breakage, or other reasons, that ONU enters timekeeping mode, relying on the last valid frequency reference value and the local crystal oscillator to continue timing and 1PPS+TOD output. This fault only affects this node and will not spread to other ONUs or OLTs; the time synchronization of the rest of the system continues to operate normally.

[0160] After the anomaly is resolved and synchronization messages resume normal transmission, the ONU's local synchronization module detects that the current local system time is different from the T time sent by the OLT. R,K There is a deviation between them. At this time, the ONU does not use a one-time jump to correct it, but uses the aforementioned smooth correction method to gradually eliminate the deviation within a preset correction period, ensuring that the 1PPS+TOD signal output to the outside world transitions smoothly during the recovery process and does not cause time jump impact on downstream equipment.

[0161] The system provided in this embodiment offers a continuous, stable, and reliable time reference for end-to-end time synchronization between OLT, ONU, and downstream terminal devices, meeting the high requirements for timing signals in application scenarios such as 5G, industrial PON, and edge computing.

[0162] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A clock synchronization circuit in a PON, characterized in that, Applied to an OLT, the OLT further includes a first CPU, a first FPGA, and a first local clock, wherein the first local clock uses a common crystal oscillator without a phase-locked loop to generate the system operating clock. The circuit includes a first timing module and a latching module located in the first FPGA, and a frequency measurement module located in the first CPU; wherein: The first timing module, including a nanosecond counter and a second counter, is configured to maintain the system time of the OLT based on the clock signal output by the first local clock and the current frequency reference value. The nanosecond counter is configured to accumulate the number of oscillations of the first local clock; each time the first local clock oscillates, the nanosecond counter increments by one. When the accumulated value of the nanosecond counter reaches the current frequency reference value, the second counter increments by one, and simultaneously, the nanosecond counter is reset to zero and begins accumulating again. The latching module is configured to latch the current count value of the nanosecond counter at the effective edge of the received external 1PPS signal in response to the external pulse-per-second (PPS) signal. The frequency measurement module is configured as follows: The difference between the count values ​​latched by the nanosecond counter at the effective edge of every two adjacent 1PPS signals is calculated to obtain the single frequency measurement value. Generate real-time frequency values ​​based on at least two single frequency measurements obtained within a preset calibration period; The real-time frequency value is compared with the nominal frequency value of the first local clock. If the deviation does not exceed a preset safety threshold, the current frequency reference value in the first timing module is updated to the real-time frequency value. If the deviation exceeds the safety threshold, the current frequency reference value in the first timing module remains unchanged.

2. The circuit according to claim 1, characterized in that: The calibration period is determined based on the operating environment of the first local clock. The calibration period for an operating environment with temperature changes is shorter than the calibration period for an operating environment without temperature changes.

3. The circuit according to claim 1 or 2, characterized in that: The frequency measurement module is specifically configured to generate the real-time frequency value after the OLT is initially powered on, including: Obtain at least two single frequency measurements from the calibration cycle; Abnormal data are removed from the at least two single-frequency measurements to obtain alternative measurement values; The candidate measurement values ​​are averaged to obtain the real-time frequency value.

4. A clock synchronization device in a PON, characterized in that, Applied to an OLT, the device includes: The clock synchronization circuit as described in any one of claims 1 to 3; The first frequency synchronization circuit is used to send the current frequency reference value determined by the clock synchronization circuit to the ONU after the ONU and the OLT have completed clock synchronization, so that the ONU can perform local time calculation based on the current frequency reference value.

5. The apparatus according to claim 4, characterized in that, The OLT further includes a first CPU and a first FPGA; the first frequency synchronization circuit includes a downstream synchronization module located in the first CPU and a first PON MAC module located in the first FPGA; wherein: The first timing module is also configured to generate a 125-microsecond transmission frame boundary based on the frequency reference value; The latch module is also configured to latch the transmission time of the Nth transmission frame; The downstream synchronization module is configured as follows: Obtain the transmission time of the Nth transmission frame; Based on the transmission time of the Nth transmission frame, determine the reception time T of the target optical network unit (ONU) for receiving the Nth transmission frame. R,N ; According to the reception time T of the Nth transmission frame R,N And the frame number difference between the Kth transmission frame and the Nth transmission frame, calculate the theoretical reception time T of the ONU receiving the Kth transmission frame. R,K ; The frame number of the Kth transmitted frame and the theoretical reception time T R,K The frequency reference value is sent to the first PON MAC module; The first PON MAC module is configured to send to the ONU the frame number of the Kth transmission frame and the theoretical reception time T. R,K The synchronization message with the frequency reference value enables the ONU to utilize the theoretical reception time T when it detects that the received transmission frame number is the frame number of the Kth transmission frame. R,K Perform a local time synchronization operation on the ONU; Where N is less than K, and both N and K are positive integers.

6. The apparatus according to claim 5, characterized in that, The device further includes an upstream synchronization module located in the first CPU, configured to perform time synchronization with an upstream clock source device; wherein: The latch module is also configured to respond to a 1PPS pulse signal sent by the upstream clock source device, latch and record the absolute time information in the TOD signal from the upstream clock source device at the current moment, and simultaneously latch the count value of the nanosecond counter at the current moment as the current count value; The upstream synchronization module is configured to determine the counter increment value based on the frequency reference value and a preset waiting time; to determine the target count value by summing the current count value and the counter increment value; and to determine the target time value by summing the absolute time information and the waiting time. The first timing module is further configured to receive a target count value and a target time value configured by the first CPU; and to update the system time of the OLT to the target time value when the nanosecond counter accumulates to the target count value.

7. The apparatus according to claim 5, characterized in that: The theoretical reception time T R,K The calculation expression is: T R,K = T R,N + (K - N) × 125 + T d ; Among them, T d The total hardware processing latency of the ONU is determined based on the MAC layer hardware processing latency between the OLT and the ONU.

8. A clock synchronization system in a PON, characterized in that, The system includes an OLT and at least one ONU, wherein the OLT is equipped with the apparatus as described in any one of claims 4 to 7, wherein a second local clock in the ONU for generating the system operating clock includes a phase-locked loop (PLL), the PLL being used to track a reference clock signal issued by the OLT, thereby synchronizing the local clock of the ONU with the local clock frequency of the OLT; the ONU further includes: The second frequency synchronization circuit is configured to receive an updated frequency reference value sent by the OLT after the ONU and the OLT have completed clock synchronization, or to periodically obtain the frequency reference value used by the first local clock in the OLT; when a change in the frequency reference value is detected, the updated frequency reference value is provided to the second timing module. The second timing module is configured to maintain the system time of the ONU based on the clock signal output by the second local clock and the updated frequency reference value.

9. The system according to claim 8, characterized in that, The ONU also includes a second CPU and a second FPGA; the second frequency synchronization circuit includes a local synchronization module located in the second CPU, and a second PON MAC module and a downlink frame counter located in the second FPGA; wherein: The second PON MAC module is configured to receive a synchronization message sent by the OLT, and parse the frame number of the Kth transmission frame and the theoretical reception time T from the synchronization message. R,K The parsing results, along with the current frequency reference value, will be reported to the local synchronization module. The local synchronization module is configured to synchronize based on the frame number of the Kth transmission frame and the theoretical reception time T. R,K Generate a synchronization time, and configure the frame number of the Kth transmission frame, the synchronization time, and the current frequency reference value into the second timing module; The downlink frame counter is configured to count the received frame numbers in real time, and trigger the second timing module when it is detected that the received frame number is equal to the frame number of the Kth transmitted frame; The second timing module is configured to update the local system time of the ONU to the synchronization time in response to the triggering of the downlink frame counter, and to continuously maintain the system time of the ONU based on the current frequency reference value and the clock signal output by the second local clock.

10. The system according to claim 9, characterized in that: The synchronization message also carries the frequency reference value; The local synchronization module is specifically configured to synchronize the theoretical reception time T sent by the OLT. R,K With local expected reception time T R,e Comparison; wherein the local expected reception time T R,e Based on the current local system time T of the ONU c And the frequency reference value is calculated; If the deviation between the two does not exceed the preset threshold, the local system time will be updated to T. R,K ; If the deviation between the two exceeds the preset threshold, then for T R,K Make corrections, where the corrected time is T. R,e ± the preset threshold.

11. The system according to claim 10, characterized in that: The local expected reception time T R,e The methods of obtaining it include: Obtain the current local system time T of the ONU c and the frame number K of the currently received downlink frame. c ; The local expected reception time is calculated using the following formula: T R,e = T c + (K - K c ) × 125; Among them, K c It is a positive integer less than K.

12. The system according to claim 10 or 11, characterized in that: The local synchronization module is further configured to, when the ONU is not receiving the synchronization message from the OLT for the first time, set the theoretical reception time T sent by the OLT. R,K With local expected reception time T R,e Compare them.

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