Communication method and communication apparatus

Abstract

The application provides a communication method and a communication device, which mainly relate to the design of a cyclic buffer sequence. The cyclic buffer sequence includes code word bits corresponding to remaining columns except for punctured columns in a first check matrix, and code word bits corresponding to extended rows with low row weights in the first check matrix are repeated at least once in the cyclic buffer sequence. Through the scheme of the application, the probability of transmitting code word bits corresponding to the extended rows with low row weights can be improved, the code word bits corresponding to the punctured columns can be quickly recovered, and the decoding performance can be improved.

Description

Technical Field

[0001] This application relates to the field of channel coding, and more specifically, to a communication method and related communication apparatus. Background Technology

[0002] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using simple feedback shift registers, reducing the coding complexity of LDPC codes.

[0003] Currently, the standard description of QC-LDPC codes uses base graphs (BGs) including BG1 and BG2. During rate matching, the first two columns of both BG1 and BG2 are fixed puncture columns. Using the first two columns of BG1 and BG2 as fixed puncture columns increases the maximum code rate supported by BG1 and BG2. For LDPC codes, each additional extension node adds one extension row and one extension column to the actual matrix used. These added extension rows and columns correspond to a set of codeword bits. During decoding, the extension rows with lower row weights in BG1 and BG2 help to quickly recover the codeword bits corresponding to the puncture columns.

[0004] In complex environments, wireless channel conditions change in real time, and initial transmissions often fail to meet system reliability requirements due to channel estimation errors. Incremental Redundancy Hybrid Automatic Repeat Request (IR-HARQ) combines channel coding and feedback retransmission. Based on the bit error rate of the initial transmission reported by the receiver, the transmitter can select from multiple incremental redundancy versions (e.g., RV0, RV1, RV2, or RV3) for retransmission. The receiver combines and decodes the initial and retransmissions, with different incremental redundancy versions corresponding to different retransmission start points. During both the initial and retransmission processes, the codeword bits corresponding to the smaller row weight extension rows of BG1 and BG2 may not be transmitted, affecting the rapid recovery of codeword bits corresponding to punctured columns. Summary of the Invention

[0005] This application provides a communication method and a communication device that can ensure the rapid recovery of codeword bits corresponding to punched columns.

[0006] Firstly, a communication method is provided, which can be executed by a transmitting device. Unless otherwise specified, "transmitting device" in this application can refer to a transmitting equipment (e.g., a network device, a terminal device, an encoding device, etc.), a component within the transmitting equipment (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the transmitting equipment. The components of the transmitting equipment can be within the transmitting device or can be independent of the transmitting device. The method can include: the transmitting device acquiring a first encoded sequence, which is a segment of codeword bits in a circular buffer sequence. The circular buffer sequence includes codeword bits corresponding to the remaining columns of a first parity check matrix, excluding the punctured column. The first parity check matrix includes the punctured column, a core column, and an extended column. The codeword bits corresponding to at least one extended row in the extended column are repeated at least once in the circular buffer sequence. The at least one extended column and at least one extended row correspond one-to-one. The element at the intersection of the at least one extended row and the punctured column is a non-zero element, and the element at the intersection of the at least one extended row and the core column is a zero element. The transmitting device then transmits the first encoded sequence.

[0007] The first encoding sequence can be a continuous codeword sequence or a non-continuous codeword sequence in the circular buffer sequence.

[0008] Among them, at least one extended row can also be called a low-weight extended row.

[0009] The above-mentioned scheme provided in this application repeats the codeword bits corresponding to the low-row-weight extended rows in the circular buffer sequence. This can increase the probability that the codeword bits corresponding to the low-row-weight extended rows are sent, facilitate the rapid recovery of the codeword bits corresponding to the punched columns, and improve decoding performance.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the method further includes: the transmitting device transmitting a second encoded sequence, the second encoded sequence including at least the codeword bits corresponding to the core column; the transmitting device receiving first indication information, the first indication information indicating that the decoding of the second encoded sequence has failed; the transmitting device transmitting the first encoded sequence includes: the transmitting device transmitting the first encoded sequence based on the first indication information.

[0011] It should be understood that the second encoding sequence mentioned above is the initial transmission sequence, and the first encoding sequence mentioned above is the retransmission sequence.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the second encoding sequence includes codeword bits corresponding to at least one extended column, while the first encoding sequence does not include codeword bits corresponding to at least one extended column.

[0013] The above-mentioned solution provided in this application ensures that the codeword bits corresponding to the extended row with low row weight are sent in the initial transmission, and the codeword bits corresponding to the extended row with low row weight are not sent again in the retransmission. This can ensure that the codeword bits corresponding to the extended row with low row weight are sent, the codeword bits corresponding to the punched column can be recovered quickly, and transmission resources can be saved.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the codeword bit corresponding to at least one of the extended columns appears once in the second encoding sequence.

[0015] The above-mentioned scheme provided in this application only requires sending the codeword bits corresponding to the low-line-weight extension line once when the initial transmission sends the codeword bits corresponding to the low-line-weight extension line. This can avoid information redundancy and save transmission resources.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the second encoding sequence includes a portion of the codeword bits corresponding to the at least one extended row, and the first encoding sequence includes the remaining portion of the codeword bits corresponding to the at least one extended row.

[0017] The above-mentioned solution provided in this application saves transmission resources by retransmitting the remaining part of the codeword bits corresponding to the extended line of low line weight after the initial transmission has sent part of the codeword bits corresponding to the extended line of low line weight.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the codeword bits corresponding to at least one of the extended columns appear once in a combined sequence of the second encoding sequence and the first encoding sequence.

[0019] The above-mentioned scheme provided in this application only requires sending the codeword bits corresponding to the extended line with low line weight once in the initial transmission and retransmission, which can avoid information redundancy and save transmission resources.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the second encoding sequence does not include codeword bits corresponding to at least one extended column, and the first encoding sequence includes codeword bits corresponding to at least one extended column.

[0021] The above-mentioned solution provided in this application ensures that the codeword bits corresponding to the extended row with low row weight are sent during the initial transmission if the codeword bits are not sent during the retransmission. This ensures that the codeword bits corresponding to the extended row with low row weight must be sent, thereby ensuring that the codeword bits corresponding to the punched column can be recovered quickly.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the codeword bit corresponding to at least one of the extended columns appears once in the first encoded sequence.

[0023] The above-mentioned scheme provided in this application only needs to send the codeword bits corresponding to the extended line with low line weight once when retransmitting the extended line with low line weight. This can avoid information redundancy and save transmission resources.

[0024] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned first encoding sequence is determined based on a first redundancy version, which is any one of RV0, RV1, RV2 or RV3, and RV0, RV1, RV2 and RV3 correspond to different starting positions in the circular buffer sequence.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, the codeword bits corresponding to at least one repeated extended column are located before the start position of RV2 in the circular buffer sequence and / or the codeword bits corresponding to at least one repeated extended column are located before the start position of RV3 in the circular buffer sequence.

[0026] The above-mentioned scheme provided in this application allows the codeword bits corresponding to the extended rows with low row weight to be sent first when they need to be sent. On the one hand, it can avoid disrupting the transmission order of the encoded sequence and ensure the accuracy of data transmission; on the other hand, it can enable the codeword bits corresponding to the punched columns to be recovered quickly, thereby improving decoding efficiency.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned punched columns are the first and second columns of the first verification matrix.

[0028] The above-mentioned scheme provided in this application uses columns with large column weights for punching, which can improve the maximum bit rate of data transmission on the one hand, and improve the threshold performance on the other hand.

[0029] In conjunction with the first aspect, in some implementations of the first aspect, the row weight of each of the at least one extended row mentioned above is 3.

[0030] Secondly, a communication method is provided, which can be executed by a receiving device. Unless otherwise specified, "receiving device" in this application can refer to a receiving device (e.g., network device, terminal device, encoding device, etc.), a component within the receiving device (e.g., processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the receiving device. The components of the receiving device can be within the receiving device or can be independent of the receiving device. The method may include: a receiving device acquiring first information to be decoded, the first information to be decoded being a codeword sequence in a circular buffer sequence, the circular buffer sequence including codeword bits corresponding to the remaining columns of a first parity check matrix excluding the punched column, the first parity check matrix including the punched column, a core column, and an extended column, the codeword bits corresponding to at least one extended row in the extended column being repeated at least once in the circular buffer sequence, the at least one extended column and at least one extended row corresponding one-to-one, the elements at the intersection of the at least one extended row and the punched column being non-zero elements, and the elements at the intersection of the at least one extended row and the core column being zero elements; the receiving device performing decoding based on the first information to be decoded and the circular buffer sequence to obtain the decoded sequence.

[0031] It should be understood that the second aspect corresponds to the first aspect mentioned above, and supplementary explanations and technical effects can be found in the description of the first aspect mentioned above.

[0032] Wherein, the first information to be decoded can be understood as the information of the first encoded sequence of the first aspect after transmission, and the second information to be decoded can be understood as the information of the second encoded sequence of the second aspect after transmission.

[0033] In conjunction with the second aspect, in some implementations of the second aspect, the above method further includes: the receiving device acquiring second information to be decoded, the second information to be decoded including at least codeword bits corresponding to the core column; the receiving device sending first indication information, the first indication information indicating that the decoding of the second information to be decoded has failed.

[0034] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned second information to be decoded includes codeword bits corresponding to at least one extended column, while the first information to be decoded does not include codeword bits corresponding to at least one extended column.

[0035] In conjunction with the second aspect, in some implementations of the second aspect, the codeword bit corresponding to at least one of the extended columns mentioned above appears once in the second information to be decoded.

[0036] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned second information to be decoded includes a portion of the codeword bits corresponding to at least one extended row, and the first information to be decoded includes the remaining portion of the codeword bits corresponding to at least one extended row.

[0037] In conjunction with the second aspect, in some implementations of the second aspect, the codeword bit corresponding to at least one of the above-mentioned extended columns appears once in the combined sequence of the second information to be decoded and the first information to be decoded.

[0038] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned second information to be decoded does not include codeword bits corresponding to at least one extended column, and the first information to be decoded includes codeword bits corresponding to at least one extended column.

[0039] In conjunction with the second aspect, in some implementations of the second aspect, the codeword bits corresponding to at least one of the above-mentioned extended columns appear once in the first information to be decoded.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned first information to be decoded is determined based on a first redundant version, which is any one of RV0, RV1, RV2 or RV3, and RV0, RV1, RV2 and RV3 correspond to different starting positions in the circular cache sequence.

[0041] In conjunction with the second aspect, in some implementations of the second aspect, the codeword bits corresponding to at least one repeated extended column are located before the start position of RV2 in the circular buffer sequence and / or the codeword bits corresponding to at least one repeated extended column are located before the start position of RV3 in the circular buffer sequence.

[0042] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned punched columns are the first and second columns of the first verification matrix.

[0043] In conjunction with the second aspect, in some implementations of the second aspect, the row weight of at least one of the above extended rows is 3.

[0044] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0045] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0046] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to perform the method of the first aspect or any possible implementation thereof; or to perform the method of the second aspect or any possible implementation thereof.

[0047] Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is used to call and run the computer programs or instructions from the at least one memory, causing the communication device to perform the method in the first aspect or any possible implementation thereof; or to perform the method in the second aspect or any possible implementation thereof.

[0048] Optionally, the at least one processor may be included in the communication device or configured outside the communication device.

[0049] In one possible implementation, the communication device further includes the at least one memory. Optionally, the processor and memory are integrated together.

[0050] In one possible implementation, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or it may be an interface circuit.

[0051] In one possible implementation, the communication device is a chip or chip system.

[0052] A sixth aspect provides a communication device, including a communication interface and a circuit, wherein the communication interface is configured to receive a signal to be processed and transmit the signal to the circuit; the circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof.

[0053] Optionally, the communication interface is further configured to output the signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0054] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0055] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0056] A ninth aspect provides a wireless communication system, including a communication device as described in the third aspect and a communication device as described in the fourth aspect. Attached Figure Description

[0057] Figure 1 Here is an example of a communication system 100 applicable to the technical solution of this application.

[0058] Figure 2 This is a schematic diagram of the basic process of wireless communication.

[0059] Figure 3 This is a schematic diagram of the parity check matrix H of an LDPC.

[0060] Figure 4 This is a Tanner plot of the parity-check matrix H of an LDPC.

[0061] Figure 5 This is a schematic diagram of the structure of the check matrix.

[0062] Figure 6 A schematic flowchart of the communication method 600 provided in this application.

[0063] Figure 7 This is a schematic diagram of an example of the base matrix provided in this application.

[0064] Figure 8 This is a schematic diagram of an example of a circular cache sequence provided in this application.

[0065] Figure 9 A schematic block diagram of the communication device 900 provided in this application.

[0066] Figure 10 A schematic structural diagram of the communication device 1000 provided in this application. Detailed Implementation

[0067] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, and future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Moreover, they can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi) and 3GPP-related communication systems, without limitation.

[0068] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0069] Figure 1 This is a schematic diagram of an example communication system 100 applicable to an embodiment of this application. Figure 1 This is a schematic diagram illustrating one possible, non-limiting system. For example... Figure 1 As shown, the communication system includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one network device (such as...). Figure 1 101a and 101b (collectively referred to as 110) and at least one terminal device (such as Figure 1 102a-102j, collectively referred to as 102, are included in RAN100. RAN100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment. Figure 1(Not shown in the image). Terminal device 102 is connected to network device 101 wirelessly. For example, network device 101 is connected to core network 200 wirelessly or via wired connection. The core network device in core network 200 and network device 101 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0070] The communication system 100 provided in this application may further include artificial intelligence (AI) network elements to implement some or all AI-related operations. AI network elements may also be referred to as AI nodes, AI devices, AI entities, AI modules, AI models, or AI units, etc. The AI ​​network elements may be built into the network elements of the communication system. For example, an AI network element may be an AI module built into: access network equipment, core network equipment, cloud server, or operation, administration, and maintenance (OAM) to implement AI-related functions. The OAM may act as the network management system for core network equipment and / or access network equipment. Alternatively, the AI ​​network element may also be an independently configured network element in the communication system. Optionally, the terminal or its built-in chip may also include an AI entity to implement AI-related functions.

[0071] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, point of sale (POS) machines, customer-premises equipment (CPEs), light user equipment (UEs), reduced capability user equipment (REDCAP UEs), wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc. Terminal equipment can also be vehicle-mounted devices (such as vehicle-mounted devices, vehicle-mounted modules, vehicle-mounted chips, on-board units (OBUs), or telematics boxes (T-BOXs)). Optionally, the UE can be used as a base station. For example, the UE can act as a scheduling entity, providing sidelink signaling between UEs in V2X or SL, etc.

[0072] In this embodiment, the device used to implement the functions of the terminal device can be the terminal device itself, or any device capable of supporting the terminal device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device is located on the terminal side and can be configured within or used in conjunction with the terminal device. The chip system can consist of chips or include chips and other discrete components. In this embodiment, the terminal device is used as an example to illustrate the device for implementing the corresponding functions of the terminal device.

[0073] The network device in this application embodiment may include a device for communicating with a terminal device. This network device may include an access network device or a radio access network device; for example, the network device may be a base station. In this application embodiment, the access network device may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. A base station can broadly encompass, or be replaced by, various names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device performing base station functions in D2D, V2X, and M2M communications, a network device (e.g., a base station) in a future communication network, or a device performing network device functions. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0074] Base stations can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, a helicopter or drone can be configured as a device to communicate with another base station.

[0075] In some deployments, the network device in this application embodiment may be a device including a CU, or a DU, or a device including both CU and DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network device may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0076] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0077] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0078] In this embodiment, the device used to implement the functions of the network device can be the network device itself; it can also be a device capable of supporting the network device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device is located on the network side and can be configured within or used in conjunction with the network device. In this embodiment, only the network device is used as an example to illustrate the implementation of the corresponding functions of the network device.

[0079] Figure 2This is a schematic diagram of the basic process of wireless communication. For example... Figure 2 As shown, in the signal transmitting device, the signal source is transmitted after sequentially undergoing source coding, channel coding, and modulation. The signal receiving device sequentially demodulates the received signal, performs channel decoding, and recovers the source before outputting the signal to the destination. Channel coding and modulation are among the core technologies in the field of wireless communication.

[0080] The communication method provided in this application can be used in dedicated network devices or general-purpose devices, and can be applied to the various network devices (e.g., base stations) and the various terminal devices mentioned above. Specifically, the communication method on the encoding side is mainly implemented through the channel coding unit (e.g., encoder or device supporting the encoder to perform corresponding functions) in these devices; the communication method on the decoding side is mainly implemented through the channel decoding unit (e.g., decoder or device supporting the decoder to perform corresponding functions) in these devices.

[0081] Optionally, the function of the channel coding unit or the channel decoding unit can be implemented by application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or by software (e.g., program code in memory), or by a combination of both, without limitation.

[0082] To facilitate understanding of the embodiments provided in this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0083] 1. LDPC code

[0084] LDPC codes are linear block codes, and their parity check matrix (JCD) is a sparse matrix. The number of zero elements in the LDPC JCD matrix is ​​far greater than the number of non-zero elements; in other words, the row and column weights of the JCD matrix are very small compared to the code length of the LDPC code. Specifically, an LDPC code with an information bit length of q and a code length of n can be uniquely determined by its JCD matrix H.

[0085] In 1981, Tanner represented the codewords of LDPC codes graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. The Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes; the other type consists of parity-check nodes, representing parity-check constraints. Each parity-check node represents a parity-check constraint. The following section will discuss this in conjunction with... Figure 2 and Figure 3 Please provide an explanation.

[0086] Figure 3 This is a schematic diagram of the parity check matrix H of an LDPC.

[0087] Figure 3 In the middle, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. Figure 3 In the diagram, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner diagram.

[0088] Figure 4 The Tanner plot of the parity-check matrix H of an LDPC.

[0089] like Figure 4As shown, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph is composed of interconnected vertices, with one vertex serving as both the start and end point of the cycle, and each node is visited only once. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to each parity bit in the LDPC. The connection between the two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th parity node and the j-th variable node, the element (i, j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. The connection between variable nodes and parity nodes can also be called an edge. The existence of a connection between the validation node and the variable node can also be described as: the validation node and the variable node are connected or have an edge. The connection between the validation node and the variable node can include either the presence of an edge or the absence of an edge.

[0090] As mentioned above, LDPC is a linear block code. A linear block code divides the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, a decoding device decodes the received signal to determine the original information bits.

[0091] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0092] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base grape (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, referred to as the base matrix H in this application. BG Basis matrix HBG An element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The following section discusses the base matrix H. BG The expansion process is described.

[0093] Based on the basis matrix H BG And the lifting size Zc can be used to transform the basis matrix H BG The matrix is ​​expanded into a complete parity-check matrix for encoding or decoding. In this application, Zc can also be referred to as the expansion factor, boosting factor, expansion value, expansion coefficient, boosting size, etc. The expansion process involves boosting all elements of the base matrix into a Zc*Zc square matrix, where 0 is boosted to a Zc*Zc zero matrix, 1 is boosted to a Zc*Zc identity matrix, and the identity matrix is ​​cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be left or right, and this application does not limit it. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking boosting 1 into a 4×4 identity matrix as an example, if the shifting values ​​are 0, 1, 2, and 3, the cyclically shifted matrix after a rightward cyclic shift is shown below:

[0094] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0095] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0096] (3) When the translation value is 2, the corresponding cyclically shifted matrix is:

[0097] (4) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0098] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the matrix corresponds to a Zc*Zc submatrix, and each element value indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. Therefore, the storage space required for the complete parity check matrix H is greatly reduced. (Exponential matrix H) b The elements in it can also be called QC blocks.

[0099] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0100]

[0101] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the matrix represents a square matrix of order Z. Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0102] For example, As shown below:

[0103]

[0104] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0105] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0106] 3. Column weight and row weight

[0107] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the descriptions of row and column weights is the parity check matrix H.

[0108] 4. Basic Structure of Basis Matrices

[0109] like Figure 5 As shown in (a), the base matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include... Figure 5As shown in (b), parts A and B are defined, where part A corresponds to information bits (or information digits, etc.), and part B is a square matrix corresponding to core check bits (or core check digits). Part B can also be the region corresponding to check columns with column weights greater than 1 in high-code-rate regions. A region of all zeros can correspond to... Figure 5 The C part of (b) is an all-zero matrix. The incremental redundancy region can correspond to Figure 5 Part D of (b). The Laptian-like region can correspond to Figure 5 The E part of (b) can be an identity matrix or a lower triangular matrix, corresponding to the parity bits of the low code rate extension.

[0110] Figure 5 The LDPC code shown employs a "raptor-like" base matrix structure, which can be progressively extended from a high-rate kernel matrix to a low-rate matrix, thus flexibly supporting encoding at various code rates. In practical applications, such as... Figure 5 As shown in (a), the first X rows and the first Y columns of the base matrix can be extracted. As the bitrate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0111] The LDPC basis matrix truncated at any bit rate can be represented by a parity-check matrix H, which can also be represented by an exponent matrix H. b Therefore, the structure of the LDPC basis matrix, the structure of the parity-check matrix H, and the structure of the exponent matrix H are related. b The structure is similar, and will not be described in detail here.

[0112] 5. Information column and validation column

[0113] The columns of the LDPC base matrix consist of information columns and check columns.

[0114] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0115] Check columns: Corresponding to check bits (or check digits, etc.), these can include core check columns and extended check columns. The core check columns are the columns corresponding to part B, and the extended check columns are the columns corresponding to part C or part E. Extended check columns can also be called raptor-like columns.

[0116] 6. Core matrix, core rows, core columns

[0117] Core line: This is the line corresponding to the core check bit. In other words, the core line is the line corresponding to the high bitrate region, or the line corresponding to part A, or the line corresponding to part B, or the line corresponding to part C.

[0118] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0119] The kernel matrix is ​​the portion of the LDPC base matrix consisting of all its core rows and columns. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the portion composed of parts A and B.

[0120] 7. Extended columns, non-extended columns, extended rows, and non-extended rows

[0121] For LDPC codes, each additional extension node adds one row and one column to the actual matrix used. In this application, these added row and column are referred to as extension columns and extension rows, respectively. Extension columns are the columns corresponding to the extension nodes; in other words, they correspond to the extended parity bits. Columns other than the extension columns are non-extension columns. Rows other than the extension rows are non-extension rows. Figure 5 For example, the columns in C and E are extended columns, and the rows in D and E are extended rows.

[0122] Furthermore, in this application, the portion consisting of non-extended columns can also be referred to as the core portion, and the portion consisting of extended columns can also be referred to as the extended portion. Figure 5 For example, the part consisting of A, B, and D is the core part, and the part consisting of C and E is the extension part.

[0123] 8. Drilling column

[0124] In LDPC codes, bits corresponding to punctured columns are not transmitted. Punctured columns can be either information columns or parity columns. Furthermore, columns in LDPC codes that are not punctured are also called non-punctured columns. Similarly, non-punctured columns can be either information columns or parity columns.

[0125] Generally, the punched columns for BG1 and BG2 are column 1 and column 2, respectively.

[0126] 9. Message length, code length, and code rate

[0127] The information length is the length of the information bits to be encoded (i.e., the number of bits contained). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0128] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0129] Bitrate refers to the ratio of information length to bit length.

[0130] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS) table.

[0131] As mentioned above, during rate matching, the first two columns of BG1 and BG2 are fixed punctured columns. Using the first two columns of BG1 and BG2 as fixed punctured columns increases the maximum code rate that BG1 and BG2 can support. For LDPC codes, each additional extension node adds one extension row and one extension column to the actual matrix used; the added extension row and column correspond to a set of codeword bits. During decoding, the extension rows with smaller row weights in BG1 and BG2 help to quickly recover the codeword bits corresponding to the punctured columns.

[0132] Wireless channel conditions in complex environments change in real time, and the initial transmission often fails to meet system reliability requirements due to channel estimation errors. IR-HARQ technology combines channel coding and feedback retransmission. Based on the bit error rate of the initial transmission reported by the receiver, the transmitter can select from multiple incremental redundancy versions (e.g., RV0, RV1, RV2, or RV3) for retransmission. The receiver combines and decodes the initial and retransmissions, with different incremental redundancy versions corresponding to different retransmission start points. During both the initial and retransmission processes, the codeword bits corresponding to the smaller row weights of BG1 and BG2 may not be transmitted, affecting the rapid recovery of codeword bits corresponding to punctured columns. Therefore, this application provides a communication method that ensures the rapid recovery of codeword bits corresponding to punctured columns.

[0133] The communication method provided in this application is described in detail below.

[0134] Figure 6 This is a schematic flowchart of the communication method 600 provided in this application. Steps S610 to S612 in method 600 can be performed by a transmitting device (or an information transmitting device). Optionally, method 600 further includes steps S614 to S616, which can be performed by a receiving device (or an information receiving device).

[0135] S610, the transmitting device acquires the first encoded sequence.

[0136] Specifically, the first encoding sequence is a segment of codeword bits in a circular buffer sequence. The circular buffer sequence includes codeword bits corresponding to the remaining columns in the first parity check matrix, excluding the punched columns. The first parity check matrix includes punched columns, core columns, and extended columns. The codeword bits corresponding to at least one extended column are repeated at least once in the circular buffer sequence. The at least one extended column and at least one extended row correspond one-to-one. The elements at the intersection of the at least one extended row and the punched column are non-zero elements, and the elements at the intersection of the at least one extended row and the core column are zero elements.

[0137] As mentioned above, based on the base matrix and the lifting size Zc, the base matrix can be expanded into a complete first parity-check matrix. Currently, the two base maps stored in the standard are BG1 and BG2. BG1 has a size of 46*68. The size of the base matrix truncated from BG1 based on a certain code rate is denoted as X*Y. Rows 1-4 of this base matrix are core rows, rows 5-X are extended rows, columns 1-26 are core columns, and columns 27-Y are extended columns. The first parity-check matrix expanded from this base matrix has rows 1-4*Zc as core rows, rows 4*Zc+1-X*Zc as extended rows, columns 1-26*Zc as core columns, and columns 26*Zc+1-Y*Zc as extended columns. That is, the rows after the expansion of the core rows of the base matrix can still be called the core rows of the first parity check matrix, the rows after the expansion of the base matrix can still be called the expansion rows of the first parity check matrix, the columns after the expansion of the parity columns of the base matrix can still be called the core columns of the first parity check matrix, and the columns after the expansion of the base matrix can still be called the expansion columns of the first parity check matrix.

[0138] Similarly, BG2 has a size of 42*52. The size of the base matrix truncated from BG2 based on a certain code rate is denoted as X*Y. Rows 1-4 of this base matrix are core rows, rows 5-X are extended rows, columns 1-14 are core columns, and columns 15-Y are extended columns. The first parity-check matrix extended from this base matrix has rows 1-4*Zc as core rows, rows 4*Zc+1-X*Zc as extended rows, columns 1-14*Zc as core columns, and columns 14*Zc+1-Y*Zc as extended columns. That is, rows after the expansion of the core rows of the base matrix can still be called core rows of the first parity-check matrix, rows after the expansion of the base matrix can still be called extended rows of the first parity-check matrix, columns after the expansion of the core columns of the base matrix can still be called core columns of the first parity-check matrix, and columns after the expansion of the base matrix can still be called extended columns of the first parity-check matrix.

[0139] For example, in the case of a punched column and the punched column being a core column, the core column involved in the embodiments of this application can be understood as a core column that does not include the punched column.

[0140] It should be understood that the circular buffer sequence entering the circular buffer does not include the codeword bits corresponding to the punched column.

[0141] Figure 7 A schematic diagram of a basis matrix is ​​shown.

[0142] Figure 7 Rows 1 to 10 and columns 1 to 32 of the base matrix are shown. It should be understood that... Figure 7 The diagram shows a portion of the base matrix, not all of it. In one example, the punched columns of the base matrix are columns 1 and 2. The extended row, which intersects the punched columns at non-zero elements and the core column at zero elements, is row 5. However, row 5 of the base matrix can be extended to rows 4*Zc+1 to 5*Zc of the first parity-check matrix. Therefore, rows 4*Zc+1 to 5*Zc of the first parity-check matrix can be considered at least one of the extended rows described above.

[0143] For example, each of the at least one extended row has a row weight of 3.

[0144] As shown above, for LDPC codes, each additional extension node adds one row and one column to the actual base matrix. In this application, the added row and column are referred to as the extension column and extension row, respectively, and can be considered as the corresponding extension row and extension column. At least one extension row corresponds to at least one extension column; therefore, the extension column corresponding to the 5th row of the base matrix should be the 27th column. The 27th column of the base matrix can be extended to columns 26*Zc+1 to 27*Zc in the first parity check matrix. Therefore, columns 26*Zc+1 to 27*Zc in the first parity check matrix can be considered as at least one extension column as described above.

[0145] It should be understood that one column of the base matrix corresponds to Zc columns in the first parity check matrix, which means one column of the base matrix corresponds to Zc codeword bits in the circular buffer sequence. Therefore, the description in this application of repeating the codeword bits corresponding to the 27th column of the base matrix at least once in the circular buffer sequence also means repeating the codeword bits corresponding to the 26*Zc+1th to 27*Zcth columns of the first parity check matrix at least once in the circular buffer sequence.

[0146] This application's embodiment uses the example of repeating the Zc codeword bits corresponding to the 27th column twice in the circular buffer sequence as an example. Figure 8 A schematic diagram of the corresponding circular cache sequence is provided.

[0147] Figure 8 The gray index value represents the position index in the circular cache sequence. For example, the first gray index value "0" represents the first position in the circular cache sequence, the second gray index value "1" represents the second position in the circular cache sequence, the third gray index value "2" represents the third position in the circular cache sequence, ..., the 68th gray index value "67" represents the 68th position in the circular cache sequence.

[0148] Figure 8 The unmarked index value below each grayed index value indicates the column number of the basis matrix corresponding to the Zc codeword bits placed at that position. Among them, the unmarked index value "2" represents the 3rd column of the basis matrix, the unmarked index value "3" represents the 4th column of the basis matrix, ..., the unmarked index value "67" represents the 68th column of the basis matrix.

[0149] The first ungrayed index value "2" represents the third column of the base matrix. Alternatively, the ungrayed index value "2" below the first grayed index value "0" represents the third column of the base matrix corresponding to the Zc codeword bits placed at the first position in the circular buffer sequence. Similarly, the ungrayed index value "2" below the first grayed index value "0" represents the Zc codeword bits corresponding to the third column of the base matrix placed at the first position in the circular buffer sequence. And so on, the ungrayed index value "3" below the second grayed index value "1" represents the Zc codeword bits corresponding to the fourth column of the base matrix placed at the second position in the circular buffer sequence, and so on, until the ungrayed index value "67" below the 68th grayed index value "67" represents the Zc codeword bits corresponding to the 68th column of the base matrix placed at the 68th position in the circular buffer sequence.

[0150] It can be seen that the Zc codeword bits corresponding to the 27th column of the basis matrix are repeated twice in the circular buffer sequence. The first repetition is at the 34th position in the circular buffer sequence, and the second repetition is at the 58th position in the circular buffer sequence.

[0151] S612, the transmitting device transmits the first encoded sequence. Correspondingly, the receiving device receives the first encoded sequence.

[0152] One possible implementation is that the first encoded sequence is a continuous sequence of codeword bits in a circular buffer sequence.

[0153] Another possible implementation is that the first encoded sequence is a non-contiguous segment of codeword bits in a circular buffer sequence.

[0154] For example, the first encoding sequence is determined based on a first redundancy version, which can be any one of RV0, RV1, RV2 or RV3, which correspond to different starting positions in the circular buffer sequence.

[0155] For example, when the first column of the base matrix is ​​a punched column, the starting position of RV0 in the circular buffer sequence is the first column of the base matrix that is not punched. For instance, if the first and second columns of the base matrix are punched columns, the starting position of RV0 in the circular buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the third column of the base matrix. When the first column of the base matrix is ​​not punched, the starting position of RV0 in the circular buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the first column of the base matrix. Alternatively, it can be understood that the starting position of RV0 in the circular buffer sequence is the first position in the circular buffer sequence.

[0156] For example, the starting position of RV1 in the circular buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the 20th column of the base matrix.

[0157] For example, the starting position of RV2 in the circular buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the 36th column of the base matrix.

[0158] For example, the starting position of RV3 in the circular buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the 59th column of the base matrix.

[0159] One possible implementation is that the codeword bits corresponding to at least one repeated extended column are located before the start of RV2 in the circular buffer sequence and / or the codeword bits corresponding to at least one repeated extended column are located before the start of RV3 in the circular buffer sequence. Therefore, it can be guaranteed that the codeword bits corresponding to at least one extended column can be sent first when needed.

[0160] For example, the starting position of RV2 in the circular buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the 36th column of the base matrix. The Zc codeword bits corresponding to the 36th column of the base matrix (i.e., the unmarked index value "35") are located at the 35th position in the circular buffer sequence (i.e., the marked index value "34"). Therefore, the Zc codeword bits corresponding to the 27th column of the base matrix in the first repetition can be placed at the 34th position in the circular buffer sequence (i.e., the marked index value "33"). Figure 8 As shown.

[0161] For example, the starting position of RV3 in the circular buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the 59th column of the base matrix. The Zc codeword bits corresponding to the 59th column of the base matrix (i.e., the unmarked index value "58") are located at the 59th position in the circular buffer sequence (i.e., the marked index value "58"). Therefore, the Zc codeword bits corresponding to the 27th column of the base matrix in the second repetition can be placed at the 58th position in the circular buffer sequence (i.e., the marked index value "57"). Figure 8 As shown.

[0162] One possible implementation, where the first encoding sequence is determined based on the first redundancy version, is as follows: if the first encoding sequence needs to send at least one codeword bit corresponding to an extended column, the starting position of the first encoding sequence can be sent from the position preceding the starting position of the first redundancy version in the circular buffer sequence; if the first encoding sequence does not need to send at least one codeword sequence corresponding to an extended column, the starting position of the first encoding sequence can be sent from the starting position of the first redundancy version in the circular buffer sequence.

[0163] Optionally, before step S612, the transmitting device may also transmit a second encoded sequence, which is also a segment of codeword bits in the circular buffer sequence. This second encoded sequence includes at least the codeword sequences corresponding to the core columns. Correspondingly, the receiving device receives this second encoded sequence. For example, if the punched columns of the base matrix are columns 1 and 2, and the core columns are columns 3 to 26, then the second encoded sequence includes at least the codeword bits corresponding to columns 3 to 26 of the base matrix.

[0164] If the receiving device fails to decode the second encoded sequence, it can send a first indication message to the sending device, which indicates that the decoding of the second encoded sequence has failed. Accordingly, the sending device receives the first indication message and sends the first encoded sequence based on the first indication message.

[0165] It should be understood that the second encoding sequence mentioned above can be the initial transmission, and the first encoding sequence mentioned above can be the retransmission.

[0166] For example, the second coding sequence is determined based on a second redundancy version. For instance, the second redundancy version is RV0.

[0167] The second coding sequence and the first coding sequence mentioned above can take many forms under different circumstances. Several possible forms are listed below.

[0168] Example 1: The second encoding sequence includes codeword bits corresponding to at least one of the above-mentioned extended columns, while the first encoding sequence does not include codeword bits corresponding to at least one of the above-mentioned extended columns.

[0169] For example, when the initial transmission code rate is low, the second encoding sequence includes codeword bits corresponding to at least one extended column, while the first encoding sequence may not include codeword bits corresponding to at least one extended column.

[0170] by Figure 8 The circular cache sequence shown is used as an example for illustration.

[0171] In one example, the second encoded sequence starts at the last codeword bit (i.e., the ungrayed index value "26") of the Zc codeword bits corresponding to the 27th column of the base matrix, which is determined based on RV0, and ends at the 27th column of the base matrix. In this codeword bit segment of the cyclic buffer sequence, at least one codeword bit corresponding to an extended column appears once, and the codeword bit corresponding to the at least one extended column is placed at the 25th position in the cyclic buffer sequence (i.e., the grayed index value "24"). The first encoded sequence starts at the last codeword bit (i.e., the ungrayed index value "46") of the Zc codeword bits corresponding to the 47th column of the base matrix, which is determined based on RV2.

[0172] In this example, the second encoding sequence includes codeword bits corresponding to at least one extended column. Therefore, the first encoding sequence does not need to repeatedly send codeword bits corresponding to at least one extended column. The starting position of the first encoding sequence can be sent from the starting position corresponding to RV2 in the circular buffer sequence. That is, the first encoding sequence can skip the codeword bits corresponding to at least one extended column at the 34th position in the circular buffer sequence.

[0173] In conjunction with the above example, the starting position of the first encoded sequence in another example is also determined based on RV2, and the ending position is the last codeword bit (i.e., the un-grayed index value "60") in the Zc codeword bits corresponding to the 61st column of the base matrix.

[0174] In this example, the second encoded sequence includes codeword bits corresponding to at least one extended column. Therefore, the first encoded sequence does not need to repeatedly transmit the codeword bits corresponding to at least one extended column. The starting position of the first encoded sequence can be started from the starting position corresponding to RV2 in the circular buffer sequence. That is, the first encoded sequence can skip the codeword bits corresponding to at least one extended column at position 34 in the circular buffer sequence. Furthermore, the first encoded sequence can also skip the codeword bits corresponding to at least one extended column at position 58 in the circular buffer sequence.

[0175] Example 2: In conjunction with Example 1, the codeword bits corresponding to at least one of the above extended columns appear once in the second encoding sequence.

[0176] by Figure 8 The circular cache sequence shown is used as an example for illustration.

[0177] In one example, the second encoded sequence begins at the position determined by RV0 and ends at the last codeword bit (i.e., the un-grayed index "36") corresponding to the 37th column of the base matrix. This codeword bit in the cyclic buffer sequence appears twice, corresponding to at least one extended column: first at position 25 (grayed index "24") and second at position 34 (grayed index "33"). The codeword bit corresponding to at least one extended column only needs to appear once in the second encoded sequence; that is, the second encoded sequence can skip either the codeword bit corresponding to at least one extended column at position 25 or position 34 in the cyclic buffer sequence.

[0178] Example 3: The second encoding sequence includes a portion of the codeword bits corresponding to at least one of the extended columns, and the first encoding sequence includes the remaining portion of the codeword bits corresponding to at least one of the extended columns.

[0179] by Figure 8 The circular cache sequence shown is used as an example for illustration.

[0180] In one example, the starting position of the second encoded sequence is the x-th codeword bit (i.e., the ungrayed index value "26") in the Zc codeword bits corresponding to the 27th column of the base matrix, which is determined based on RV0. In this codeword bit of the circular buffer sequence, a portion of the codeword bits corresponding to at least one extended column appears, that is, the first x codeword bits of the Zc codeword bits corresponding to at least one extended column appear. The first x codeword bits corresponding to at least one extended column are placed at the 25th position in the circular buffer sequence (i.e., the grayed index value "24"). The starting position of the first encoded sequence is the last codeword bit (i.e., the ungrayed index value "46") in the Zc codeword bits corresponding to the 47th column of the base matrix, which is determined based on RV2.

[0181] In this example, the second encoding sequence includes the first x codeword bits of the Zc codeword bits corresponding to at least one extended column. Therefore, the first encoding sequence does not need to repeatedly send the first x codeword bits of the Zc codeword bits corresponding to at least one extended column. The starting position of the first encoding sequence can be sent from the (x+1)th codeword bit of the Zc codeword bits at the position preceding the starting position of RV2 in the circular buffer sequence. That is, the first encoding sequence can skip the first x codeword bits of the Zc codeword bits corresponding to at least one extended column at the 34th position in the circular buffer sequence.

[0182] It should be understood that x is less than Zc.

[0183] Example 4: In conjunction with Example 3, the codeword bit corresponding to at least one of the above extended columns appears once in the combined sequence of the second encoding sequence and the first encoding sequence.

[0184] by Figure 8 The circular cache sequence shown is used as an example for illustration.

[0185] In one example, the starting position of the second encoded sequence is the x-th codeword bit (i.e., the ungrayed index value "26") in the Zc codeword bits corresponding to the 27th column of the base matrix, which is determined based on RV0. In this codeword bit segment of the circular buffer sequence, a portion of the codeword bits corresponding to at least one extended column appears, that is, the first x codeword bits in the Zc codeword bits corresponding to at least one extended column appear. The first x codeword bits corresponding to at least one extended column are placed at the 25th position in the circular buffer sequence (i.e., the grayed index value "24"). The starting position of the first encoded sequence is the last codeword bit (i.e., the ungrayed index value "60") in the Zc codeword bits corresponding to the 61st column of the base matrix, which is determined based on RV2.

[0186] In this example, the second encoded sequence includes the first x codeword bits of the Zc codeword bits corresponding to at least one extended column. Therefore, the first encoded sequence does not need to repeatedly transmit the first x codeword bits of the Zc codeword bits corresponding to at least one extended column. The starting position of the first encoded sequence can begin transmission from the (x+1)th codeword bit of the Zc codeword bits at the position preceding the starting position of RV2 in the circular buffer sequence. That is, the first encoded sequence can skip the first x codeword bits of the Zc codeword bits corresponding to at least one extended column at position 34 in the circular buffer sequence. Furthermore, the first encoded sequence can also skip the codeword bits corresponding to at least one extended column at position 58 in the circular buffer sequence.

[0187] Example 5: The second encoding sequence does not include the codeword bits corresponding to at least one of the above-mentioned extended columns, while the first encoding sequence includes the codeword bits corresponding to at least one of the above-mentioned extended columns.

[0188] For example, when the initial transmission code rate is high, the second encoding sequence does not include codeword bits corresponding to at least one extended column, while the first encoding sequence may include codeword bits corresponding to at least one extended column.

[0189] by Figure 8 The circular cache sequence shown is used as an example for illustration.

[0190] In one example, the second encoded sequence starts at the last codeword bit (i.e., the un-grayed index value "25") of the Zc codeword bits corresponding to the 26th column of the base matrix, which is determined based on RV0, and ends at the last codeword bit of the Zc codeword bits corresponding to the 26th column of the base matrix. No codeword bit corresponding to at least one extended column appears in this codeword bit of the cyclic buffer sequence. The first encoded sequence starts at the last codeword bit (i.e., the un-grayed index value "46") of the Zc codeword bits corresponding to the 47th column of the base matrix, which is determined based on RV2.

[0191] In this example, the second encoding sequence does not include codeword bits corresponding to at least one extended column. Therefore, the first encoding sequence needs to send codeword bits corresponding to at least one extended column. The starting position of the first encoding sequence can be sent from the position before the starting position of RV2 in the circular buffer sequence. That is, the first encoding sequence first sends codeword bits corresponding to at least one extended column at the 34th position in the circular buffer sequence.

[0192] Example 6: In conjunction with Example 5, the codeword bit corresponding to at least one of the above extended columns appears once in the first encoded sequence.

[0193] by Figure 8 The circular cache sequence shown is used as an example for illustration.

[0194] In one example, the second encoded sequence starts at the last codeword bit (i.e., the un-grayed index value "25") of the Zc codeword bits corresponding to the 26th column of the base matrix, which is determined based on RV0, and ends at the last codeword bit of the Zc codeword bits corresponding to the 26th column of the base matrix. No codeword bit corresponding to at least one extended column appears in this codeword bit of the cyclic buffer sequence. The first encoded sequence starts at the last codeword bit (i.e., the un-grayed index value "60") of the Zc codeword bits corresponding to the 61st column of the base matrix, which is determined based on RV2.

[0195] In this example, the second encoded sequence does not include codeword bits corresponding to at least one extended column. Therefore, the first encoded sequence needs to send codeword bits corresponding to at least one extended column. The first encoded sequence can start sending from the position preceding the starting position of RV2 in the circular buffer sequence; that is, the first encoded sequence first sends the codeword bits corresponding to at least one extended column at position 34 in the circular buffer sequence. Furthermore, the first encoded sequence does not need to repeat sending the codeword bits corresponding to at least one extended column; that is, the first encoded sequence can skip the codeword bits corresponding to at least one extended column at position 58 in the circular buffer sequence.

[0196] This embodiment illustrates the example of repeating the codeword bits corresponding to the 27th column of the base matrix at least once in the circular buffer sequence. Alternatively, the codeword bits corresponding to multiple columns of the base matrix can be repeated at least once in the circular buffer sequence; these multiple columns can be consecutive or non-consecutive. One possible implementation is that the repeated codeword bits corresponding to these multiple columns are located before the start position of RV2 in the circular buffer sequence and / or the repeated codeword bits corresponding to these multiple columns are located before the start position of RV3 in the circular buffer sequence.

[0197] It should be understood that the embodiments in this application are described using a single retransmission as an example, but this application does not limit the number of retransmissions. For example, a maximum number of transmissions can be pre-configured, and the sum of the initial transmission and retransmissions should not exceed this maximum number of transmissions. Alternatively, a maximum number of retransmissions can be pre-configured, and the sum of the retransmissions should not exceed this maximum number of retransmissions.

[0198] Optionally, method 600 may also include processing by the receiving end device. This will be described below with reference to S614 to S616.

[0199] S614, the receiving device acquires the first information to be decoded.

[0200] It should be understood that, due to the introduction of channel noise signals during transmission, the first coded sequence output by the transmitting device may differ from the first coded sequence received by the receiving device. The following example illustrates how the receiving device obtains the first information to be decoded from the transmitting device.

[0201] Specifically, the first information to be decoded is a segment of codeword bits in a circular buffer sequence. The circular buffer sequence includes codeword bits corresponding to the remaining columns in a first parity check matrix, excluding the punched columns. The first parity check matrix includes punched columns, core columns, and extended columns. The codeword bits corresponding to at least one extended column are repeated at least once in the circular buffer sequence. The at least one extended column and at least one extended row correspond one-to-one. The elements at the intersection of the at least one extended row and the punched column are non-zero elements, and the elements at the intersection of the at least one extended row and the core column are zero elements.

[0202] It should be understood that the first parity check matrix and circular buffer sequence involved in S614 can be referred to the description in S610 above, and will not be repeated here.

[0203] S616, the receiving device decodes based on the first information to be decoded and the circular buffer sequence to obtain the decoded sequence.

[0204] Specifically, the first piece of information to be decoded is a codeword bit in the circular buffer sequence.

[0205] One possible implementation is that the first piece of information to be decoded is a continuous sequence of codeword bits in a circular buffer sequence.

[0206] Another possible implementation is that the first piece of information to be decoded is a non-contiguous codeword bit in a circular buffer sequence.

[0207] For example, the first information to be decoded is determined based on a first redundant version, which is any one of RV0, RV1, RV2 or RV3, and RV0, RV1, RV2 and RV3 correspond to different starting positions in the circular buffer sequence.

[0208] One possible implementation is that the codeword bits corresponding to at least one repeated extended column are located before the start position of RV2 in the circular buffer sequence and / or the codeword bits corresponding to at least one repeated extended column are located before the start position of RV3 in the circular buffer sequence.

[0209] Optionally, before step S616, the receiving device may also acquire second decoding information, which is also a codeword sequence in the circular buffer sequence, and the second decoding information includes at least the codeword bits corresponding to the core column.

[0210] It should be understood that, due to the potential introduction of channel noise signals during transmission, the second coded sequence output by the transmitting device may differ from the second coded sequence received by the receiving device. The following example illustrates how the receiving device obtains the second information to be decoded from the transmitting device.

[0211] If the receiving device fails to decode the second information to be decoded, it can send a first indication message to the sending device, which indicates that the decoding of the second information to be decoded has failed.

[0212] It should be understood that the aforementioned second information to be decoded may be transmitted initially, and the aforementioned first information to be decoded may be transmitted again.

[0213] For example, the second information to be decoded is determined based on a second redundancy version. For instance, the second redundancy version is RV0.

[0214] The second information to be decoded and the first information to be decoded mentioned above can take many forms under different circumstances. Several possible forms are listed below.

[0215] Example 1: The second information to be decoded includes codeword bits corresponding to at least one extended column, while the first information to be decoded does not include codeword bits corresponding to at least one extended column.

[0216] It should be understood that Example 1 corresponds to Example 1 in step S612 above, and will not be repeated here.

[0217] Example 2, in conjunction with Example 1, shows that the codeword bits corresponding to at least one of the above extended columns appear once in the second information to be decoded.

[0218] It should be understood that Example 2 corresponds to Example 2 in step S612 above, and will not be repeated here.

[0219] Example 3: The second information to be decoded includes a portion of the codeword bits corresponding to the at least one extended row, and the first information to be decoded includes the remaining portion of the codeword bits corresponding to the at least one extended row.

[0220] It should be understood that Example 3 corresponds to Example 3 in step S612 above, and will not be repeated here.

[0221] Example 4, in conjunction with Example 3, the codeword bits corresponding to at least one of the above extended columns appear once in the combined sequence of the second and first information to be decoded.

[0222] It should be understood that Example 4 corresponds to Example 4 in step S612 above, and will not be repeated here.

[0223] Example 5: The second information to be decoded does not include the codeword bits corresponding to at least one of the above-mentioned extended columns, while the first information to be decoded includes the codeword bits corresponding to at least one of the above-mentioned extended columns.

[0224] It should be understood that Example 5 corresponds to Example 5 in step S612 above, and will not be repeated here.

[0225] Example 6, in conjunction with Example 5, shows that the codeword bits corresponding to at least one of the above extended columns appear once in the first information to be decoded.

[0226] It should be understood that Example Six corresponds to Example Six in step S612 above, and will not be repeated here. It should be understood that the receiving device can determine the position of the first information to be decoded in the circular buffer sequence based on the first redundancy version. Furthermore, the receiving device can determine the position of the second information to be decoded in the circular buffer sequence based on the second redundancy version. Based on this, the receiving device can merge the first and second information to be decoded for decoding to obtain the decoded sequence.

[0227] The following example illustrates how a receiving device determines the position of the first information to be decoded in a circular buffer sequence based on a first redundancy version. Since different redundancy versions correspond to different starting positions in the circular buffer sequence, the receiving device can determine the starting position of the first information to be decoded in the circular buffer sequence based on the first redundancy version. In one example, the ending position corresponding to each redundancy version in the circular buffer sequence is also predefined, so the receiving device can determine the ending position of the first information to be decoded in the circular buffer sequence based on the first redundancy version. In another example, the receiving device can determine the ending position of the second information to be decoded in the circular buffer sequence based on the length of the second information to be decoded.

[0228] For example, if the first redundancy version is RV2, and RV2's starting position in the cyclic buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the 36th column of the base matrix, and the ending position of RV2 in the cyclic buffer sequence is predefined as the last codeword bit among the Zc codeword bits corresponding to the 47th column of the base matrix, then the receiving device can determine that the first information to be decoded is from the first codeword bit to the last codeword bit among the Zc codeword bits corresponding to the 36th column of the base matrix in the cyclic buffer sequence. Alternatively, if the first redundancy version is RV2, and RV2's starting position in the cyclic buffer sequence is the first codeword bit among the Zc codeword bits corresponding to the 36th column of the base matrix, and the receiving device can determine that the length of the first information to be decoded is 12*Zc, then the receiving device can still determine that the first information to be decoded is from the first codeword bit to the last codeword bit among the Zc codeword bits corresponding to the 36th column of the base matrix in the cyclic buffer sequence.

[0229] For example, this embodiment of the application describes the first code-to-decode information as the code-to-decode information retransmitted for the first time. The receiving device may also receive code-to-decode information retransmitted multiple times. The processing of each retransmitted code-to-decode information can refer to the processing of the first code-to-decode information. If the receiving device receives code-to-decode information retransmitted multiple times, the receiving device can determine the position of each retransmitted code-to-decode information in the circular buffer sequence and merge the retransmitted code-to-decode information for decoding.

[0230] By using communication method 600, it is possible to ensure that the codeword bits corresponding to the extended rows with smaller row weights of the base matrix are sent during the initial transmission and retransmission, and to ensure the rapid recovery of the codeword bits corresponding to the punched columns, thereby improving decoding performance.

[0231] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0232] It is also understood that some coded sequence names are involved in the various embodiments of this application, and their naming does not limit the protection scope of the embodiments of this application.

[0233] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0234] It is also understood that, in the above method embodiments, the methods and operations implemented by the device can also be implemented by the components of the device (such as chips or circuits), without limitation.

[0235] Corresponding to the methods described in the above embodiments, this application also provides corresponding apparatuses, which include modules for executing the methods described above. These modules can be software, hardware, or a combination of both. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0236] Figure 9 A schematic block diagram of the communication device 900 provided in this application. Figure 9 The communication device 900 includes a processing unit 910 and a communication unit 920. This communication unit may also be referred to as a transceiver unit.

[0237] In one possible implementation, the device 900 can implement steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 910 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 920 is used to perform transmission-related operations of the transmitting device in the above method embodiments. For example, each unit of the communication device 900 is used to implement the following functions:

[0238] The processing unit 910 is used to acquire the cyclic buffer sequence; the communication unit 620 is used to send the first encoded sequence, which is a codeword sequence in the cyclic buffer sequence.

[0239] In various embodiments of the communication device 900 corresponding to the transmitting end device, the processing unit 910 is used to perform processing and / or operations implemented internally by the transmitting end device other than the sending and receiving actions, and the communication unit 920 is used to perform the receiving (or input) action of the transmitting end device, and / or to perform the sending (or output) action of the transmitting end device.

[0240] In another possible implementation, the device 900 can implement steps or processes corresponding to those executed by the receiving device in the above method embodiments, wherein the processing unit 910 is used to perform processing-related operations of the receiving device in the above method embodiments, and the communication unit 920 is used to perform transmission-related operations of the receiving device in the above method embodiments. For example, each unit of the communication device 900 is used to implement the following functions:

[0241] The communication unit 920 is used to acquire first information to be decoded, which is a codeword sequence in a circular buffer sequence; the processing unit 910 is used to decode based on the first information to be decoded to obtain the decoded sequence; the communication unit 920 is also used to output the decoded sequence.

[0242] In various embodiments of the communication device 900 corresponding to the receiving device, the processing unit 910 is used to perform processing and / or operations implemented internally by the receiving device, other than the sending and receiving actions. The communication unit 920 is used to perform the receiving (or input) action of the receiving device, and / or to perform the sending (or output) action of the receiving device.

[0243] It should be understood that the device 900 here is embodied in the form of a functional unit. The term "unit" here may refer to application-specific integrated circuits (ASICs), electronic circuits, processors (e.g., shared processors, proprietary processors, or group processors) and memories for executing one or more software or firmware programs, combined logic circuits, and / or other suitable components that support the described functions.

[0244] The apparatus 900 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting or receiving device in the above-described methods. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, a communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, each executing the transmitting and receiving operations and related processing operations in the respective method embodiments.

[0245] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In embodiments of this application, the device 900 can be the transmitting end device or the receiving end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on a chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitations are imposed here.

[0246] Figure 10 A schematic structural diagram of the communication device 1000 provided in this application. Figure 10 The communication device 1000 includes one or more processors 1010, which, through logic circuits and / or by executing a computer program, enable the communication device 1000 to implement the methods in any possible implementation of the above-described method embodiments. Optionally, the communication device may further include one or more memories 720 and one or more communication interfaces 1030. The processor 1010 is used to control the communication interface 1030 to transmit and receive signals, the memory 1020 is used to store the computer program, and the processor 1010 is used to call and run the computer program from the memory 1020, so that the communication device 1000 performs the processes performed by the transmitting or receiving device in the various method embodiments of this application.

[0247] For example, processor 1010 may have Figure 9 The processing unit 910 shown has the following functions, and the communication interface 1030 may have... Figure 9 The communication unit 1020 shown has the following functions. Specifically, the processor 1010 can be used to perform processing or operations executed internally by the communication device, and the communication interface 1030 is used to perform the sending and / or receiving operations of the communication device.

[0248] In one possible implementation, the communication device 1000 is a chip or a chip system. For example, it is a circuit or chip responsible for communication functions (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip or system-in-package (SIP) chip containing a modem core).

[0249] Optionally, the memory and processor in the above-described device embodiments can be physically independent units, or the memory can be integrated with the processor. This application does not impose any limitations on this.

[0250] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0251] In addition, this application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0252] Furthermore, this application also provides a chip including a processor, a memory for storing a computer program disposed independently of the chip, the processor being used to execute the computer program stored in the memory, causing a device on which the chip is mounted to perform operations and / or processes performed by a transmitting or receiving device in any of the method embodiments.

[0253] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include the memory.

[0254] Optionally, the processor can be one or more, and the memory can be one or more.

[0255] Furthermore, this application also provides a communication device (e.g., a chip or chip system) including a processor and a communication interface. According to the operations and / or processing performed by the transmitting or receiving device in any of the foregoing method embodiments, the communication interface is used to receive (or input) message bits to be encoded, and the processor encodes the message bits to be encoded. Optionally, the communication interface is also used to send (or output) data and / or information processed by the processor.

[0256] Furthermore, this application also provides a communication device including at least one processor coupled to at least one memory, the at least one processor being configured to execute a computer program or instructions stored in the at least one memory, causing the communication device to perform operations and / or processes performed by a transmitting end device or a receiving end device in any of the method embodiments.

[0257] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the method embodiments of this application.

[0258] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0259] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly implemented by the hardware processor, or implemented by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0260] The memory in this application embodiment can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be cache, random access memory (RAM), etc., and RAM can be used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0261] The methods provided in the above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, in the form of a computer program product. The computer program product may include one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media.

[0262] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0263] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0264] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0265] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0266] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0267] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0268] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A communication method, characterized in that, include: Obtain a first encoding sequence, which is a segment of codeword bits in a circular cache sequence. The circular cache sequence includes codeword bits corresponding to the remaining columns in a first parity check matrix, excluding the punched columns. The first parity check matrix includes the punched columns, core columns, and extended columns. The codeword bits corresponding to at least one extended column are repeated at least once in the circular cache sequence. The at least one extended column and at least one extended row correspond one-to-one. The elements at the intersection of the at least one extended row and the punched column are non-zero elements, and the elements at the intersection of the at least one extended row and the core column are zero elements. Send the first encoded sequence.

2. The method according to claim 1, characterized in that, The method further includes: Send a second encoded sequence, the second encoded sequence including at least the codeword bits corresponding to the core column; Receive a first indication message, which indicates that the decoding of the second encoded sequence has failed; Sending the first encoded sequence includes: sending the first encoded sequence based on the first indication information.

3. The method according to claim 2, characterized in that, The second encoding sequence includes codeword bits corresponding to the at least one extended column, while the first encoding sequence does not include codeword bits corresponding to the at least one extended column.

4. The method according to claim 3, characterized in that, The codeword bit corresponding to at least one extended column appears once in the second encoding sequence.

5. The method according to claim 2, characterized in that, The second encoding sequence includes a portion of the codeword bits corresponding to the at least one extended line, and the first encoding sequence includes the remaining portion of the codeword bits corresponding to the at least one extended line.

6. The method according to claim 5, characterized in that, The codeword bits corresponding to at least one extended column appear once in the combined sequence of the second encoding sequence and the first encoding sequence.

7. The method according to claim 2, characterized in that, The second encoding sequence does not include the codeword bits corresponding to the at least one extended column, and the first encoding sequence includes the codeword bits corresponding to the at least one extended column.

8. The method according to claim 7, characterized in that, The codeword bits corresponding to at least one extended column appear once in the first encoded sequence.

9. The method according to any one of claims 1 to 8, characterized in that, The first encoding sequence is determined based on a first redundancy version, which is any one of RV0, RV1, RV2 or RV3, and RV0, RV1, RV2 and RV3 correspond to different starting positions in the circular buffer sequence.

10. The method according to claim 9, characterized in that, The codeword bits corresponding to the repeated at least one extended column are located before the start position of RV2 in the cyclic buffer sequence and / or the codeword bits corresponding to the repeated at least one extended column are located before the start position of RV3 in the cyclic buffer sequence.

11. The method according to any one of claims 1 to 10, characterized in that, The punched columns are the first and second columns of the first verification matrix.

12. The method according to any one of claims 1 to 11, characterized in that, The row weight of each of the at least one extended row is 3.

13. A communication method, characterized in that, include: Obtain first decoding information, which is a segment of codeword bits in a circular cache sequence. The circular cache sequence includes codeword bits corresponding to the remaining columns in a first parity check matrix excluding the punched columns. The first parity check matrix includes the punched columns, core columns, and extended columns. The codeword bits corresponding to at least one extended column are repeated at least once in the circular cache sequence. The at least one extended column and at least one extended row correspond one-to-one. The elements at the intersection of the at least one extended row and the punched column are non-zero elements, and the elements at the intersection of the at least one extended row and the core column are zero elements. Decoding is performed based on the first information to be decoded and the circular buffer sequence to obtain the decoded sequence.

14. A communication device, characterized in that, It includes at least one processor, said at least one processor being configured to execute a computer program to cause the communication device to perform the method as described in any one of claims 1 to 13.

15. The communication device according to claim 14, characterized in that, It also includes at least one memory for storing computer programs.

16. The communication device according to claim 14 or 15, characterized in that, It also includes a communication interface for inputting and / or outputting signals.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, cause the method as described in any one of claims 1 to 13 to be performed.

18. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the method as described in any one of claims 1 to 13 to be performed.

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