A decoding method and device based on repetition coding, equipment and medium

Abstract

A decoding method and device based on repetition coding, equipment and medium, relate to the technical field of data transmission. The method is applied to a receiving end device, comprising: initializing an LLR sequence of a current FEC encoding block and a cost function for evaluating the quality of the LLR sequence; receiving OFDM symbols corresponding to the FEC encoding block, demodulating an OFDM symbol to obtain an original LLR value when the OFDM symbol is received, obtaining an updated LLR sequence according to the original LLR value, and updating the cost function accordingly; when FEC decoding has not been started, after completing the reception and updating of each OFDM symbol, if the value of the new cost function is greater than or equal to a preset convergence threshold, the FEC decoding is started in advance before the completion of the reception of all symbols; if all symbols have been received and the FEC decoding has not been started, the FEC decoding is started based on the current LLR sequence. The application shortens the decoding delay and reduces the power consumption when the channel is good, and guarantees the decoding reliability when the channel is poor.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to a decoding method, apparatus, device and medium based on repetitive coding. Background Technology

[0002] To ensure data transmission reliability under interference such as noise and fading, the receiving end typically uses forward error correction (FEC) coding combined with repetition coding for data transmission. This involves mapping bits in the same FEC coding block to multiple symbols through repetition coding and sending them. The receiving end then merges and decodes the received symbols to obtain a more robust log-likelihood ratio (LLR) information, thereby reducing the bit error rate and improving transmission reliability.

[0003] Related technologies typically employ a decoding method based on repetition coding. This involves the receiving device waiting for all symbols corresponding to the current FEC coding block to be received before demodulating each received symbol one by one to obtain the original LLR value of the bit carried by each symbol. Then, according to the repetition coding mapping rule, multiple original LLR values ​​carrying the same bit are merged into the LLR value of the corresponding position of that bit in the FEC coding block to obtain the complete merged LLR sequence of the FEC coding block. After merging all symbols, the receiving device then starts FEC decoding once based on the complete LLR sequence and outputs the decoding result of the FEC coding block.

[0004] However, in application scenarios with good channel conditions or high repetition rates, the overall reliability of the resulting LLR sequence is often sufficient to support correct decoding once some symbols have been merged, and the merging of subsequent symbols contributes little to the decoding result. The aforementioned related technical solutions, by waiting for all symbols to be received before initiating FEC decoding, require the receiving equipment to continue waiting for the reception and merging of remaining symbols even when the required reliability has been achieved, thus increasing the decoding delay of a single FEC coded block. Summary of the Invention

[0005] This application provides a decoding method, apparatus, device, and medium based on repetition coding, which shortens decoding delay and reduces power consumption when the channel is good, and ensures the decoding reliability of FEC coded blocks based on repetition coding when the channel conditions are poor.

[0006] Firstly, this application provides a decoding method based on repetition coding, applied to a receiving device, comprising: initializing the log-likelihood ratio (LLR) sequence and cost function of the current FEC coded block, wherein the LLR sequence contains the LLR values ​​corresponding to each bit of the FEC coded block, and the cost function is a numerical value used to evaluate the quality of the LLR sequence; receiving OFDM symbols corresponding to the FEC coded block, wherein when receiving an OFDM symbol, receiving and updating the currently received OFDM symbol is performed, the receiving and updating process including: demodulating the currently received OFDM symbol to obtain the original LLR value, and determining the bits carried by the currently received OFDM symbol in the FEC coding according to the repetition coding mapping rule. At the corresponding position in the block, the original LLR value is merged into the corresponding LLR value in the LLR sequence to obtain the updated LLR sequence. The cost function is then updated based on the updated LLR sequence to obtain a new cost function. Before FEC decoding is started, after each OFDM symbol reception and update process is completed, if the value of the new cost function is greater than or equal to the preset convergence threshold, FEC decoding is started based on the current LLR sequence before all symbols corresponding to the FEC coded block are received. If all symbols corresponding to the FEC coded block have been received but FEC decoding has not yet started, FEC decoding is started based on the current LLR sequence. The FEC decoding result of the FEC coded block is output.

[0007] By adopting the above technical solution, the receiving device performs reception and update processing for each OFDM symbol received. The original LLR values ​​are merged into the corresponding positions in the LLR sequence according to the repetition coding mapping rule, causing the absolute value of the LLR value at that position to increase successively. The cost function is updated accordingly, thereby quantifying the overall reliability of the current LLR sequence symbol by symbol. Addressing the issues of related technologies that wait for all symbols to be received before initiating FEC decoding, and continue waiting for remaining symbols even when reliability requirements are met, thus increasing decoding delay and wasting power, the receiving device initiates FEC decoding in advance when the value of the new cost function is greater than or equal to a preset convergence threshold. This allows FEC decoding to be combined with the reception of subsequent symbols in parallel, without waiting for remaining symbols. For situations with poor channel conditions and the cost function never reaching the threshold, the receiving device initiates FEC decoding as a fallback after all symbols have been received, maintaining the same decoding performance as the fixed-wait scheme. Therefore, the receiving device shortens the decoding delay of a single FEC coding block and reduces power consumption when the channel is good, while ensuring decoding reliability when the channel is poor.

[0008] In conjunction with some embodiments of the first aspect, some embodiments further include: initializing the repetition count of each bit in the LLR sequence, where the repetition count represents the number of times the corresponding bit has been merged; updating the repetition count of the bits at the corresponding positions during the reception and update process; before FEC decoding is started, after completing the reception and update process for each OFDM symbol, obtaining the repetition count of each bit in the current LLR sequence and the current cost function; when the repetition count of a bit in the LLR sequence is less than a preset counting threshold, or the value of the new cost function is less than a preset convergence threshold, continuing to receive the next OFDM symbol and performing reception and update processing; when the repetition count of each bit in the LLR sequence is greater than or equal to the preset counting threshold, and the value of the new cost function is greater than or equal to the preset convergence threshold, starting FEC decoding based on the current LLR sequence before all symbols corresponding to the FEC coding block have been received.

[0009] By adopting the above technical solution, the receiving device establishes a repetition count for each bit in the LLR sequence during initialization, and updates the repetition count of the merged bits during each reception and update process, so that the amount of soft information sources currently accumulated for each bit can be recorded separately. In the start judgment, the receiving device requires that the repetition count of each bit is greater than or equal to a preset counting threshold and the current cost function value is greater than or equal to a preset convergence threshold before starting FEC decoding in advance. Since the cost function represents the overall level of the LLR sequence, even if individual bits have too few merges and insufficient soft information, the cost function may accidentally reach the threshold due to the large LLR values ​​of other bits. By introducing the bit-by-bit constraint of repetition counting, the receiving device eliminates premature start in such cases, ensuring that each bit has accumulated sufficient soft information sources when starting early, thereby increasing the probability of successfully decoding the FEC coded block after starting FEC decoding in advance.

[0010] In conjunction with some embodiments of the first aspect, in some embodiments, the cost function is determined based on the LLR value corresponding to each bit in the LLR sequence, and the cost function is calculated according to the following formula: Where Q represents the cost function, L represents the number of bits in the FEC coded block, and i represents the bit index. , This represents the LLR value corresponding to the i-th bit in the LLR sequence; the value of the cost function increases as the absolute value of the LLR value corresponding to each bit in the LLR sequence increases.

[0011] By adopting the above technical solution, the receiving device takes the cost function as the ratio of the sum of squares of the LLR values ​​corresponding to each bit in the LLR sequence to the number of bits L, that is, the average energy of the LLR sequence. Since the larger the absolute value of the LLR value, the higher the reliability of the decision of the corresponding bit, after the receiving device adopts the sum of squares form, the value of the cost function increases monotonically with the increase of the absolute value of the LLR value of each bit, thus continuously reflecting the overall reliability of the LLR sequence with a single value.

[0012] In conjunction with some embodiments of the first aspect, in some embodiments, the cost function is updated according to the updated LLR sequence to obtain a new cost function, including: determining the change in the LLR value at the corresponding position in the LLR sequence relative to the value before merging after the original LLR value of the currently received OFDM symbol is merged into the LLR sequence; and performing a recursive operation on the cost function before this reception based on the change to obtain a new cost function after this reception.

[0013] By adopting the above technical solution, after each merging of the original LLR values, the receiving device first determines the change in the LLR value at the corresponding position in the LLR sequence relative to the value before merging. Then, based on this change, it performs a recursive operation on the cost function before this reception to obtain a new cost function. Since only the LLR value at the corresponding position of the bit carried by each OFDM symbol changes when it is received and merged, the receiving device only needs to perform incremental calculations based on the changed corresponding positions using the recursive operation. It does not need to traverse all bits in the LLR sequence and recalculate the sum of squares each time it is updated, thereby reducing the computational complexity of updating the cost function and enabling the receiving device to update the cost function in real time during the symbol-by-symbol reception and merging process.

[0014] In conjunction with some embodiments of the first aspect, in some embodiments, the preset convergence threshold is determined based on the channel state, and the method further includes: determining a channel quality parameter characterizing the current channel quality based on the channel state information obtained when receiving OFDM symbols; mapping the channel quality parameter to a preset convergence threshold according to a preset mapping relationship, wherein in the mapping relationship, the preset convergence threshold increases as the channel quality parameter increases; and in the determination of starting FEC decoding, the preset convergence threshold obtained by mapping is used as the preset convergence threshold.

[0015] By adopting the above technical solution, the receiving device determines the channel quality parameters based on the channel state information acquired when receiving OFDM symbols, and then maps them to a preset convergence threshold according to a preset mapping relationship. In this mapping relationship, the preset convergence threshold increases with the increase of the channel quality parameters. When the channel quality is good, the receiving device maps to a higher preset convergence threshold, requiring the LLR sequence to reach a higher reliability level before initiation, ensuring a high probability of successful decoding after early initiation when the channel is good. When the channel quality is poor, the receiving device maps to a lower preset convergence threshold, allowing the LLR sequence to initiate at a relatively lower reliability level, avoiding difficulty in early initiation due to an excessively high threshold. Thus, the receiving device adaptively changes the timing of early initiation according to channel quality, balancing decoding reliability and decoding delay under different channel conditions.

[0016] In conjunction with some embodiments of the first aspect, some embodiments further include: during the iterative decoding process after initiating FEC decoding, obtaining iterative state information fed back by FEC decoding that characterizes the current decoding convergence degree; adjusting a preset convergence threshold according to the iterative state information to obtain an adjusted preset convergence threshold; and using the adjusted preset convergence threshold as the preset convergence threshold when performing the determination to initiate FEC decoding on an FEC coding block received after the FEC coding block.

[0017] By adopting the above technical solution, during the iterative decoding process after initiating FEC decoding, the receiving device acquires the iterative state information from the FEC decoding feedback, which characterizes the current decoding convergence level. Based on this information, it adjusts the preset convergence threshold and then uses the adjusted preset convergence threshold to determine the initiation of subsequent received FEC coded blocks. When the iterative state information indicates a low decoding convergence level, the receiving device increases the preset convergence threshold, allowing subsequent blocks to start earlier with a higher LLR reliability. When decoding converges with fewer iterations and there is a reliability margin, the receiving device decreases the preset convergence threshold, allowing subsequent blocks to start even earlier to further reduce latency. Thus, the receiving device uses the actual decoding results as feedback to form a closed-loop adjustment of the preset convergence threshold, ensuring that the threshold continuously matches the current decoding difficulty, reducing decoding latency while guaranteeing successful decoding.

[0018] In conjunction with some embodiments of the first aspect, in some embodiments, after initiating FEC decoding, the method further includes: if FEC decoding fails to decode the FEC coded block after reaching a preset maximum number of iterations, and the symbols corresponding to the FEC coded block have not all been received, then continue receiving the remaining OFDM symbols of the FEC coded block; for each OFDM symbol to be received, perform reception and update processing to obtain an updated LLR sequence; and continue FEC decoding based on the updated LLR sequence until FEC decoding successfully decodes the FEC coded block, or all symbols corresponding to the FEC coded block have been received.

[0019] By adopting the above technical solution, if the receiving device fails to decode the FEC coded block successfully after reaching the preset maximum number of iterations and before all symbols have been received after initiating FEC decoding in advance, it continues to receive the remaining OFDM symbols. For each symbol received, it performs reception and update processing, further increasing the absolute value of the LLR value at the corresponding position in the LLR sequence and improving the overall reliability. Then, it continues FEC decoding based on the updated LLR sequence. Therefore, if decoding is not successful immediately after initiation, the receiving device does not need to revert to a fixed waiting mode. Instead, it gradually approaches successful decoding through continuous reception and decoding, preserving the latency benefits of initiation while ensuring decoding reliability by supplementing the soft information of subsequent symbols.

[0020] Secondly, this application provides a decoding apparatus based on repetition coding, applied to a receiving end device, characterized in that it includes: an initialization module, used to initialize the log-likelihood ratio (LLR) sequence and cost function of the current FEC coding block, wherein the LLR sequence contains the LLR values ​​corresponding to each bit of the FEC coding block, and the cost function is a value used to evaluate the quality of the LLR sequence; and a receiving and updating module, used to receive OFDM symbols corresponding to the FEC coding block one by one, and to perform receiving and updating processing on the currently received OFDM symbol when receiving an OFDM symbol, wherein the receiving and updating processing includes: demodulating the currently received OFDM symbol to obtain the original LLR value, determining the position of the bit carried by the currently received OFDM symbol in the FEC coding block according to the repetition coding mapping rule, and merging the original LLR value into the LLR sequence. The LLR value at the corresponding position in the R sequence is used to obtain the updated LLR sequence, and the cost function is updated according to the updated LLR sequence to obtain a new cost function; the control module is used to control the FEC decoding module to start FEC decoding based on the current LLR sequence after each OFDM symbol reception and update processing is completed, if the value of the new cost function is greater than or equal to the preset convergence threshold, and before all symbols corresponding to the FEC coding block have been received; and it is used to control the FEC decoding module to start FEC decoding based on the current LLR sequence when all symbols corresponding to the FEC coding block have been received but FEC decoding has not yet started; the FEC decoding module is used to perform FEC decoding on the LLR sequence under the control of the control module and output the FEC decoding result of the FEC coding block.

[0021] Thirdly, this application provides a receiving device, characterized in that the receiving device includes: one or more processors and a memory; the memory is coupled to one or more processors, the memory is used to store computer program code, the computer program code includes computer instructions, and one or more processors call the computer instructions to cause the receiving device to perform the method described in any of the above embodiments.

[0022] Fourthly, this application provides a computer-readable storage medium storing computer instructions that, when executed on a receiving device, cause the receiving device to perform the method described in any of the above embodiments.

[0023] It is understood that the receiving device provided in the second aspect, the computer-readable storage medium provided in the third aspect, and the computer program product provided in the fourth aspect are all used to execute the methods provided in the embodiments of this application. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods, and will not be repeated here. Attached Figure Description

[0024] Figure 1 A schematic diagram of a system frame structure for a decoding method based on repetitive encoding in an embodiment of this application;

[0025] Figure 2 This is a flowchart illustrating a decoding method based on repeated encoding in an embodiment of this application;

[0026] Figure 3 This is another flowchart illustrating a decoding method based on repeated encoding in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the channel quality parameter-threshold mapping relationship curve of a decoding method based on repetitive coding in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of a virtual device structure for a decoding device based on repeated encoding in an embodiment of this application;

[0029] Figure 6 This is a schematic diagram of the physical device structure of a receiving end device in the embodiments of this application.

[0030] Figure Labels

[0031] 501. Initialization module; 502. Update receiving module; 503. Control module; 504. FEC decoding module; 505. Threshold configuration module; 506. Threshold adjustment module.

[0032] 601. CPU (Central Processing Unit); 602. ROM (Read-Only Memory); 603. RAM (Random Access Memory); 604. Bus; 605. I / O Interface; 606. Input Section; 607. Output Section; 608. Storage Section; 609. Communication Section; 610. Driver; 611. Removable Media. Detailed Implementation

[0033] The terminology used in the following embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification of this application, the singular expressions “a,” “an,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this application refers to any or all possible combinations including one or more of the listed items.

[0034] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0035] Combination Figure 1 This section introduces application scenarios for embodiments of this application. Please refer to [link / reference]. Figure 1 This is a schematic diagram of a system frame structure for a decoding method based on repetitive encoding in an embodiment of this application.

[0036] The decoding method based on repetitive coding provided in this application can be applied to digital communication systems that use Orthogonal Frequency Division Multiplexing (OFDM) modulation and forward error correction (FEC) coding concatenated with repetitive coding for data transmission. Exemplarily, this communication system can be a broadband power line carrier communication system, such as a communication system conforming to standards like ITU G.hn, HomePlug AV, IEEE 1901.1, or the State Grid dual-mode communication interconnection technical specification; it can also be other wired or wireless communication systems that use repetitive coding to improve transmission reliability, and this application does not limit this. In the above communication systems, the quality of the communication channel often changes dynamically with time, noise, fading, and other factors. Repetitive coding provides time diversity by repeatedly transmitting the same information bit on multiple symbols, thereby resisting channel fading and noise and improving the reliability of data transmission.

[0037] like Figure 1As shown, in the above communication system, a data frame in the time domain can sequentially include a preamble OFDM symbol, a frame control OFDM symbol, and a user data OFDM symbol. The preamble OFDM symbol can be used for synchronization and channel estimation, while both the frame control OFDM symbol and the user data OFDM symbol can be transmitted using repetition coding. Taking the part using repetition coding as an example, the transmitting end can sequentially perform FEC coding, repetition coding, constellation mapping, and OFDM modulation on the data to be transmitted before transmitting it through the channel. Correspondingly, the receiving end can sequentially perform OFDM demodulation, frequency domain equalization, and demapping on the received OFDM symbol to obtain the original LLR value of each bit carried by the OFDM symbol. Then, according to the repetition coding mapping rule, the original LLR values ​​carrying the same bit are merged to obtain the LLR sequence of the FEC coded block, which is then sent to the FEC decoder for decoding.

[0038] Furthermore, such as Figure 1 As shown, the L bits contained in an FEC coding block are repeatedly encoded and mapped onto the N OFDM symbols corresponding to that FEC coding block, meaning the same bit is repeatedly carried on different OFDM symbols. The receiving device receives the N OFDM symbols one by one and merges the original LLR values ​​of the same bit on different OFDM symbols into the corresponding positions in the LLR sequence of the FEC coding block according to the repeated encoding mapping rule. As the number of received and merged OFDM symbols increases, the reliability of the LLR values ​​corresponding to each bit in the LLR sequence gradually improves.

[0039] In related technologies, receiving equipment typically needs to wait for all N OFDM symbols corresponding to an FEC coding block to be received and merged before initiating FEC decoding based on the complete LLR sequence. However, in application scenarios with good channel conditions or high repetition rates, the overall reliability of the resulting LLR sequence is often sufficient to support correct decoding when some OFDM symbols have been merged, and the contribution of subsequent OFDM symbol merging to the decoding result is limited. If, in this case, the receiving equipment still waits for all OFDM symbols to be received before initiating FEC decoding, it will cause the receiving equipment to continuously wait for the reception and merging of the remaining symbols even when the reliability requirement has been met. This will increase the decoding delay of a single FEC coding block, reduce decoding efficiency, and cause unnecessary power consumption waste.

[0040] Based on this, the embodiments of this application are as follows: Figure 1In the application scenario shown, during the process of receiving and merging OFDM symbols one by one, the overall reliability of the current LLR sequence is dynamically monitored using a cost function used to evaluate the quality of the LLR sequence. When the value of the cost function reaches a preset convergence threshold, FEC decoding is initiated in advance before all OFDM symbols corresponding to the FEC coding block have been received. Conversely, when channel conditions are poor and the initiation condition has not been met even after all OFDM symbols have been received, FEC decoding is initiated as a fallback after all symbols have been received. Thus, under good channel conditions, the waiting can be ended early, allowing the decoding process to be merged and performed in parallel with the reception of subsequent symbols, thereby reducing the decoding latency of a single FEC coding block, improving decoding efficiency, and reducing power consumption. Under poor channel conditions, it can still maintain the same decoding performance as related technologies, ensuring the decoding reliability of the FEC coding block.

[0041] The method provided in this embodiment is described in detail below. Please refer to [link / reference]. Figure 2 This is a flowchart illustrating a decoding method based on repeated encoding in an embodiment of this application.

[0042] S101. Initialize the log-likelihood ratio (LLR) sequence and cost function of the current FEC coded block. The LLR sequence contains the LLR values ​​corresponding to each bit of the FEC coded block, and the cost function is a numerical value used to evaluate the quality of the LLR sequence.

[0043] In this step, the FEC coding block refers to the coded data block generated by the transmitting end during forward error correction (FEC) coding, which serves as the basic unit of FEC decoding. It contains a predetermined number of bits, denoted by L in this embodiment, where L is a positive integer. The FEC coding used in the FEC coding block can be channel coding with error correction capabilities, such as LDPC codes, Turbo codes, or convolutional codes. This application does not limit the specific type of FEC coding. The current FEC coding block refers to the FEC coding block that the receiving device is currently receiving and processing. The receiving device can process FEC coding blocks sequentially; that is, after completing the processing of one FEC coding block, the processing flow described in this embodiment is repeated for the next FEC coding block.

[0044] The Log-Likelihood Ratio (LLR) sequence is a sequence formed by arranging the LLR values ​​corresponding to each bit of the FEC coded block in order of their position within the FEC coded block. It can be represented as {LLR(i)}, where i is the bit index, i = 0, 1, ..., L-1. The LLR value (Log-Likelihood Ratio) is soft information used to characterize the confidence level of a corresponding bit taking a certain logical value. Its sign indicates the tendency for the bit to be judged as 0 or 1, and its absolute value indicates the reliability of that judgment. The larger the absolute value of the LLR value, the higher the reliability of the judgment for the corresponding bit. The LLR sequence carries the accumulated soft information of each bit in the FEC coded block after receiving and combining, and serves as the input for subsequent FEC decoding.

[0045] The cost function is a numerical value used to evaluate the quality of the LLR sequence. It is used to characterize the overall reliability of the current LLR sequence. The higher the value of the cost function, the higher the overall reliability of the current LLR sequence, and the more conducive it is to successful FEC decoding. The cost function can be determined according to the LLR value corresponding to each bit in the LLR sequence. The specific form of the cost function is not limited in the embodiments of this application, as long as it can characterize the overall reliability of the LLR sequence.

[0046] This step is performed when the receiving device begins processing a new FEC coded block, that is, before receiving any OFDM symbol corresponding to the current FEC coded block. Specifically, the receiving device may set the LLR values ​​corresponding to each bit in the LLR sequence of length L to their initial values. For example, the receiving device may set all LLR values ​​in the LLR sequence {LLR(i)} to zero to indicate that there is no usable soft information for each bit before any OFDM symbol has been received. The receiving device may also set the cost function to its initial value. For example, the cost function Q may be set to zero to indicate that the quality of the LLR sequence is at its lowest before any OFDM symbol has been received.

[0047] Furthermore, the receiving device can initialize the currently received OFDM symbol sequence number n, exemplarily setting it to zero, and initialize a status flag used to identify whether FEC decoding has been initiated, setting it to the "not initiated" state for subsequent steps to determine. Through this initialization, the receiving device establishes an LLR sequence for accumulating soft information symbol by symbol for the current FEC coded block, as well as a cost function for dynamically evaluating the quality of this sequence, thereby providing an initial basis for subsequently receiving OFDM symbols one by one and merging and updating them.

[0048] S102. Receive OFDM symbols corresponding to FEC coding blocks. When receiving an OFDM symbol, perform reception and update processing on the currently received OFDM symbol. The reception and update processing includes: demodulating the currently received OFDM symbol to obtain the original LLR value; determining the position of the bit carried by the currently received OFDM symbol in the FEC coding block according to the repetition coding mapping rule; merging the original LLR value into the LLR value at the corresponding position in the LLR sequence to obtain the updated LLR sequence; and updating the cost function according to the updated LLR sequence to obtain the new cost function.

[0049] In this step, an OFDM symbol (Orthogonal Frequency Division Multiplexing) refers to a modulation symbol carrying data bits formed using orthogonal frequency division multiplexing modulation. An OFDM symbol may include multiple subcarriers, each carrying corresponding bits of modulation information. The OFDM symbol corresponding to an FEC coded block refers to an OFDM symbol carrying the bits of the FEC coded block. Since the transmitting end uses repeated encoding for the FEC coded block, each bit of the FEC coded block will be repeatedly encoded, mapped, and carried on multiple OFDM symbols. Therefore, the number of OFDM symbols corresponding to the FEC coded block is multiple, denoted by N in this embodiment, where N is a positive integer greater than 1.

[0050] The repetition coding mapping rule refers to the correspondence rule used by the transmitting end when performing repetition coding, which maps each bit of the FEC coding block to each OFDM symbol (and each subcarrier in each OFDM symbol). This rule is pre-agreed upon by the communication system, and the receiving end device knows or stores this rule in advance, so as to determine the position of the bits carried by each subcarrier in the FEC coding block according to the currently received OFDM symbol. The original LLR value refers to the LLR value of each bit carried by the OFDM symbol directly obtained by the receiving end device after demodulating the currently received OFDM symbol. It is the LLR value before it has been merged with the existing LLR values ​​in the LLR sequence. The LLR value at the corresponding position refers to the LLR value at the position in the LLR sequence corresponding to the bit carried by the currently received OFDM symbol.

[0051] The reception and update process refers to a set of processing operations performed by the receiving device for a currently received OFDM symbol, including demodulation, position determination, LLR combining, and cost function update. This step is executed after the receiving device completes the initialization in step S101, and the receiving device performs the reception and update process once for each OFDM symbol received. That is, the reception and update process is executed sequentially as the OFDM symbols corresponding to the FEC coding block are received one by one.

[0052] Specifically, the process by which the receiving device performs the receiving and updating process may include the following steps:

[0053] First, the receiving device receives a current OFDM symbol and demodulates the currently received OFDM symbol. For example, the receiving device can sequentially perform OFDM demodulation, channel estimation and frequency domain equalization, and demapping on the currently received OFDM symbol, thereby extracting the original LLR values ​​of the bits carried on each subcarrier of the currently received OFDM symbol from the equalized symbol.

[0054] Secondly, the receiving device determines the position of each bit carried by the currently received OFDM symbol in the FEC coding block according to the repetition coding mapping rule, that is, determines which positions in the LLR sequence correspond to the bits carried by each subcarrier in the currently received OFDM symbol.

[0055] Third, the receiving device merges the original LLR value with the LLR value at the corresponding position in the LLR sequence to obtain an updated LLR sequence. That is, for each bit carried by the currently received OFDM symbol, the receiving device merges the original LLR value of the bit with the accumulated LLR value at the corresponding position in the LLR sequence, and updates the LLR value at the corresponding position with the merging result. The merging can adopt a merging method that reflects the accumulation of soft information. For example, the receiving device can use the Maximum Ratio Combining (MRC) algorithm for merging. As multiple original LLR values ​​carrying the same bit are merged successively, the absolute value of the LLR value at the corresponding position of the bit increases, that is, the reliability of the decision of the bit is improved.

[0056] For example, the receiving device can use a Maximum Ratio Combining (MRC) algorithm based on channel state information for combining. Taking the original LLR value carried by the nth OFDM symbol currently received and corresponding to the i-th bit in the FEC coded block as an example, the receiving device combines the original LLR value with the LLR value corresponding to the i-th bit position in the LLR sequence according to the following formula:

[0057]

[0058] Among them, the left side of the equal sign This represents the LLR value at the position corresponding to the i-th bit in the LLR sequence after this merging, and the right side of the equals sign represents... This indicates the LLR value at this location before the current merger; This represents the repetition count of the i-th bit before this merge, i.e., the number of times this bit has been merged before this merge; n represents the sequence number of the currently received OFDM symbol, and k represents the subcarrier index carrying the i-th bit in the currently received OFDM symbol; This represents the channel state information of the k-th subcarrier in the n-th OFDM symbol. This represents the original LLR value of the i-th bit carried on the k-th subcarrier in the n-th OFDM symbol.

[0059] As can be seen from the above formula, the receiving device uses the accumulated LLR value and its repetition count at this position before merging as a basis, and includes the original LLR value after being weighted by the channel state information. It then normalizes the value according to the updated number of mergings, so that the original LLR value provided by the subcarrier with better channel quality (i.e., larger value) occupies a larger weight in the merging result. As a result, the absolute value of the LLR value at the corresponding bit position gradually increases with the number of mergings, and the reliability gradually improves.

[0060] Fourth, the receiving device updates the cost function according to the updated LLR sequence to obtain a new cost function. That is, after the LLR sequence changes due to this merging, the receiving device redetermines the value of the cost function according to the updated LLR sequence, so that the cost function can reflect the latest overall reliability of the current LLR sequence.

[0061] It should be noted that after the receiving device completes the receiving and updating process and obtains the new cost function each time, it enters the subsequent start-up judgment stage (i.e., step S103). If the subsequent judgment result is that FEC decoding has not yet been started, the receiving device continues to receive the next OFDM symbol and performs the receiving and updating process again on the next OFDM symbol. This process is repeated one by one until the conditions for starting FEC decoding are met or all OFDM symbols corresponding to the FEC coding block have been received.

[0062] S103. Before FEC decoding is started, after each OFDM symbol reception and update process is completed, if the value of the new cost function is greater than or equal to the preset convergence threshold, then FEC decoding is started based on the current LLR sequence before all symbols corresponding to the FEC coding block are received.

[0063] FEC decoding not started means that the FEC decoding process for the current FEC encoded block has not yet started by the receiving device. The receiving device can determine whether FEC decoding has started by using the status flag in step S101.

[0064] The preset convergence threshold refers to a pre-set cost function threshold value used to determine whether the overall reliability of the current LLR sequence is sufficient to support the successful initiation of FEC decoding; when the value of the cost function reaches the preset convergence threshold, it is considered that the quality of the current LLR sequence is sufficient to support correct decoding.

[0065] The preset convergence threshold can be preset according to the LLR quality level required to ensure successful FEC decoding. Its value should satisfy the following: when the value of the cost function reaches the threshold, FEC decoding based on the current LLR sequence can successfully decode the FEC coded block with a high probability.

[0066] The specific value of the preset convergence threshold can be determined in advance by simulation or actual measurement, combined with the FEC coding type, bit rate and target bit error rate. For example, in the implementation where the cost function is the average energy of the LLR sequence, the preset convergence threshold can correspond to an LLR average energy level that is sufficient to guarantee successful decoding. The preset convergence threshold can be a fixed value or can be configured according to actual needs. This application does not limit the specific value of the preset convergence threshold.

[0067] FEC decoding refers to the process by which the receiving device performs error correction decoding based on the LLR sequence, according to the decoding algorithm corresponding to the FEC encoding used in the FEC coding block. For example, the FEC decoding can employ an iterative decoding algorithm, such as the belief propagation decoding algorithm for LDPC codes or the Max-Log-MAP decoding algorithm for Turbo codes. Starting FEC decoding based on the current LLR sequence means that the receiving device uses the merged LLR sequence obtained up to the current time as the input to the FEC decoding process and begins executing the FEC decoding procedure.

[0068] This step is performed after the receiving device completes the reception and update processing for each OFDM symbol, and before FEC decoding of the current FEC coded block has started. Specifically, after completing the reception and update processing for an OFDM symbol and obtaining the new cost function, the receiving device first determines whether FEC decoding of the current FEC coded block has started.

[0069] If FEC decoding has already started, the receiving device does not need to perform the start-up judgment in this step; if FEC decoding has not yet started, the receiving device compares the value of the new cost function with the preset convergence threshold. When the value of the new cost function is greater than or equal to the preset convergence threshold, it indicates that the overall reliability of the current LLR sequence is sufficient to support correct decoding. At this time, even if all the symbols corresponding to the FEC coding block have not been received, the receiving device will start FEC decoding based on the current LLR sequence before all the symbols corresponding to the FEC coding block have been received, and set the status flag to "started".

[0070] When the value of the new cost function is less than the preset convergence threshold, it indicates that the overall reliability of the current LLR sequence is not sufficient to support correct decoding. At this time, the receiving device will not start FEC decoding, but will continue to receive the next OFDM symbol and perform the reception and update process on it before all the symbols corresponding to the FEC coding block have been received. That is, it will return to step S102 until the value of the new cost function reaches the preset convergence threshold and FEC decoding is started in advance, or until all the symbols corresponding to the FEC coding block have been received and the process proceeds to step S104.

[0071] Through this step, the receiving device can dynamically monitor the overall reliability of the LLR sequence represented by the cost function during the process of receiving and merging OFDM symbols one by one. When the reliability reaches the required level, FEC decoding is started in advance before all symbols corresponding to the FEC coding block are received. This allows the FEC decoding process to be carried out in parallel with the reception and merging of subsequent OFDM symbols, thereby reducing the decoding latency of the current FEC coding block and improving decoding efficiency.

[0072] S104. If all symbols corresponding to the FEC coded block have been received but FEC decoding has not yet started, then start FEC decoding based on the current LLR sequence.

[0073] The reception of all symbols corresponding to the FEC coding block is considered complete. This means that all N OFDM symbols corresponding to the FEC coding block have been received by the receiving device and the reception and update process has been completed. For example, the receiving device can determine whether all symbols corresponding to the FEC coding block have been received by judging whether the number n of the currently received OFDM symbol has reached N-1 (i.e., whether the number of received symbols has reached N).

[0074] This step is executed after all symbols corresponding to the FEC coding block have been received and FEC decoding has not been initiated in step S103. In other words, this step is a fallback initiation stage when channel conditions are poor and the cost function value has not reached the preset convergence threshold before all OFDM symbols have been received. Specifically, after completing the reception and update processing of each OFDM symbol and executing the initiation judgment in step S103, if the judgment result is to temporarily not initiate FEC decoding, it further determines whether all symbols corresponding to the FEC coding block have been received.

[0075] If not all OFDM symbols have been received, the receiving device continues to receive the next OFDM symbol and performs reception and update processing.

[0076] If all reception has been completed but FEC decoding has not yet started, the receiving device will start FEC decoding based on the current LLR sequence (i.e., the complete LLR sequence obtained by merging all N OFDM symbols) and set the status flag to "started".

[0077] Therefore, even when channel conditions are poor and the early start condition is not met, the receiving equipment can still start FEC decoding after all OFDM symbols have been received, thus ensuring the same decoding performance as related technologies and avoiding the loss of decoding reliability due to the introduction of the early start mechanism.

[0078] It should be noted that the two starting scenarios of the receiving device in advance in step S103 and the fallback starting of FEC decoding in this step are mutually exclusive: For the same FEC code block, the receiving device will start FEC decoding at most once. That is, once the FEC decoding is started in advance in step S103, the receiving device will not perform the fallback starting in this step; the receiving device will only perform the fallback starting in this step if the FEC decoding is never started in advance until all the symbols corresponding to the FEC code block are received.

[0079] S105. Output the FEC decoding result of the FEC encoded block.

[0080] The FEC decoding result refers to the decoded output obtained by the receiving device after performing FEC decoding on the FEC encoded block. It may include the information bits recovered after error correction of the FEC encoded block, and may also include indication information indicating whether the FEC decoding was successful.

[0081] This step is executed after the receiving device completes the FEC decoding of the FEC encoded block, that is, after the FEC decoding initiated in advance in step S103 or the FEC decoding initiated as a fallback in step S104 is completed. Specifically, after initiating FEC decoding, the receiving device decodes the current LLR sequence according to the decoding algorithm used; after decoding is completed, the receiving device outputs the FEC decoding result of the FEC encoded block for subsequent processing.

[0082] After outputting the FEC decoding result, the receiving device can return to step S101 to re-initialize for the next FEC coding block and repeat the processing flow described in steps S101 to S105 above, thereby realizing block-by-block processing of multiple consecutive FEC coding blocks.

[0083] It should be noted that if the receiving device starts FEC decoding in advance in step S103, and the FEC encoding block is successfully decoded before all the symbols corresponding to the FEC encoding block are received, the receiving device can output the FEC decoding result and can choose to stop receiving the remaining OFDM symbols of the FEC encoding block, thereby further saving the time and power consumption required for reception while ensuring correct decoding.

[0084] In this embodiment, after the receiving device completes the reception and update processing of each OFDM symbol, it updates the cost function according to the updated LLR sequence to quantify the overall reliability of the current LLR sequence symbol by symbol. When the value of the new cost function is greater than or equal to the preset convergence threshold, FEC decoding is started in advance before all symbols are received. FEC decoding is started as a fallback when all symbols are received but FEC decoding has not yet started. Therefore, when the channel conditions are good, the receiving device can combine FEC decoding with the reception of subsequent OFDM symbols in parallel without waiting for the remaining symbols. When the channel conditions are poor, FEC decoding can still be started after all symbols are received. This effectively solves the problems of related technologies that require waiting for all symbols to be received before starting FEC decoding and continue to wait for the remaining symbols when the reliability requirement has been met, thereby increasing decoding delay and wasting power consumption. Thus, it achieves the reduction of decoding delay of a single FEC coding block, reduction of power consumption, and improvement of decoding efficiency while ensuring decoding reliability.

[0085] In the above embodiments, the receiving device updates the cost function symbol by symbol and compares it with a preset convergence threshold, thereby enabling FEC decoding to start in advance before all symbols have been received, thus reducing the decoding latency and power consumption of a single FEC coding block while ensuring decoding reliability.

[0086] In practical applications, whether the cost function can accurately reflect the overall reliability of the current LLR sequence directly affects whether the timing of initiating FEC decoding in advance is appropriate. If the method of determining the cost function is not reasonable enough, there may be situations where the cost function has reached the preset convergence threshold but the LLR sequence is not actually sufficient to support correct decoding, or the LLR sequence has actually met the decoding requirements but the cost function has not yet reached the preset convergence threshold, thus affecting the balance between decoding latency and decoding reliability.

[0087] In conjunction with the above embodiments, the following is a summary... Figure 3 The specific method by which the receiving device updates the cost function based on the updated LLR sequence is further explained. Please refer to [link / reference]. Figure 3 This is another flowchart illustrating a decoding method based on repeated encoding in an embodiment of this application.

[0088] S201. While initializing the LLR sequence and cost function of the current FEC coded block, initialize the repetition count of each bit in the LLR sequence. The repetition count represents the number of times the corresponding bit has been merged.

[0089] Here, the repetition count refers to the count value used to characterize the number of times the corresponding bit in the LLR sequence has been merged up to the current time, which can be expressed as: where i is the bit index For any given bit, the repetition count is incremented each time the original LLR value is merged. Therefore, the repetition count of a bit indicates how many OFDM symbols the currently accumulated soft information for that bit originates from. Since the transmitter uses repetitive encoding for each bit of the current FEC coded block, each bit is repeatedly carried on multiple OFDM symbols. Therefore, after all OFDM symbols corresponding to the current FEC coded block have been received, the repetition count of the i-th bit will reach the total number of repetitions for that bit. , It is a positive integer.

[0090] This step is performed before the receiving device begins processing the current FEC coding block, i.e., before receiving any OFDM symbol corresponding to the current FEC coding block, and is performed simultaneously with the initialization of the LLR sequence and cost function of the current FEC coding block in step S101. Specifically, while setting the LLR value corresponding to each bit in the LLR sequence of length L to its initial value and the cost function to its initial value, the receiving device also sets the repetition count of each bit in the LLR sequence to its initial value. For example, the receiving device can set the repetition count of each bit to its initial value. All bits are set to zero to indicate that none of them have been combined with the original LLR value before any OFDM symbols have been received. By introducing and initializing the repetition count for each bit during the initialization phase, the receiving device provides a basis for introducing constraints on the number of times each bit has been combined during the subsequent start-up decision.

[0091] S202. In the receiving and updating process, in addition to merging the original LLR value into the LLR value at the corresponding position in the LLR sequence and updating the cost function, the repetition count of the bit at the corresponding position is updated.

[0092] This step is a further refinement of the reception and update processing in step S102, and is performed by the receiving device each time it receives an OFDM symbol and performs reception and update processing on the currently received OFDM symbol. Specifically, after the receiving device demodulates the currently received OFDM symbol to obtain the original LLR value, determines the position of the bit carried by the currently received OFDM symbol in the current FEC coding block according to the repetition coding mapping rule, merges the original LLR value into the LLR value at the corresponding position in the LLR sequence, and updates the cost function, it further updates the repetition count of the bit at the corresponding position. That is, for each bit carried by the currently received OFDM symbol, the receiving device merges the original LLR value of the bit into the LLR value at the corresponding position of the bit and increments the repetition count at the corresponding position of the bit once.

[0093] For example, the receiving device may perform a repetition count on the corresponding bit position. The operation increments by 1. As the receiving device receives and merges OFDM symbols one by one, the repetition count at the corresponding position of each bit accumulates with the number of times it is merged, thus reflecting the amount of soft information sources currently accumulated for each bit in real time.

[0094] S203. Before FEC decoding is started, after each OFDM symbol reception and update process is completed, obtain the repetition count of each bit in the current LLR sequence and the current cost function.

[0095] When the number of repeated bits in the LLR sequence is less than the preset counting threshold, or the value of the new cost function is less than the preset convergence threshold, continue to receive the next OFDM symbol and perform reception and update processing.

[0096] In this step, the preset counting threshold refers to a pre-set repetition count threshold used to determine whether the number of soft information sources currently accumulated by each bit is sufficient, which can be represented as R. Only when the repetition count of each bit in the LLR sequence reaches this threshold is it considered that each bit has accumulated a sufficient number of soft information sources, thereby avoiding insufficient soft information for individual bits due to too few merging times. The value of the preset counting threshold R should satisfy R being less than or equal to positive integers, where The total repetition count of the i-th bit is set to a preset counting threshold R, which ensures that the repetition count of each bit may reach the threshold before all OFDM symbols corresponding to the current FEC coded block are received. The preset counting threshold R can be pre-set according to the degree of soft information accumulation required for decoding. For example, the preset counting threshold R can be half of the minimum total repetition count of each bit (rounded down), and satisfy R ≤ the minimum total repetition count of each bit. The preset counting threshold R can be a fixed value or configured according to actual needs. This invention does not limit the specific value of the preset counting threshold R.

[0097] This step is performed after the receiving device completes the reception and update processing of each OFDM symbol, and before FEC decoding of the current FEC coded block has started. Specifically, after completing the reception and update processing of an OFDM symbol, the receiving device first determines whether FEC decoding of the current FEC coded block has started; if FEC decoding has not started, the receiving device obtains the repetition count of each bit in the current LLR sequence and the current cost function, and uses this information to determine the conditions for early decoding.

[0098] When the number of repeated bits in the LLR sequence is less than the preset counting threshold, or the value of the new cost function is less than the preset convergence threshold, it indicates that the number of soft information sources accumulated for each bit is not sufficient, or the overall reliability of the current LLR sequence is not sufficient to support correct decoding. That is, at least one of the above two conditions is not met. At this time, the receiving device does not start FEC decoding, but continues to receive the next OFDM symbol and perform reception and update processing on the next OFDM symbol before all OFDM symbols corresponding to the current FEC coding block have been received. That is, it returns to the reception and update processing refined in step S202.

[0099] S204. When the repetition count of each bit in the LLR sequence is greater than or equal to the preset counting threshold, and the value of the new cost function is greater than or equal to the preset convergence threshold, FEC decoding is started based on the current LLR sequence before all symbols corresponding to the FEC coding block have been received.

[0100] This step is performed after the receiving device executes step S203 (acquisition and judgment) and before FEC decoding of the current FEC coded block is started. Specifically, when the repetition count of each bit in the LLR sequence is greater than or equal to a preset counting threshold, and the value of the new cost function is greater than or equal to a preset convergence threshold, it indicates that the number of soft information sources accumulated for each bit is sufficient, and the overall reliability of the current LLR sequence is sufficient to support correct decoding. That is, the above two conditions are met simultaneously. At this time, even if all the symbols corresponding to the current FEC coded block have not been received, the receiving device starts FEC decoding based on the current LLR sequence and sets the status flag used to identify whether FEC decoding has been started to the started state.

[0101] It should be noted that the dual-condition judgment described in steps S203 and S204 is for... Figure 2 In the embodiment, step S103 is a further limitation based on whether the cost function reaches the preset convergence threshold. That is, on the basis that the cost function reaches the preset convergence threshold, it is further required that the repetition count of each bit reaches the preset count threshold. This is to avoid prematurely starting FEC decoding due to the cost function being accidentally too high when the number of individual bit merging is too small, thereby increasing the probability of successful decoding after starting FEC decoding in advance.

[0102] If the dual conditions described in steps S203 and S204 are not simultaneously met, and FEC decoding has not yet started even after all symbols corresponding to the current FEC coding block have been received, the receiving device will continue to operate according to the procedure. Figure 2 In the embodiment, step S104 performs fallback startup, that is, FEC decoding is started based on the LLR sequence obtained by merging all OFDM symbols, thereby ensuring that it still has the same decoding performance as related technologies under poor channel conditions.

[0103] S205. After starting FEC decoding in S103 or S204, if the FEC decoding has reached the preset maximum number of iterations but still fails to decode the FEC coded block, and the symbols corresponding to the FEC coded block have not been fully received, then continue to receive the remaining OFDM symbols of the FEC coded block.

[0104] The preset maximum number of iterations refers to a pre-set value that limits the upper limit of the number of iterations allowed in a single round of FEC iterative decoding. When FEC decoding uses an iterative decoding algorithm, the receiving device performs iterations sequentially in a single round of decoding. If the FEC coded block is not successfully decoded after reaching the maximum number of iterations, it is considered that the current round of decoding has failed under the current LLR sequence. The preset maximum number of iterations can be preset based on the convergence characteristics of the decoding algorithm and constraints on decoding delay and computational complexity. It can be a fixed value or configured according to actual needs. This invention does not limit the specific value of the preset maximum number of iterations. Successful decoding of the FEC coded block means that the decoding result obtained from FEC decoding passes the verification, i.e., the information bits of the FEC coded block are correctly recovered.

[0105] This step is performed after the receiving device initiates FEC decoding in advance in step S103 or step S204. Specifically, after initiating FEC decoding in advance, the receiving device performs iterative decoding based on the current LLR sequence. When FEC decoding reaches the preset maximum number of iterations but still fails to decode the FEC coded block, the receiving device further determines whether all symbols corresponding to the current FEC coded block have been received. If not all symbols corresponding to the current FEC coded block have been received, it indicates that there are still redundant OFDM symbols carrying the bits of the FEC coded block that have not been received. At this time, the receiving device continues to receive the remaining OFDM symbols of the current FEC coded block in order to further improve the overall reliability of the LLR sequence by merging more original LLR values.

[0106] It should be noted that if FEC decoding fails to decode the FEC block after reaching the preset maximum number of iterations, and all symbols corresponding to the current FEC block have been received, the receiving device will stop receiving and instead proceed according to... Figure 2 In the embodiment, step S105 outputs the FEC decoding result.

[0107] S206. For each OFDM symbol that is received, perform reception and update processing to obtain the updated LLR sequence;

[0108] This step is performed when the receiving device executes step S205 and continues receiving the remaining OFDM symbols of the current FEC coding block. Specifically, for each continuously received OFDM symbol, the receiving device performs the same receiving and updating process as steps S102 and S202, that is, demodulating each continuously received OFDM symbol to obtain the original LLR value, determining the position of the bit carried by the continuously received OFDM symbol in the current FEC coding block according to the repetition coding mapping rule, merging the original LLR value with the corresponding LLR value in the LLR sequence to obtain the updated LLR sequence, and updating the cost function and the repetition count of the corresponding bit. Thus, by merging the continuously received OFDM symbols, the receiving device further increases the absolute value of the LLR value at the corresponding position in the LLR sequence, thereby further improving the overall reliability of the updated LLR sequence.

[0109] S207. Continue FEC decoding based on the updated LLR sequence until FEC decoding successfully decodes the FEC coded block, or all symbols corresponding to the FEC coded block are received.

[0110] This step is executed after the receiving device performs step S206 and obtains the updated LLR sequence. Together with steps S205 and S206, it constitutes the continuation of reception and decoding when decoding has not yet succeeded after FEC decoding has been started in advance. Specifically, the receiving device continues FEC decoding based on the updated LLR sequence. When FEC decoding uses an iterative decoding algorithm, the receiving device can reread the current LLR sequence before each iteration, so that the newly received and merged LLR values ​​during the iterative decoding process can be used in the current iteration in a timely manner, thereby continuously improving the probability of successful decoding without restarting the entire round of decoding. The receiving device repeatedly executes the process of continuing to receive the remaining OFDM symbols, performing reception and update processing on the continued received OFDM symbols, and continuing FEC decoding based on the updated LLR sequence until FEC decoding successfully decodes the FEC coded block, or all symbols corresponding to the current FEC coded block have been received.

[0111] There are two possible branching scenarios:

[0112] Firstly, when the FEC decoding successfully decodes the FEC code block before all the symbols corresponding to the current FEC code block have been received, the receiving device ends the decoding of the current FEC code block and can choose to stop receiving the remaining OFDM symbols of the current FEC code block, thereby further saving the time and power consumption required for reception while ensuring the correct decoding. Then, it switches to outputting the FEC decoding result.

[0113] Secondly, while FEC decoding is still in progress and all symbols corresponding to the current FEC coded block have been received, the receiving device continues to perform FEC decoding based on the LLR sequence obtained by merging all OFDM symbols, and then outputs the FEC decoding result. Through steps S205 to S207, the receiving device enables the pre-started FEC decoding process to be performed in parallel with the reception and merging of subsequent OFDM symbols. Even if decoding is not successful immediately after pre-start, it can still gradually approach successful decoding through continued reception and decoding, thereby improving decoding efficiency while ensuring decoding reliability.

[0114] In this embodiment, when the receiving device updates the cost function based on the updated LLR sequence, it determines the value of the cost function based on the absolute value of the LLR value at each position in the LLR sequence. This allows the cost function to accurately reflect the overall reliability of the current LLR sequence as the absolute value of the LLR value at each position increases sign by sign. Therefore, the cost function determined by the receiving device can truly characterize whether the current LLR sequence is sufficient to support correct decoding, and thus more accurately determine the timing for early FEC decoding. This effectively solves the problem that when the cost function determination method is not reasonable enough, the cost function may have reached the preset convergence threshold but the LLR sequence is not actually sufficient to support correct decoding, or the LLR sequence may have met the decoding requirements but the cost function has not yet reached the preset convergence threshold. This achieves a better balance between decoding latency and decoding reliability in the scenario of early FEC decoding, and further improves decoding efficiency.

[0115] Furthermore, in conjunction with the above embodiments, a specific method for calculating the cost function is given.

[0116] S301. The cost function is determined based on the LLR value corresponding to each bit in the LLR sequence, and the cost function is calculated according to the following formula:

[0117]

[0118] Where Q represents the cost function, L represents the number of bits in the FEC coded block, and i represents the bit index. , This represents the LLR value corresponding to the i-th bit in the LLR sequence; the value of the cost function increases as the absolute value of the LLR value corresponding to each bit in the LLR sequence increases.

[0119] The cost function Q is used to characterize the overall reliability of the current LLR sequence. In this step, the receiving device takes the cost function Q as the average energy of the LLR sequence, which is the ratio of the sum of the squares of the LLR values ​​corresponding to each bit in the LLR sequence to the number of bits L contained in the FEC coded block. The average energy of the LLR sequence refers to the average of the squares of the LLR values ​​corresponding to each bit in the LLR sequence, which can reflect the overall level of reliability of the decision for each bit.

[0120] This step is performed when the receiving device needs to determine the cost function based on the LLR sequence. That is, when the cost function is initialized in step S101 and when the cost function is updated based on the updated LLR sequence in steps S102 and S202, the receiving device can determine the value of the cost function according to the calculation method given in this step.

[0121] Since a larger absolute value of the LLR value indicates a higher reliability of the corresponding bit decision, when the absolute value of the LLR value corresponding to each bit in the LLR sequence increases, the square of each LLR value increases accordingly, and the value of the cost function Q increases accordingly. Therefore, a larger value of the cost function Q indicates a higher overall reliability of the current LLR sequence.

[0122] It should be noted that the cost function only needs to be able to characterize the overall reliability of the LLR sequence. The average energy form given in this step is an exemplary implementation of the cost function. The cost function can also be the sum of the absolute values ​​of the LLR values ​​corresponding to each bit, or the sum or average of other functions that monotonically increase with the absolute value of the LLR values ​​corresponding to each bit. This invention does not limit the specific form of the cost function.

[0123] The cost function is updated based on the updated LLR sequence to obtain a new cost function, including:

[0124] S302. Determine the change in the LLR value at the corresponding position in the LLR sequence relative to the value before merging after the original LLR value of the currently received OFDM symbol is merged into the LLR sequence.

[0125] The change refers to the change in the LLR value at the corresponding position in the LLR sequence after merging the original LLR value of the currently received OFDM symbol, relative to the change before merging the original LLR value. Since the cost function Q is determined according to the sum of the squares of the LLR values ​​corresponding to each bit in the LLR sequence, the change can correspond to the difference between the squares of the LLR values ​​at the corresponding position before and after merging.

[0126] This step is performed after the receiving device executes the reception and update processing, merges the original LLR values ​​of the currently received OFDM symbols into the corresponding LLR values ​​in the LLR sequence, and before the updated cost function is obtained. Specifically, for each bit carried and merged by the currently received OFDM symbol, the receiving device records the value of the LLR value at the corresponding position of that bit before this merging, and the value of the LLR value at the corresponding position of that bit after this merging, and determines the change in the LLR value at that position relative to before merging based on this.

[0127] S303. Based on the change, perform a recursive operation on the cost function before this reception to obtain the new cost function after this reception.

[0128] The cost function prior to this reception refers to the cost function determined based on the LLR sequence at that time before merging the original LLR values ​​of the currently received OFDM symbols; the recursive operation refers to the operation of incrementally updating the cost function based on the cost function prior to this reception, only according to the change in the LLR value at the corresponding position caused by this merging, without having to resum the LLR values ​​corresponding to all bits in the updated LLR sequence before determining the cost function.

[0129] This step is performed after the receiving device executes step S302 and determines the change amount. Figure 2 The embodiment describes a specific implementation of updating the cost function based on the updated LLR sequence to obtain a new cost function. Specifically, the receiving device performs a recursive operation on the cost function before this reception based on the change in the LLR value at the corresponding position determined in step S302. That is, the difference between the squares of the LLR values ​​at each corresponding position involved in this merging and those before and after merging is accumulated into the sum of the squares of the LLR values ​​corresponding to the cost function before this reception, and then averaged according to the number of bits L contained in the FEC coding block to obtain the new cost function after this reception.

[0130] Since only the LLR value of the corresponding position of the bit carried by each OFDM symbol changes when it is received and merged, the recursive operation method only needs to perform incremental calculation based on the changed corresponding position, without having to traverse all bits in the updated LLR sequence. Therefore, it can reduce the computational complexity of the update cost function and is beneficial for the receiving device to update the cost function symbol by symbol in real time.

[0131] In this embodiment, since the cost function is taken as the average energy of the LLR sequence, which can change monotonically with the reliability of the LLR sequence in numerical form, and can be updated incrementally symbol by symbol through recursive operation, the receiving device can evaluate the overall reliability of the current LLR sequence in real time with low computational complexity. This effectively solves the problem of difficulty in quantifying the quality of the LLR sequence in real time with low complexity during symbol-by-symbol reception and merging, thereby achieving accurate judgment of the timing of early FEC decoding.

[0132] Based on the above embodiments, the method provided in this embodiment will be described in further detail below. Please refer to... Figure 4 This is a schematic diagram of the channel quality parameter-threshold mapping relationship curve of a decoding method based on repetitive coding in an embodiment of this application.

[0133] S401. Determine the channel quality parameters that characterize the current channel quality based on the channel state information obtained when receiving OFDM symbols;

[0134] Channel State Information (CSI) refers to information characterizing the transmission characteristics of a communication channel when receiving OFDM symbols. The receiving device can obtain this information during channel estimation and frequency domain equalization of OFDM symbols. For example, CSI may include the channel gain and signal-to-noise ratio (SNR) of each subcarrier. Channel Quality Parameters are parameters determined based on the CSI and used to characterize the current channel quality. A higher value for the channel quality parameter indicates better current channel quality. For example, the channel quality parameter may be the average SNR of each subcarrier or the average channel gain, etc., values ​​that reflect the overall channel quality.

[0135] This step is performed when the receiving device receives OFDM symbols. Specifically, the receiving device acquires channel state information during the process of receiving OFDM symbols and performing channel estimation and frequency domain equalization. Then, it determines the channel quality parameters that characterize the current channel quality based on the channel state information. For example, the receiving device can average the signal-to-noise ratio of each subcarrier acquired when receiving OFDM symbols and use the average value as the channel quality parameter.

[0136] S402. According to the preset mapping relationship, the channel quality parameters are mapped to a preset convergence threshold, wherein the preset convergence threshold increases as the channel quality parameters increase in the mapping relationship.

[0137] The preset mapping relationship refers to a pre-defined correspondence used to map channel quality parameters to preset convergence thresholds. In this mapping relationship, the preset convergence threshold increases with the increase of the channel quality parameters; that is, the better the channel quality, the higher the preset convergence threshold obtained. The preset mapping relationship can be a function or a lookup table. For example, the receiving device can pre-store a mapping curve that monotonically increases with the channel quality parameters, or pre-store a mapping table consisting of several channel quality parameter value ranges and corresponding preset convergence threshold values. The preset mapping relationship can be pre-calibrated through simulation or actual measurement, combined with the adopted FEC coding type, code rate, and target bit error rate. This invention does not limit the specific form of the preset mapping relationship.

[0138] This step is performed after the receiving device executes step S401 and determines the channel quality parameters. Specifically, the receiving device maps the channel quality parameters determined in step S401 to corresponding preset convergence thresholds according to a preset mapping relationship.

[0139] Since the preset convergence threshold in the mapping relationship increases with the increase of the channel quality parameter, when the channel quality is good, the receiving device maps to a higher preset convergence threshold, thus requiring the LLR sequence to reach a higher reliability before starting FEC decoding, so as to further ensure the probability of successful decoding after starting FEC decoding in advance when the channel quality is good.

[0140] When the channel quality is poor, the receiving device maps to a lower preset convergence threshold, so that FEC decoding can be started when the reliability of the LLR sequence reaches a relatively low level, so as to avoid difficulty in starting in advance due to the threshold being too high when the channel quality is poor.

[0141] S403. In the judgment of starting FEC decoding, the preset convergence threshold obtained by mapping is used as the preset convergence threshold.

[0142] This step is executed after the receiving device performs step S402 and obtains the preset convergence threshold through mapping, and also when the receiving device performs the determination to start FEC decoding. Specifically, the receiving device... Figure 2 Step S103 of the embodiment or Figure 2 In the determination of starting FEC decoding in step S204 of the embodiment, the preset convergence threshold obtained by mapping in step S402 is used as the preset convergence threshold for comparison with the value of the cost function. That is, the value of the new cost function is compared with the preset convergence threshold obtained by mapping. When the value of the new cost function is greater than or equal to the preset convergence threshold obtained by mapping, FEC decoding is started in advance under the condition that the corresponding start conditions are met.

[0143] S404. During the iterative decoding process after starting FEC decoding, obtain the iterative state information fed back by FEC decoding that represents the current degree of decoding convergence;

[0144] Among them, the iteration state information refers to the information fed back by FEC decoding during the iterative decoding process, which characterizes the current degree of decoding convergence. For example, the iteration state information may include the actual number of iterations consumed to successfully decode the FEC coded block, the number of satisfying or unsatisfied check equations, or an indication of whether the decoding has converged, etc., which can reflect the speed or difficulty of decoding convergence.

[0145] This step is performed during the iterative decoding process after the receiving device initiates FEC decoding. Specifically, during the iterative decoding process using an iterative decoding algorithm in FEC decoding, the receiving device obtains the iteration status information fed back by FEC decoding in order to evaluate the actual decoding convergence degree after initiating FEC decoding ahead of time under the current preset convergence threshold.

[0146] It should be noted that the determination of the preset convergence threshold in this application includes two stages: initial mapping and iterative correction. The receiving device first determines the convergence threshold based on the channel quality parameters of the current coding block, through... Figure 4 The channel quality parameter-threshold mapping relationship shown determines the initial value of the preset convergence threshold. Based on this, the receiving device then corrects the initial value according to the iteration state information of the coding block, and uses the corrected threshold as the preset convergence threshold used in subsequent coding blocks. The two do not generate two independent thresholds in parallel for the same coding block, but rather constitute a serial processing flow of "mapping first, then adjusting".

[0147] S405. Adjust the preset convergence threshold according to the iteration state information to obtain the adjusted preset convergence threshold.

[0148] This step is performed after the receiving device executes step S404 and obtains the iteration state information. The receiving device adjusts the preset convergence threshold based on the current decoding convergence degree represented by the iteration state information.

[0149] Specifically, let the initial threshold obtained by mapping the channel quality parameters be... The receiving device determines the adjustment amount based on the iteration status information of the current coded block (such as the actual number of iterations used to start FEC decoding, whether the decoding has converged, etc.). Then the preset convergence threshold used in subsequent coding blocks is That is, using the mapping value As a threshold benchmark, obtained through iterative feedback This serves as a dynamic correction to the benchmark, thereby enabling closed-loop adjustment of the threshold based on the actual decoding performance while maintaining channel quality adaptability.

[0150] It should be noted that the iterative corrections in steps S404 and S405 are generated based on the decoding feedback of the current coding block, and the correction results are applied to the threshold determination of subsequent coding blocks. Therefore, for any coding block, the convergence threshold used is a uniquely determined value, and there is no situation where two thresholds are effective at the same time.

[0151] S406. When performing the judgment to start FEC decoding on the FEC encoded block received after the FEC encoded block, the adjusted preset convergence threshold is used as the preset convergence threshold.

[0152] The FEC code block received after the FEC code block refers to the subsequent FEC code block received and processed by the receiving device after it has completed the processing of the current FEC code block.

[0153] This step is performed after the receiving device executes step S405 and obtains the adjusted preset convergence threshold, and also when the receiving device performs a determination to initiate FEC decoding on an FEC encoded block received after the current FEC encoded block. Specifically, when the receiving device determines to initiate FEC decoding on a subsequently received FEC encoded block, it uses the adjusted preset convergence threshold obtained in step S405 as the preset convergence threshold to compare with the value of the cost function of that subsequent FEC encoded block.

[0154] In this embodiment, the receiving device determines the channel quality parameters based on the channel state information obtained when receiving OFDM symbols, and maps them to a preset convergence threshold that increases with the channel quality parameters according to a preset mapping relationship. After starting FEC decoding, the receiving device also adjusts the preset convergence threshold based on the iterative state information fed back by FEC decoding and uses it for subsequent FEC coding blocks. Therefore, the preset convergence threshold on which the early start of FEC decoding is based can both adapt to the current channel quality and form a closed-loop adjustment based on the actual decoding convergence degree. This effectively solves the problem that when the preset convergence threshold is fixed, it is difficult to adapt to changes in channel quality and the actual decoding difficulty. It is also easy to start early due to a high threshold or fail to start early due to a low threshold. Thus, it achieves a balance between decoding reliability and decoding delay and improves decoding efficiency under different channel conditions.

[0155] The receiving device in the embodiments of this application is described below from the perspective of a virtual device. Please refer to [link / reference]. Figure 5 This is a schematic diagram of a virtual device structure for a decoding device based on repeated encoding in an embodiment of this application.

[0156] It should be noted that, Figure 5The structure of the decoding device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0157] It should be noted that, Figure 5 The decoding apparatus shown includes at least an initialization module 501, a receive update module 502, a control module 503, and an FEC decoding module 504. In addition to the aforementioned modules, the decoding apparatus may also include a threshold configuration module 505 and a threshold adjustment module 506.

[0158] The initialization module 501 is used to initialize the log-likelihood ratio (LLR) sequence and cost function of the current FEC coded block, wherein the LLR sequence contains the LLR values ​​corresponding to each bit of the FEC coded block, and the cost function is a numerical value used to evaluate the quality of the LLR sequence.

[0159] As an optional implementation, the initialization module 501 is further configured to initialize the repetition count of each bit in the LLR sequence while initializing the LLR sequence and cost function of the current FEC coded block. The repetition count is used to indicate the number of times the corresponding bit has been merged. For example, the initialization module 501 can set the LLR value, cost function, and repetition count of each bit in the LLR sequence to zero, and can further initialize the currently received OFDM symbol sequence number and the status flag used to identify whether FEC decoding has been started to initial values.

[0160] The initialization module 501 is connected to the receiving update module 502 and is used to provide the receiving update module 502 with the initialized LLR sequence, cost function and repetition count of each bit before the receiving update module 502 starts processing the OFDM symbol corresponding to the current FEC coding block.

[0161] The receive update module 502 is used to receive OFDM symbols corresponding to FEC coding blocks one by one, and to perform receive and update processing on the currently received OFDM symbol when receiving an OFDM symbol. The receive and update processing includes: demodulating the currently received OFDM symbol to obtain the original LLR value, determining the position of the bit carried by the currently received OFDM symbol in the FEC coding block according to the repetition coding mapping rule, merging the original LLR value into the LLR value at the corresponding position in the LLR sequence to obtain the updated LLR sequence, and updating the cost function according to the updated LLR sequence to obtain the new cost function.

[0162] As an optional implementation, the receive update module 502, in addition to merging the original LLR values ​​into the corresponding LLR values ​​in the LLR sequence and updating the cost function during the receive and update processing, is also used to update the repetition count of the bits at the corresponding positions. For example, the receive update module 502 can use a maximum ratio combining algorithm based on channel state information for merging and perform an auto-increment operation on the repetition count of the bits at the corresponding positions.

[0163] As an optional implementation, when the receiving update module 502 updates the cost function according to the updated LLR sequence and obtains a new cost function, it determines the change of the LLR value at the corresponding position in the LLR sequence after the original LLR value of the currently received OFDM symbol is merged into the LLR sequence, relative to the value before merging. Based on this change, it performs a recursive operation on the cost function before this reception to obtain a new cost function after this reception.

[0164] The receiving update module 502 is connected to the initialization module 501, the control module 503, the FEC decoding module 504, and the threshold configuration module 505 respectively. It is used to receive the initialization result provided by the initialization module 501, provide the updated LLR sequence, the new cost function, and the repetition count of each bit obtained after each OFDM symbol reception and update processing to the control module 503 for start judgment, and provide the current LLR sequence to the FEC decoding module 504 for FEC decoding.

[0165] The control module 503 is used to control the FEC decoding module 504 to start FEC decoding based on the current LLR sequence after each OFDM symbol reception and update processing is completed, if the value of the new cost function is greater than or equal to the preset convergence threshold, before all symbols corresponding to the FEC coding block have been received; and to control the FEC decoding module 504 to start FEC decoding based on the current LLR sequence after all symbols corresponding to the FEC coding block have been received but FEC decoding has not yet started.

[0166] As an optional implementation, the control module 503 is used to obtain the repetition count of each bit in the current LLR sequence and the current cost function before FEC decoding is started; when the repetition count of a bit in the LLR sequence is less than a preset counting threshold, or the value of the new cost function is less than a preset convergence threshold, the control module 502 is controlled to continue receiving the next OFDM symbol and perform reception and update processing; when the repetition count of each bit in the LLR sequence is greater than or equal to the preset counting threshold, and the value of the new cost function is greater than or equal to the preset convergence threshold, the control module 504 is controlled to start FEC decoding based on the current LLR sequence before all symbols corresponding to the FEC coding block have been received.

[0167] As an optional implementation, the control module 503 is also used to, during the iterative decoding process after starting FEC decoding, if the FEC decoding has reached the preset maximum number of iterations but still fails to decode the FEC coded block, and the symbols corresponding to the FEC coded block have not all been received, control the receiving update module 502 to continue receiving the remaining OFDM symbols of the FEC coded block and perform receiving and update processing on each OFDM symbol to be received, and control the FEC decoding module 504 to continue FEC decoding based on the updated LLR sequence until the FEC decoding successfully decodes the FEC coded block, or all the symbols corresponding to the FEC coded block have been received.

[0168] The control module 503 is connected to the receive update module 502, the FEC decoding module 504, the threshold configuration module 505, and the threshold adjustment module 506 respectively. It is used to make a start judgment based on the current cost function, the repetition count of each bit, and the symbol reception progress provided by the receive update module 502. Based on this, it controls the FEC decoding module 504 to start FEC decoding or controls the receive update module 502 to continue receiving OFDM symbols. In the start judgment, the preset convergence threshold provided by the threshold configuration module 505 or the threshold adjustment module 506 is used.

[0169] The FEC decoding module 504 is used to perform FEC decoding on the LLR sequence under the control of the control module 503 and output the FEC decoding result of the FEC encoded block.

[0170] As an optional implementation, the FEC decoding module 504 uses an iterative decoding algorithm for FEC decoding, including, for example, the belief propagation decoding algorithm for LDPC codes or the Max-Log-MAP decoding algorithm for Turbo codes. Before each iteration, the FEC decoding module 504 rereads the current LLR sequence, so that the LLR values ​​newly received and merged by the receiving update module 502 during the iterative decoding process can be used in the current iteration in a timely manner.

[0171] The FEC decoding module 504 is connected to the receiving update module 502, the control module 503, and the threshold adjustment module 506, respectively. It is used to receive the current LLR sequence or the updated LLR sequence provided by the receiving update module 502, start or continue FEC decoding under the control of the control module 503, and provide the iterative state information that represents the current degree of decoding convergence fed back during the iterative decoding process to the threshold adjustment module 506.

[0172] The threshold configuration module 505 is used to determine the channel quality parameters that characterize the current channel quality based on the channel state information obtained when receiving OFDM symbols, and to map the channel quality parameters to a preset convergence threshold according to a preset mapping relationship, wherein the preset convergence threshold increases as the channel quality parameters increase in the mapping relationship.

[0173] The threshold configuration module 505 is connected to the receive update module 502 and the control module 503 respectively. It is used to obtain the channel state information obtained when receiving OFDM symbols from the receive update module 502, and provide the mapped preset convergence threshold to the control module 503 so that the control module 503 can use the mapped preset convergence threshold as the preset convergence threshold in the judgment of starting FEC decoding.

[0174] The threshold adjustment module 506 is used to obtain the iterative state information that represents the current degree of decoding convergence fed back by the FEC decoding module 504 during the iterative decoding process after the FEC decoding is started, and adjust the preset convergence threshold according to the iterative state information to obtain the adjusted preset convergence threshold.

[0175] The threshold adjustment module 506 is connected to the FEC decoding module 504 and the control module 503 respectively. It is used to obtain iteration state information from the FEC decoding module 504 and provide the adjusted preset convergence threshold to the control module 503. When the control module 503 performs the judgment to start FEC decoding on the FEC encoding block received after the FEC encoding block, it uses the adjusted preset convergence threshold as the preset convergence threshold.

[0176] The above modules work together. The output of the initialization module 501 is connected to the receiving update module 502. The receiving update module 502 is connected to the initialization module 501, the control module 503, the FEC decoding module 504, and the threshold configuration module 505. The control module 503 is connected to the receiving update module 502, the FEC decoding module 504, the threshold configuration module 505, and the threshold adjustment module 506. The FEC decoding module 504 is connected to the receiving update module 502, the control module 503, and the threshold adjustment module 506. The threshold configuration module 505 is connected to the receiving update module 502 and the control module 503. The threshold adjustment module 506 is connected to the FEC decoding module 504 and the control module 503. Therefore, after initialization module 501 completes initialization, receiving and updating module 502 receives and merges OFDM symbols symbol by symbol, updates the LLR sequence, cost function and the repetition count of each bit. Control module 503, in conjunction with the preset convergence threshold configured by threshold configuration module 505 and the repetition count of each bit, makes a start judgment and controls the start and continuation of FEC decoding module 504. FEC decoding module 504 feeds back the iteration status information to threshold adjustment module 506 to realize the closed-loop adjustment of the preset convergence threshold between FEC coding blocks, thereby jointly realizing the decoding process that adaptively determines the FEC decoding start time according to the quality of the received signal.

[0177] The receiving device in this application embodiment is described below from a hardware processing perspective. Please refer to [link / reference]. Figure 6 This is a schematic diagram of the physical device structure of a receiving end device in an embodiment of this application.

[0178] It should be noted that, Figure 6 The structure of the receiving device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0179] like Figure 6 As shown, the receiving device includes a CPU 601, which can perform various appropriate actions and processes based on a program stored in the read-only memory ROM 602 or a program loaded from the storage section 608 into the random access memory RAM 603, such as performing the methods described in the above embodiments. The RAM 603 also stores various programs and data required for system operation. The CPU 601, ROM 602, and RAM 603 are interconnected via a bus 604. An I / O interface 605 is also connected to the bus 604.

[0180] The following components are connected to I / O interface 605: input section 606 including audio input devices, push-button switches, etc.; output section 607 including a liquid crystal display (LCD) and audio output devices, indicator lights, etc.; storage section 608 including a hard disk, etc.; and communication section 609 including a network interface card such as a LAN (Local Area Network) card, modem, etc. Communication section 609 performs communication processing via a network such as the Internet. Drive 610 is also connected to I / O interface 605 as needed. Removable media 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 610 as needed so that computer programs read from them can be installed into storage section 608 as needed.

[0181] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 609, and / or installed from removable medium 611. When the computer program is executed by CPU 601, it performs the various functions defined in this application.

[0182] It should be noted that specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0183] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those shown in the drawings.

[0184] Specifically, the receiving device in this embodiment includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements a decoding method based on repetitive encoding provided in the above embodiment.

[0185] In another aspect, this application also provides a computer-readable storage medium, which may be included in the receiving device described in the above embodiments; or it may exist independently and not assembled into the receiving device. The storage medium carries one or more computer programs that, when executed by a processor of the receiving device, cause the receiving device to implement a decoding method based on repetitive encoding provided in the above embodiments.

[0186] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0187] As used in the above embodiments, depending on the context, the term "when..." can be interpreted as meaning "if...", "after...", "in response to determining...", or "in response to detecting...". Similarly, depending on the context, the phrase "when determining..." or "if (the stated condition or event) is interpreted as meaning "if determining...", "in response to determining...", "when (the stated condition or event) is detected", or "in response to detecting (the stated condition or event)".

[0188] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A decoding method based on repetition coding, applied to a receiving end device, characterized in that, include: Initialize the log-likelihood ratio (LLR) sequence and cost function of the current FEC coded block. The LLR sequence contains the LLR values ​​corresponding to each bit of the FEC coded block, and the cost function is a numerical value used to evaluate the quality of the LLR sequence. The OFDM symbol corresponding to the FEC coding block is received. When an OFDM symbol is received, the currently received OFDM symbol is processed for reception and update. The reception and update process includes: demodulating the currently received OFDM symbol to obtain the original LLR value; determining the position of the bit carried by the currently received OFDM symbol in the FEC coding block according to the repetition coding mapping rule; merging the original LLR value into the LLR value at the corresponding position in the LLR sequence to obtain the updated LLR sequence; and updating the cost function according to the updated LLR sequence to obtain a new cost function. Before FEC decoding is started, after each OFDM symbol is received and updated, if the value of the new cost function is greater than or equal to a preset convergence threshold, then FEC decoding is started based on the current LLR sequence before all symbols corresponding to the FEC coding block are received. If all symbols corresponding to the FEC coded block have been received but FEC decoding has not yet started, then FEC decoding is started based on the current LLR sequence. Output the FEC decoding result of the FEC encoded block.

2. The method according to claim 1, characterized in that, Also includes: Initialize the repetition count for each bit in the LLR sequence, where the repetition count represents the number of times the corresponding bit has been merged. In the receiving and updating process, the repetition count of the corresponding bit position is updated; Before FEC decoding is started, after each OFDM symbol is received and updated, the repetition count of each bit in the current LLR sequence and the current cost function are obtained. When the number of repeated bits in the LLR sequence is less than a preset counting threshold, or the current value of the cost function is less than the preset convergence threshold, the next OFDM symbol is received and the receiving and updating process is performed. When the repetition count of each bit in the LLR sequence is greater than or equal to a preset counting threshold, and the current value of the cost function is greater than or equal to the preset convergence threshold, FEC decoding is initiated based on the current LLR sequence before all symbols corresponding to the FEC coding block have been received.

3. The method according to claim 1, characterized in that, The cost function is determined based on the LLR value corresponding to each bit in the LLR sequence, and the cost function is calculated according to the following formula: Where Q represents the cost function, L represents the number of bits contained in the FEC coded block, and i represents the bit index and , This represents the LLR value corresponding to the i-th bit in the LLR sequence; The value of the cost function increases as the absolute value of the LLR value corresponding to each bit in the LLR sequence increases.

4. The method according to claim 3, characterized in that, The step of updating the cost function based on the updated LLR sequence to obtain a new cost function includes: After the original LLR value of the currently received OFDM symbol is merged into the LLR sequence, the change in the LLR value at the corresponding position in the LLR sequence relative to the value before merging is determined. Based on the change, a recursive operation is performed on the cost function before this reception to obtain a new cost function after this reception.

5. The method according to claim 1 or 2, characterized in that, The preset convergence threshold is determined based on the channel state, and the method further includes: Based on the channel state information obtained when receiving the OFDM symbol, determine the channel quality parameters that characterize the current channel quality; According to a preset mapping relationship, the channel quality parameters are mapped to the preset convergence threshold, wherein the preset convergence threshold increases as the channel quality parameters increase. In the determination of starting FEC decoding, the preset convergence threshold obtained by mapping is used as the preset convergence threshold.

6. The method according to claim 5, characterized in that, Also includes: During the iterative decoding process after FEC decoding is initiated, the iterative state information that represents the current degree of decoding convergence, fed back by the FEC decoding, is obtained; The preset convergence threshold is adjusted based on the iterative state information to obtain the adjusted preset convergence threshold; When performing the determination to initiate FEC decoding on an FEC encoded block received after the FEC encoded block, the adjusted preset convergence threshold is used as the preset convergence threshold.

7. The method according to claim 1, characterized in that, Following the initiation of FEC decoding, the following is also included: If the FEC decoding fails to decode the FEC code block after reaching the preset maximum number of iterations, and the symbols corresponding to the FEC code block have not all been received, then the remaining OFDM symbols of the FEC code block will continue to be received. For each OFDM symbol that is received, the receive and update process is performed to obtain the updated LLR sequence; FEC decoding continues based on the updated LLR sequence until the FEC decoding successfully decodes the FEC coded block, or all symbols corresponding to the FEC coded block are received.

8. A decoding device based on repetition coding, applied to a receiving end device, characterized in that, include: An initialization module is used to initialize the log-likelihood ratio (LLR) sequence and cost function of the current FEC coding block. The LLR sequence contains the LLR values ​​corresponding to each bit of the FEC coding block, and the cost function is a numerical value used to evaluate the quality of the LLR sequence. The receive update module is used to receive OFDM symbols corresponding to the FEC coding block one by one, and to perform receive and update processing on the currently received OFDM symbol when receiving an OFDM symbol. The receive and update processing includes: demodulating the currently received OFDM symbol to obtain the original LLR value, determining the position of the bit carried by the currently received OFDM symbol in the FEC coding block according to the repetition coding mapping rule, merging the original LLR value into the LLR value at the corresponding position in the LLR sequence to obtain the updated LLR sequence, and updating the cost function according to the updated LLR sequence to obtain a new cost function. The control module is configured to, when FEC decoding has not yet started, after completing the reception and update processing of each OFDM symbol, if the current value of the cost function is greater than or equal to a preset convergence threshold, control the FEC decoding module to start FEC decoding based on the current LLR sequence before all symbols corresponding to the FEC coding block have been received; and to control the FEC decoding module to start FEC decoding based on the current LLR sequence when all symbols corresponding to the FEC coding block have been received but FEC decoding has not yet started. The FEC decoding module is used to perform FEC decoding on the LLR sequence under the control of the control module and output the FEC decoding result of the FEC encoded block.

9. A receiving device, characterized in that, The receiving device includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions, and the one or more processors call the computer instructions to cause the receiving device to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing computer instructions, characterized in that, When the computer instructions are executed on the receiving device, the receiving device performs the method as described in any one of claims 1 to 7.

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