A high speed communication system and method

Abstract

The embodiment of the application provides a high-speed communication system and method, the high-speed communication system comprises: a sending end configured with a coupling capacitor, configured to send a data signal to a receiving end; the receiving end comprises a tracking calibration circuit and an analog clock data recovery circuit; the tracking calibration circuit is configured to generate a control word to preliminarily calibrate the phase or amplitude of the received data signal according to the data signal; the analog clock data recovery circuit is configured to further calibrate the preliminarily calibrated data signal; wherein the tracking calibration circuit and the analog clock data recovery circuit work cooperatively, the tracking calibration circuit is used to calibrate the jitter caused by the common noise source, and the analog clock data recovery circuit is used to calibrate the remaining independent jitter caused by the inter-channel difference. The technical scheme of the application can effectively solve the problem that the traditional UCIE architecture in the prior art is difficult to support 64Gbps high-speed data transmission, and also cannot effectively resist the jitter caused by the power supply and thermal noise.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a high-speed communication system and method. Background Technology

[0002] With the surge in computing power demands from artificial intelligence and machine learning, chiplet integration technology using 2.5D or 3D packaging has become widely adopted. Universal Chiplet Interconnect Express (UCIe), as an industry-standard, specifies that interconnect interfaces must meet requirements for high bandwidth density, high energy efficiency, and low latency. In the UCIe protocol, data transmission rates have increased to 64Gbps, posing significant challenges to high-speed architecture design, requiring designs to support single-ended signals, low power consumption, small area, and low latency. Existing traditional UCIE architectures typically employ DC-coupled technology and use RX TRACK (receiver tracking) technology to track signal phase. However, this traditional architecture (such as...) Figure 1 As shown, the RX TRACK technology has significant drawbacks when dealing with 64Gbps high-speed transmission: First, it cannot effectively combat the effects of inter-module crosstalk and external noise. Second, due to differences in layout, power distribution, and inter-module crosstalk, significant differences arise between multiple lanes, resulting in inconsistent timing characteristics. Furthermore, traditional UCIE architectures typically rely on a forward clock transmission mechanism and lack efficient clock recovery schemes for single-end low-power scenarios, making it difficult to maintain stable data transmission performance at 64Gbps.

[0003] In the aforementioned traditional technologies, the lack of effective equalization mechanisms and fine-grained clock recovery methods makes it difficult for traditional UCIE architectures to support high-speed data transmission of 64Gbps. Specifically, channel insertion loss and attenuation cause signal eye diagram closure, while traditional RX TRACK technology can only perform coarse-grained phase tracking, failing to address jitter caused by common noise sources (such as power supply noise and thermal noise) or eliminate independent jitter caused by physical differences between lanes. Furthermore, existing solutions often cannot provide sufficient equalization capability while maintaining low power consumption, leading to increased bit error rate at high speeds and failing to meet the stringent reliability and energy efficiency requirements of the UCIe protocol. Therefore, an architecture that combines efficient equalization technology with fine-grained clock data recovery technology is urgently needed to solve these technical problems. Summary of the Invention

[0004] This application provides a high-speed communication system and method to at least solve the problems in the prior art where the traditional UCIE architecture cannot support 64Gbps high-speed data transmission and cannot effectively combat jitter caused by power supply and thermal noise.

[0005] According to one embodiment of this application, a high-speed communication system is provided, comprising:

[0006] A transmitting end equipped with a coupling capacitor is configured to transmit a data signal to a receiving end, wherein the coupling capacitor is configured to perform high-pass filtering and amplitude equalization on the data signal;

[0007] The receiving end includes a tracking calibration circuit and an analog clock data recovery circuit;

[0008] The tracking calibration circuit is configured to generate a control word based on the data signal to preliminarily calibrate the phase or amplitude of the received data signal;

[0009] An analog clock data recovery circuit is configured to recalibrate a data signal that has undergone preliminary calibration; wherein the tracking calibration circuit and the analog clock data recovery circuit work together, the tracking calibration circuit is used to calibrate jitter caused by a common noise source, and the analog clock data recovery circuit is used to calibrate the remaining independent jitter caused by inter-channel differences.

[0010] In one embodiment of this application, the transmitting end includes: a data transmitting unit configured to transmit high-speed data signals; a clock transmitting unit configured to transmit reference clock signals; and a tracking signal transmitting unit configured to transmit tracking signals for calibration of the receiving end.

[0011] In one embodiment of this application, the coupling capacitor includes: a series capacitor disposed on the signal path between the transmitting end and the receiving end; a transmitting end matching resistor and a receiving end terminating resistor; wherein, the series capacitor, the transmitting end matching resistor and the receiving end terminating resistor together constitute a high-pass filter, used to filter out the DC component of the data signal and perform high-pass equalization on the data signal.

[0012] In one embodiment of this application, the analog clock data recovery circuit includes: a sampling circuit configured to perform data sampling and / or edge sampling on the data signal processed by the tracking calibration circuit; a phase comparison circuit configured to calculate the phase error between the current sampling clock and the optimal sampling point of the data eye diagram based on the sampling result; and a decision and control circuit configured to generate a phase adjustment command based on the phase error, wherein the phase adjustment command is used to adjust the phase of the sampling clock so that the sampling clock is locked in the center of the data eye diagram.

[0013] In one embodiment of this application, the tracking calibration circuit further includes a digitally controlled delay line;

[0014] The tracking calibration circuit is also used to adjust the delay of the digital control delay line to compensate for systematic deviations between multiple lanes.

[0015] In one embodiment of this application, the receiving end further includes: a signal receiving unit configured to receive the high-speed data signal, the reference clock signal, and the tracking signal.

[0016] According to one embodiment of this application, a high-speed communication method is provided, comprising:

[0017] A data signal is transmitted to a receiving end through a transmitting end configured with a coupling capacitor, wherein the coupling capacitor performs high-pass filtering and amplitude equalization on the data signal;

[0018] The receiving end generates a control word based on the received equalized data signal, performs preliminary calibration on the phase or amplitude of the data signal to calibrate jitter caused by common noise sources, and performs a second calibration on the data signal after preliminary calibration to calibrate the remaining independent jitter caused by inter-channel differences.

[0019] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0020] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0021] By applying the technical solution of this application, the data signal is high-pass filtered and amplitude equalized by the coupling capacitor configured at the transmitting end. Combined with the collaborative work of the tracking calibration circuit and the analog clock data recovery circuit at the receiving end, the tracking calibration circuit first generates a control word based on the data signal to perform preliminary calibration on the phase or amplitude of the received data signal to eliminate jitter caused by common noise sources. Subsequently, the analog clock data recovery circuit recalibrates the data signal after preliminary calibration to eliminate the remaining independent jitter caused by inter-channel differences. This achieves effective suppression of jitter across the entire frequency band of the data signal, solving the problem that the traditional UCIE architecture cannot support 64Gbps high-speed data transmission and cannot effectively combat jitter caused by power supply and thermal noise. This ensures the stable operation of the high-speed communication system and improves the data transmission rate and anti-interference capability. Attached Figure Description

[0022] Figure 1 This is an existing conventional UCIE architecture scheme according to an embodiment of this application;

[0023] Figure 2 This is a structural block diagram of a high-speed communication system according to an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the structure of a high-speed communication system according to an embodiment of this application;

[0025] Figure 4 This is a flowchart of a high-speed communication method according to an embodiment of this application. Detailed Implementation

[0026] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0028] To facilitate understanding of the technical solutions in this application, a brief introduction to the technologies involved in this solution is provided.

[0029] This embodiment provides a high-speed communication system. Figure 2 This is a structural block diagram of a high-speed communication system according to an embodiment of this application, such as... Figure 2 As shown, the high-speed communication system includes:

[0030] The transmitting end, equipped with a coupling capacitor, is configured to transmit a data signal to the receiving end. The coupling capacitor is configured to perform high-pass filtering and amplitude equalization on the data signal.

[0031] The receiver includes a tracking calibration circuit and an analog clock data recovery circuit;

[0032] The tracking calibration circuit is configured to generate a control word based on the data signal to initially calibrate the phase or amplitude of the received data signal;

[0033] The analog clock data recovery circuit is configured to recalibrate the data signal after preliminary calibration. The tracking calibration circuit and the analog clock data recovery circuit work together. The tracking calibration circuit is used to calibrate the jitter caused by the common noise source, and the analog clock data recovery circuit is used to calibrate the remaining independent jitter caused by inter-channel differences.

[0034] In this embodiment, the coupling capacitor refers to the AC coupling capacitor added at the TX end (transmitter) to replace the traditional DC coupling technology of UCIE, performing high-pass filtering on the signal to combat channel attenuation and provide equalization capability. The data signal refers to the high-speed binary bit stream transmitted on the DATA Lane. Its eye diagram quality is affected by factors such as channel insertion loss and noise, and needs to be ensured correct reception at 64Gbps through equalization and clock recovery techniques. Amplitude equalization can compensate for the attenuation of the high-speed signal due to channel insertion loss, thereby improving the data eye diagram quality at the receiver and ensuring correct sampling at 64Gbps.

[0035] Specifically, the transmitting end is configured to include a coupling capacitor connected between the transmitting end and the receiving end for transmitting data signals to the receiving end. During this process, the coupling capacitor performs a high-pass filtering operation on the transmitted data signal, thereby producing an amplitude equalization effect and improving signal quality.

[0036] Specifically, the tracking calibration circuit is configured to perform a phase or amplitude calibration process based on the data signal. Specifically, the circuit receives the data signal from the receiving end as input and generates a control word for control based on the analysis or processing of the data signal. This control word is then output to act on the receiving link, thereby achieving preliminary calibration of the received data signal in the phase or amplitude dimension. This aims to eliminate non-ideal deviations generated during signal transmission, laying the foundation for subsequent correct data sampling. The data signal after preliminary calibration is then recalibrated, specifically through an analog clock data recovery circuit. This circuit receives the data signal that has already undergone pre-processing or initial adjustment and performs further phase or timing corrections to ensure the accuracy of data sampling and the stability of clock recovery, thus completing a fine-tuned calibration process for the data signal.

[0037] Optionally, the tracking calibration circuit and the analog clock data recovery circuit work together. The tracking calibration circuit is used to calibrate jitter caused by a common noise source, while the analog clock data recovery circuit is used to calibrate the remaining independent jitter caused by inter-channel differences. In this embodiment, the tracking calibration circuit calibrates the jitter generated by the common noise source, while the analog clock data recovery circuit calibrates the independent jitter caused by inter-channel differences. The two work together to achieve comprehensive jitter correction.

[0038] By applying the technical solution of this embodiment, a data signal is transmitted to the receiving end through a coupling capacitor configured at the transmitting end. The coupling capacitor is used to perform high-pass filtering and amplitude equalization on the data signal, thereby improving the signal quality to support high-speed data transmission of 64Gbps. At the receiving end, the tracking calibration circuit first generates a control word based on the received data signal to perform preliminary calibration on the phase or amplitude of the signal to eliminate jitter caused by common noise sources. Subsequently, the analog clock data recovery circuit recalibrates the data signal after preliminary calibration to solve the independent jitter caused by channel differences. The two work together to complete the complete calibration of the data signal, thereby effectively combating jitter caused by power supply and thermal noise and improving the signal integrity and transmission stability of the high-speed communication system.

[0039] Optionally, the sender includes:

[0040] The data transmission unit is configured to transmit high-speed data signals;

[0041] A clock transmitting unit is configured to transmit a reference clock signal;

[0042] The tracking signal transmitting unit is configured to transmit a tracking signal for receiver calibration.

[0043] In this embodiment, the transmitting end is specifically divided into a data transmitting unit, a clock transmitting unit, and a tracking signal transmitting unit. The data transmitting unit is responsible for generating and transmitting high-speed data signals carrying service information, the clock transmitting unit is used to output a reference clock signal as a time base, and the tracking signal transmitting unit is specifically used to generate a tracking signal for the receiving end to perform initial alignment. This structure clearly decomposes the signal sources of the transmitting end, enabling the receiving end to clearly distinguish and acquire signals of different natures. For example, the high-speed data signal is processed by the receiving end's tracking calibration circuit and analog clock data recovery circuit, the reference clock signal provides a stable clock base for the receiving end, and the tracking signal is directly input to the tracking calibration circuit to generate a control word, thereby achieving preliminary calibration of jitter caused by a common noise source.

[0044] Optionally, the coupling capacitor includes: a series capacitor disposed on the signal path between the transmitting end and the receiving end; a matching resistor at the transmitting end and a terminating resistor at the receiving end; wherein, the series capacitor, the matching resistor at the transmitting end and the terminating resistor at the receiving end together constitute a high-pass filter, used to filter out the DC component of the data signal and perform high-pass equalization on the data signal.

[0045] In this embodiment, the coupling capacitor is specifically composed of a series capacitor, a transmitting-end matching resistor, and a receiving-end terminating resistor. The series capacitor is directly connected in series on the signal transmission path between the transmitting and receiving ends. The transmitting-end matching resistor is located on the transmitting-end output side, and the receiving-end terminating resistor is located on the receiving-end input side. These three components are connected in a specific topology to jointly construct a passive high-pass filter structure. During data signal transmission, this high-pass filter utilizes the DC blocking and AC passing characteristics of the series capacitor to effectively filter out any DC bias components that may exist in the signal, preventing DC level drift from interfering with subsequent circuits. At the same time, it utilizes the frequency response characteristics formed by the resistor and capacitor to boost the amplitude of the segment's data signal (i.e., high-pass equalization) to compensate for the attenuation caused by the skin effect and dielectric loss in the high-speed channel. By clarifying this specific circuit configuration and signal conditioning mechanism, this scheme achieves complete filtering of the DC component of the data signal and precise equalization of its components, significantly improving the signal integrity of 64Gbps high-speed data transmission, effectively suppressing the jitter caused by power supply noise and thermal noise, and ensuring that the receiving end can accurately recover the clock and data.

[0046] Optional, the analog clock data recovery circuit includes:

[0047] The sampling circuit is configured to perform data sampling and / or edge sampling on the data signal processed by the tracking calibration circuit.

[0048] The phase comparison circuit is configured to calculate the phase error between the current sampling clock and the optimal sampling point of the data eye diagram based on the sampling result.

[0049] The decision and control circuit is configured to generate a phase adjustment command based on the phase error, wherein the phase adjustment command is used to adjust the phase of the sampling clock so that the sampling clock is locked in the center of the data eye diagram.

[0050] In this embodiment, the voltage state or transition edge position of the signal at a specific moment is acquired. "Edge sampling" specifically refers to capturing the instantaneous transition from low to high or from high to low level to more sensitively reflect clock phase deviation. By quantifying the delay or lead of the actual sampling moment relative to the center of the signal eye diagram (the ideal position with maximum noise margin and lowest bit error rate), the abstract time deviation is transformed into a processable numerical signal. The decision and control circuit generates a phase adjustment command based on this phase error. By fine-tuning the phase of the sampling clock, closed-loop feedback control is achieved, gradually bringing the sampling clock closer to and ultimately locking it at the center of the data eye diagram. Through the coordinated operation of the above sampling, comparison, and control, not only is precise cancellation of independent jitter caused by inter-channel differences achieved, but it also ensures that the sampling moment is always in the region of optimal signal quality.

[0051] Optionally, the tracking calibration circuit also includes a digitally controlled delay line; the tracking calibration circuit is also used to adjust the delay of the digitally controlled delay line to compensate for systematic deviations between multiple lanes.

[0052] In this embodiment, the newly added digital control delay line in the tracking calibration circuit refers to an electronic component that can precisely adjust the signal transmission timing through digital signals. Its working mechanism is to receive the control word generated by the tracking calibration circuit, and then dynamically adjust the conduction state or capacitive load of the internal delay unit, thereby changing the time delay of the signal passing through the delay line. Specifically, when the system detects that the transmission time between lanes is inconsistent due to different PCB layout trace lengths, uneven power supply noise distribution, or device process deviations, the digital control delay line can perform microsecond or nanosecond-level delay compensation on the data signal of a specific lane according to the control word, so that the multi-lane signals that originally had phase or amplitude deviations are re-aligned at the receiving end. Through this precise adjustment of the delay, the systematic deviation between multiple lanes is effectively offset, ensuring the timing consistency of each data channel during high-speed transmission, thereby improving the signal integrity of the high-speed communication system at a rate of 64Gbps and the decoding accuracy of the receiving end.

[0053] Optionally, the receiver may also include a signal receiving unit configured to receive high-speed data signals, reference clock signals, and tracking signals.

[0054] In this embodiment, the signal receiving unit added to the receiving end serves as the entry point of the high-speed data transmission link. Specifically, it is configured to receive high-speed data signals, reference clock signals, and tracking signals for calibration from the transmitting end in parallel. The high-speed data signals carry actual service information, the reference clock signals provide reference timing, and the tracking signals serve as an independent calibration reference source. Through a multi-channel parallel access mechanism, the signal receiving unit ensures that the three different types of signals can enter the receiving end stably and synchronously, enabling subsequent circuits to clearly distinguish between data flow and control flow, thus avoiding signal crosstalk or timing misalignment.

[0055] Figure 3 This is a schematic diagram of the structure of a high-speed communication system according to an embodiment of this application, such as... Figure 3As shown, unlike the traditional UCIE DC Couple technology, this invention adds a Couple capacitor at the TX end to perform high-pass filtering on the signal, combating channel attenuation. While achieving equalization capabilities, it also achieves lower power consumption and incorporates CDR (Clock and Data Recovery) technology within each lane to track jitter caused by power supply noise and thermal noise. Specifically, TRACK tracking is used to calibrate most of the jitter, and multiple lanes share the same calibration; the lane-specific CDR is used to calibrate the remaining independent jitter.

[0056] like Figure 3 As shown, the transmitting end refers to the chip module in the data stream transmission direction (such as the TX part in Die0), which includes LANE-TX-DATA, LANE-TX-CLK, and LANE-TX-TRACK signal interfaces. It is responsible for transmitting the data signal to the channel after processing by the TX equalization circuit. The receiving end refers to the chip module in the data stream reception direction (such as the RX part in Die1), which includes LANE-RX-DATA, LANE-RX-CLK, and LANE-RX-TRACK signal interfaces. It is responsible for recovering the data from the channel and locking the middle position of the eye diagram for sampling through equalization and CDR technology. The 64Gbps high-speed architecture connects two dies, namely die0 and die1. The scenario is that the data stream is sent from TX to RX. Wherein: the TX of die0 are LANE-TX-DATA, LANE-TX-CLK, and LANE-TX-TRACK, respectively, and the RX of die1 are LANE-RX-DATA, LANE-RX-CLK, and LANE-RX-TRACK, respectively. Data is sent / received through the DATA lane, and the clock is sent / received through the CLK lane. The received clock is processed and used for sampling the received data. Due to the bit error rate requirement, the sampling position needs to be in the middle of the data eye diagram. However, due to various non-ideal factors, if the data can be received correctly at a rate of 64Gb / s, CDR tracking is required to lock the clock in the middle of the data eye diagram.

[0057] The equalization system, composed of R1 and C1 in TX and R2 in RX, ensures sufficient equalization capability at low power consumption. The CDR circuit consists of a data / edge sampling circuit, a PI phase adjustment circuit, and a data logic circuit for CDR decision. The data / edge sampling circuit samples the middle and edges of the data; the PI phase adjustment circuit, i.e., the phase difference circuit, adjusts the clock phase; and the data logic circuit for CDR decision sends the sampled data / edge data to the data control logic to determine the clock phase position (advanced or delayed). Simultaneously, the architecture still performs RX TRACK tracking and calibration, adjusted via the DCDL control word. The proposed architecture allows for the integration of RX TRACK and CDR.

[0058] This embodiment provides a high-speed communication method, which is executed by the aforementioned high-speed communication system. Figure 4 This is a flowchart of a high-speed communication method according to an embodiment of this application, such as... Figure 4 As shown, the method includes:

[0059] S402. A data signal is transmitted to a receiving end through a transmitting end configured with a coupling capacitor, wherein the coupling capacitor performs high-pass filtering and amplitude equalization on the data signal.

[0060] In this embodiment, the coupling capacitor includes a series capacitor, a transmitting end matching resistor, and a receiving end terminating resistor. The transmitting end matching resistor and the receiving end terminating resistor constitute a voltage bias and together with the series capacitor form an equalization system.

[0061] S404. The receiving end generates a control word based on the received equalized data signal, performs preliminary calibration on the phase or amplitude of the data signal to calibrate the jitter caused by the common noise source, and performs a second calibration on the data signal after preliminary calibration to calibrate the remaining independent jitter caused by the differences between channels.

[0062] This application also provides a high-speed communication method, which is executed by the aforementioned high-speed communication system. The method involves transmitting a data signal to a receiving end through a transmitting end equipped with a coupling capacitor. The coupling capacitor is used to perform high-pass filtering and amplitude equalization on the data signal, reducing power consumption while ensuring the eye diagram quality of the signal. The receiving end generates a control word based on the received equalized data signal to perform preliminary calibration of the phase or amplitude of the data signal to cancel jitter caused by common power supply noise or thermal noise. Subsequently, the pre-calibrated data signal is recalibrated to finely adjust independent jitter caused by inter-channel differences. This staged, multi-level calibration mechanism enables the receiving end to accurately lock the center of the data eye diagram at a high rate of 64Gbps, thereby effectively improving the bit error rate performance and reliability of high-speed data transmission.

[0063] Optionally, the recalibration of the data signal after preliminary calibration includes:

[0064] S1) Perform data sampling and / or edge sampling on the data signal after preliminary calibration;

[0065] S2) Calculate the phase error between the current sampling clock and the optimal sampling point of the data eye diagram;

[0066] S3) Generate a phase adjustment command based on the phase error to adjust the phase of the sampling clock so that the sampling clock is locked in the center of the data eye diagram.

[0067] In this embodiment, data sampling and / or edge sampling of the pre-calibrated data signal refers to the receiving end using the current sampling clock to capture the state of the pre-calibrated data waveform, obtaining discrete data bits or signal transition edge information, providing basic samples for subsequent error calculation. Calculating the phase error between the current sampling clock and the optimal sampling point of the data eye diagram involves using an algorithm to analyze the sampling results and determine the specific deviation of the current clock phase from the center of the data receiving window (i.e., the center of the eye diagram). This error value reflects the accuracy of clock alignment. Generating a phase adjustment command based on the phase error and adjusting the phase of the sampling clock to lock it in the center of the data eye diagram means that the control logic dynamically adjusts the output phase of the clock generator based on the calculated deviation, driving the sampling clock to gradually move and stabilize at the center position where the data eye diagram opening is maximum and the noise tolerance is highest, thereby completing the recalibration of the pre-calibrated data signal. Through the synergistic effect of the above steps, independent jitter caused by inter-channel differences can be effectively calibrated, ensuring that the sampling clock is always accurately located in the optimal position during high-speed data transmission, significantly improving the noise immunity and data transmission reliability of 64Gbps and above high-speed communication systems.

[0068] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0069] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps in any of the above method embodiments.

[0070] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0071] Embodiments of this application also provide an electronic device including a processor and a memory storing a computer program, the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0072] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0073] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0074] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0075] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0076] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A high-speed communication system, characterized in that, The system includes: A transmitting end equipped with a coupling capacitor is configured to transmit a data signal to a receiving end, wherein the coupling capacitor is configured to perform high-pass filtering and amplitude equalization on the data signal; The receiving end includes a tracking calibration circuit and an analog clock data recovery circuit; The tracking calibration circuit is configured to generate a control word based on the data signal to preliminarily calibrate the phase or amplitude of the received data signal; An analog clock data recovery circuit is configured to recalibrate a data signal that has undergone preliminary calibration; wherein the tracking calibration circuit and the analog clock data recovery circuit work together, the tracking calibration circuit is used to calibrate jitter caused by a common noise source, and the analog clock data recovery circuit is used to calibrate the remaining independent jitter caused by inter-channel differences.

2. The system according to claim 1, characterized in that, The sending end includes: The data transmission unit is configured to transmit high-speed data signals; A clock transmitting unit is configured to transmit a reference clock signal; A tracking signal transmitting unit is configured to transmit a tracking signal for calibration of the receiving end.

3. The system according to claim 1, characterized in that, The coupling capacitor includes: A series capacitor is disposed on the signal path between the transmitting end and the receiving end; The transmitting end matching resistor and the receiving end terminating resistor; The series capacitor, the transmitting end matching resistor, and the receiving end terminating resistor together constitute a high-pass filter, which is used to filter out the DC component of the data signal and perform high-pass equalization on the data signal.

4. The system according to claim 1, characterized in that, The analog clock data recovery circuit includes: The sampling circuit is configured to perform data sampling and / or edge sampling on the data signal processed by the tracking calibration circuit. A phase comparison circuit is configured to calculate the phase error between the current sampling clock and the optimal sampling point of the data eye diagram based on the sampling result. The decision and control circuit is configured to generate a phase adjustment command based on the phase error, wherein the phase adjustment command is used to adjust the phase of the sampling clock so that the sampling clock is locked in the center of the data eye diagram.

5. The system according to claim 1, characterized in that, The tracking calibration circuit also includes a digitally controlled delay line; The tracking calibration circuit is also used to adjust the delay of the digital control delay line to compensate for systematic deviations between multiple lanes.

6. The system according to claim 2, characterized in that, The receiving end also includes: The signal receiving unit is configured to receive the high-speed data signal, the reference clock signal, and the tracking signal.

7. A high-speed communication method, characterized in that, The method is performed by the high-speed communication system according to any one of claims 1 to 6, and the method includes: A data signal is transmitted to a receiving end through a transmitting end configured with a coupling capacitor, wherein the coupling capacitor performs high-pass filtering and amplitude equalization on the data signal; The receiving end generates a control word based on the received equalized data signal, performs preliminary calibration on the phase or amplitude of the data signal to calibrate jitter caused by common noise sources, and performs a second calibration on the data signal after preliminary calibration to calibrate the remaining independent jitter caused by inter-channel differences.

8. The method according to claim 7, characterized in that, The recalibration of the data signal after preliminary calibration includes: Perform data sampling and / or edge sampling on the data signal after preliminary calibration; Calculate the phase error between the current sampling clock and the optimal sampling point of the data eye diagram; A phase adjustment command is generated based on the phase error to adjust the phase of the sampling clock so that the sampling clock is locked in the center of the data eye diagram.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 7 to 8.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 7 to 8.

11. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 7 to 8.

Images