A hardware isolation-based decryption method, device and electronic equipment

Abstract

The application discloses a decryption method and device based on hardware isolation and electronic equipment, and belongs to the technical field of data security. The method comprises the following steps: receiving a descriptor sent by a host computer, wherein the descriptor comprises a routing label and a key handle index, and the routing label is used for determining a target device; determining a key corresponding to the key handle index, wherein the target hardware is provided with a first area, the key is pre-stored in the first area, and the first area is an area that is inaccessible to the host computer; sending a ciphertext data acquisition request to the host computer; receiving to-be-decrypted ciphertext data sent by the host computer, and decrypting the to-be-decrypted ciphertext data according to the key to obtain plaintext data corresponding to the to-be-decrypted ciphertext data; and sending the plaintext data to the target device. The host computer only contacts the to-be-decrypted ciphertext data and the key handle index, and the target hardware directly sends the plaintext data to the target device after decryption, thereby avoiding the contact of the host computer with the plaintext data and the key.

Description

Technical Field

[0001] This application belongs to the field of data security technology, and in particular relates to a decryption method, apparatus and electronic device based on hardware isolation. Background Technology

[0002] Currently, the decryption of high-speed data streams (such as network packets and video streams) generally employs an architecture that combines a hardware decryption module with host central processing unit (CPU) scheduling. A typical process is as follows: the host sends the ciphertext data and key to the hardware decryption module, which then decrypts the data and sends the plaintext data back to the host for further processing. It is evident that in the existing decryption process, both the key and plaintext are exposed on the host, which is often easily compromised, leading to data leakage. Therefore, current technologies cannot prevent the host from accessing the plaintext data and key, posing a risk of data leakage. Summary of the Invention

[0003] This application provides a hardware-isolated decryption method, apparatus, and electronic device to address the problem of data leakage in related technologies.

[0004] In a first aspect, embodiments of this application provide a hardware-isolated decryption method applied to target hardware, comprising: The receiving host sends a descriptor, which includes a routing label and a key handle index, wherein the routing label is used to determine the target device; The key corresponding to the key handle index is determined. The target hardware has a first area that stores the key in advance, and the first area is an area that is inaccessible to the host. Send a request to the host to retrieve encrypted data; The system receives ciphertext data to be decrypted from the host and decrypts the ciphertext data to be decrypted according to the key to obtain plaintext data corresponding to the ciphertext data to be decrypted. Send the plaintext data to the target device.

[0005] Optionally, the descriptor may further include the source physical address of the ciphertext data to be decrypted; The ciphertext data retrieval request includes the source physical address of the ciphertext data to be decrypted.

[0006] Optionally, the target hardware has a first area storing a first correspondence between routing labels and target addresses, wherein the routing label is the logical address of the target device and the target address is the physical address of the target device; Sending the plaintext data to the target device includes: The target address is determined based on the routing label and the first correspondence, and the plaintext data is sent to the target address.

[0007] Optionally, the descriptor further includes an authorization token, which is used to determine whether the host is an authorized entity; Determining the key corresponding to the key handle index includes: Within the first region, the message authentication code is calculated by performing a message authentication code operation on the key handle index based on the verification key stored in the first region, and the first authentication code is obtained. If the authorization token is the same as the first authentication code, the key corresponding to the key handle index is determined according to the key handle index; If the authorization token is different from the first authentication code, delete the key.

[0008] Optionally, before sending the plaintext data to the target address, the method further includes: The end address is determined based on the target address and the length of the plaintext data; the end address is the last address corresponding to the continuous storage of the plaintext data in the target device, starting from the target address. Determine whether both the target address and the end address are within a preset trusted range; If the target address or the end address is not within a preset trusted range, delete the plaintext data and the key.

[0009] Optionally, the method further includes deleting the key in any of the following cases: Complete the decryption of the encrypted data; The temperature change of the target hardware exceeds a preset threshold. The voltage change of the target hardware exceeds a preset threshold; The clock frequency of the target hardware changes beyond a preset threshold; The timer starts counting from the moment the host sends the descriptor, and the preset time period expires.

[0010] Secondly, embodiments of this application provide a hardware-isolated decryption method applied to a host, comprising: Send a descriptor to the target hardware, the descriptor including a routing label and a key handle index, the routing label being used to identify the target device; Receive the encrypted data acquisition request sent by the target hardware; Send the encrypted data to be decrypted to the target hardware.

[0011] Optionally, the descriptor may further include the source physical address of the ciphertext data to be decrypted; The ciphertext data retrieval request includes the source physical address of the ciphertext data to be decrypted.

[0012] Optionally, after sending the descriptor to the target hardware, the method further includes: The first thread is put into a suspended state, and the CPU resources occupied by the first thread are released. The first thread is the thread that sent the descriptor. The device receives a first signal sent by the target hardware, the first signal being used to indicate that the plaintext data corresponding to the ciphertext data to be decrypted has been sent to the target device. The first thread is released from suspension based on the first signal.

[0013] Thirdly, embodiments of this application provide a hardware-isolated decryption device applied to target hardware, the device comprising: The first receiving module is used to receive a descriptor sent by the host. The descriptor includes a routing label and a key handle index. The routing label is used to determine the target device. A determination module is used to determine the key corresponding to the key handle index. The target hardware has a first area that stores the key in advance, and the first area is an area that is inaccessible to the host. The first sending module is used to send a request to the host to obtain encrypted data; The second receiving module is used to receive the ciphertext data to be decrypted sent by the host, and decrypt the ciphertext data to be decrypted according to the key to obtain plaintext data corresponding to the ciphertext data to be decrypted. The second sending module is used to send the plaintext data to the target device.

[0014] Fourthly, embodiments of this application provide a hardware-isolated decryption device applied to a host, the device comprising: The first sending module is used to send a descriptor to the target hardware. The descriptor includes a routing label and a key handle index. The routing label is used to identify the target device. A receiving module is used to receive a request for obtaining encrypted data sent by the target hardware; The second sending module is used to send the encrypted data to be decrypted to the target hardware.

[0015] Fifthly, embodiments of this application provide an electronic device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps in the hardware-isolated decryption method as described in the first aspect or the second aspect.

[0016] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing a program or instructions that, when executed by a processor, implement the steps in the hardware-isolated decryption method as described in the first or second aspect.

[0017] In a seventh aspect, embodiments of this application provide a computer program product, including computer instructions that, when executed by a processor, implement the steps in the hardware-isolated decryption method as described in the first or second aspect.

[0018] In this embodiment, a host sends a descriptor, which includes a routing label and a key handle index. The routing label is used to identify the target device. The host then determines the key corresponding to the key handle index. The target hardware has a first area pre-stored with the key, and this first area is inaccessible to the host. A request to acquire encrypted data is sent to the host. The host sends encrypted data to be decrypted, and the encrypted data is decrypted using the key to obtain plaintext data corresponding to the encrypted data. The plaintext data is then sent to the target device. Because the host sends a descriptor including a routing label and a key handle index, the host only needs to access the encrypted data to be decrypted and the key handle index. The target hardware determines the key based on the key handle index and, after decrypting the plaintext data, directly sends the plaintext data to the target device, avoiding contact between the host and the plaintext data and the key, thereby reducing the risk of data leakage. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating a hardware-isolated decryption method provided in an embodiment of this application; Figure 2 An architecture diagram between target hardware and host provided in an embodiment of this application; Figure 3 A flowchart illustrating a target address verification method provided in this application embodiment; Figure 4 A flowchart illustrating a key deletion method provided in this application embodiment; Figure 5 A flowchart illustrating another hardware-isolated decryption method provided in this application embodiment; Figure 6 Another architecture diagram between target hardware and host provided in this application embodiment; Figure 7 A timing diagram of a hardware-isolated decryption method provided in an embodiment of this application; Figure 8 This is a structural diagram of a hardware-isolated decryption device provided in an embodiment of this application; Figure 9 This is a structural diagram of another hardware-isolated decryption device provided in an embodiment of this application; Figure 10 This is a structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0022] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, and the number of objects is not limited; for example, the first object can be one or more.

[0023] In this application embodiment, a decryption method, apparatus and electronic device based on hardware isolation are proposed to solve the problem of easy data leakage in related technologies.

[0024] See Figure 1 , Figure 1 This is a flowchart of a hardware-isolated decryption method provided in an embodiment of this application. The method is applied to target hardware and includes the following steps: Step 101: Receive a descriptor sent by the host. The descriptor includes a routing label and a key handle index. The routing label is used to determine the target device.

[0025] The target hardware mentioned above can be a device with a microcontroller unit (MCU), such as a dongle or a USB flash drive. The host mentioned above can be a local computer or server, or a cloud computer, such as a virtual machine or cloud host. Hardware isolation can refer to the forced separation of some data from the general computing environment (such as an operating system) through physical or circuit-level hardware methods.

[0026] In this embodiment, the host and the target hardware can be connected via an external interface, thereby achieving physical isolation between the host and the target hardware. Data interaction between the host and the target hardware must follow a preset protocol. The descriptor sent by the host can be a descriptor sent via the CPU, or the host can send the address of the descriptor in the host memory to the target hardware, and the target hardware can directly retrieve it from the host memory based on the address of the descriptor in the host memory. It should be noted that the host does not store the key; therefore, the descriptor sent includes the key handle index. However, this does not include the key itself.

[0027] It is understood that the descriptor may also include the host's identity and authorization information, so that the target hardware can verify the host's identity and access permissions, avoiding abuse of host permissions or attacks. The descriptor may also include the length information of the ciphertext to be decrypted, encryption algorithm information, or cryptographic initialization vector, providing basic information for subsequent decryption steps.

[0028] Step 102: Determine the key corresponding to the key handle index. The target hardware has a first area that stores the key in advance, and the first area is an area that is inaccessible to the host.

[0029] In this embodiment, the target hardware has a first area inaccessible to the host, and the first area stores the key. The target hardware can determine the corresponding key based on the received key handle index. This eliminates the need to receive keys from a host or network, thus preventing the host from accessing the keys or attackers from obtaining them through network eavesdropping. For example, the target hardware can store multiple keys and a table mapping keys to key handle indices. The target hardware looks up the received key handle index in the table to determine the corresponding key and extracts it for subsequent decryption.

[0030] It is understood that the first region may also include a key storage area, which is specifically used to store multiple keys and the first correspondence between each key and the key handle index; after the key is determined according to the key handle index, the key can be loaded into the area of ​​the first region other than the key storage area for subsequent decryption.

[0031] Step 103: Send a request to the host to retrieve encrypted data.

[0032] In this embodiment of the application, after the target hardware determines the key based on the key handle index, the target hardware can initiate a ciphertext data acquisition request to the host and actively pull the ciphertext data to be decrypted.

[0033] Step 104: Receive the ciphertext data to be decrypted sent by the host, and decrypt the ciphertext data to be decrypted according to the key to obtain the plaintext data corresponding to the ciphertext data to be decrypted.

[0034] Step 105: Send the plaintext data to the target device.

[0035] In this embodiment of the application, after the target hardware decrypts and obtains the plaintext data, it can directly send the plaintext data to the target device without returning the plaintext data to the host, thus avoiding the transmission of plaintext data from the host to the target device and thereby avoiding contact between the host and the plaintext data.

[0036] In this embodiment, since the descriptor sent by the host includes a routing label and a key handle index, the host only needs to access the ciphertext data to be decrypted and the key handle index. The target hardware determines the key based on the key handle index and, after decrypting the plaintext data, directly sends the plaintext data to the target device, thus avoiding contact between the host and the plaintext data and the key, thereby solving the problem of easy data leakage in related technologies.

[0037] Optionally, the descriptor may further include the source physical address of the ciphertext data to be decrypted; The ciphertext data retrieval request includes the source physical address of the ciphertext data to be decrypted.

[0038] In this implementation, the host only sends the source physical address of the ciphertext data to be decrypted to the target hardware, without sending the ciphertext data itself. This provides a buffer for the target hardware to verify the host's identity and permissions. Only after successful verification does the target hardware actively request the ciphertext data from the host based on its source physical address. If verification fails, the ciphertext data is no longer transmitted, saving resources. Furthermore, having the target hardware actively request the ciphertext data instead of having it pushed by the host also reduces the host's memory or CPU resource consumption.

[0039] Optionally, the target hardware has a first area storing a first correspondence between routing labels and target addresses, wherein the routing label is the logical address of the target device and the target address is the physical address of the target device; Sending the plaintext data to the target device includes: The target address is determined based on the routing label and the first correspondence, and the plaintext data is sent to the target address.

[0040] In this embodiment, the target hardware has a first area inaccessible to the host, which stores a first correspondence between routing labels and target addresses. The routing label is the logical address of the target device. Neither the host nor the target hardware can directly operate on the data in the target device through its logical address; operation on the data in the target device is only possible through its physical address. Therefore, the host only holds the routing label, and the first correspondence between the routing label and the target address is stored in the first inaccessible area, preventing the host from obtaining the physical address of the target device. This avoids the host directly obtaining decrypted plaintext data from the target device. The first correspondence can be a table of correspondences between routing labels and target addresses.

[0041] For example, by setting a first area in the target hardware that is inaccessible to the host, the hardware-level bridging logic between the host and the target hardware can be configured to execute asymmetric mapping rules, which can be expressed by the following formula: , Where addr is the address variable from which the host initiates the access. This refers to the memory space accessible to the host. This is an address translation function for the target hardware, used to translate the address initiated by the host into an address within the target hardware. This refers to the physical address range of the first region. This means that any address `addr` accessible to the host, after being translated by the target hardware's address translation function, is prohibited from falling within the physical address range of the first region in the target hardware. This ensures that, regardless of whether it's through standard memory access instructions or attacks controlled by the attacker, the host cannot access or read the first region of the target hardware, achieving hardware-level isolation between the host and the first region of the target hardware.

[0042] For example, see Figure 2 , Figure 2This application provides an architecture diagram of target hardware and a host, wherein the target hardware is internally divided into a first region and an interaction region. The physical address of the first region is not mapped to the host; isolation between the host and the first region of the target hardware can be achieved through a unidirectional data isolation gateway or an asymmetric mapping bridge. The physical address of the interaction region can be mapped to the host, allowing the host to issue instructions and input encrypted data. The base address register (BAR) space mapped to the interaction region is... In the diagram, the host address space refers to the area accessible to the host. Any address in the host address space, after being translated by the target hardware's address translation function, yields a corresponding address in the target hardware's Peripheral Component Interconnect Express (PCIe) Base Address Register (BAR) mapping area, generating a bus transaction conforming to preset rules. After further judgment by the internal isolation bus, if the translated address is within the interactive area, the mapping is successful, and the host can successfully access it; if the translated address is within the first area, the mapping fails, and the host cannot complete the access.

[0043] For example, the interaction area may include a high-speed bus endpoint controller such as a PCIe Endpoint, a configuration register array, a built-in multichannel Direct Memory Access (DMA) controller, and input First-In First-Out (FIFO) and output FIFO for data stream buffering; the configuration register array may include a doorbell register and a status register, and the physical address space of this area is mapped to an external host, allowing the host to issue instructions and pump in encrypted data. The first region may include an internal secure master controller (MCU), a protected key storage medium, an independent hardware decryption engine, an environmental monitoring sensor array, an independent security watchdog, and secure random access memory (RAM). For example, the protected key storage medium may be an electronic fuse (eFuse) bound using physically unclonable function (PUF) technology or built-in secure flash memory (Flash). The independent hardware decryption engine may support hardware pipelines for symmetric cryptographic algorithms such as Advanced Encryption Standard (AES) or SM4 Block Cipher (SM4).

[0044] Optionally, the descriptor further includes an authorization token, which is used to determine whether the host is an authorized entity; Determining the key corresponding to the key handle index includes: Within the first region, the message authentication code is calculated by performing a message authentication code operation on the key handle index based on the verification key stored in the first region, and the first authentication code is obtained. If the authorization token is the same as the first authentication code, the key corresponding to the key handle index is determined according to the key handle index; If the authorization token is different from the first authentication code, delete the key.

[0045] In this embodiment, the authorization token contains the host's identity and authorization information. Before determining the key, it can be verified whether the host is an authorized entity to prevent unauthorized decryption of the encrypted data. This verification operation can be performed in the first area, where the verification key is stored. In this embodiment, the verification key can be directly used to perform message authentication code calculation on the key handle index; alternatively, the verification key can be used as the master key to generate a temporary verification key, which is then used to perform message authentication code calculation on the key handle index. The resulting first authentication code is then compared with the authorization token. Compare them.

[0046] For example, when the host initiates a decryption task, it does not send the plaintext key through any connection, but instead writes the key handle index and dynamic authorization token to the configuration register of the interaction area. After the MCU in the first area completes hardware-level hash comparison and security verification, it directly extracts the plaintext key from the key storage medium and loads it into the secure RAM for use by the hardware decryption engine.

[0047] This can be understood as performing a message authentication code operation on the key handle index, or performing a message authentication code operation on a combination of the key handle index and the routing label fields to obtain the first authentication code. This can also verify whether the target device receiving plaintext data is an authorized device. It can also be understood that the descriptor may include information such as a random number, timestamp, the source physical address of the ciphertext data to be decrypted, and the data length of the ciphertext data to be decrypted. Therefore, performing a message authentication code operation on the key handle index can also be performing a message authentication code operation on a combination of the key handle index, random number, timestamp, source physical address of the ciphertext data to be decrypted, the data length of the ciphertext data to be decrypted, and the routing label fields to obtain the first authentication code. This can also achieve effects such as replay protection and integrity verification.

[0048] In the event of a verification failure, the key stored in the first area can also be deleted. For example, the key can be deleted by repeatedly overwriting the first area with hardware-generated random data (such as all 1s, all 0s, or random bits), or by the target hardware forcibly seizing control of the memory bus and directly issuing an erase command to the first area in the event of a system malfunction (such as a system crash or software blocking erasure), or by generating an abnormal level to bypass the software logic and trigger the self-destruct circuit of the target hardware.

[0049] Optionally, before sending the plaintext data to the target address, the method further includes: The end address is determined based on the target address and the length of the plaintext data; the end address is the last address corresponding to the continuous storage of the plaintext data in the target device, starting from the target address. Determine whether both the target address and the end address are within a preset trusted range; If the target address or the end address is not within a preset trusted range, delete the plaintext data and the key.

[0050] It is understandable that the target device corresponding to the routing label sent by the host may be an untrusted device, meaning that the target device may leak plaintext data. This is especially true when the host is a cloud-based host, as it is prone to sending routing labels corresponding to untrusted devices to the target hardware.

[0051] Therefore, to ensure that the decrypted plaintext data is not intercepted by the host system, a hardware-level routing control and address forced verification mechanism is adopted during the plaintext output stage. In this implementation, after determining the target address based on the routing label, the target address can be verified to determine whether it is a trusted address. If it is not a trusted address, the plaintext data and the key are deleted. For example, see... Figure 3 , Figure 3 A flowchart of a target address verification method provided in this application embodiment includes the following steps: Step 301: Obtain the route label.

[0052] Step 302: Query the first correspondence between the route label and the destination address.

[0053] The first correspondence between the routing label and the destination address is stored in a first area, which is an area in the target hardware that is inaccessible to the host. The destination address may be the starting address of the storage area in the target device.

[0054] For example, within the first physically isolated zone, a hardware-level routing whitelist table (RWT) is pre-configured. This table lists logical route labels. The logical routing label is hard-coded and mapped to the base address of a trusted physical target device within the system (i.e., the aforementioned starting address). When the host issues a decryption task, it can only transmit the logical routing label. Before outputting plaintext data, the chip's internal DMA controller translates the routing label into the actual physical address through a hardware lookup table. This allows data to be pushed, thereby depriving the host of its ability to directly and absolutely address and tamper with the plaintext data flow. Translation can be based on the following formula: .

[0055] Step 303: Analyze and determine the target address.

[0056] Step 304: Determine whether the target address is an untrusted address and whether an out-of-bounds error will occur.

[0057] Before sending plaintext data, it is determined whether the destination address is within a preset trusted address range, and the ending address is also determined based on information such as the length of the plaintext data to determine whether it is still within the preset trusted address range. An out-of-bounds error occurs when the destination address is within the preset trusted address range, but the ending address is not, resulting in some plaintext data being exposed to areas accessible to the host, causing data leakage.

[0058] Step 3041: If the target address is in an untrusted address region or an out-of-bounds error occurs, the target hardware deletes the plaintext data and key.

[0059] If the target address is in an untrusted address area or an out-of-bounds error occurs, it means that the plaintext data may be leaked. This decryption may be initiated by an attacker. To avoid data leakage, both the plaintext data and the key can be deleted.

[0060] Step 3042: If the target address is in a trusted address range or there is no risk of exceeding the boundary, send plaintext data to the target address.

[0061] If the target address is a trusted address range or will not cross the boundary, it means that the plaintext data will not be leaked, and plaintext data can be sent to the target address.

[0062] For example, in a scenario where plaintext data must be output to a trusted area of ​​a shared bus, a hardware address boundary checker is deployed in series in the output control logic. Let the boundary of this trusted area be... The plaintext data has a length of Data_Len. Before each bus write transaction, the DMA controller must perform the following logical checks:

[0063] , Among them, Trigger_Action refers to triggering a handling action, Drop_Plaintext refers to discarding plaintext data, raise_NMI refers to triggering a non-maskable interrupt (NMI), and Execute_Zeroization refers to performing a zeroing operation. If it is determined that the write address is out of bounds or points to an untrusted region, the address boundary checker can directly physically truncate the output data stream inside the chip within nanoseconds, directly discard the plaintext data in the output FIFO, and trigger the highest priority interrupt and key emergency destruction process.

[0064] Optionally, the method further includes deleting the key in any of the following cases: Complete the decryption of the encrypted data; The temperature change of the target hardware exceeds a preset threshold. The voltage change of the target hardware exceeds a preset threshold; The clock frequency of the target hardware changes beyond a preset threshold; The timer starts counting from the moment the host sends the descriptor, and the preset time period expires.

[0065] In this embodiment, to further prevent key leakage, the key can also be deleted under preset conditions. For example, the key can be deleted by repeatedly overwriting the first area with hardware-generated random data (such as all 1s, all 0s, or random bits), or by forcibly seizing control of the memory bus and directly issuing an erase command to the first area in the event of system abnormalities (such as system crashes or software blocking erasure), or by generating abnormal levels to bypass software logic and trigger the self-destruct circuit of the target hardware.

[0066] See Figure 4 , Figure 4 This is a flowchart illustrating a key deletion method provided in an embodiment of this application. The target hardware initially enters an idle waiting state. When the host triggers the doorbell register of the target hardware, the target hardware enters the identity and authorization verification stage. If verification fails, it returns to the idle waiting state. If verification succeeds, it enters the decryption stage to decrypt the ciphertext data to be decrypted; after decrypting the last data block of the ciphertext data to be decrypted, it enters the key deletion stage.

[0067] Furthermore, if a watchdog timeout occurs during the identity and authorization verification phase, or if an attack is detected by the sensor during the idle waiting state, the system will enter the key deletion phase. The watchdog can refer to an independent hardware timer within the target hardware, which starts counting when the doorbell is triggered. If no verification success or failure result is returned after a preset time, it is determined that the watchdog has timed out. The sensor can refer to a continuously monitoring sensor installed on the target hardware. If the sensor detects that parameters of the target hardware (such as core voltage, clock frequency, or temperature) exceed a preset threshold, it indicates that an attack is targeting the target hardware.

[0068] For example, a hardware-level key instantaneous erasure (Zeroization) mechanism triggered by multiple conditions can be designed within the physically isolated first region. Its triggering logic can be expressed by the following formula: .

[0069] in, This indicates that the state machine has received a completion signal. Indicates an environmental alarm signal. This indicates a watchdog timeout signal. This indicates the flow path that jumps to the destruction state.

[0070] In the case where the state machine actively destroys itself upon receiving a completion signal, this can be achieved through a counter built into the hardware decryption engine, generated within a single system clock cycle after the output of the last plaintext data block (End of File). The triggering of the zeroing signal in the secure RAM allows the use of a hardware-level pseudo-random number generator (PRNG) to overwrite the memory block storing the key in plaintext form, thus eliminating data residue.

[0071] When environmental alarm signals are detected by environmental monitoring, the core voltage can be monitored in real time by an internally integrated sensor array. Clock frequency With chip temperature If any parameter exceeds the safety threshold, the sensor will generate an abnormal level, bypassing all software logic and directly triggering the hardware self-destruct circuit. This achieves physical destruction by cutting off the power supply to the safety RAM or forcibly pulling the storage cell level low. The parameter determination can be expressed by the following formula: , Where [V] min V max [F] represents the preset core voltage range. min ,F max [T] represents the preset clock frequency range. max This is the preset upper limit for chip temperature.

[0072] To prevent watchdog timeout and trigger anti-suspend destruction, if the watchdog timeout occurs and the state machine does not return a completion signal, a separate hardware watchdog timer is generated. This allows for forced takeover of the bus and execution of a key erasure process for secure RAM, proactively defending against attempts by hackers to exploit bus deadlock for side-channel attacks. For example, it can be used... Indicates the start time of the decryption task. Indicates the current time, indicates The maximum safety tolerance time, and the watchdog timeout determination, can be expressed by the following formula: .

[0073] See Figure 5 , Figure 5 A flowchart of another hardware-isolated decryption method provided in this application embodiment, applied to a host, the method includes the following steps: Step 501: Send a descriptor to the target hardware. The descriptor includes a routing label and a key handle index. The routing label is used to identify the target device.

[0074] In this embodiment, the host and the target hardware can be in the same device or in different devices connected via an external interface. The descriptor sent by the host can be a descriptor sent from the host memory or a descriptor sent from the host CPU. It should be noted that the descriptor sent by the host includes a key handle index, not the key itself.

[0075] It is understood that the descriptor may also include the host's identity and authorization information, so that the target hardware can verify the host's identity and access permissions, avoiding abuse of host permissions or attacks. The descriptor may also include the length information of the ciphertext to be decrypted, encryption algorithm information, or cryptographic initialization vector, providing basic information for subsequent decryption steps.

[0076] Step 502: Receive the encrypted data acquisition request sent by the target hardware.

[0077] In this embodiment of the application, the host may not directly send the encrypted data to be decrypted to the target hardware, but instead wait to receive the encrypted data acquisition request initiated by the target hardware.

[0078] Step 503: Send the encrypted data to be decrypted to the target hardware.

[0079] Understandably, after receiving the encrypted data retrieval request sent by the target hardware, the host sends the encrypted data to be decrypted to the target hardware in accordance with the encrypted data retrieval request.

[0080] In this embodiment, the host only accesses the ciphertext data to be decrypted and the key handle index, avoiding contact between the host and the plaintext data and the key, thereby solving the problem of easy data leakage in related technologies.

[0081] Optionally, the descriptor may further include the source physical address of the ciphertext data to be decrypted; The ciphertext data retrieval request includes the source physical address of the ciphertext data to be decrypted.

[0082] In this embodiment, the host only sends the source physical address of the ciphertext data to be decrypted to the target hardware, without sending the ciphertext data itself, thus providing a buffer for the target hardware to verify the host's identity and permissions. Only after successful verification does the host send the ciphertext data to be decrypted based on the target hardware's ciphertext data retrieval request; if verification fails, the ciphertext data is no longer transmitted, saving resources. Furthermore, having the target hardware retrieve the ciphertext data instead of pushing it from the host also reduces the host's memory or CPU resource consumption.

[0083] Optionally, after sending the descriptor to the target hardware, the method further includes: The first thread is put into a suspended state, and the CPU resources occupied by the first thread are released. The first thread is the thread that sent the descriptor. The device receives a first signal sent by the target hardware, the first signal being used to indicate that the plaintext data corresponding to the ciphertext data to be decrypted has been sent to the target device. The first thread is released from suspension based on the first signal.

[0084] In this embodiment, after sending the descriptor to the target hardware, the host no longer continuously queries the target hardware for processing results. Instead, it suspends the first thread, thereby reducing the host system load. The first thread is the thread corresponding to sending the descriptor, i.e., the thread corresponding to the task of decrypting the ciphertext data to be decrypted. When the first thread is suspended, the CPU resources occupied by the first thread are released. After the target hardware completes processing, the host receives a first signal sent by the target hardware and releases the first thread from suspension based on the first signal, allowing the first thread to continue subsequent processing.

[0085] See Figure 6 , Figure 6 This is another architecture diagram between the target hardware and the host provided in an embodiment of this application. The host includes host memory and a host CPU. The host memory can be used to store encrypted data and descriptors, and the host CPU can be used to execute scheduling functions. The target hardware includes a FIFO unit and a built-in DMA in the external interaction area, as well as a main control MCU, a decryption engine, and a first area.

[0086] like Figure 6 As shown, the host CPU triggers the doorbell register of the target hardware via the PCIe bus. The target hardware's built-in DMA retrieves a descriptor containing identity and authorization information from the host memory via the PCIe bus. The host MCU verifies the host's identity and authorization. After successful verification, the host MCU determines the key corresponding to the key handle index in the descriptor in the first area. The DMA then retrieves the encrypted data from the host memory via the PCIe bus. The encrypted data is input to the decryption engine through the input FIFO unit. The first area loads the key into the decryption engine. The decryption engine decrypts the encrypted data according to the key and sends the resulting plaintext data to the target device (such as an encrypted network card or video memory) through the output FIFO unit.

[0087] This solution refactors the existing host-key and ciphertext distribution-hardware decryption-plaintext return architecture into a new architecture where the host only configures routing labels and descriptors, the hardware independently extracts the key using built-in authentication, the hardware pulls and decrypts the ciphertext, and the hardware directly pushes the plaintext to the destination device. Throughout this process, the host becomes a bypass scheduler responsible only for issuing commands, while the plaintext key and plaintext data are confined to the hardware-level data path.

[0088] See Figure 7 , Figure 7 A timing diagram of a hardware-isolated decryption method provided in this application embodiment includes the following steps: Step 701: Configure the descriptor. The host CPU constructs a composite descriptor data structure in the host system memory. Its bit field definition may include: the physical address of the source of the ciphertext stream to be decrypted. Routing labels Data length Security control words Key handle index Dynamic authorization token or cryptographic initialization vector The security control word is used to define encryption algorithms and modes such as the 256-bit Advanced Encryption Standard-256-GCM (AES-256-GCM).

[0089] Step 702: Trigger the doorbell. The host CPU writes the starting address of the descriptor in the host memory to the doorbell register in the target hardware's interactive area. This write operation generates a hardware pulse, triggering an internal interrupt in the target hardware, thereby triggering the target hardware to start. This causes the DMA controller to request the descriptor from the host memory based on the descriptor's starting address. After sending the descriptor's starting address, the host suspends the corresponding first thread and releases CPU resources, waiting for the target hardware's processing result, entering an asynchronous waiting state.

[0090] Step 703: Verify host identity and permissions. After receiving the doorbell event, the DMA controller initiates a continuous burst read via the PCIe bus based on the starting address of the descriptor. It reads the complete descriptor, captures it, and sends it to the physically isolated security domain (i.e., the aforementioned first area). It then transmits the key handle index and authorization token from the descriptor to the MCU. The MCU verifies the authorization token. For example, it can perform cryptographic verification based on challenge-response or hash-based message authentication code (HMAC), according to the following formula: , Where Verify is the verification function. For authorization tokens, HMAC is a hash verification with a key. Here, `||` is the key handle index, `Nonce` is a random number, and `Master_Key` is the key pre-stored in the first area for verifying authorization information. It's understandable that after the key handle index and the random number, fields such as timestamps, the source physical address of the ciphertext data to be decrypted, data length, or routing tags can be appended to improve the reliability of the verification.

[0091] After successful verification, the MCU indexes the key handle. Retrieve the real plaintext key from the key storage medium It is then loaded into secure RAM. If verification fails, the process terminates.

[0092] Step 704: Request the ciphertext data to be decrypted. After successful verification, the DMA controller can retrieve the ciphertext data based on its source physical address. and data length information The decryption engine continuously pulls the ciphertext data to be decrypted into the input FIFO unit at the target hardware's maximum payload size. The decryption engine then extracts the ciphertext data from the FIFO unit using the key stored in secure RAM. and cryptographic initialization vector Multi-stage pipelined decryption calculations are performed to obtain plaintext data.

[0093] Step 7051: Plaintext Data Output. The decryption engine sends the processed plaintext data to the output FIFO unit. The output control logic is based on the routing label. The absolute physical address (i.e., the aforementioned target address) is obtained by consulting the first mapping relationship RWT and a boundary check is performed. After the check passes, the DMA controller directly pushes the plaintext data to the designated secure hardware interface in blind output mode.

[0094] Step 7052: Write back the status and delete the key. After all data is cleared and the push confirmation is received, the DMA writes back the status word to the preset completion ring in the host memory and triggers a PCIe extended message signal interrupt (MSI-X) to asynchronously wake up the host CPU to complete the subsequent logic.

[0095] Understandably, if the preset conditions in the aforementioned key deletion method occur during the decryption process, the key deletion process will be initiated.

[0096] See Figure 8 This application provides a hardware-isolated decryption device 80, applied to target hardware, the device comprising: The first receiving module 801 is used to receive a descriptor sent by the host. The descriptor includes a routing label and a key handle index. The routing label is used to determine the target device. The determination module 802 is used to determine the key corresponding to the key handle index. The target hardware has a first area that stores the key in advance, and the first area is an area that is inaccessible to the host. The first sending module 803 is used to send a request to the host to obtain encrypted data; The second receiving module 804 is used to receive the ciphertext data to be decrypted sent by the host, and decrypt the ciphertext data to be decrypted according to the key to obtain plaintext data corresponding to the ciphertext data to be decrypted. The second sending module 805 is used to send the plaintext data to the target device.

[0097] Optionally, the descriptor may further include the source physical address of the ciphertext data to be decrypted; The ciphertext data retrieval request includes the source physical address of the ciphertext data to be decrypted.

[0098] Optionally, the target hardware has a first area storing a first correspondence between routing labels and target addresses, wherein the routing label is the logical address of the target device and the target address is the physical address of the target device; The second sending module 805 is also used for: The target address is determined based on the routing label and the first correspondence, and the plaintext data is sent to the target address.

[0099] Optionally, the descriptor further includes an authorization token, which is used to determine whether the host is an authorized entity; the determining module 802 is further used to: Within the first region, the message authentication code is calculated by performing a message authentication code operation on the key handle index based on the verification key stored in the first region, and the first authentication code is obtained. If the authorization token is the same as the first authentication code, the key corresponding to the key handle index is determined according to the key handle index; If the authorization token is different from the first authentication code, delete the key.

[0100] Optionally, the second transmitting module 805 is further configured to: The end address is determined based on the target address and the length of the plaintext data; the end address is the last address corresponding to the continuous storage of the plaintext data in the target device, starting from the target address. Determine whether both the target address and the end address are within a preset trusted range; If the target address or the end address is not within a preset trusted range, delete the plaintext data and the key.

[0101] Optionally, the device further includes: The deletion module is used to delete the key in any of the following situations: Complete the decryption of the encrypted data; The temperature change of the target hardware exceeds a preset threshold. The voltage change of the target hardware exceeds a preset threshold; The clock frequency of the target hardware changes beyond a preset threshold; The timer starts counting from the moment the host sends the descriptor, and the preset time period expires.

[0102] The hardware-isolated decryption device 80 provided in this application embodiment can implement all the processes implemented in the above-described hardware-isolated decryption method embodiment and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0103] See Figure 9 This application provides another hardware-isolated decryption device 90, applied to a host, the device comprising: The first sending module 901 is used to send a descriptor to the target hardware. The descriptor includes a routing label and a key handle index. The routing label is used to identify the target device. The first receiving module 902 is used to receive the encrypted data acquisition request sent by the target hardware; The second sending module 903 is used to send the encrypted data to be decrypted to the target hardware.

[0104] Optionally, the descriptor may further include the source physical address of the ciphertext data to be decrypted; The ciphertext data retrieval request includes the source physical address of the ciphertext data to be decrypted.

[0105] Optionally, the hardware-isolated decryption device 90 further includes: The adjustment module is used to adjust the first thread to a suspended state and release the central processing unit resources occupied by the first thread, wherein the first thread is the thread corresponding to the one that sent the descriptor. The second receiving module is used to receive a first signal sent by the target hardware, the first signal being used to indicate that the plaintext data corresponding to the ciphertext data to be decrypted has been sent to the target device. The release module is used to release the suspended state of the first thread based on the first signal.

[0106] The hardware-isolated decryption device 90 provided in this application embodiment can implement all the processes implemented in the above-described hardware-isolated decryption method embodiment and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0107] See Figure 10 This application provides an electronic device 100, including a processor 1001, a memory 1002, and a program or instructions stored in the memory 1002 and executable on the processor 1001. When the program or instructions are executed by the processor 1001, they implement the various processes of the above-described hardware-isolated decryption method and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0108] This application also provides a computer-readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the embodiments of the hardware-isolated decryption method described above, and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0109] This application also provides a computer program product, including computer instructions. When the computer instructions are executed by a processor, they implement the various processes of the embodiments of the hardware-isolated decryption method described above, and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0110] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0111] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0112] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A decryption method based on hardware isolation, characterized in that, Applied to target hardware, including: The receiving host sends a descriptor, which includes a routing label and a key handle index, wherein the routing label is used to determine the target device; The key corresponding to the key handle index is determined. The target hardware has a first area that stores the key in advance, and the first area is an area that is inaccessible to the host. Send a request to the host to retrieve encrypted data; The system receives ciphertext data to be decrypted from the host and decrypts the ciphertext data to be decrypted according to the key to obtain plaintext data corresponding to the ciphertext data to be decrypted. Send the plaintext data to the target device.

2. The method according to claim 1, characterized in that, The descriptor also includes the source physical address of the ciphertext data to be decrypted; The ciphertext data retrieval request includes the source physical address of the ciphertext data to be decrypted.

3. The method according to claim 1 or 2, characterized in that, The target hardware has a first area storing a first correspondence between routing labels and target addresses, wherein the routing label is the logical address of the target device and the target address is the physical address of the target device; Sending the plaintext data to the target device includes: The target address is determined based on the routing label and the first correspondence, and the plaintext data is sent to the target address.

4. The method according to claim 3, characterized in that, The descriptor also includes an authorization token, which is used to determine whether the host is an authorized entity; Determining the key corresponding to the key handle index includes: Within the first region, the message authentication code is calculated by performing a message authentication code operation on the key handle index based on the verification key stored in the first region, and the first authentication code is obtained. If the authorization token is the same as the first authentication code, the key corresponding to the key handle index is determined according to the key handle index; If the authorization token is different from the first authentication code, delete the key.

5. The method according to claim 3, characterized in that, Before sending the plaintext data to the target address, the method further includes: The end address is determined based on the target address and the length of the plaintext data; the end address is the last address corresponding to the continuous storage of the plaintext data in the target device, starting from the target address. Determine whether both the target address and the end address are within a preset trusted range; If the target address or the end address is not within a preset trusted range, delete the plaintext data and the key.

6. The method according to claim 1, characterized in that, The method further includes deleting the key in any of the following cases: Complete the decryption of the encrypted data; The temperature change of the target hardware exceeds a preset threshold. The voltage change of the target hardware exceeds a preset threshold; The clock frequency of the target hardware changes beyond a preset threshold; The timer starts counting from the moment the host sends the descriptor, and the preset time period expires.

7. A decryption method based on hardware isolation, characterized in that, Applied to the host, including: Send a descriptor to the target hardware, the descriptor including a routing label and a key handle index, the routing label being used to identify the target device; Receive the encrypted data acquisition request sent by the target hardware; Send the encrypted data to be decrypted to the target hardware.

8. The method according to claim 7, characterized in that, The descriptor also includes the source physical address of the ciphertext data to be decrypted; The ciphertext data retrieval request includes the source physical address of the ciphertext data to be decrypted.

9. The method according to claim 7 or 8, characterized in that, After sending the descriptor to the target hardware, the method further includes: The first thread is put into a suspended state, and the CPU resources occupied by the first thread are released. The first thread is the thread that sent the descriptor. The device receives a first signal sent by the target hardware, the first signal being used to indicate that the plaintext data corresponding to the ciphertext data to be decrypted has been sent to the target device. The first thread is released from suspension based on the first signal.

10. A decryption device based on hardware isolation, characterized in that, Applied to target hardware, the device includes: The first receiving module is used to receive a descriptor sent by the host. The descriptor includes a routing label and a key handle index. The routing label is used to determine the target device. A determination module is used to determine the key corresponding to the key handle index. The target hardware has a first area that stores the key in advance, and the first area is an area that is inaccessible to the host. The first sending module is used to send a request to the host to obtain encrypted data; The second receiving module is used to receive the ciphertext data to be decrypted sent by the host, and decrypt the ciphertext data to be decrypted according to the key to obtain plaintext data corresponding to the ciphertext data to be decrypted. The second sending module is used to send the plaintext data to the target device.

11. A decryption device based on hardware isolation, characterized in that, Applied to a host computer, the device includes: The first sending module is used to send a descriptor to the target hardware. The descriptor includes a routing label and a key handle index. The routing label is used to identify the target device. A receiving module is used to receive a request for obtaining encrypted data sent by the target hardware; The second sending module is used to send the encrypted data to be decrypted to the target hardware.

12. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the hardware-isolated decryption method as described in any one of claims 1 to 9.

13. A computer-readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the hardware-isolated decryption method as described in any one of claims 1 to 9.

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