A high-speed communication system between MCUs based on double SPI bus and DMA interrupt

Abstract

The application belongs to the technical field of microcontroller communication, and particularly relates to a high-speed communication system between MCUs based on double SPI buses and DMA interrupts, which establishes two independent SPI communication links between two MCUs, respectively undertakes data transmission in opposite directions, and combines DMA to automatically receive and send data, uses DMA to complete interrupt or full interrupt to realize data frame receiving completion determination, so as to realize high-speed, stable and low-CPU-occupied data communication between the MCUs, can realize efficient and stable frame completion determination by using fixed-length DMA transmission, and can flexibly reconfigure length parameters in subsequent transmission by software, so as to better meet actual engineering application requirements.

Description

Technical Field

[0001] This application belongs to the field of microcontroller communication technology, specifically relating to a high-speed communication system between MCUs based on dual SPI bus and DMA interrupt. Background Technology

[0002] As the complexity of embedded systems continues to increase, system architectures employing multiple MCUs working collaboratively are becoming increasingly common. In applications such as industrial automation, robot control, smart terminals, complex sensor fusion, high-speed data acquisition, and edge computing, it is often necessary for two MCUs to perform different tasks. For example, one MCU might handle low-level control and data acquisition, while the other handles upper-level computation, protocol processing, or external communication. In such systems, frequent and large-volume data exchanges between the two MCUs are often required; therefore, the communication performance between the MCUs directly impacts the overall real-time performance and stability of the system.

[0003] Common communication methods between two MCUs include UART, I2C, CAN, and SPI.

[0004] UART communication is simple to implement, consumes fewer hardware resources, and is suitable for point-to-point low-speed asynchronous communication. UART communication usually has an idle interrupt mechanism, which makes it easy to identify the end of variable-length data frames, but its overall transmission rate is limited, and it can easily become a performance bottleneck in scenarios that require the exchange of large data blocks or have high latency requirements.

[0005] I2C communication is suitable for short-distance, low-speed, multi-device connection scenarios, but it is limited by bus speed and protocol overhead and is not suitable for high-speed transmission of large amounts of data.

[0006] CAN communication has good anti-interference and bus arbitration capabilities, but its protocol payload is small and its frame structure is fixed, making it inefficient for high-throughput data exchange between two MCUs.

[0007] SPI communication offers advantages such as clock synchronization, simple interface, and high transmission rate, making it a popular choice for short-distance, high-speed communication between MCUs. However, traditional SPI communication typically operates on a master-slave architecture, with the communication clock initiated by the master and the slave device responding passively. Directly using this single-channel SPI communication between two MCUs usually suffers from the following drawbacks:

[0008] The communication roles of both parties are unequal, resulting in insufficient flexibility.

[0009] In bidirectional communication, a single-channel SPI typically needs to take turns occupying the bus, which limits its overall efficiency.

[0010] When using DMA to receive data, SPI communication typically lacks a natural frame end determination mechanism similar to UART communication's idle interrupt, making it difficult to identify when a frame of data has been received.

[0011] If the system relies on CPU polling, byte-by-byte processing, or frequent interrupts to participate in sending and receiving, it will result in high CPU usage and affect the real-time performance of the system.

[0012] To reduce the CPU load and improve communication throughput in SPI communication, SPI is currently often combined with DMA. The transmitting end uses DMA to move data to the SPI transmit register, and the receiving end uses DMA to move data from the SPI receive register to the memory buffer. However, in practical applications, the SPI+DMA scheme usually needs to pre-set the expected receive length to accurately determine the completion time of reception. Furthermore, the data length in actual engineering applications is not always fixed; if the length changes, the DMA parameters need to be reconfigured. Therefore, current SPI communication technology still has shortcomings in balancing high-speed transmission, bidirectional communication, low CPU usage, clear determination of reception completion, and flexible length configuration. Especially in some practical scenarios, the data length of a single transmission is usually fixed within a single communication transaction, such as a frame of sampled data, a set of control parameters, an image segment, or a block of buffered synchronization data. For such scenarios, DMA can be used to receive fixed-length data and generate an interrupt upon completion, thus achieving clear frame boundary determination. However, the data transmission length of a single transmission may differ between different task stages, different command types, or different tasks. Therefore, the communication scheme also needs the ability to reset the data transmission length via software.

[0013] In view of the aforementioned technical problems, this application is hereby submitted. Summary of the Invention

[0014] The purpose of this application is to address the problems of low efficiency in single-channel SPI bidirectional communication, insufficient flexibility of traditional master-slave structures, difficulty in determining the completion time of reception in SPI+DMA scenarios, and high CPU usage in current SPI communication methods. It provides a high-speed inter-MCU communication system based on dual SPI buses and DMA interrupts. By establishing two independent SPI communication links between two MCUs, each handling data transmission in opposite directions, and combining this with DMA for automatic data transmission and reception, the system utilizes DMA completion interrupts or full interrupts to determine the completion of data frame reception. This achieves high-speed, stable, and low CPU usage data communication between MCUs. It can achieve efficient and stable frame completion determination using fixed-length DMA transmission, and allows for flexible reconfiguration of length parameters in subsequent transmissions via software, thus better meeting the needs of practical engineering applications.

[0015] The technical solution of this application is:

[0016] 1. A high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt, characterized in that it includes: a first MCU and a second MCU;

[0017] Both the first MCU and the second MCU include a transmit buffer, a DMA transmit module, an SPI transmit interface, an SPI receive interface, a DMA receive module, a receive buffer, an interrupt handling module, and a length configuration module.

[0018] The SPI transmitting interface of the first MCU is connected to the SPI receiving interface of the second MCU through the SPI bus to form the first SPI communication link. In the first SPI communication link, the first MCU is the transmitting end and the second MCU is the receiving end. The SPI transmitting interface of the second MCU is connected to the SPI receiving interface of the first MCU through the SPI bus to form the second SPI communication link. In the second SPI communication link, the second MCU is the transmitting end and the first MCU is the receiving end.

[0019] When sending data, the length configuration module sets the length of the data to be sent, and the data is transferred from the sending buffer to the SPI sending interface via the DMA sending module for transmission.

[0020] During data reception, the length configuration module sets the desired reception length. The data received by the SPI receiving interface is transferred to the receiving buffer by the DMA receiving module. After the data received by the DMA receiving module reaches the desired reception length, the interrupt handling module completes the reception end determination.

[0021] According to at least one embodiment of this application, in the above-described high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt, the SPI bus includes a clock line SCK, a data line MOSI, and a chip select line NSS.

[0022] According to at least one embodiment of this application, in the above-described high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt, the clock signal is generated by the transmitting MCU and output to the receiving MCU.

[0023] According to at least one embodiment of this application, in the above-described high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt, during a single data transmission process:

[0024] The transmitting MCU writes the data to be sent into the transmission buffer and sets the length N of the data to be sent this time through the length configuration module according to the current task requirements. Then, it starts the DMA transmission module to automatically move the data in the transmission buffer to the transmission register of the SPI transmission interface and sends the data to the receive register of the SPI receiving interface of the receiving MCU according to the communication clock.

[0025] The receiving MCU sets the expected receiving length N through the length configuration module and starts the DMA receiving module to automatically transfer the data received by the receiving register of the SPI receiving interface to the receiving buffer until the cumulative received data length reaches the expected receiving length N.

[0026] According to at least one embodiment of this application, in the above-described high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt, during a single data transmission process:

[0027] When the cumulative data length received by the receiving MCU reaches the expected receiving length N, the DMA receiving module triggers a completion interrupt, a DMA full interrupt, or an equivalent interrupt event. The interrupt handling module responds to the interrupt, determines that the data transmission is complete, and performs subsequent processing on the data in the receiving buffer, including data parsing and verification.

[0028] According to at least one embodiment of this application, in the above-described high-speed communication system between MCUs based on dual SPI bus and DMA interrupt, during a data transmission process: DMA automatically triggers a completion interrupt, DMA full interrupt, or an equivalent interrupt event, the receiving MCU enters the interrupt service routine and performs one or more of the following actions: setting the reception completion flag, notifying the upper-layer task that the current frame has been received, switching the reception buffer, and starting the next task processing.

[0029] According to at least one embodiment of this application, in the above-described high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt, when a data transmission hot task is started, the software selects the current task type or data type, sets the data transmission length according to the current task requirements, and the length configuration module sets the length of the data to be sent and the expected length to be received.

[0030] According to at least one embodiment of this application, in the above-described high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt, the task type or data type includes control instructions, status parameters, sampling data, image slices, and cache block synchronization data.

[0031] This application has at least the following beneficial technical effects:

[0032] A high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt is provided, which has the following advantages:

[0033] High bidirectional communication efficiency: Two independent SPI buses are used to handle data transmission in two directions respectively, avoiding the problem of frequent direction switching or bus resource contention when a single SPI needs to transmit and receive bidirectionally, thereby improving bidirectional communication efficiency. It is suitable for large data volume transmission scenarios such as image slicing, sampling data blocks, parameter synchronization data, and buffer mirror data, and can stably achieve high-speed data exchange.

[0034] Low CPU utilization: Data sending and receiving are automatically completed through DMA. The CPU does not need to participate in data sending and receiving byte by byte. It can only intervene in the case of DMA interruption or exception, thus significantly reducing the CPU load.

[0035] Clear determination of reception completion: By using DMA transmission completion interrupt, full interrupt or equivalent event, the determination of the end of a complete data reception can be realized. It can replace the role of traditional serial port idle interrupt in data frame end identification and can solve the problem of frame boundary not being easy to determine in SPI+DMA scenario.

[0036] Supports single fixed-length transmission and flexible software reconfiguration of length: During a single data transmission, a preset fixed length is used, enabling the DMA to complete the transfer according to the predetermined length and accurately trigger the interrupt. This simplifies protocol processing and improves the determinism of receiving completion judgment. Although the length of a single data transmission remains fixed during the transmission, this length is not permanent but can be reconfigured by software before the start of subsequent transmissions. This is applicable not only to fixed-length scenarios but also to application scenarios where the length of a single transmission varies in different task scenarios but the length of each data transmission is predictable.

[0037] The system has a clear structure and is easy to implement in engineering: it is based on common MCU SPI peripherals, DMA controllers and interrupt mechanisms, without the need for additional complex dedicated communication chips. It has the advantages of low hardware cost, clear software implementation and easy deployment and portability.

[0038] Good real-time performance and stability: Through dual-link independent transmission, DMA automatic transfer and interrupt-driven processing mechanism, the latency can be effectively reduced, the uncertainty caused by CPU polling can be reduced, and the real-time performance and operational stability of the system can be improved. Attached Figure Description

[0039] Figure 1 An architecture diagram of a high-speed inter-MCU communication system based on dual SPI buses and DMA interrupts provided in this application embodiment;

[0040] Figure 2 This is a diagram showing the dual SPI bus connection relationship provided in an embodiment of this application;

[0041] Figure 3 A data transmission process diagram provided for an embodiment of this application;

[0042] Figure 4 This application provides a flowchart for determining data reception based on DMA completion interruption in an embodiment of the present application.

[0043] Figure 5 This is a communication flowchart provided for embodiments of the present application, showing a fixed length for a single data transmission and subsequent reconfigurability via software.

[0044] To better illustrate this embodiment, some content in the accompanying drawings may be omitted, enlarged, or reduced. They are for illustrative purposes only and should not be construed as limiting the scope of this application. Detailed Implementation

[0045] To make the technical solution and advantages of this application clearer, the technical solution of this application will be described in a clearer and more complete manner below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of this application, and are only used to explain this application, not to limit this application. It should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, and other related parts can be referred to the general design.

[0046] Furthermore, unless otherwise defined, the technical or scientific terms used in this application description shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The word "comprising" as used in this application description indicates that the concept preceding the word encompasses the concepts listed following the word and their equivalents, without excluding other related concepts.

[0047] Furthermore, the terms indicating location used in the description of this application are only used to indicate relative directions or positional relationships. When the absolute position of the described object changes, its relative positional relationship may also change accordingly. It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation" and "connection" used in the description of this application should be interpreted broadly. For example, a connection can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand its specific meaning in this application according to the specific circumstances.

[0048] A high-speed inter-MCU communication system based on dual SPI bus and DMA interrupts, such as Figure 1 As shown, it includes a first MCU and a second MCU.

[0049] Both the first MCU and the second MCU include a transmit buffer, a DMA transmit module, an SPI transmit interface, an SPI receive interface, a DMA receive module, a receive buffer, an interrupt handling module, and a length configuration module.

[0050] Two independent SPI communication links are established between the first MCU and the second MCU: a first SPI communication link and a second SPI communication link. The first SPI communication link is used for the first MCU to send data to the second MCU, and the second SPI communication link is used for the second MCU to send data to the first MCU. The first and second SPI communication links are in opposite directions and are independent of each other, enabling the two MCUs to exchange data bidirectionally through independent channels, thus forming a high-speed bidirectional communication structure between the MCUs.

[0051] The SPI transmitting interface of the first MCU is connected to the SPI receiving interface of the second MCU through the SPI bus to form the first SPI communication link. In the first SPI communication link, the first MCU is the transmitting end and the second MCU is the receiving end. The SPI transmitting interface of the second MCU is connected to the SPI receiving interface of the first MCU through the SPI bus to form the second SPI communication link. In the second SPI communication link, the second MCU is the transmitting end and the first MCU is the receiving end.

[0052] The first MCU and the second MCU form a bidirectional communication connection through two SPI buses, such as Figure 2 As shown, one SPI bus forms a transmission channel from the first MCU to the second MCU, with the first MCU acting as the current transmitter and the second MCU as the current receiver; the other SPI bus forms a transmission channel from the second MCU to the first MCU, with the second MCU acting as the current transmitter and the first MCU as the current receiver, as shown. Figure 2 As shown.

[0053] Both SPI buses operate in half-duplex mode. Each SPI bus includes a clock line SCK, a data line MOSI, and a chip select line NSS. The clock signal is generated by the transmitting MCU and output to the receiving MCU to complete synchronous transmission.

[0054] Because the two SPI communication links are set up independently, data transmission in both directions can occur simultaneously or separately without switching directions back and forth on the same SPI bus. By physically separating the two SPI communication links, the problem of frequent switching between master / slave roles or transmit / receive directions required in bidirectional communication with a single SPI channel is avoided, which helps improve communication efficiency and system real-time performance.

[0055] Both the first MCU and the second MCU are configured with SPI interfaces and DMA channels corresponding to the sending and receiving directions, respectively, and establish a sending buffer and a receiving buffer. When sending data, the length configuration module sets the length of the data to be sent. The data is transferred from the sending buffer to the SPI sending interface via the DMA sending module for transmission. When receiving data, the length configuration module sets the desired receiving length. The data received by the SPI receiving interface is transferred to the receiving buffer via the DMA receiving module. After the data received by the DMA receiving module reaches the desired receiving length, the interrupt handling module completes the reception end determination.

[0056] During a data transmission process, such as Figure 3 As shown:

[0057] The transmitting MCU writes the data to be sent into the transmission buffer and sets the length N of the data to be sent in this transmission through the length configuration module according to the current task requirements. Then, it starts the DMA transmission module to automatically move the data in the transmission buffer to the transmission register of the SPI transmission interface and sends the data to the receive register of the SPI receive interface of the receiving MCU according to the communication clock.

[0058] The receiving MCU sets the expected receiving length N through the length configuration module and starts the DMA receiving module to automatically transfer the data received by the receiving register of the SPI receiving interface to the receiving buffer until the cumulative received data length reaches the expected receiving length N.

[0059] When the cumulative data length received by the receiving MCU reaches the expected receiving length N, the DMA receiving module triggers a completion interrupt, a DMA full interrupt, or an equivalent interrupt event. The interrupt handling module responds to the interrupt, determines that the data transmission is complete, and performs subsequent processing on the data in the receiving buffer, including data parsing and verification.

[0060] During data transfer, DMA replaces the CPU to complete most of the data transfer work. The CPU only performs result confirmation and upper-level task processing after an interrupt is triggered, which can significantly reduce CPU utilization.

[0061] The DMA completion interrupt is used as the criterion for determining the completion of SPI reception, such as... Figure 4 As shown, firstly, the receiving MCU presets the expected reception length N according to the current data transmission hot task, and then starts SPI reception and DMA reception. The DMA automatically transfers data between the SPI receive register and the receive buffer, and accumulates the received data length in real time. When the accumulated reception quantity has not reached N, the DMA continues to transfer received data. When the accumulated reception quantity reaches N, the DMA automatically triggers a completion interrupt, a DMA full interrupt, or an equivalent interrupt event. After the receiving MCU enters the interrupt service routine, it performs one or more of the following operations:

[0062] Set the receive completion flag;

[0063] Notify the upper-layer task that the current frame has been received;

[0064] Switch the receive buffer;

[0065] Initiate the next task processing.

[0066] The above method does not rely on the idle interrupt of UART communication, but uses DMA completion events to identify whether a data frame has been received. It is particularly suitable for communication scenarios such as SPI, which does not have the ability to determine an idle frame naturally.

[0067] The length of data transmitted in a single data transmission remains fixed during the current communication process. However, this length can be reset by software before the start of subsequent data transmission hot tasks. The setting method is to specify the length of the next frame to be received in the data frame via the SPI bus, or to set it manually according to the task.

[0068] Specifically, when the system starts a new data transmission hot task, the software first selects the current task type or data type, such as control commands, status parameters, sampled data, image slices, or buffer block synchronization data. Then, according to the current task requirements, the data transmission length L is set. The length configuration module sets the length of the data to be sent and the expected length to be received. During this transmission, the length L remains unchanged. Both the sending MCU and the receiving MCU perform DMA transmission and reception according to this fixed length to ensure that the DMA can complete the complete data transfer according to the expected length to be received. When the DMA completes the interrupt and is triggered, the transmission is determined to be over.

[0069] If the system needs to initiate the next data transmission hot task, the software of the first or second MCU can reset the new data transmission length L1 according to the task requirements, reconfigure the DMA send length and DMA receive length, and start a new round of SPI + DMA transmission to adapt to the data transmission length requirements under different task scenarios, such as... Figure 5 As shown, this means that the entire system is not required to have a fixed single length in the long term. Instead, a length configuration method of "fixed for one time and variable between tasks" is adopted to balance the certainty of receiving completion judgment and the flexibility of task application.

[0070] In a specific example, when the first MCU needs to transmit 256 bytes of sampled data to the second MCU, the first MCU configures the length to 256, and the second MCU simultaneously configures its receive length to 256. After the first MCU initiates DMA transmission, the 256 bytes of data are sent to the second MCU via the SP communication I link. The second MCU's DMA triggers a completion interrupt after receiving 256 bytes, thus determining that the frame reception is complete and processing it. The next data transmission hot task becomes transmitting 32 bytes of control information; the software reconfigures the DMA transmit / receive length to 32 and restarts communication.

[0071] It supports dynamic adjustment of data transmission length between different tasks, but the length is fixed for each individual transmission, thus ensuring the deterministic determination of DMA completion interruption. There are two methods to set the data transmission length. The first method is that when the two MCUs perform the first 256-byte transmission task, they have agreed that the next transmission data length will be 32 bytes. The other method is that the 256-byte content to be transmitted includes the next transmission data length of 32 bytes. Switching the data length should not be too frequent.

[0072] The high-speed inter-MCU communication system based on dual SPI buses and DMA interrupts disclosed in the above embodiments improves communication throughput and real-time performance by constructing two independent and opposite-direction SPI buses between the two MCUs. This allows the two MCUs to undertake data transmission and reception tasks through independent channels, making it suitable for bidirectional high-speed communication with large data volumes. DMA is used for data transfer during transmission and reception, reducing the CPU's burden of byte-by-byte data transmission. Furthermore, DMA is used to complete interrupts, full-load interrupts, or equivalent interrupt events, establishing a data frame completion determination mechanism suitable for SPI communication. In addition, a communication mechanism with "fixed single data transmission length and software-reconfigurable data transmission length" is designed. Before each specific data transmission begins, the software presets the length of the data to be transmitted and the expected length to be received, maintaining a fixed length during the transmission process. This allows for accurate determination of the end of the data frame through DMA interrupts. Simultaneously, before subsequent data transmissions begin, the software is allowed to reset the data length according to task requirements, thus balancing efficiency and flexibility.

[0073] The technical solution of this application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. Those skilled in the art should understand that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt, characterized in that, include: First MCU, Second MCU; Both the first MCU and the second MCU include a transmit buffer, a DMA transmit module, an SPI transmit interface, an SPI receive interface, a DMA receive module, a receive buffer, an interrupt handling module, and a length configuration module. The SPI transmitting interface of the first MCU is connected to the SPI receiving interface of the second MCU through the SPI bus to form the first SPI communication link. In the first SPI communication link, the first MCU is the transmitting end and the second MCU is the receiving end. The SPI transmitting interface of the second MCU is connected to the SPI receiving interface of the first MCU through the SPI bus to form the second SPI communication link. In the second SPI communication link, the second MCU is the transmitting end and the first MCU is the receiving end. When sending data, the length configuration module sets the length of the data to be sent, and the data is transferred from the sending buffer to the SPI sending interface via the DMA sending module for transmission. During data reception, the length configuration module sets the desired reception length. The data received by the SPI receiving interface is transferred to the receiving buffer by the DMA receiving module. After the data received by the DMA receiving module reaches the desired reception length, the interrupt handling module completes the reception end determination.

2. The high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt as described in claim 1, characterized in that, The SPI bus includes a clock line SCK, a data line MOSI, and a chip select line NSS.

3. The high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt as described in claim 2, characterized in that, The clock signal is generated by the transmitting MCU and output to the receiving MCU.

4. The high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt as described in claim 3, characterized in that, During a data transmission process: The transmitting MCU writes the data to be sent into the transmission buffer and sets the length N of the data to be sent in this transmission through the length configuration module according to the current task requirements. Then, it starts the DMA transmission module to automatically move the data in the transmission buffer to the transmission register of the SPI transmission interface and sends the data to the receive register of the SPI receive interface of the receiving MCU according to the communication clock. The receiving MCU sets the expected receiving length N through the length configuration module and starts the DMA receiving module to automatically transfer the data received by the receiving register of the SPI receiving interface to the receiving buffer until the cumulative received data length reaches the expected receiving length N.

5. The high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt according to claim 4, characterized in that, During a data transmission process: When the cumulative data length received by the receiving MCU reaches the expected receiving length N, the DMA receiving module triggers a completion interrupt, a DMA full interrupt, or an equivalent interrupt event. The interrupt handling module responds to the interrupt, determines that the data transmission is complete, and performs subsequent processing on the data in the receiving buffer, including data parsing and verification.

6. The high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt according to claim 5, characterized in that, During a data transmission: DMA automatically triggers a completion interrupt, a full DMA interrupt, or an equivalent interrupt event. The receiving MCU enters the interrupt service routine and performs one or more of the following actions: setting the receive completion flag, notifying the upper-layer task that the current frame has been received, switching the receive buffer, and starting the next task processing.

7. The high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt according to claim 6, characterized in that, When a data transmission hot task is started, the software selects the current task type or data type, sets the data transmission length according to the current task requirements, and sets the length of the data to be sent and the expected length to be received in the length configuration module.

8. The high-speed inter-MCU communication system based on dual SPI bus and DMA interrupt according to claim 7, characterized in that, Task types or data types include control commands, status parameters, sampled data, image slices, and cache block synchronization data.

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