A data processing system and method based on application-specific integrated circuit (ASIC) chips

Abstract

This invention discloses a data processing system and method based on a dedicated integrated circuit chip, belonging to the field of integrated circuit thermal management technology. Existing chip thermal management solutions suffer from large response delays or the inability to sense internal thermal gradients, making it difficult to perform real-time and refined management of local hotspots. This system includes a common substrate, a three-dimensional stacked computing chip array, a through-silicon via (TSV) microbump array, a gridded micro temperature sensor array, an on-chip network router, and a hardware thermal management module. When overheating is detected, a back pressure signal is generated and the corresponding routing selection weight is reduced, causing the data flow to bypass the overheated area. This invention couples the substrate thermal physical structure with the on-chip data flow scheduling hardware at the level, enabling real-time perception and adaptive guidance of local hotspots without operating system intervention. It can be used in thermal management scenarios of three-dimensional heterogeneous integrated chips.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit thermal management technology, specifically to a data processing system and method based on a dedicated integrated circuit chip. Background Technology

[0002] As Moore's Law slows down, application-specific integrated circuit (ASIC) data processing systems are increasingly adopting three-dimensional heterogeneous integration technology. This involves vertically stacking and interconnecting multiple functional dies through through-silicon vias (TSVs). Data exchange between computing units occurs via on-chip networks (ISPs). The ISP routers are responsible for addressing, buffering, and forwarding data packets. Existing ISP interconnection protocols typically natively support adaptive routing based on link congestion. When an overload is detected on a link, the router can forward data packets to an alternative path to avoid transmission delays caused by network congestion. However, the aforementioned adaptive routing mechanism only addresses network congestion and does not establish a correlation with the physical thermal state inside the chip.

[0003] Currently, the industry mainly adopts two existing technical solutions to address the hotspot problem of 3D heterogeneous integrated application-specific integrated circuits (ASICs). The first type is the passive heat dissipation solution. This solution adds heat dissipation structures such as heat spreaders or liquid cooling plates to the outside of the chip package to conduct the heat generated by the chip to the external environment. Its structure mainly includes ASIC die, packaging substrate, thermal interface material, heat spreader or liquid cooling plate, external cooling fan or water cooling circulation system. Its working principle is to control the overall temperature of the chip within a safe range by relying on heat conduction and heat convection outside the chip. However, since there are multiple layers of packaging structure conduction paths between the heat dissipation structures such as heat spreaders and liquid cooling plates and the internal interconnect layers of the chip, this solution cannot solve the local thermal gradient problem of the interconnect layers in the 3D stacked structure inside the chip. Hotspots will still form instantaneously inside the chip and continue to accumulate.

[0004] The second category is software-level thermal throttling solutions. Existing methods involve periodically collecting the overall or localized temperature of the chip using a small number of temperature sensors deployed around the chip. The collected temperature data is then reported to the firmware or operating system via a low-speed bus. The power management unit in the firmware or operating system determines whether to trigger thermal protection based on a preset threshold. If the temperature exceeds the threshold, the firmware forcibly reduces the chip's clock frequency or suspends the scheduling of some computing tasks until the temperature returns to a safe range, at which point the normal frequency is restored. Because this solution relies on the firmware or operating system for temperature judgment and frequency adjustment, its response time is typically in the millisecond range. This is several orders of magnitude slower than the nanosecond-level speed at which heat is generated by internal logic switching, making it unable to respond promptly to sudden surges in localized hotspots. Furthermore, the solution reduces the frequency or suspends tasks for the entire or large area rather than targeting specific overheated physical areas, leading to a complete interruption of the data processing pipeline and significantly sacrificing system computing power and data throughput performance. Therefore, we propose a data processing system and method based on an application-specific integrated circuit (ASIC) chip. Summary of the Invention

[0005] The purpose of this invention is to provide a data processing system based on a dedicated integrated circuit chip.

[0006] The technical problem this invention aims to solve is that when processing high-concurrency, high-throughput data, the vertical stacking structure of a three-dimensional heterogeneous application-specific integrated circuit (ASIC) causes a sharp increase in local power density within the chip, forming local hot spots. Existing passive heat dissipation solutions cannot solve the thermal gradient problem of the interconnect layers within the chip, while existing software-level thermal throttling solutions suffer from large response delays and require frequency reduction or task pausing to cope with the surge in local hot spots, resulting in data processing pipeline disruptions and a significant decrease in system computing power and throughput performance. Therefore, how to achieve real-time and refined management of local hot spots in three-dimensional ASICs without sacrificing data processing throughput performance is the core technical problem this invention aims to solve.

[0007] To address the aforementioned technical problems, this invention provides a data processing system based on an application-specific integrated circuit (ASIC) chip, comprising a common substrate, a three-dimensional stacked computing chip array disposed on the common substrate, a through-silicon via (TSV) microbump array connecting adjacent computing chips, a micro temperature sensor array meshed between the common substrate and the TSV microbump array, an on-chip network router corresponding to each computing chip, and a hardware thermal management module communicatively connected to both the micro temperature sensor array and the on-chip network router. The hardware thermal management module is configured to read real-time temperature values ​​collected by the micro temperature sensor array, compare the real-time temperature values ​​with a preset hotspot determination threshold to obtain a hotspot status flag, generate a back pressure signal when the corresponding physical coordinate location is determined to be in an overheated state, and thereby reduce the routing selection weight of the on-chip network router connected to that location. The on-chip network router is configured to select a candidate path with a weight greater than the other candidate paths as the actual forwarding path based on the routing selection weights of each candidate path, so that the data flow physically bypasses the overheated physical coordinate location. This invention also provides a corresponding data processing method for the aforementioned system.

[0008] Compared with the prior art, the beneficial effects of the present invention by adopting the above technical solution are as follows:

[0009] 1. This invention, by embedding a micro temperature sensor array based on a PN junction in a grid pattern between a common substrate and a through-silicon via (TSV) microbump array physical structure, can obtain the precise three-dimensional temperature distribution state inside the chip. Compared with the existing software solution that only places a small number of temperature sensors on the edge of the die or the package shell and reports them through a low-speed bus, the sensing path is shorter and the sensing granularity is finer.

[0010] 2. This invention dynamically modifies the routing weight of the data flow directly at the router level through a hardware thermal management module, physically bypassing the overheated area without the need for operating system or firmware intervention for judgment and scheduling. This avoids interruption of the data processing pipeline caused by overall frequency reduction or task suspension, and helps maintain the system's throughput performance.

[0011] 3. This invention avoids frequent switching of routing weights caused by physical nodes repeatedly entering and exiting overheated states near the threshold by setting a hysteresis judgment mechanism for recovery threshold and hotspot judgment threshold, thus avoiding routing jitter.

[0012] 4. This invention uses non-uniform task reconfiguration technology to adjust the distribution ratio of new tasks in different physical regions according to temperature conditions without reducing the operating frequency of any individual computing chip, thereby achieving a balanced distribution of the overall power density of the chip and taking into account both heat dissipation requirements and the throughput and long-term reliability of the data processing system. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the overall hardware thermal management closed-loop process in an embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram of the hotspot route weight adaptive adjustment sub-process in an embodiment of the present invention;

[0015] Figure 3 This is a schematic diagram of the global non-uniform task allocation process in an embodiment of the present invention. Detailed Implementation

[0016] The following is in conjunction with the appendix Figure 1-3 The specific embodiments of the present invention will be further described below. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0017] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0018] I. System Overall Architecture:

[0019] The data processing system based on application-specific integrated circuit (ASIC) chip provided in this embodiment consists of three parts: a hardware physical structure layer, a hardware thermal management control layer, and an on-chip network routing and scheduling layer. The three parts work together to form a closed-loop structure in which perception, decision-making, and execution are interconnected. The system includes a common substrate 101, a three-dimensional stacked computing chip array 103 disposed on the common substrate 101, a silicon via microbump array 104 connecting adjacent computing chips, a micro temperature sensor array 102 meshed between the physical structures of the common substrate 101 and the silicon via microbump array 104, an on-chip network router 105 corresponding to each computing chip 103, and a hardware thermal management module 106 that is communicatively connected to both the micro temperature sensor array 102 and the on-chip network router 105.

[0020] The common substrate 101 is a silicon-based substrate, i.e., a silicon interposer, that carries multiple computing chips. The three-dimensional stacked computing chip array 103 includes general computing chips, tensor computing acceleration chips, and storage chips. The chips are vertically interconnected and electrically connected through the silicon via microbump array 104. The on-chip network router 105 forms a mesh topology, with each router node connected to its corresponding computing chip, responsible for addressing, buffering, and forwarding the external data flow of that computing chip. The input of the hardware thermal management module 106 is connected to the output of the micro temperature sensor array 102 via a signal line, and its output is connected to the routing weight register of each on-chip network router 105 via a signal line to achieve direct coupling between temperature status and routing scheduling. Under normal operating conditions, the data flow is transmitted along the default path. When an overheating state is detected at a certain physical coordinate location, the hardware thermal management module 106 drives the corresponding router to reduce the routing selection weight at that location, thereby redirecting the cross-regional data flow to the candidate path with a higher weight value.

[0021] II. Substrate-level micro-thermal sensing network topology:

[0022] In this embodiment, each temperature sensor unit in the micro temperature sensor array 102 is constructed based on the physical characteristic that the forward conduction voltage drop of the PN junction is linearly negatively correlated with temperature. It is used to convert the temperature signal at its physical coordinate position into an analog voltage signal. The data processing system also includes an analog-to-digital converter circuit 107, which is connected to the output terminal of the micro temperature sensor array 102 and is used to convert the analog voltage signal into a digital temperature value. The hardware thermal management module 106 summarizes the digital temperature values ​​according to the array coordinate number of the micro temperature sensor array 102 to form a thermal map matrix covering the entire plane of the common substrate 101, and refreshes the thermal map matrix at a preset clock cycle, thereby realizing real-time monitoring of the three-dimensional thermal state inside the chip.

[0023] The heatmap matrix can be represented as:

[0024] ;

[0025] in, Represents a heatmap matrix. Indicates the position located at the array coordinates. Line number The digital temperature values ​​collected by the temperature sensor unit of the column, This indicates the row number of the temperature sensor array. This indicates the number of columns in the temperature sensor array; for example, in one specific embodiment, and Each can be an integer not less than eight, so that the thermal map matrix can cover the physical region where each computational core is located on the common substrate 101, and achieve a more refined thermal state division.

[0026] In an alternative embodiment of this invention, the temperature sensor unit in the micro temperature sensor array 102 can also be replaced by a thin-film thermistor embedded in the common substrate 101. In this case, the system also includes a bridge circuit 111 connected to the temperature sensor unit, which amplifies the electrical signal output by the temperature sensor unit that varies with resistance and then inputs it to the analog-to-digital conversion circuit 107. The logic for forming the heat map matrix and adjusting the routing weights is consistent with the aforementioned PN junction-based implementation. This alternative implementation is comparable to the PN junction-based implementation in terms of process maturity and can be used as an alternative solution for selecting temperature sensing devices.

[0027] III. Hardware-level thermal sensing adaptive routing core algorithm:

[0028] In this embodiment, the hardware thermal management module 106 and the on-chip network router 105 form a hardware closed-loop adaptive mechanism, the implementation process of which is as follows:

[0029] The hardware thermal management module 106 reads the heat map matrix at a fixed clock cycle. Obtain the real-time temperature values ​​at each of the 101 physical coordinate positions of the common substrate at the current moment. The hardware thermal management module 106 will assign each temperature value Compared with the preset hotspot determination threshold By comparing the data, it is determined whether the physical node corresponding to the coordinate position has entered an overheated state, and the hot spot status flag is obtained. :when Greater than or equal to hour, A value of one indicates that the physical node is in an overheated state. Less than hour, A value of zero indicates that the physical node is within the normal temperature range;

[0030] exist When the value is 1, the hardware thermal management module 106 generates a backpressure signal corresponding to the physical node, and maps the backpressure signal to the routing weight penalty value of the on-chip network router 105 connected to the physical node, thereby updating the routing selection weight. The update relationship can be expressed as:

[0031] ;

[0032] in, This indicates that the updated coordinates are The routing weight corresponding to the location on the router port. This indicates the original routing weight of the router port before the update. This represents the preset hot penalty coefficient, which is greater than zero and not greater than one, and is used to control the magnitude of the decrease in route weight. The aforementioned hotspot status flag, exemplarily, in one specific implementation, represents the heat penalty coefficient. It can be set to 0.5, meaning that when a physical node enters an overheated state, its corresponding routing selection weight is reduced to half of the value before the update, thereby significantly reducing the probability of data flow passing through the overheated area while maintaining a certain throughput capacity.

[0033] When the on-chip network router 105 receives a forwarding request for cross-regional data flow, it selects the routing weights based on the current candidate paths. The candidate path with a weight value greater than the corresponding weight values ​​of the other candidate paths is selected as the actual forwarding path of the data stream, thereby physically bypassing the physical nodes that have been determined to be overheated and redirecting the data stream to redundant computing units or storage units with lower temperatures.

[0034] The hardware thermal management module 106 continuously monitors the real-time temperature values ​​of the bypassed overheating nodes. When the value falls back to the preset recovery threshold The following will change the hotspot status flag of this node. The value is reset to zero, and the routing weights of the routers connected to the node are gradually restored to their pre-update values, so that data flow scheduling is brought back into the availability range of the physical node. The restoration threshold... Less than the hotspot determination threshold The temperature difference between the two constitutes a hysteresis interval, used to prevent frequent switching of routing selection weights caused by slight fluctuations in physical node temperature near a threshold, thereby avoiding routing jitter. For example, in one specific implementation, the hotspot determination threshold... It can be set to a specific value, the recovery threshold. It can be set to another specific value that is less than this specific value, with a certain temperature margin between the two;

[0035] The above steps are executed repeatedly with a fixed clock cycle, forming a continuous hardware closed-loop feedback control, which realizes real-time perception of local hotspots and dynamic adaptive guidance of data flow during chip operation. The whole process is completed by hardware circuits without the need for operating system or firmware to participate in judgment and scheduling.

[0036] In an alternative implementation of this embodiment, the update method for the routing weight in the step can also be different from the aforementioned calculation method. Instead, a lookup table corresponding to temperature ranges and routing weight penalty values ​​can be embedded inside the hardware thermal management module 106. The hardware thermal management module 106 directly obtains the corresponding routing weight penalty value from the lookup table based on the temperature range in which the real-time temperature value is located, and updates the routing selection weight of the corresponding router accordingly. This alternative implementation method can save the logic gate overhead caused by real-time calculation, further reduce the circuit area occupied by the hardware thermal management module 106, and is suitable for application scenarios where chip area is more sensitive.

[0037] IV. Non-uniform task reconstruction techniques:

[0038] Building upon the aforementioned thermally-sensing adaptive routing, the hardware thermal management module 106 of this embodiment is further configured to implement dynamic non-uniform distribution of data processing tasks across different physical regions at the chip-wide level. Specifically, the hardware thermal management module 106 uses a thermal map matrix covering the entire common substrate 101. The system periodically calculates the available computing power weight of each computing chip (103). The available computing power weight is negatively correlated with the temperature value of the physical region where the computing chip is located. That is, the number of new tasks assigned to the physical region with a higher temperature value is less than the number of new tasks assigned to the physical region with a lower temperature value. According to the available computing power weight, the data processing system allocates new data processing tasks to different computing chips (103). Thus, without reducing the operating frequency of any individual computing chip, the system achieves a balanced distribution of the overall power density of the chip through non-uniform adjustment of task distribution. This non-uniform task reconstruction technology and the aforementioned thermal sensing adaptive routing algorithm together constitute a three-level collaborative closed loop in which sensing, routing and task distribution cooperate with each other. The combination of the two forms the complete functional content of the hardware thermal management module (106).

[0039] V. Physical Packaging Structure:

[0040] The actual chip packaging structure of this embodiment, from bottom to top, includes a packaging substrate 108, a common substrate 101 with the embedded micro temperature sensor array 102 and corresponding signal wiring, a silicon via microbump array 104, multiple stacked computing chips 103 bare dies, and a top heat dissipation cover 109. The hardware thermal management module 106 can be integrated into the three-dimensional stacked structure as an independent control chip, or it can be directly integrated into the active circuit area inside the common substrate 101 as a functional module. Neither integration method changes the core sensing and routing scheduling logic of this invention, and both fall within the protection scope of this invention.

[0041] It should be noted that the specific implementation of each step of the data processing method corresponding to the data processing system of the present invention has been described in detail in the foregoing system embodiments, and will not be repeated here. Those skilled in the art can make appropriate adjustments or substitutions to the specific parameters and device selections of the above embodiments based on the disclosure of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0042] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, any modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope defined by the claims of the present invention.

Claims

1. A data processing system based on a dedicated integrated circuit chip, characterized in that, include: A common substrate, a three-dimensional stacked computing chip array disposed on the common substrate, a through-silicon via (TSV) microbump array for connecting adjacent computing chips, a micro temperature sensor array, meshed and embedded between the common substrate and the TSV microbump array, for collecting real-time temperature values ​​at different physical coordinate positions on the common substrate, an on-chip network router, corresponding to each computing chip, for addressing, buffering, and forwarding data streams, and a hardware thermal management module, communicatively connected to both the micro temperature sensor array and the on-chip network router, configured to: read the real-time temperature values ​​collected by the micro temperature sensor array, and... The value is compared with a preset hotspot determination threshold to obtain a hotspot status flag bit corresponding to the physical coordinate location. When the hotspot status flag bit indicates that the corresponding physical coordinate location is in an overheated state, a back pressure signal corresponding to the physical coordinate location is generated, and the routing selection weight of the on-chip network router connected to the physical coordinate location is reduced according to the back pressure signal. The on-chip network router is configured to: when receiving a forwarding request for cross-regional data flow, select a candidate path with a routing selection weight value greater than the corresponding weight values ​​of the other candidate paths as the actual forwarding path according to the routing selection weights of each candidate path, so that the data flow bypasses the physical coordinate location in an overheated state.

2. The data processing system based on a dedicated integrated circuit chip according to claim 1, characterized in that: Each temperature sensor unit in the miniature temperature sensor array is constructed based on the characteristic that the forward conduction voltage drop of the PN junction is linearly negatively correlated with temperature, and is used to convert the temperature signal into an analog voltage signal. The data processing system also includes an analog-to-digital converter circuit connected to the output terminal of the miniature temperature sensor array, used to convert the analog voltage signal into a digital temperature value. The hardware thermal management module summarizes the digital temperature values ​​according to the array coordinate number of the miniature temperature sensor array to form a heat map matrix, and refreshes the heat map matrix at a preset clock cycle.

3. The data processing system based on a dedicated integrated circuit chip according to claim 1, characterized in that: The hardware thermal management module reduces the routing weight based on the back pressure signal by multiplying the original value of the routing weight of the on-chip network router connected to the physical coordinate location by a difference to obtain the updated value of the routing weight. The difference is 1 minus a preset thermal penalty coefficient, where the thermal penalty coefficient is greater than 0 and not greater than 1. The hardware thermal management module is also configured to continuously monitor the real-time temperature value of the physical coordinate location in an overheated state. When the real-time temperature value falls below a preset recovery threshold, the hotspot status flag of the physical coordinate location is reset, and the routing weight of the on-chip network router connected to the physical coordinate location is restored to the original value. The recovery threshold is less than the hotspot determination threshold.

4. A data processing system based on a dedicated integrated circuit chip according to claim 1, characterized in that, The hardware thermal management module is further configured to: periodically calculate the available computing power weight of each computing chip based on the real-time temperature value collected by the micro temperature sensor array. The available computing power weight is negatively correlated with the temperature value of the physical region where the corresponding computing chip is located. The data processing system allocates new data processing tasks to different computing chips according to the available computing power weight, so that the amount of new data processing tasks allocated to the physical region with the lower temperature value is greater than the amount of new data processing tasks allocated to the physical region with the higher temperature value.

5. A data processing system based on a dedicated integrated circuit chip according to claim 1, characterized in that: The temperature sensor unit in the miniature temperature sensor array is a thin-film thermistor embedded in the common substrate. It also includes a bridge circuit connected to the temperature sensor unit for amplifying the signal output by the temperature sensor unit and inputting it to the analog-to-digital converter circuit.

6. A data processing system based on a dedicated integrated circuit chip according to claim 1, characterized in that: The hardware thermal management module has a built-in lookup table that corresponds to temperature ranges and routing weight penalty values. The hardware thermal management module retrieves the corresponding routing weight penalty value from the lookup table based on the temperature range in which the real-time temperature value is located, and updates the routing selection weight of the corresponding on-chip network router based on the routing weight penalty value.

7. A data processing method based on an application-specific integrated circuit (ASIC) chip, applied to a data processing system comprising a common substrate, a three-dimensional stacked array of computing chips disposed on the common substrate, an array of through-silicon via (TSV) bumps connecting adjacent computing chips, a gridded array of miniature temperature sensors embedded between the common substrate and the TSV bump array, and an on-chip network router corresponding to each of the computing chips, characterized in that, include: The system reads real-time temperature values ​​from different physical coordinate positions of the common substrate collected by the micro temperature sensor array, compares these real-time temperature values ​​with a preset hotspot determination threshold, and obtains a hotspot status flag bit for the corresponding physical coordinate position. When the hotspot status flag bit indicates that the corresponding physical coordinate position is in an overheated state, a back pressure signal corresponding to that physical coordinate position is generated, and the routing selection weight of the on-chip network router connected to that physical coordinate position is reduced according to the back pressure signal. When a forwarding request for cross-regional data flow is received, the system selects a candidate path with a routing selection weight value greater than the corresponding weight values ​​of the other candidate paths as the actual forwarding path, based on the routing selection weight values ​​of each candidate path, so that the data flow bypasses the physical coordinate position in an overheated state.

8. The data processing method based on a dedicated integrated circuit chip according to claim 7, characterized in that: Each temperature sensor unit in the miniature temperature sensor array is constructed based on the characteristic that the forward conduction voltage drop of the PN junction is linearly negatively correlated with temperature, and outputs an analog voltage signal. The method further includes: converting the analog voltage signal into a digital temperature value through an analog-to-digital converter circuit, summarizing the digital temperature values ​​according to the array coordinate number of the miniature temperature sensor array to form a heat map matrix, and refreshing the heat map matrix at a preset clock cycle.

9. A data processing method based on an application-specific integrated circuit chip according to claim 7, characterized in that: The step of reducing the routing weight based on the back pressure signal includes: multiplying the original value of the routing weight of the on-chip network router connected to the physical coordinate location by a difference to obtain the updated value of the routing weight, wherein the difference is 1 minus a preset heat penalty coefficient, and the heat penalty coefficient is greater than 0 and not greater than 1. The method further includes: continuously monitoring the real-time temperature value of the physical coordinate location in an overheated state, and when the real-time temperature value falls below a preset recovery threshold, resetting the hotspot status flag of the physical coordinate location, and restoring the routing weight of the on-chip network router connected to the physical coordinate location to the value before the update, wherein the recovery threshold is less than the hotspot determination threshold.

10. A data processing method based on a dedicated integrated circuit chip according to claim 7, characterized in that, Also includes: Based on the real-time temperature values ​​collected by the micro temperature sensor array, the available computing power weight of each computing chip is periodically calculated. The available computing power weight is negatively correlated with the temperature value of the physical region where the corresponding computing chip is located. According to the available computing power weight, new data processing tasks are allocated to different computing chips, so that the amount of new data processing tasks allocated to physical regions with low temperature values ​​is greater than the amount of new data processing tasks allocated to physical regions with high temperature values.

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