Ethernet signal transmission method for an Ethernet switch

Abstract

The application discloses an Ethernet signal transmission method for an Ethernet switch and belongs to the technical field of Ethernet communication. The method oversamples an Ethernet signal received by an entrance port, extracts a jump edge position and records a phase offset value of the jump edge relative to a local clock; divides a receiving clock into a leading, synchronous or lagging state according to the positive and negative and size of the phase offset value, and takes a time slot length corresponding to the lagging state as a minimum adjustment step; compensates for a delay of the receiving signal according to the minimum adjustment step, and obtains a to-be-switched signal aligned with a global reference clock; inserts a label code element with a port identifier into an idle interval between Ethernet frames of the to-be-switched signal and records an insertion position; and a switching matrix forwards the to-be-switched signal to a destination port according to the port identifier. The method can reduce the influence of clock phase deviation on switching and convergence, and can transmit the port identifier by using the idle interval between frames, so that the quality of an exit signal is improved.

Description

Technical Field

[0001] This invention relates to the field of Ethernet communication technology, specifically to an Ethernet signal transmission method for an Ethernet switch. Background Technology

[0002] During the aggregation and forwarding of multi-port signals in Ethernet switches, the receiving clocks of each input port are typically generated by independent clock sources, resulting in frequency deviations and phase drift. The phase offset between the bit stream recovered at the receiving end and the global reference clock changes over time, leading to timing inconsistencies before the signal enters the switching matrix. Existing solutions often employ fixed-step delay compensation or frame alignment based on elastic buffers. Fixed-step compensation cannot simultaneously accommodate both leading and lagging clock states; if the step size is too small, the buffer depth increases, while if the step size is too large, residual phase errors become significant. Although elastic buffers can absorb some clock deviations, their adjustment unit is a complete bit or a fixed depth, which cannot determine the minimum compensation step size based on the actual phase offset direction and magnitude of the current port. When the receiving clock is lagging, improper selection of the buffer readout position can easily occur, resulting in bit loss or duplication.

[0003] For port identification in switching matrices, existing solutions typically require parsing fields such as address and VLAN in the Ethernet frame header to obtain input port information, or transmitting port identifiers through a separate out-of-band channel. Parsing the frame header introduces additional processing latency and requires the switching device to fully parse the frame format, making it unsuitable for transparent forwarding scenarios; the out-of-band channel method requires additional signal lines or transmission resources, and there is a time alignment error between the identification signal and the data signal. While there are idle intervals between Ethernet frames, these intervals are not used for transmitting port identifiers.

[0004] During the insertion and removal of tag symbols, the duty cycle of the signal at the destination port output side is prone to shift. Existing methods typically output the bit stream after tag removal directly, without utilizing the signal level changes before and after the tag to correct the output waveform. This results in insufficient eye diagram margin for the high-speed output signal, affecting data recovery at the downstream receiver. Multiport Ethernet switching still has shortcomings in receive clock phase compensation and port identifier transmission. Summary of the Invention

[0005] To address the issues of insufficient granularity of multi-port receive clock phase offset compensation and reliance on frame header parsing or out-of-band channels for port identifier transmission in existing Ethernet switches, this invention provides an Ethernet signal transmission method for Ethernet switches. The method aims to utilize oversampled phase offset values ​​to divide the receive clock state, determine the minimum adjustment step size in the lag state, and perform delay compensation on the received signal to align the signals of each input port with the global reference clock. A tag symbol with a port identifier is inserted into the idle interval between Ethernet frames, and the insertion position is recorded. The switching matrix forwards the tag symbol to the destination port. After removing the tag symbol at the destination port, the duty cycle of the output signal is calibrated using the level change before and after the tag.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The present invention provides an Ethernet signal transmission method for an Ethernet switch, comprising: oversampling the received Ethernet signal at the ingress port, extracting the transition edge position of each bit, and recording the phase offset value of the transition edge relative to the local clock; dividing the received clock at the ingress port into a leading state, a synchronous state, and a lagging state according to the sign and magnitude of the phase offset value, and using the time slot length corresponding to the lagging state as the minimum adjustment step size; performing delay compensation on the received signal according to the minimum adjustment step size to obtain a signal to be switched aligned with the global reference clock; identifying the idle interval between Ethernet frames from the signal to be switched, inserting a tag symbol with a port identifier into the idle interval, and recording the insertion position of the tag symbol in the signal to be switched; sending the signal to be switched after inserting the tag symbol to the switching matrix, and having the switching matrix forward the signal to be switched to the destination port according to the port identifier in the tag symbol; at the output side of the destination port, after detecting the tag symbol, removing the tag symbol according to the insertion position, and calibrating the duty cycle of the output signal using the signal level change before and after the tag symbol. This method utilizes port identification tags to achieve deterministic forwarding of signals in the switching matrix, while performing delay compensation based on the phase offset of the transition edge, so that each input signal is aligned with the global reference clock, thereby reducing the delay deviation and bit error rate during multi-port switching.

[0007] Preferably, the process of oversampling the Ethernet signal received at the ingress port, extracting the transition edge position of each bit, and recording the phase offset value of the transition edge relative to the local clock includes: continuously sampling the received signal using a sampling clock that has been frequency-multiplied by the local clock to obtain continuous sampling points; determining the position of the sampling point as a transition edge when the amplitude difference between adjacent sampling points changes from negative to positive or from positive to negative; and using the time difference between the transition edge and the rising edge of the local clock as the phase offset value of the bit. By using frequency-multiplied sampling and amplitude difference transition determination, high-precision transition edge position information can be obtained with relatively low hardware overhead.

[0008] Preferably, the process of dividing the received clock at the input port into a leading state, a synchronous state, and a lagging state based on the sign and magnitude of the phase offset value, and using the time slot length corresponding to the lagging state as the minimum adjustment step size, includes: arranging the phase offset values ​​of several consecutively received bits at the same port in chronological order to form a phase offset sequence; counting the number of offsets greater than zero and the number of offsets less than zero in the phase offset sequence; if the proportion of offsets greater than zero to the sequence length exceeds a first preset proportion, the received clock is determined to be in a leading state; if the proportion of offsets less than zero to the sequence length exceeds a second preset proportion, the received clock is determined to be in a lagging state; otherwise, the received clock is determined to be in a synchronous state; in the lagging state, the time slot length corresponding to the median of the absolute values ​​of all negative phase offset values ​​is taken as the minimum adjustment step size. Using statistical proportions and the median to determine the clock state and adjustment step size can suppress misjudgments caused by single-bit jitter and improve the stability of clock state judgment.

[0009] Preferably, the process of delay compensation of the received signal according to the minimum adjustment step size to obtain the signal to be exchanged aligned with the global reference clock includes: writing the received signal into the buffer of the input port in the order of arrival; when it is necessary to read the signal from the buffer, inserting a waiting time between two adjacent bits according to the minimum adjustment step size; when the accumulated waiting time reaches one bit cycle, skipping one sampling point in the buffer, and using the skipped sampling point as the starting point of the next bit. By gradually inserting the waiting time according to the minimum adjustment step size and skipping the sampling point after accumulating to one bit cycle, fine delay compensation can be achieved while maintaining signal continuity.

[0010] Preferably, the process of skipping a sampling point in the buffer includes: when the accumulated waiting time reaches one bit cycle, determining whether the amplitude of the current sampling point is the same as the amplitude of the previous sampling point; if they are the same, skipping the current sampling point; if they are different, not skipping the current sampling point, and waiting for the next adjacent bit boundary to make another determination. This method can avoid skipping sampling points at the location where the signal changes, thus avoiding the loss of transition edge information, and ensuring that the compensated signal still retains complete transition characteristics.

[0011] Preferably, the process of identifying idle intervals between Ethernet frames in the signal to be switched, inserting tag symbols with port identifiers within the idle intervals, and recording the insertion positions of the tag symbols in the signal to be switched includes: detecting the intervals between adjacent transition edges of the signal to be switched, identifying continuous regions with intervals greater than the frame header preamble interval as idle intervals; selecting the idle symbol position closest to the next frame header within the idle interval, encoding the port identifier as a tag symbol and inserting it at that position; and recording the offset of the idle symbol position relative to the first transition edge of the next frame header preamble as the insertion position. Inserting tag symbols using inter-frame idle intervals does not occupy additional effective data bandwidth, and by recording the relative position with the frame header, the tag can be accurately located at the egress side.

[0012] Preferably, the tag code element is generated as follows: the port identifier is converted into a binary sequence; a start boundary field is added to the beginning of the binary sequence, and an end boundary field is added to the end; the bits of the binary sequence between the start and end boundary fields are inverted and then superimposed bit by bit to generate a check field; the start boundary field, binary sequence, check field, and end boundary field are arranged in order to obtain the tag code element. By using the start boundary, check field, and end boundary, the recognition reliability and anti-false positive capability of the tag code element during transmission can be improved.

[0013] Preferably, the process of sending the signal to be exchanged after inserting the tag code to the switching matrix, and the switching matrix forwarding the signal to the destination port according to the port identifier in the tag code includes: the switching matrix parsing the port identifier in the tag code to obtain the input port information; performing a bit-by-bit XOR comparison between the port identifier and the port number of each entry in the port mapping table in the switching matrix to obtain the comparison result; when the difference in the comparison result is zero bits, the destination port number of the corresponding entry is used as the forwarding destination port; and setting the selection state of the crossbar switch of the switching matrix according to the forwarding destination port to connect the input channel to the destination output channel. By performing a bit-by-bit XOR comparison, port matching can be quickly completed with simple digital logic, improving the forwarding speed of the switching matrix.

[0014] Preferably, the process of performing a bit-by-bit XOR comparison between the port identifier and the port number of each entry in the port mapping table in the switching matrix includes: reading an entry from the port mapping table and obtaining the valid bit of the entry; when the valid bit is high, comparing the port number of the entry with the port identifier in the tag code bit by bit; if at least one bit is different, discarding the entry and reading the next entry; if all bits are the same, determining the output port corresponding to the entry as the forwarding destination port. By controlling the valid bit and performing bit-by-bit comparison, invalid entries can be avoided from participating in the matching, reducing the number of comparisons.

[0015] Preferably, at the exit side of the destination port, after detecting the tag symbol, the process of removing the tag symbol according to the insertion position and calibrating the duty cycle of the output signal using the signal level change before and after the tag symbol includes: finding the corresponding bit position in the bit stream on the exit side according to the insertion position; extracting the binary sequence of the same length as the tag symbol at that bit position and comparing it with the pre-stored tag symbol; if they are completely consistent, deleting the binary sequence from the bit stream; measuring the duration from the start edge to the end edge of the tag symbol, comparing the duration with the standard symbol period to obtain the duty cycle deviation; and adjusting the rising edge delay parameter or falling edge delay parameter of the waveform shaper on the exit side according to the duty cycle deviation. By deleting the tag symbol to restore the original signal and calibrating the duty cycle using the edge duration of the tag symbol, the waveform quality of the exit signal can be improved.

[0016] The technical effects and advantages provided by the present invention in the above technical solution are as follows: The received Ethernet signal at the ingress port is oversampled to extract the transition edge position of each bit, and the time difference between the transition edge and the rising edge of the local clock is used as the phase offset value. The phase offset values ​​of several consecutive bits at the same port are arranged chronologically, and the proportion of positive and negative phase offsets to the sequence length is calculated to classify the received clock as leading, synchronous, or lagging. In the lagging state, the time slot length corresponding to the median of the absolute values ​​of all negative phase offsets is taken as the minimum adjustment step size. Delay compensation is applied to the received signal according to this minimum adjustment step size. Waiting time is inserted between adjacent bits in the buffer. After the accumulated waiting time reaches one bit cycle, a sampling point in the buffer is skipped, resulting in a signal to be switched aligned with the global reference clock. Selecting the compensation step size based on the direction and magnitude of the phase offset and finely controlling the sampling points can reduce the impact of clock phase deviations between different ingress ports on switching convergence, reduce the probability of incorrect sampling point selection near the transition edge during buffer readout, and reduce residual phase errors caused by excessively large step sizes and buffer delays caused by excessively small step sizes.

[0017] In the signal to be switched, the Ethernet inter-frame idle interval is identified, and a tag symbol with a port identifier is inserted at the idle symbol position closest to the next frame header. The offset of the tag symbol relative to the first transition edge of the preamble of the next frame header is recorded as the insertion position. The switching matrix parses the port identifier in the tag symbol and compares it bit by bit with the port number in each entry of the port mapping table. Based on the comparison result, the crossbar switch is activated, and the signal to be switched is forwarded to the destination port. The port identifier is inserted into the data stream through the inter-frame idle interval. The insertion position is recorded, and the port identifier is transmitted with the signal itself, without occupying an additional out-of-band channel or requiring the parsing of frame header address information, making it suitable for transparent forwarding scenarios. At the destination port exit side, the tag symbol is located according to the insertion position, and the corresponding binary sequence is deleted. The duration from the start edge to the end edge of the tag symbol is measured and compared with the standard symbol period to obtain the duty cycle deviation. The rising edge or falling edge delay parameters of the waveform shaper on the exit side are adjusted. By using the signal level changes before and after the tag symbol to correct the output waveform, the impact of tag insertion / deletion on the output signal duty cycle can be reduced, improving the quality of the exit signal. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0019] Figure 1 This is a flowchart of an Ethernet signal transmission method used in Ethernet switches; Figure 2 This is the read pointer control flowchart of the delay compensation module; Figure 3 This is a schematic diagram showing the relationship between the cumulative waiting time of the delay compensation module and the bit period; Figure 4 This is a schematic diagram of edge transition interval and idle interval detection; Figure 5 It is the curve showing the change in duty cycle deviation and delay adjustment steps on the export side. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] See Figure 1This invention provides an Ethernet signal transmission method for an Ethernet switch. After receiving an Ethernet signal at the ingress port, the received Ethernet signal is oversampled to extract the transition edge position of each bit and record the phase offset value of the transition edge relative to the local clock. Based on the sign and magnitude of the phase offset value, the received clock at the ingress port is divided into a leading state, a synchronous state, and a lagging state, with the time slot length corresponding to the lagging state as the minimum adjustment step size. Delay compensation is performed on the received signal according to the minimum adjustment step size to obtain a signal to be switched aligned with the global reference clock. Idle intervals between Ethernet frames are identified from the signal to be switched, and tag symbols with port identifiers are inserted into the idle intervals, with the insertion position of the tag symbols in the signal to be switched recorded. The signal to be switched after inserting the tag symbols is sent to the switching matrix, which forwards the signal to be switched to the destination port according to the port identifier in the tag symbols. At the output side of the destination port, after detecting the tag symbols, the tag symbols are removed according to the insertion position, and the duty cycle of the output signal is calibrated using the signal level change before and after the tag symbols.

[0022] In practical implementation, the Ethernet signal received at the ingress port of the Ethernet switch is a differential analog signal. The oversampling module in the ingress port uses a sampling clock multiplied by the local clock to continuously sample the received signal, obtaining continuous sampling points. The sampling clock frequency is a fixed multiple of the local clock frequency, which is eight times. The continuous sampling points are arranged in sampling time order and written to the sampling point buffer of the ingress port. Each sampling point buffer unit stores the sampling point amplitude and sampling time sequence number.

[0023] When the amplitude difference between adjacent sampling points changes from negative to positive or from positive to negative, it indicates that a level flip has occurred in the received signal between the adjacent sampling points. The position of the next sampling point among the adjacent sampling points is determined as the transition edge, and the sampling time sequence number corresponding to the transition edge is recorded.

[0024] The time difference between the transition edge and the rising edge of the local clock is used as the phase offset value for the corresponding bit. The sign and magnitude of the phase offset value are calculated using the following formula:

[0025] in, Indicates the first The phase offset value corresponding to each bit; Indicates the first The time position of each bit's transition edge on the oversampled time axis; Indicates the relationship with the first The time position of the bit transition edge on the oversampled time axis at the nearest rising edge of the local clock; subscript For bit sequence number, It is a positive integer; This serves as a time position identifier for the transition edge; This identifies the rising edge time position of the local clock. The oversampled time axis is represented by the sampling time sequence number, and the rising edge time position of the local clock is determined by the local clock edge counter in the input port.

[0026] The phase offset values ​​of several consecutively received bits from the same port are arranged in chronological order to form a phase offset sequence. The length of the phase offset sequence is set to 1024. The number of offsets greater than zero and the number of offsets less than zero in the phase offset sequence are counted. A positive offset counter is established to count the number of offsets greater than zero. A negative offset counter is established to count the number of offsets less than zero. When the phase offset value is zero, neither the positive nor negative offset counters are incremented. The proportion of offsets greater than zero to the length of the phase offset sequence is calculated to obtain the positive offset proportion. The proportion of offsets less than zero to the length of the phase offset sequence is calculated to obtain the negative offset proportion.

[0027] The first preset ratio is set to 60%. This is based on the principle that when more than half of the phase offset values ​​in the phase offset sequence show an offset in the same direction, it is possible to reliably determine whether the receiving clock is leading or lagging, and it can tolerate misjudgments caused by a small amount of sampling jitter. The second preset ratio is also set to 60%. This is based on the same principle as the first preset ratio. If the positive offset ratio exceeds the first preset ratio, the receiving clock is determined to be leading. If the negative offset ratio exceeds the second preset ratio, the receiving clock is determined to be lagging. If neither the positive nor negative offset ratio exceeds the first or second preset ratio, the receiving clock is determined to be synchronized.

[0028] In the lag state, the absolute values ​​of all negative phase offsets are taken. These absolute values ​​are then arranged in ascending order. If the number of negative phase offsets is odd, the median is taken as the middle absolute value after sorting. If the number of negative phase offsets is even, the median is taken as the average of the two middle absolute values ​​after sorting. The slot length corresponding to the median absolute value is used as the minimum adjustment step size. The slot length refers to the time interval between two adjacent sampling points of the sampling clock. In some embodiments, in the lag state, if the slot length corresponding to the median absolute value is less than one sampling clock cycle, the minimum adjustment step size is set to one sampling clock cycle. In the lead or synchronization state, the minimum adjustment step size is not updated; the minimum adjustment step size determined in the previous lag state is maintained.

[0029] In specific implementation, please refer to Figure 2The buffer in the Ethernet switch's ingress port is a ring buffer, which contains write pointers and read pointers. The received signal, after oversampling, has sampled points written to the ring buffer in arrival order. The write pointer increments with each sampling clock cycle, writing one sample point per clock cycle. The ring buffer has a depth of 2048 sample points.

[0030] When a signal needs to be read from the ring buffer, the delay compensation module controls the read pointer to read the sample point from the ring buffer. The delay compensation module internally sets up an accumulator register, initially set to zero. A wait time is inserted between two adjacent bits according to a minimum adjustment step size. The minimum adjustment step size is obtained by the delay compensation module from the clock state analysis module. Each time a wait time is inserted, the accumulator register is incremented by the minimum adjustment step size, and the accumulated wait time in the accumulator register is compared with one bit period. The bit period is defined as the sampling clock period multiplied by an oversampling factor of eight. The sampling clock period is the reciprocal of the sampling clock frequency.

[0031] When the accumulated waiting time reaches one bit cycle, the delay compensation module determines whether the amplitude of the current sampling point is the same as the amplitude of the previous sampling point. The method for determining whether they are the same is as follows: the digital code of the amplitude of the current sampling point is compared bit by bit with the digital code of the amplitude of the previous sampling point. If all bits are the same, the amplitude is determined to be the same; if at least one bit is different, the amplitude is determined to be different.

[0032] If the amplitude of the current sampling point is the same as the amplitude of the previous sampling point, the delay compensation module skips the current sampling point in the circular buffer. The operation of skipping the current sampling point is as follows: the circular buffer read pointer is incremented by one bit, and the next sampling point after the current sampling point is read, with the skipped sampling point as the starting point of the next bit. Simultaneously, the delay compensation module subtracts one bit cycle from the accumulated waiting time in the accumulator register to obtain the updated accumulated waiting time.

[0033] If the amplitude of the current sampling point is different from the amplitude of the previous sampling point, the delay compensation module does not skip the current sampling point, but uses the current sampling point as the output of the current bit, and waits for the next adjacent bit boundary to make another judgment. In some embodiments, the determination of the accumulated waiting time reaching one bit period is made using the following formula:

[0034] in, Indicates the first The cumulative waiting time after each insertion waiting time; This indicates the number of insertion wait times. It is a positive integer; Indicates the minimum adjustment step size; This represents one bit cycle. When the cumulative waiting time... Greater than or equal to one bit period At that time, the delay compensation module triggers an amplitude comparison operation.

[0035] It is understandable that after triggering the amplitude comparison operation, the delay compensation module will use the updated cumulative waiting time as the basis for the next accumulation, regardless of whether the current sampling point is skipped. When the current sampling point is skipped, the cumulative waiting time is subtracted by one bit period. When the current sampling point is not skipped, the cumulative waiting time remains unchanged and continues to accumulate during subsequent insertion of waiting time.

[0036] See Figure 3 In the graph, the horizontal axis represents the number of insertion wait times, and the vertical axis represents the cumulative wait time, in units of sampling clock cycles. The blue solid line curve shows the trend of cumulative wait time as the number of insertion wait times increases; the red dashed line represents a fixed bit period of 8 sampling clock cycles; the gray dotted line represents the current minimum adjustment step size, which is 0.5 sampling clock cycles; the green triangle indicates the event of skipping the current sampling point when the cumulative wait time reaches or exceeds the bit period threshold.

[0037] As shown in the graph, the accumulated waiting time exhibits a periodic upward and then sharp downward fluctuation trend. When the accumulated waiting time gradually approaches the bit period (i.e., close to the red dashed line), a comparison is triggered between the amplitude of the current sampling point and the amplitude of the previous sampling point. If the amplitudes are the same, the current sampling point is skipped (as shown by the green triangle), and the accumulated waiting time decreases by one bit period, entering the next round of accumulation. If the amplitudes are different, the current sampling point is not skipped, the accumulated waiting time remains unchanged, and the accumulation of waiting time continues. The minimum adjustment step size, indicated by the gray dashed line, remains stable, indicating that in the leading or synchronous state, the minimum adjustment step size is not updated, maintaining the value determined in the previous lagging state. The peak value of the accumulated waiting time in the graph exceeds the bit period multiple times, reflecting the dynamic adjustment process of the delay compensation module inserting the waiting time.

[0038] In practical implementation, the idle interval detection module at the Ethernet switch's ingress port performs edge-to-edge detection on the signal to be switched. The idle interval detection module includes an edge-to-edge interval counter. This counter counts the sampling clock cycles between every two adjacent edge transitions. When the interval between adjacent edge transitions satisfies the following formula, the continuous region between adjacent edge transitions is identified as an idle interval:

[0039] in, Indicates the first Interval of adjacent transition edges The sequence number of the adjacent transition edges. It is a positive integer; This indicates the frame header preamble interval. The frame header preamble interval is determined by the physical layer encoding type and oversampling factor configured on the Ethernet switch's ingress port and is stored in the configuration register of the idle interval detection module.

[0040] After identifying the idle interval, the idle interval detection module waits for the first transition edge of the next frame header preamble. When the idle interval detection module detects the first transition edge of the frame header preamble, it traces back from that first transition edge to find the nearest complete idle symbol position. The complete idle symbol position is the interval of consecutive sampling points corresponding to one complete symbol period within the idle interval.

[0041] The idle interval insertion module inserts a tag symbol at the selected complete idle symbol position. The tag symbol insertion operation is as follows: the idle interval insertion module writes the tag symbol output by the tag symbol generation module into the storage area corresponding to the complete idle symbol position in the signal to be exchanged, overwriting the original idle signal at the complete idle symbol position. The tag symbol length is configured to be the same as the length of the complete idle symbol position. The idle interval detection module records the insertion position of the tag symbol in the signal to be exchanged. The insertion position is the offset of the complete idle symbol position relative to the first transition edge of the preamble of the next frame. The offset is represented by the number of sampling clock cycles, with the starting point of the offset being the starting boundary of the complete idle symbol position and the ending point being the first transition edge of the preamble of the next frame. The idle interval detection module writes the offset into the insertion position register.

[0042] The tag symbol generation module receives the port identifier of the ingress port. The port identifier is the physical port number of the ingress port. The tag symbol generation module converts the port identifier into a binary sequence. The length of the binary sequence is determined by the maximum number of ports on the Ethernet switch. The bit order of the binary sequence is arranged from most significant bit to least significant bit. The tag symbol generation module adds a start boundary field to the beginning of the binary sequence and an end boundary field to the end of the binary sequence. The start boundary field and the end boundary field are provided by the Ethernet switch configuration register. The start boundary field and the end boundary field are each set to a different fixed binary sequence. The start boundary field is used to identify the start boundary of the tag symbol, and the end boundary field is used to identify the end boundary of the tag symbol.

[0043] The tag symbol generation module inverts each bit of the binary sequence between the start and end boundary fields to obtain an inverted sequence. This inverted sequence is then divided into multiple check segments, each 4 bits long. If the length of the inverted sequence is not a multiple of 4, the module pads the end with binary zeros until the length is a multiple of 4.

[0044] The tag code generation module performs a bitwise XOR operation on the four inverted bits in each check segment to generate one check bit. All check bits are arranged in the order of the check segments to form the check field. The tag code generation module then arranges the start boundary field, binary sequence, check field, and end boundary field in sequence to obtain the tag code. Finally, the tag code generation module outputs the tag code to the idle interval insertion module.

[0045] In some embodiments, when the idle interval detection module backtracks to find the complete idle symbol position, it scans point by point forward from the first transition edge of the frame header preamble according to the sampling point sequence number. If the idle interval detection module detects no transition edges within a consecutive symbol period during the scanning process, it takes the sampling point interval without transition edges as the complete idle symbol position. It can be understood that the offset stored in the insertion position register is used to locate the tag symbol on the exit side. The insertion position register is updated after the tag symbol is inserted.

[0046] See Figure 4 In the figure, the vertical axis represents the number of sampling clock cycles between adjacent transition edges, and the horizontal axis represents the sequence number of adjacent transition edges. Blue solid dots represent normal transition edge intervals, and red squares represent idle transition edge intervals. The gray dashed line in the figure represents the threshold number of sampling clock cycles for the frame header preamble interval, and the green dashed line represents the tag symbol insertion position.

[0047] As shown in the figure, the blue normal transition edge intervals are concentrated within a relatively small range of sampling clock cycles, with values ​​all lower than the frame header preamble interval threshold and remaining relatively stable, indicating that the transition edge intervals in normal data frames are short and continuous. The red idle transition edge intervals are significantly larger than the frame header preamble interval threshold, distributed across a larger range of sampling clock cycles, and dispersed throughout the entire range of adjacent transition edge numbers, consistent with the characteristics of idle intervals between Ethernet frames. The green dashed line indicates that the tag symbol insertion position is located at the beginning of the sequence number, indicating that the tag symbol is inserted within the idle interval before the frame header preamble, utilizing the complete idle symbol position to cover the original idle signal.

[0048] In practical implementation, the switching matrix includes a tag parsing unit, a port mapping table storage unit, a comparison unit, and a crossbar switch. The tag parsing unit receives the signal to be switched after inserting tag symbols. The tag parsing unit detects the start boundary field and end boundary field from the signal to be switched after inserting tag symbols. The tag parsing unit extracts the binary sequence between the start boundary field and the end boundary field and uses this binary sequence as the port identifier. The tag parsing unit outputs the port identifier to the comparison unit.

[0049] The port mapping table storage unit stores the port mapping table. The port mapping table contains multiple entries. Each entry contains a valid bit, a port number, and a destination port number. The port mapping table storage unit provides entries to the comparison unit in ascending order of entry number. The comparison unit reads an entry from the port mapping table storage unit and checks the valid bit of the currently read entry.

[0050] When the valid bit of the currently read entry is high, the comparison unit performs a bitwise XOR comparison between the port number in the currently read entry and the port identifier in the tag code. The bitwise XOR comparison is performed in a bit comparator array within the comparison unit. The bit comparator array contains the same number of bit comparators as the port identifier bit width. Each bit comparator corresponds to one bit position. Each bit comparator receives the binary value of the port number in the currently read entry at the corresponding bit position and the binary value of the port identifier in the tag code at the corresponding bit position.

[0051] The bit comparator performs an XOR operation on the two input binary values ​​to obtain the bit difference indicator value. A bit difference indicator value of zero indicates that the two input binary values ​​are the same, and a bit difference indicator value of one indicates that the two input binary values ​​are different. The bit difference indicator values ​​output by all bit comparators are fed into the difference bit accumulator. The difference bit accumulator sums all the bit difference indicator values ​​to obtain the difference number of bits. The difference number of bits is calculated using the following formula:

[0052] in, Indicates the first The number of difference bits corresponding to each table entry; Indicates the item number. It is a positive integer; Indicates the position number of the bit. It is a positive integer. The range of values ​​is to ; This indicates the bit width of the port identifier, which is determined by the maximum number of ports on the Ethernet switch. Indicates the first The port number in the first table entry The binary value at the units position; The port identifier in the tag code element is in the 1st position. The binary value at the units position; This represents a bitwise XOR operation. When... and When they are the same, The value is zero; when and At the same time, The value is one.

[0053] After the difference bit accumulator obtains the difference bit count, the comparison unit determines whether the difference bit count is zero. When the difference bit count is zero, the comparison unit uses the destination port number in the currently read entry as the forwarding destination port and outputs the forwarding destination port to the crossbar switch. When the difference bit count is not zero, the comparison unit discards the currently read entry and reads the next entry from the port mapping table storage unit, repeating the valid bit check and bit-by-bit XOR comparison for the next entry.

[0054] The crossbar switch receives the forwarding destination port output from the comparator unit. Internally, the crossbar switch contains a decoder and a crosspoint switch array. The decoder decodes the binary port number corresponding to the forwarding destination port into a hot-swappable output channel selection signal. The crosspoint switch array contains multiple input channels and multiple output channels; each input channel corresponds to one input channel of the switching matrix, and each output channel corresponds to one destination port. The hot-swappable output channel selection signal output by the decoder controls the closure of the corresponding crosspoint switch in the crosspoint switch array. After the crosspoint switch is closed, a connection is formed between the input channel of the switching matrix and the destination output channel.

[0055] In some embodiments, when the comparison unit checks the valid bits of the currently read entry, if the valid bit is low, the comparison unit discards the currently read entry and reads the next entry from the port mapping table storage unit. It can be understood that the comparison unit reads entries in the port mapping table storage unit from smallest to largest according to the entry number, and stops reading after finding an entry with zero difference bits.

[0056] In practical implementation, the egress side of the destination port of the Ethernet switch includes a tag detection module, a duty cycle calibration module, and a waveform shaper. The egress bitstream is the serial bitstream recovered after being forwarded to the destination port by the switching matrix. The egress side insertion position register stores the insertion position recorded on the ingress side. The insertion position stored in the insertion position register is the offset of the tag symbol start boundary relative to the first transition edge of the preamble of the next frame header, and the offset is expressed in the number of sampling clock cycles.

[0057] The export-side tag detection module locates the corresponding bit position according to the insertion position. The tag detection module detects the first transition edge of the frame header preamble in the export-side bitstream. The first transition edge of the frame header preamble is determined by identifying the start of the alternating level transitions in the preamble. The tag detection module backtracks from the first transition edge of the frame header preamble, with a backtracking step size equal to the offset in the insertion position register. The sampling point located after backtracking is the bit position where the tag symbol start boundary is located, and this backtracked sampling point position is recorded as the tag symbol start position.

[0058] The tag detection module reads consecutive bits according to the tag code length, starting from the beginning position of the tag code, to obtain the extracted binary sequence. The tag code length is provided by the configuration register in the exit-side tag detection module, and is the same as the tag code length generated by the entry-side tag code generation module. The tag code length is equal to the sum of the start boundary field length, the port identifier binary sequence length, the check field length, and the end boundary field length.

[0059] The tag detection module pre-stores tag symbols. These pre-stored tag symbols are stored in a tag symbol register. The pre-stored tag symbols include a start boundary field, a port identifier binary sequence, a check field, and an end boundary field. The tag detection module compares the retrieved binary sequence bit-by-bit with the pre-stored tag symbols. The bit-by-bit comparison method is as follows: the tag detection module sets up a bit comparator array, which contains the same number of bit comparators as the tag symbol length. Each bit comparator performs an XOR operation on the binary value at the corresponding bit position of the retrieved binary sequence and the pre-stored tag symbol to obtain a bit difference indicator value. All bit difference indicator values ​​are fed into a difference bit accumulator, which sums all bit difference indicator values ​​to obtain the total number of difference bits. If the total number of difference bits is zero, it is determined that the retrieved binary sequence is completely identical to the pre-stored tag symbol.

[0060] If the retrieved binary sequence is completely identical to the pre-stored tag code, the tag detection module deletes the retrieved binary sequence from the output bitstream. Specifically, the deletion operation involves the tag detection module controlling the output buffer to disable write operations in the bit interval between the start and end positions of the tag code, and resuming write operations in the bit interval after the end position of the tag code. This prevents the binary sequence corresponding to the tag code from being written to the output buffer, and the bitstream in the output buffer becomes the payload bitstream after deleting the tag code.

[0061] When the start edge of the tag symbol start boundary field is detected, the duty cycle calibration module starts the time-to-digital converter (TD-RCD) to begin counting. When the end edge of the tag symbol end boundary field is detected, the duty cycle calibration module stops the TD-RCD counting. The TD-RCD uses a sampling clock as a reference and records the number of sampling clock cycles between the start and end edges. Multiplying this number by the sampling clock cycle yields the duration from the start to the end edge of the tag symbol. In some embodiments, the TD-RCD uses an oversampled clock, with the sampling clock cycle being the oversampled clock cycle. The TD-RCD can record the fractional part of the sampling clock cycle.

[0062] The duty cycle calibration module compares the duration from the start edge to the end edge of the tag symbol with the standard symbol period to obtain the duty cycle deviation. The standard symbol period is stored in the configuration register of the duty cycle calibration module and is determined by the Ethernet physical layer coding type. The duty cycle deviation is calculated using the following formula:

[0063] in, Indicates the first The duty cycle deviation corresponding to the duration from the start edge to the end edge of the detected tag symbol; Indicates the first The duration from the start edge to the end edge of the detected tag symbol; Indicates the standard symbol period; Indicates the symbol period identifier; Indicates the test sequence number. It is a positive integer; Indicates the duration of tag symbol measurement; This indicates the standard symbol period identifier. When... Greater than hour, Greater than zero; when Less than hour, Less than zero.

[0064] The duty cycle calibration module adjusts the rising edge delay parameter or falling edge delay parameter of the output-side waveform shaper based on the duty cycle deviation. The output-side waveform shaper includes adjustable rising edge delay lines and adjustable falling edge delay lines. The adjustable rising edge delay line consists of multiple cascaded delay units, each providing a fixed delay step. The adjustable falling edge delay line also consists of multiple cascaded delay units, each providing a fixed delay step. The duty cycle calibration module converts the duty cycle deviation into a delay adjustment step count, determined by multiplying the absolute value of the duty cycle deviation by the standard symbol period and dividing by the fixed delay step count of the delay unit. When the duty cycle deviation is greater than zero, the duty cycle calibration module decreases the delay step count of the adjustable rising edge delay line or increases the delay step count of the adjustable falling edge delay line. When the duty cycle deviation is less than zero, the duty cycle calibration module increases the delay step count of the adjustable rising edge delay line or decreases the delay step count of the adjustable falling edge delay line. The duty cycle calibration module writes the delay adjustment steps into the control register of the adjustable rising edge delay line or the adjustable falling edge delay line to complete the duty cycle calibration of the output signal.

[0065] It is understandable that after the tag detection module deletes the tag symbols, the payload bit stream in the output buffer continues to be output to the waveform shaper. The waveform shaper shapes the payload bit stream according to the adjusted rising edge delay parameters and falling edge delay parameters, and outputs the calibrated Ethernet signal.

[0066] See Figure 5 In this figure, the horizontal axis represents the detection sequence number, the left side of the vertical axis is represented by blue dots to indicate the duty cycle deviation (dimensionless), the right side of the vertical axis is represented by orange solid lines to indicate the delay adjustment steps, and the gray dashed lines represent the zero reference line of the standard symbol period deviation.

[0067] The figure shows that the duty cycle deviation gradually decreases as the detection sequence number increases. In the initial stage of the detection sequence, the duty cycle deviation is relatively large, around 0.05; subsequently, the duty cycle deviation decreases rapidly, reaching nearly 0.01 when the detection sequence number is around 100; as the detection sequence number continues to increase, the duty cycle deviation approaches zero and remains within a low fluctuation range during subsequent detections, close to the zero line of the standard symbol period deviation. The corresponding delay adjustment step count curve rises rapidly in the early stage of the detection sequence number, increasing from zero to approximately 60 steps, and then remains stable. This indicates that the output-side duty cycle calibration module dynamically adjusts the delay steps of the adjustable delay line according to the duty cycle deviation in the initial stage to calibrate the duty cycle of the output signal; after reaching a stable state, the delay adjustment step count remains constant, indicating that the duty cycle calibration is complete and the output signal duty cycle has been effectively corrected.

[0068] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for transmitting Ethernet signals using an Ethernet switch, characterized in that, The method includes: The Ethernet signal received at the ingress port is oversampled, the position of the transition edge of each bit is extracted, and the phase offset value of the transition edge relative to the local clock is recorded. Based on the sign and magnitude of the phase offset, the receiving clock at the input port is divided into leading, synchronous, and lagging states, and the time slot length corresponding to the lagging state is used as the minimum adjustment step size. The received signal is delayed and compensated according to the minimum adjustment step size to obtain the signal to be exchanged that is aligned with the global reference clock; Identify the free intervals between Ethernet frames in the signal to be switched, insert tag symbols with port identifiers into the free intervals, and record the insertion positions of the tag symbols in the signal to be switched. The signal to be exchanged after inserting the tag code is sent to the switching matrix. The switching matrix forwards the signal to be exchanged to the destination port according to the port identifier in the tag code. At the output side of the destination port, after detecting the tag symbol, the tag symbol is removed according to the insertion position, and the duty cycle of the output signal is calibrated by using the signal level change before and after the tag symbol.

2. The Ethernet signal transmission method for an Ethernet switch according to claim 1, characterized in that, The process of oversampling the Ethernet signal received at the ingress port, extracting the transition edge position of each bit, and recording the phase offset value of the transition edge relative to the local clock includes: The received signal is continuously sampled using a sampling clock that has been multiplied by the local clock to obtain continuous sampling points. When the amplitude difference between adjacent sampling points changes from negative to positive or from positive to negative, the location of that sampling point is determined to be a transition edge. The time difference between the transition edge and the rising edge of the local clock is used as the phase offset value of the bit.

3. The Ethernet signal transmission method for an Ethernet switch according to claim 1, characterized in that, The process of dividing the received clock at the input port into leading, synchronous, and lagging states based on the sign and magnitude of the phase offset value, and using the time slot length corresponding to the lagging state as the minimum adjustment step size, includes: The phase offset values ​​of several bits received consecutively from the same port are arranged in chronological order to form a phase offset sequence; Count the number of offsets greater than zero and the number of offsets less than zero in the phase offset sequence; If the proportion of the number of offsets greater than zero to the sequence length exceeds the first preset proportion, the receiving clock is determined to be in an advanced state. If the proportion of the number of offsets less than zero to the sequence length exceeds the second preset proportion, the receiving clock is determined to be in a lagging state. Otherwise, the receiving clock is determined to be in a synchronized state; In the lag state, the time slot length corresponding to the median of the absolute values ​​of all negative phase offsets is taken as the minimum adjustment step size.

4. The Ethernet signal transmission method for an Ethernet switch according to claim 1, characterized in that, The step of performing delay compensation on the received signal according to the minimum adjustment step size to obtain the signal to be exchanged aligned with the global reference clock includes: The received signals are written into the buffer of the ingress port in the order of arrival; When a signal needs to be read from the buffer, a wait time is inserted between two adjacent bits with the minimum adjustment step size; When the accumulated waiting time reaches one bit cycle, skip one sampling point in the buffer and use the skipped sampling point as the starting point of the next bit.

5. The Ethernet signal transmission method for an Ethernet switch according to claim 1, characterized in that, The process of identifying the idle intervals between Ethernet frames from the signal to be switched, inserting tag symbols with port identifiers within the idle intervals, and recording the insertion positions of the tag symbols in the signal to be switched includes: The interval between adjacent transition edges of the signal to be exchanged is detected, and continuous regions with intervals greater than the frame header preamble interval are identified as free intervals. In the idle interval, select the idle symbol position closest to the frame header of the next frame, encode the port identifier as a tag symbol, and insert it into that position; The offset of the idle symbol position relative to the first transition edge of the preamble of the next frame header is recorded as the insertion position.

6. The Ethernet signal transmission method for an Ethernet switch according to claim 1, characterized in that, The step of sending the signal to be exchanged after inserting the tag code to the exchange matrix, and the exchange matrix forwarding the signal to be exchanged to the destination port according to the port identifier in the tag code, includes: The port identifiers in the tag code elements are parsed using the exchange matrix to obtain the input port information; The port identifier is compared bit by bit with the port number of each entry in the port mapping table in the exchange matrix to obtain the comparison result; When the difference in the comparison result is zero, the destination port number of the corresponding entry will be used as the forwarding destination port. Based on the forwarding destination port, set the selection state of the cross switch of the switching matrix so that the input channel is connected to the destination output channel.

7. The Ethernet signal transmission method for an Ethernet switch according to claim 1, characterized in that, The step of detecting a tag symbol at the output side of the destination port, removing the tag symbol according to its insertion position, and calibrating the duty cycle of the output signal using the signal level change before and after the tag symbol includes: In the bit stream at the output side, find the corresponding bit position according to the insertion position; Extract the binary sequence of the same length as the tag code at that bit position and compare it with the pre-stored tag code; If they are completely identical, then the binary sequence is deleted from the bitstream; The duration from the start edge to the end edge of the tag symbol is measured, and the duration is compared with the standard symbol period to obtain the duty cycle deviation. Adjust the rising edge delay parameter or falling edge delay parameter of the waveform shaper on the exit side according to the duty cycle deviation.

8. The Ethernet signal transmission method for an Ethernet switch according to claim 5, characterized in that, The tag code elements are generated in the following way: Convert the port identifier into a binary sequence, add a start boundary field at the beginning of the binary sequence, and add an end boundary field at the end; The check field is generated by inverting each bit of the binary sequence between the start boundary field and the end boundary field and then concatenating them bit by bit. Arrange the start boundary field, binary sequence, check field, and end boundary field in order to obtain the tag code.

9. The Ethernet signal transmission method for an Ethernet switch according to claim 4, characterized in that, The skipping of a sampling point in the buffer includes: When the accumulated waiting time reaches one bit cycle, determine whether the amplitude of the current sampling point is the same as the amplitude of the previous sampling point; If they are the same, skip the current sampling point; If they are different, the current sampling point is not skipped, and the judgment is made again when the next adjacent bit boundary is reached.

10. A method for transmitting Ethernet signals in an Ethernet switch according to claim 6, characterized in that, The step of performing a bitwise XOR comparison between the port identifier and the port number of each entry in the port mapping table in the exchange matrix includes: Read an entry from the port mapping table and obtain the valid bits of that entry; When the valid bit is high, the port number of the table entry is compared bit by bit with the port identifier in the tag code. If at least one bit is different, discard the entry and read the next entry; If all bits are the same, the output port corresponding to that entry is determined as the forwarding destination port.

Images