A PRP protocol data receiving method and device based on FPGA implementation

Abstract

The application discloses a PRP protocol data receiving method and device based on FPGA, and belongs to the technical field of industrial Ethernet communication. The method comprises the following steps: receiving a data frame through a dual-port, extracting feature information in parallel during a streaming receiving process and attaching the feature information to the data frame, setting the port identification field at the PRP redundant control label position as the same value during the extraction to eliminate the difference between the dual-port redundant frames, multiplexing a check calculation timing, completing frame check and length detection in parallel, synchronously completing message type judgment and marking, judging the data frame marked as the PRP message type based on the feature information, discarding the repeated and later data frame, and transmitting the non-PRP message. The application can complete deduplication without buffering the whole frame, greatly shortens the PRP message receiving processing delay, effectively reduces the FPGA logic and storage resource occupation, and can support higher processing bandwidth under limited resources.

Description

Technical Field

[0001] This invention belongs to the field of industrial Ethernet communication technology, specifically relating to a PRP protocol data receiving method and apparatus based on FPGA implementation. Background Technology

[0002] Parallel Redundancy Protocol (PRP) is a core protocol for achieving high-availability communication in the industrial Ethernet field. It transmits the same data frames simultaneously through dual redundant links, and the receiving end performs deduplication on duplicate frames, thereby achieving redundant communication with zero switching time. It is widely used in scenarios with extremely high requirements for communication reliability and real-time performance, such as smart grids, rail transit, and industrial automation.

[0003] Currently, the reception and deduplication of PRP messages generally adopt a serial processing architecture: first, the received message is identified as a PRP message, then feature fields for matching are extracted, and finally, redundant frames are compared and deduplicated based on the feature fields. This type of solution often relies on CPU / DSP software processing or uses serially executed hardware logic.

[0004] The aforementioned existing technical solutions have the following drawbacks: First, the processing latency is large, which cannot meet the requirements for deterministic low latency. Due to the use of a serial process of "first identify, then extract, then match", feature extraction can only be started after the message type is identified, and feature calculation and comparison can only begin after the complete message is received. The entire processing link introduces additional buffering and waiting latency, which makes it difficult to meet the zero-latency forwarding requirements in industrial control scenarios.

[0005] Second, on-chip cache resources are expensive. The serial processing mechanism requires caching the complete received message before performing feature extraction and matching operations. The cache resource usage increases linearly with the message length, which consumes a large amount of FPGA on-chip storage resources in long frame and high bandwidth scenarios.

[0006] Third, the trade-off between processing bandwidth and resource consumption is significant. Message matching throughput is highly dependent on the scale of hardware logic resources; increasing processing bandwidth requires a corresponding increase in computing and storage resources. Under conditions of limited FPGA resources, it is difficult to simultaneously achieve high-bandwidth processing and low resource consumption, limiting the deployment and application of the PRP protocol in high-speed industrial networks.

[0007] Therefore, how to achieve low-latency, high-bandwidth PRP message reception and redundancy deduplication processing under limited hardware resources is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0008] The purpose of this invention is to provide a PRP protocol data receiving method and apparatus based on FPGA, so as to achieve low latency and high bandwidth PRP protocol data reception and redundancy deduplication processing, thereby improving processing performance while effectively reducing the FPGA on-chip storage and logic resource consumption.

[0009] To address the aforementioned technical problems, this invention provides a PRP protocol data reception method implemented using FPGA, comprising: S1. Receive data frames through dual ports; during the streaming reception of the data frames, extract the feature information of the data frames in parallel and append it to the data frames; when extracting the feature information, set the port identifier field corresponding to the PRP redundancy control tag position in the data frame to the same value to eliminate the port difference of the dual-port redundant frames. S2. Utilizing the verification calculation timing during the data frame reception process, frame verification and length detection are performed in parallel, and data frames that fail verification or whose frame length does not meet the preset range are discarded; at the same time, message type determination is performed synchronously based on the extracted feature information, and the data frames are marked according to the message type. S3. Based on the feature information, perform deduplication on the data frames marked as PRP message type, and discard duplicate and later data frames; for the data frames marked as non-PRP message type, pass through and receive them.

[0010] According to the above scheme, the feature information includes: first feature information, second feature information, and third feature information; The first feature information is the CRC8 value calculated based on the source MAC address of the data frame; The second feature information is obtained by setting the port identifier field corresponding to the PRP redundancy control tag position in the data frame to the same value, and then performing CRC32 operation on all content from the start of the data frame to the FCS field to obtain the second feature information. The third feature information includes the field combination corresponding to the PRP redundancy control tag position in the data frame and the physical port identifier.

[0011] According to the above scheme, the deduplication determination is performed based on dual storage areas; the dual storage areas include a first storage area and a second storage area; the first storage area includes multiple storage slices, each storage slice includes multiple storage entries, and the storage entries are used to store concatenated information composed of physical port identifiers and second feature information; the second storage area is used to store the valid flag bits of the entries, as well as the write address pointers of the storage slices; the storage entries correspond one-to-one with the valid flag bits, and the write address pointers correspond one-to-one with the storage slices.

[0012] According to the above scheme, the plagiarism detection includes: Using the first feature information as a region index, locate the target storage region in the first storage region; The splicing information of the current data frame is compared with all valid storage entries in the target storage area. If there are matching entries with different physical port identifiers and the same second feature information, the current data frame is determined to be a duplicate PRP message; otherwise, the current data frame is determined to be a non-duplicate PRP message.

[0013] According to the above scheme, the matching comparison with all valid storage entries in the target storage area includes: All storage entries within the target storage area are read in parallel within the same clock cycle; All read storage entries are divided into several groups, and each group is compared in parallel. The matching comparison of all storage entries is completed within multiple clock cycles.

[0014] According to the above scheme, after the current data frame is determined to be a duplicate PRP message, the current data frame is discarded and the storage entry is cleared. The storage entry clearing includes: clearing the storage entry containing the splicing information that matches the current data frame to zero, and setting the valid flag position corresponding to the storage entry to free.

[0015] According to the above scheme, after the current data frame is determined to be a non-duplicate PRP message, a cyclic write operation is performed; the cyclic write operation includes: Write the splicing information of the current data frame into the storage entry according to the write address pointer corresponding to the target storage area; Set the valid flag corresponding to the storage entry to occupied, and increment the write address pointer corresponding to the target storage area once cyclically within the storage range of the target storage area.

[0016] According to the above scheme, after completing frame verification and length detection, step S2 also includes reception time compensation: calculate the dwell time of the data frame in the front-end receiving module based on the length of the data frame, and correct and compensate the reception timestamp of the data frame.

[0017] According to the above scheme, after determining that the current data frame is a non-repeating PRP message, the current data frame is received according to the set transmission mode; when in RCT field processing mode, the PRP redundancy control tag field of the current data frame is removed or retained according to the specific settings of the mode before the current data frame is received; when in message pass-through mode, the additional feature information of the current data frame is removed before the current data frame is received.

[0018] The present invention also provides a PRP protocol data receiving device based on FPGA, comprising: The receiving and extraction module is used to receive data frames through dual ports; during the streaming reception of data frames, the feature information of the data frames is extracted in parallel and appended to the data frames; when extracting the feature information, the port identifier field corresponding to the PRP redundancy control tag position in the data frame is set to the same value to eliminate the port difference of the dual-port redundant frames. The verification and classification module is used to perform frame verification and length detection in parallel by utilizing the verification calculation timing during the data frame reception process, and discarding data frames that fail verification or whose frame length does not meet the preset range; at the same time, it performs message type determination based on the extracted feature information and marks the data frames according to the message type. The deduplication processing module is used to determine the deduplication of data frames marked as PRP message type based on the feature information, discard duplicate and later data frames, and transmit data frames marked as non-PRP message type through the transmission.

[0019] Beneficial effects Compared with existing technologies, this invention extracts feature information in parallel during the streaming reception of data frames and synchronously completes message type determination by reusing the verification calculation timing. It eliminates the need to buffer the entire frame before performing serial processing, significantly reducing the reception and processing latency of PRP messages and achieving near-zero latency redundancy deduplication. At the same time, the port identifier field is normalized during the feature extraction stage to eliminate the inherent differences between dual-port redundant frames, allowing feature information to be directly used for redundant frame matching and determination. This ensures accurate deduplication without consuming excessive additional logic and storage resources, and can support higher processing bandwidth with limited FPGA resources.

[0020] Furthermore, a dual-storage architecture that separates data and indexes is adopted, storing the concatenated data of port identifiers and feature information, valid flags, and write address pointers in separate areas, ensuring independent and efficient index management. By dividing storage entries into segments, the target comparison range can be quickly located, significantly reducing the matching scale of a single deduplication and improving processing efficiency. Each segment independently manages write pointers and valid status, facilitating the cyclic reuse and orderly management of storage space, and supporting higher message processing throughput with limited storage resources.

[0021] Furthermore, by using the first feature information as the area index to locate the target storage area, the matching comparison of the entire database is converged into a single area, which greatly reduces the number of comparison entries in a single deduplication and effectively improves the matching efficiency. At the same time, by combining the port identifier and the second feature information for two-factor matching judgment, it can accurately distinguish between cross-port PRP redundant duplicate frames and non-redundant data streams on the same port, and effectively reduce misjudgments caused by single check value conflicts, significantly improving the accuracy of redundant frame identification. Attached Figure Description

[0022] Figure 1This is a schematic diagram of the PRP terminal deployment topology according to an embodiment of the present invention; Figure 2 This is a block diagram of the overall architecture of a PRP protocol transparent redundancy transceiver device according to an embodiment of the present invention; Figure 3 This is a flowchart of a PRP message receiving and deduplication process according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a dual-storage area message index storage structure according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the input data format bit field of a filtering processing module according to an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0024] The PRP protocol data receiving method and apparatus based on FPGA provided in this invention are implemented based on the FPGA hardware parallel processing architecture. By taking advantage of the parallel computing of FPGA, the message scheduling and management logic can be flexibly designed. It can achieve compatibility and adaptation between Parallel Redundancy Protocol (PRP) messages and regular messages in multiple service scenarios, and ensure deterministic low latency and high reliability of data reception. It is suitable for scenarios with extremely high requirements for real-time and reliability communication, such as industrial control, rail transit, and smart grids.

[0025] See Figure 1 The method and apparatus of this embodiment are deployed in an industrial high-reliability dual-network redundant communication topology with the PRP terminal as the core node for redundancy processing. The PRP terminal has built-in PRP redundancy control logic and has multiple channels of dual Ethernet independent transceiver channels: in the vertical direction, it is directly connected to the network terminal to realize the data aggregation and distribution of the upper-layer business terminal; in the horizontal direction, it is bidirectionally connected to multiple network switches (switch 1 to switch N), respectively accessing two physically isolated independent switching networks, thereby constructing an A and B dual-redundant communication plane, which is suitable for industrial sites with strict requirements for zero packet loss and high fault tolerance in communication.

[0026] Based on the above deployment, this solution has the following characteristics: First, seamless redundancy and fault tolerance. When any single link or switch fails, the PRP terminal automatically filters duplicate packets and switches to the normal link, ensuring zero interruption and zero switching latency in business communication. Second, compatibility with ordinary single-network terminals. The network terminal does not need to support PRP itself; dual-network redundancy can be achieved through just one PRP terminal, significantly reducing the workload of on-site equipment modification. Third, flexible network expansion. It supports the access of multiple switches and can be adapted to large-scale distributed industrial sites, balancing redundancy reliability and network scalability.

[0027] See Figure 2 The internal logic of the FPGA is functionally divided into the PRP receiving side and the PRP sending side. The receiving side includes a message parsing module (corresponding to the receive extraction module, labeled RGMII_PRP_RX0~RGMII_PRP_RXn in the figure, where RGMII_PRP_RX0 and RGMII_PRP_RX1 correspond to the dual-port receive channels of network ports 0 and 1 of the device, and RGMII_PRP_RXn-1~RGMII_PRP_RXn are the receive channels of multiple extended network ports), a message processing module (corresponding to the verification and classification module, labeled PRP_MAC_RX in the figure, the MAC layer of one message processing module processes the reception of two ports simultaneously), and a filtering processing module for PRP messages and ordinary messages (corresponding to the deduplication processing module, labeled PRP_RX_FIRTER in the figure); the sending side includes a PRP data message sending module (labeled DP_PRP_TX in the figure), a message sending MAC layer module (labeled PRP_MAC_TX in the figure), and a multi-port sending processing module (labeled RGMII_PRP_TX0~RGMII_PRP_TXn in the figure). The entire process of receiving, judging, and forwarding is completed by FPGA hardware logic without software intervention, thereby achieving deterministic low-latency and near-zero-latency message processing.

[0028] This embodiment discloses a PRP protocol data reception method implemented based on FPGA, including steps S1 to S3. The streaming reception timing of each step uses multiplexed data frames and is executed in parallel, eliminating the need to buffer entire frames before serial processing. The specific implementation of each step is described in detail below with reference to the receiving module.

[0029] S1. Receive data frames through dual ports; during the streaming reception of the data frames, extract the feature information of the data frames in parallel and append it to the data frames; when extracting the feature information, set the port identifier field corresponding to the PRP redundancy control tag position in the data frame to the same value to eliminate the port difference of the dual-port redundant frames.

[0030] Specifically, this step is performed by the message parsing module (corresponding to...). Figure 2The RGMII_PRP_RXn module is used for implementation. The message parsing module performs real-time parsing of message fields based on the input content of the network message, extracts the MAC field of the message in advance, and records the message reception time information. Unlike the existing serial matching scheme that "first completes PRP message type identification, and then performs message comparison and feature extraction" (the message matching throughput rate of this type of scheme is highly dependent on the scale of hardware logic resources, and resource consumption directly limits the processing bandwidth), this embodiment utilizes the advantages of FPGA parallel computing. According to the data format of the PRP message, it completes key field extraction and feature operation in parallel within the transmission sequence of the original data stream, and simultaneously completes message reassembly. This avoids the buffer resource overhead caused by the traditional scheme of receiving the complete message and then repeating the operation, while significantly reducing the message processing latency.

[0031] In the process of extracting feature information, the port identifier field corresponding to the PRP redundancy control tag position in the data frame is set to the same value. The port identifier field is the only field that differs between the redundant frames transmitted by ports A and B. After normalizing it to the same value (e.g., setting it to 0), the port difference between the dual-port redundant frames is eliminated, so that the subsequent redundancy determination based on feature information is not affected by the port difference.

[0032] Furthermore, the feature information includes first feature information, second feature information, and third feature information.

[0033] The first feature information is the CRC8 value calculated based on the source MAC address of the data frame: the message parsing module extracts the source MAC address in the data frame and performs CRC8 operation, and then uses the operation result as the first feature information, which is used as the area index for subsequent deduplication.

[0034] The second feature information is obtained as follows: after setting the port identifier field at the corresponding PRP redundancy control tag position in the data frame to the same value, a CRC32 operation is performed on all content from the start of the data frame to the Ethernet FCS field to obtain the second feature information. That is, the calculation range for CRC32 check is set to all message content from the start of the data frame to the FCS field, and during the calculation process, the port identifier field in the PRP redundancy control tag is replaced with the same value (e.g., replaced with 0) before participating in the CRC32 operation, thus ensuring that the redundant frames of ports A and B obtain consistent second feature information. The second feature information is pre-calculated and stored during the extraction stage and used as the basis for content verification during subsequent deduplication.

[0035] The third feature information includes a combination of fields corresponding to the PRP redundancy control tag position in the data frame and a physical port identifier; specifically, it includes a combination of the port identifier field, length field (SIZE), and suffix field (SUFFIX) in the PRP redundancy control tag, and the physical port identifier (PORT) corresponding to the data frame. This third feature information is used for subsequent message type determination and dual-port differentiation.

[0036] S2. Utilizing the verification calculation timing during the data frame reception process, frame verification and length detection are performed in parallel, and data frames that fail verification or whose frame length does not meet the preset range are discarded; at the same time, message type determination is performed synchronously based on the extracted feature information, and the data frames are marked according to the message type.

[0037] Specifically, this step is performed by the message processing module (corresponding to...) Figure 2 The PRP_MAC_RX implementation allows a message processing module's MAC layer to simultaneously process received data from two ports (RGMII_PRP_RX0 and RGMII_PRP_RX1). The message processing module decodes the messages input from the message parsing module and, using FPGA parallel computing, synchronously completes the following checks within the CRC checksum calculation timeline during data frame reception: Firstly, frame verification and length detection. CRC verification and length judgment are performed on the data frames input from both ports. If the data frame has a CRC field error, is too short, or is too long (i.e., the frame length does not meet the preset range), it will be discarded or an abnormal message alarm will be issued according to the system configuration.

[0038] Secondly, message type determination and marking. Based on the extracted third feature information, message type determination is performed synchronously: whether the current data frame is a PRP message is determined by whether the suffix field SUFFIX is 0x88FB, whether the length field SIZE matches, and whether the port identifier field indicates port A / B; and whether the current data frame is a monitoring message is determined by whether the destination MAC address of the data frame is 01-15-4E-00-01-XX and whether the type field is 0x88FB. Based on this, the data frame is marked as a PRP message type, a non-PRP message type, or a monitoring message type for subsequent processing.

[0039] Third, dual-port data merging. The message processing module processes the data from both ports and merges them into a single output. The subsequent module distinguishes which port the data frame comes from based on the physical port identifier (PORT) in the third feature information.

[0040] Since the above detections are performed synchronously with the CRC calculation of the original data stream, message type parsing and field extraction are completed simultaneously, thus further saving message filtering and aging time.

[0041] Furthermore, step S2, after completing frame verification and length detection, also includes reception time compensation: calculating the dwell time of the data frame in the preceding receiving module based on the data frame length, and correcting and compensating the data frame's reception timestamp. Specifically, the message processing module parses the input PRP message into a data stream mode, calculates the dwell time of the data frame in the message parsing module (RGMII_PRP_RXn) and the hardware link (whose delay is a fixed software configuration value) based on the data frame length, and corrects the reception time recorded by the message parsing module accordingly, thereby directly completing reception time compensation on the MAC side. Since the message processing delay can be measured and compensated on the MAC side, the accuracy of the message upload time is ensured.

[0042] S3. Based on the feature information, perform deduplication on the data frames marked as PRP message type, and discard duplicate and later data frames; for the data frames marked as non-PRP message type, pass through and receive them.

[0043] Specifically, this step is handled by the filtering module (corresponding to...) Figure 2 The filtering module receives data from the packet processing module. This data frame already contains first feature information, second feature information, third feature information, and physical port identifier. The filtering module determines whether the current data frame is a PRP packet based on the network interface type (ETH_TYPE): for non-PRP packet types, the additional feature information is removed and the data is directly transmitted and uploaded; for PRP packet types, the deduplication process is initiated based on the feature information. See [link to relevant documentation] for details. Figure 3 For the data format of the input filtering processing module, please refer to [link / reference]. Figure 5 The meanings of each field in the diagram are as follows.

[0044] SOP (Start of Frame) and EOP (End of Frame): These are used to identify the start and end of a data frame, respectively; the case where EOP is not zero only occurs in the last data tick.

[0045] RSV (Reserved Field): Fields that are not of interest; the default value is 0.

[0046] ETH_TYPE (Network Interface Type Field): Used to identify the type of network interface data frame. The filtering module uses this field to determine whether the current data frame is a PRP message.

[0047] PORT (Physical Port Identifier Field): Used to identify the physical port to which the data frame belongs, in bytes.

[0048] LEN (Length Field): Used to indicate the length of the data frame, in bytes.

[0049] CRC8 (First Feature Information Field): This is the CRC8 value calculated based on the source MAC address, which is used as the area index in subsequent deduplication judgment.

[0050] CRC32 (Second Feature Information Field): This is the CRC32 value calculated by modifying all bytes before the CRC field and the port identifier field (original A / B flag byte) in the PRP redundancy control tag to the same value. It is used as the basis for content verification in deduplication judgment.

[0051] The third feature information (RCT field combination): It is composed of the port identifier field LANID, the length field SIZE and the suffix field SUFFIX in the PRP redundancy control tag. It is output in the last data beat of the data frame and is used for message type judgment and port differentiation.

[0052] Furthermore, the plagiarism detection is performed based on a dual-storage area; the dual-storage area includes a first storage area and a second storage area. See also Figure 4 Both storage areas use the first feature information (CRC8) corresponding to the second feature information (CRC32) as the basis for area retrieval and collaboratively store message index information.

[0053] The first storage area (used to record the checksum information of received packets according to the source address) includes multiple storage areas, each storage area includes multiple storage entries, and the storage entries are used to store the concatenated information composed of the physical port identifier and the second feature information. In this embodiment, the first storage area is divided into 256 storage areas from 0 to 255 based on the first feature information (CRC8 value of the source MAC address); each storage area is allocated 16 storage entries, and the word width of a single storage entry is 36 bits, which can completely accommodate the concatenated information composed of the physical port identifier (PORT) and the second feature information (CRC32) without the need to set additional valid bits.

[0054] The second storage area (used to record valid information of received messages by source address and the address of the next update for each storage area) stores the valid flag bits of entries and the write address pointers of storage areas; each storage entry corresponds one-to-one with the valid flag bits, and each write address pointer corresponds one-to-one with the storage area. In this embodiment, the second storage area is set independently of the first storage area and is divided into 256 groups of entries from 0 to 255, where the valid flag bits VLD0 to VLD255 correspond to the valid status of each storage area from 0 to 255, and each group of entries also includes the next write address pointer for the corresponding storage area. A valid flag bit of 0 indicates that there are no valid records in the storage area, and a valid flag bit of 1 indicates that there is at least one valid record in the storage area and contains the written address. It should be noted that the valid flag bits do not participate in the matching judgment of the second feature information (CRC32) and are only used to quickly skip empty storage areas or judge the validity of storage areas.

[0055] By adopting the dual storage area architecture that separates data and index, the splicing information, valid flags, and write address pointers are stored in separate areas, making index management independent and efficient. At the same time, by dividing the storage entries into areas, the target comparison range can be quickly located, significantly reducing the matching scale of a single deduplication and supporting a higher message processing throughput with limited storage resources.

[0056] After the device is powered on, a zeroing operation is performed on the first and second storage areas: all addresses in the first storage area are traversed, and the storage cells are initialized to all zeros; all entries in the second storage area are traversed, and the valid flag bit and write address pointer are initialized to 0. The first storage area has a bit width of 36 bits and is used to store the data concatenated from the physical port identifier and the second feature information; the second storage area is used to store the valid flag bit and write address pointer of the corresponding storage area.

[0057] Furthermore, the deduplication determination includes: using the first feature information as a segment index to locate the target storage segment in the first storage area; matching and comparing the splicing information of the current data frame with all valid storage entries in the target storage segment; if there are matching entries with different physical port identifiers and consistent second feature information, the current data frame is determined to be a duplicate PRP message; otherwise, the current data frame is determined to be a non-duplicate PRP message.

[0058] Specifically, upon receiving a message request, the physical port identifier (PORT), second feature information (CRC32), and first feature information (CRC8) are extracted from the data frame; the first feature information (CRC8) is used as the segment index to locate the 16-word segment base address of the target storage segment in the first storage area.

[0059] Furthermore, the matching comparison with all valid storage entries in the target storage area includes: reading all storage entries in the target storage area in parallel within the same clock cycle; dividing all read storage entries into several groups, comparing each group in parallel, and completing the matching comparison of all storage entries within multiple clock cycles. In this embodiment, utilizing the parallel computing characteristics of the FPGA, 16 storage entries in the target storage area are read in parallel within one clock cycle, and a two-stage comparison pipeline is constructed: in each stage, the splicing information (physical port identifier and second feature information) of 8 storage entries is compared in parallel with the splicing information of the current data frame. The first stage uses CRC8 plus an offset of 0~7 as an index, and the second stage uses CRC8 plus an offset of 8~15 as an index. Thus, the entire traversal of the 16-word storage area can be completed in only 2 clock cycles, greatly reducing the deduplication delay and adapting to high-speed network environments.

[0060] Result Determination: If a matching entry with different physical port identifiers and identical second feature information appears in the two comparisons, the current data frame is determined to be a duplicate PRP message; if no matching entry appears in either comparison, the current data frame is determined to be a non-duplicate PRP message, and the process jumps to the loop writing procedure. It should be noted that in this embodiment, "duplicate" is strictly limited to "different physical port identifiers and identical second feature information," meaning that only when the physical ports are different and the message checksums are the same are they considered duplicate frames under the PRP protocol; if the second feature information and the physical port identifier are the same, they are considered different data streams, and no duplicate determination is triggered. Therefore, by using a two-factor matching of the second feature information and the physical port identifier, legitimate duplicate PRP frames and abnormal frames from the same port can be accurately distinguished, avoiding the misjudgment problem of traditional single CRC32 schemes under hash collisions.

[0061] Furthermore, after the current data frame is determined to be a duplicate PRP message, the current data frame is discarded, and storage entry clearing is performed. Storage entry clearing includes: zeroing the storage entry containing the splicing information matching the current data frame, and simultaneously setting the valid flag bit corresponding to that storage entry to free. Specifically, the content of the matching entry in the first storage area is zeroed (physical port identifier and second feature information are set to 0), the valid flag bit of the corresponding entry in the second storage area is zeroed to release index resources, and the write address pointer of that storage area in the second storage area remains unchanged. The determination result "duplicate" is returned along with the physical port identifier corresponding to that entry.

[0062] By adopting the above self-cleaning duplicate processing strategy instead of simply discarding, we can effectively deal with the extreme scenario where the first feature information (CRC8) and the second feature information (CRC32) conflict at the same time, ensuring that the backup message can be successfully reported at least once, and implementing the data integrity principle of "better too much than too little".

[0063] Further, after the current data frame is determined to be a non-duplicate PRP message, a cyclic write operation is performed. The cyclic write operation includes: writing the concatenation information of the current data frame into a storage entry according to the write address pointer corresponding to the target storage area; setting the valid flag corresponding to the storage entry to occupied, and cyclically incrementing the write address pointer corresponding to the target storage area once within the storage range of the target storage area. Specifically, the write address is determined by adding the current write address pointer offset (0~15) in the second storage area to the base address of the storage area determined by the first feature information (CRC8). The write data is a 36-bit concatenation information formed by concatenating the physical port identifier of the current data frame with the second feature information. Subsequently, the corresponding valid flag in the second storage area is set to 1 to indicate that there is valid data in the storage area, and the write address pointer is incremented by 1, and the increment is limited to the range of 0~15 (i.e., modulo 16 counting).

[0064] By using a 16-word memory area for cyclic overlay and a separate second memory area to manage the valid flag and write address pointer, efficient cyclic reuse of memory space can be achieved without introducing additional valid bits, significantly reducing on-chip RAM resource consumption.

[0065] Furthermore, after determining that the current data frame is a non-repeating PRP message, the current data frame is received according to the set transmission mode; when in RCT field processing mode, the PRP redundancy control tag field of the current data frame is removed or retained according to the specific settings of the mode before the current data frame is received; when in message pass-through mode, the feature information attached to the current data frame is removed before the current data frame is received.

[0066] Specifically, for data frames marked as PRP message type and determined to be duplicates, in PRP message deduplication mode, the duplicate PRP message is discarded. For PRP messages determined to be non-duplicates, if in RCT field processing mode, the PRP redundancy control tag field is removed before uploading, or it is uploaded without removing the PRP redundancy control tag field, depending on the specific settings. If in message pass-through mode, the additional feature information attached to the data frame is removed before the message is directly uploaded. For data frames marked as non-PRP message type, their additional feature information is also removed before direct pass-through and upload.

[0067] This embodiment combines the area index of the first feature information (CRC8), the content verification of the second feature information (CRC32), and the port differentiation of the physical port identifier (PORT), forming a three-level conflict avoidance mechanism of CRC8, CRC32, and physical port identifier, significantly improving the stability and reliability of the system under large-scale concurrent packets. This embodiment utilizes the standard process of data reception and CRC judgment to complete the parsing and feature value processing of PRP data, saving deduplication time. Furthermore, packet processing latency is measurable and compensated on the MAC side, ensuring the accuracy of upload time. In addition, this embodiment adaptively parses network packets based on the extracted packet content, can autonomously parse local packets and adapt to configuration lists, and has high flexibility in processing PRP packets and ordinary packets.

[0068] Example 2 This embodiment provides a PRP protocol data receiving device based on FPGA, including a receiving and extraction module, a verification and classification module, and a deduplication processing module. Each module is implemented by FPGA hardware logic, and its functions correspond one-to-one with the steps and hardware modules on the receiving side in Embodiment 1.

[0069] Receive and extract module (corresponding) Figure 2 The message parsing module (RGMII_PRP_RXn) is used to receive data frames through dual ports. During the streaming reception of data frames, it extracts the feature information of the data frames in parallel and appends it to the data frames. When extracting the feature information, the port identifier field corresponding to the PRP redundancy control tag position in the data frame is set to the same value to eliminate the port difference of the dual-port redundant frames. Specifically, the receiving extraction module parses the message fields in real time, extracts the MAC field in advance and records the reception time information. Within the transmission time sequence of the original data stream, it calculates the first feature information (CRC8 value of the source MAC address), the second feature information (CRC32 value of the content from the start of the data frame to the FCS field after setting the port identifier field to the same value), and the third feature information (the combination of the port identifier field, length field SIZE, suffix field SUFFIX in the PRP redundancy control tag and the physical port identifier PORT) in parallel and completes message reassembly synchronously.

[0070] Verification and classification module (corresponding) Figure 2The message processing module (PRP_MAC_RX) utilizes the verification calculation timing during data frame reception to perform frame verification and length detection in parallel, discarding data frames that fail verification or whose length does not meet the preset range. Simultaneously, it synchronously determines the message type based on extracted feature information and marks the data frames according to the message type. Specifically, the verification classification module performs CRC verification and length determination on the dual-port input data frames, discarding or issuing an alarm for CRC errors, excessively short frames, and excessively long frames according to system configuration. It determines the PRP message (based on whether SUFFIX is 0x88FB, whether SIZE matches, and whether the port identifier field indicates A / B) and the monitoring message (based on whether the destination MAC is 01-15-4E-00-01-XX and whether the type is 0x88FB) based on third feature information. It merges the dual-port data into one stream, which is then distinguished by the subsequent module based on the physical port identifier. Furthermore, the verification classification module calculates the dwell time of the data frame in the preceding receiving module and hardware link based on its length, and corrects and compensates for the received timestamp.

[0071] Deduplication processing module (corresponding) Figure 2 The filtering module PRP_RX_FIRTER is used to perform deduplication on data frames marked as PRP message type based on the feature information, discarding duplicate and later-arriving data frames; and transparently transmitting data frames marked as non-PRP message type. Specifically, the deduplication module performs deduplication based on the dual storage area (first storage area and second storage area) described in Embodiment 1: using the first feature information as the area index to locate the target storage area, and completing the matching comparison of 16 storage entries in 2 clock cycles through two-stage pipelines with 8 parallel paths per stage, determining duplicate PRP messages based on "different physical port identifiers and consistent second feature information"; discarding duplicate PRP messages and performing storage entry clearing (self-clearing), performing cyclic writing on non-duplicate PRP messages, and completing reception and uploading according to PRP message deduplication mode, RCT field processing mode, or message transparent transmission mode.

[0072] Example 3 Based on the aforementioned receiving method and apparatus, this embodiment further provides an implementation method for transmitting-side processing and overall time synchronization that works in conjunction with the receiving side, thereby constituting a complete PRP protocol transparent redundancy transceiver device. (See transmitting side for details.) Figure 2 The PRP_TX part.

[0073] PRP data packet sending module (corresponding) Figure 2The module processes two sets of data (DP_PRP_TX). In multi-port scenarios, multiple PRP data packet sending modules are instantiated according to actual needs to achieve independent processing of each sending port. For a single module, the two sets of input data can be configured to select the active port, while the other port is considered inactive. Packets from inactive ports are discarded (data should be avoided as much as possible when sending to inactive ports), non-PRP data from active ports are transparently transmitted, and PRP packets from active ports are processed, copied, and then sent to both sending ports. This module also has the function of sending monitoring packets to both ports at a specified time. Furthermore, this module performs the following functions: First, it places the padding of short packets in the sent packets before the PRP redundancy control tag, thus the PRP packet padding is completed by this module, and the padding length will not trigger the padding condition of the sending MAC layer; second, it performs PRP identification on the sent packets and copies and sends the packets that need to be copied; third, it triggers the packet assembly of monitoring packets when a monitoring pulse arrives.

[0074] The system relies on the receiving and extraction module (RGMII_PRP_RX0) to parse messages. Valid data frames, after redundancy checks, can be directly forwarded to the target device via the FPGA's output interface or passed to the internal processing module if required. The entire receiving, judging, and forwarding process is completed by the FPGA hardware logic without software intervention, achieving deterministic low-latency and near-zero-latency processing. When one redundant link fails, it can quickly switch to another link, with a communication interruption time ≤1μs. It also features data frame verification and anomaly monitoring functions, effectively preventing data loss and erroneous transmission.

[0075] Message sending MAC layer module (corresponding) Figure 2 The PRP_MAC_TX parameter in the PRP data packet sending module performs MAC layer verification on the packets output by the PRP data packet sending module, including length verification, CRC addition, and packet output timestamp feedback.

[0076] Multi-port transmission processing module (corresponding) Figure 2 The RGMII_PRP_TX0~RGMII_PRP_TXn in the protocol will send out MAC layer messages according to the message protocol. Multiple protocols such as RGMII, RMII, and GMII can be selected.

[0077] Regarding time synchronization, both the receiving side (PRP_RX) and transmitting side (PRP_TX) modules utilize gPTP and SYNCE messages to achieve high-precision phase / frequency synchronization. This enables accurate measurement of message link delay and leverages the high precision of the FPGA to achieve precise control over link delay, achieving synchronization accuracy up to the nanosecond level. The synchronization deviation of dual-path redundant data frames can reach ≤5ns. Combined with the aforementioned MAC-side receive time compensation, this invention can provide targeted compensation for link delay and data processing delay, further improving synchronization accuracy and handover reliability.

[0078] In summary, this invention utilizes an FPGA hardware parallel processing architecture and a "streaming reception, parallel extraction, and multiplexing verification timing" processing mechanism to achieve deterministic low-latency and near-zero-latency redundant deduplication and forwarding of PRP messages. It eliminates dual-port redundant frame differences through port-normalized feature extraction, reduces resource consumption and increases bandwidth (supporting up to 5Gbps high-speed data transmission) through dual storage areas separating data and indexes and a segmented parallel pipeline, and enhances reliability through a three-level conflict avoidance mechanism using CRC8, CRC32, and physical port identifiers. Simultaneously, it supports dynamic monitoring of PRP mode without system restart, is compatible with complex industrial scenarios requiring multiple redundancy modes, and boasts advantages such as high reliability, deterministic latency, high synchronization accuracy, strong compatibility, and low resource consumption.

[0079] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0080] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A PRP protocol data receiving method based on FPGA implementation, characterized in that, include: S1. Receive data frames through dual ports; During the streaming reception of the data frame, the feature information of the data frame is extracted in parallel and appended to the data frame. When extracting the feature information, the port identifier field corresponding to the PRP redundancy control tag position in the data frame is set to the same value to eliminate the port difference of the dual-port redundant frame. S2. Utilizing the verification calculation timing during the data frame reception process, frame verification and length detection are performed in parallel, and data frames that fail verification or whose frame length does not meet the preset range are discarded; at the same time, message type determination is performed synchronously based on the extracted feature information, and the data frames are marked according to the message type. S3. Based on the feature information, perform deduplication on the data frames marked as PRP message type, and discard duplicate and later data frames; for the data frames marked as non-PRP message type, pass through and receive them.

2. The PRP protocol data receiving method based on FPGA implementation according to claim 1, characterized in that, The feature information includes: first feature information, second feature information, and third feature information; The first feature information is the CRC8 value calculated based on the source MAC address of the data frame; The second feature information is obtained by setting the port identifier field corresponding to the PRP redundancy control tag position in the data frame to the same value, and then performing CRC32 operation on all content from the start of the data frame to the FCS field to obtain the second feature information. The third feature information includes the field combination corresponding to the PRP redundancy control tag position in the data frame and the physical port identifier.

3. The PRP protocol data receiving method based on FPGA implementation according to claim 2, characterized in that, The deduplication determination is performed based on a dual storage area; the dual storage area includes a first storage area and a second storage area; the first storage area includes multiple storage slices, each storage slice includes multiple storage entries, and the storage entries are used to store concatenated information composed of physical port identifiers and second feature information; the second storage area is used to store the valid flag bit of the entry and the write address pointer of the storage slice; the storage entry corresponds one-to-one with the valid flag bit, and the write address pointer corresponds one-to-one with the storage slice.

4. The PRP protocol data receiving method based on FPGA implementation according to claim 3, characterized in that, The plagiarism detection determination includes: Using the first feature information as a region index, locate the target storage region in the first storage region; The splicing information of the current data frame is compared with all valid storage entries in the target storage area. If there are matching entries with different physical port identifiers and the same second feature information, the current data frame is determined to be a duplicate PRP message; otherwise, the current data frame is determined to be a non-duplicate PRP message.

5. The PRP protocol data receiving method based on FPGA implementation according to claim 4, characterized in that, The matching comparison with all valid storage entries within the target storage area includes: All storage entries within the target storage area are read in parallel within the same clock cycle; All read storage entries are divided into several groups, and each group is compared in parallel. The matching comparison of all storage entries is completed within multiple clock cycles.

6. The PRP protocol data receiving method based on FPGA implementation according to claim 4, characterized in that, After the current data frame is determined to be a duplicate PRP message, the current data frame is discarded and the storage entry is cleared. The storage entry clearing includes: clearing the storage entry containing the splicing information that matches the current data frame to zero, and setting the valid flag position corresponding to the storage entry to free.

7. The PRP protocol data receiving method based on FPGA implementation according to claim 4, characterized in that, After the current data frame is determined to be a non-duplicate PRP message, a cyclic write operation is performed; the cyclic write operation includes: Write the splicing information of the current data frame into the storage entry according to the write address pointer corresponding to the target storage area; Set the valid flag corresponding to the storage entry to occupied, and increment the write address pointer corresponding to the target storage area once cyclically within the storage range of the target storage area.

8. The PRP protocol data receiving method based on FPGA implementation according to claim 1, characterized in that, Step S2, after completing frame verification and length detection, also includes reception time compensation: calculating the dwell time of the data frame in the front-end receiving module based on the length of the data frame, and correcting and compensating the reception timestamp of the data frame.

9. The PRP protocol data receiving method based on FPGA implementation according to claim 4, characterized in that, After determining that the current data frame is a non-repeating PRP message, the current data frame is received according to the set transmission mode. When in RCT field processing mode, the PRP redundancy control tag field of the current data frame is removed or retained according to the specific settings of the mode before the current data frame is received. When in message pass-through mode, the additional feature information of the current data frame is removed before the current data frame is received.

10. A PRP protocol data receiving device implemented based on FPGA, characterized in that, include: The receiving and extraction module is used to receive data frames through dual ports; During the streaming reception of data frames, feature information of the data frames is extracted in parallel and appended to the data frames. When extracting the feature information, the port identifier field corresponding to the PRP redundancy control tag position in the data frame is set to the same value to eliminate the port difference of the dual-port redundant frame. The verification and classification module is used to perform frame verification and length detection in parallel by utilizing the verification calculation timing during the data frame reception process, and discarding data frames that fail verification or whose frame length does not meet the preset range; at the same time, it performs message type determination based on the extracted feature information and marks the data frames according to the message type. The deduplication processing module is used to determine the deduplication of data frames marked as PRP message type based on the feature information, discard duplicate and later data frames, and transmit data frames marked as non-PRP message type through the transmission.

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