FPGA-based multi-channel video smooth switching system and method

Abstract

The application discloses a multi-path video smooth switching system and method based on FPGA, which comprises an FPGA and an external memory connected with the FPGA, wherein the FPGA is internally provided with a video timing generation module, an external video detection module, a video switching control module and a cache control module. The external video detection module judges whether the video switching occurs by detecting whether the period of the input line synchronization signal deviates from the normal range; when detecting that the switching occurs, the video switching control module starts counting and generates a flag signal; the cache control module freezes the read-write pointer of the external memory according to the flag signal, and continuously outputs the video data of the last complete picture before the switching; after the counting reaches a preset value, a new video effective judgment signal is latched, and the normal output of the new picture is restored. The application can realize the smooth switching of the multi-path video at the display end without relying on the front-end switching instruction, and effectively avoids the picture tearing, shaking or black screen phenomenon.

Description

Technical Field

[0001] This invention belongs to the field of video processing technology, specifically relating to a multi-channel video smooth switching system and method based on FPGA (Field Programmable Gate Array), which is suitable for application scenarios such as airborne displays that have high requirements for the quality of video switching. Background Technology

[0002] In airborne display systems, pilots need to view different screens as needed. These screens switch rapidly between different video sources based on pilot commands, and are ultimately displayed on the onboard monitor. For the display devices, these input videos from different sources differ in resolution, frame rate, and timing.

[0003] To simplify circuitry and save costs, some designs use multiplexers to switch multiple videos of the same format but different resolutions between multiplexers. The monitor, however, can only passively receive and display one video stream, and is typically not given specific switching instructions. This leads to screen tearing, flickering, or even black screens when the monitor relocks the signal. This is especially problematic when the input source includes analog video signals. After receiving a new signal, the analog video decoder's internal clock-locked loop, automatic gain control, and other analog circuitry require tens or even hundreds of milliseconds to stabilize before outputting a stable video sequence. Without effective processing, screen tearing, flickering, or black screens become even more pronounced. This visual interference during switching significantly impacts the pilot's visual experience.

[0004] To avoid visual interference caused by such brief switching, the traditional method is to use a matrix switcher with "seamless" switching capabilities, which typically integrates a frame synchronizer and double buffering mechanism. However, in most cases, to save costs, product vendors usually use multi-channel analog switch integrated circuits for video selection and switching. Therefore, for the monitor, the switching moment is completely random and discontinuous. The monitor can only identify the switching moment itself and process it accordingly.

[0005] Existing technologies include some FPGA-based video switching solutions, but these often rely on switching commands sent by an external master control unit to trigger the gating operation, and mostly employ double buffering or ordinary first-in-first-out (FIFO) buffering methods. When faced with the clock-locked loop and automatic gain control relocking process caused by signal switching in the analog video decoder, these solutions are prone to screen tearing, jitter, or black screen phenomena on the display because they cannot autonomously identify the switching time, failing to meet the high reliability requirements of scenarios such as airborne applications. Furthermore, existing solutions also include technologies that achieve multi-channel video switching through a unified clock source, but these address the problem of asynchronous clocks among multiple hosts and do not address the signal stabilization time issue of the analog video decoder.

[0006] Therefore, there is an urgent need for a technical solution that can detect video switching and achieve smooth screen transitions on the display without relying on front-end switching commands. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and propose a multi-channel video smooth switching system and method based on FPGA. This system and method do not rely on front-end switching instructions and can realize smooth processing of video switching screens at the display end, ensuring the temporal continuity and stability of the output video, achieving truly seamless or smooth switching, and avoiding phenomena such as screen jitter, tearing or black screen.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: A multi-channel video smooth switching system based on FPGA includes an FPGA and an external memory connected to the FPGA.

[0009] The FPGA is internally equipped with a video timing generation module, an external video detection module, a video switching control module, and a buffer control module.

[0010] The video timing generation module is used to count based on the output video pixel clock, generating the horizontal synchronization signal (hsync), vertical synchronization signal (vsync), and data enable signal (den) required for the output video. This module sends the generated timing signals to the buffer control module for FIFO (First-In-First-Out) data read operation, sends the generated vertical synchronization signal to the video switching control module for frame counting, and simultaneously outputs the timing signals and RGB data synchronously to the external video encoder for encoding output.

[0011] The external video detection module uses a local clock with the same frequency as the external video to determine the period of the input horizontal synchronization signal. When the horizontal synchronization period is greater than or less than five clock cycles of the normal period, the instability indicator signal (sig_no) is pulled high; otherwise, the instability indicator signal is pulled low and sent to the video switching control module. The normal period refers to the standard period value of the horizontal synchronization signal corresponding to the standard format of the input video.

[0012] The video switching control module connects the external video detection module and the video timing generation module, and is used for logical processing based on the unstable indication signal and the field synchronization signal. Specifically, when the unstable indication signal changes, the switching change signal (sig_chg) is pulled high, and the counter (cnt) accumulates based on the rising edge of the field synchronization signal while the switching change signal is high, until the counter reaches a preset value n, at which point the counter is reset to zero, and the switching change signal is pulled low. The flag signal (flag) is pulled high when the unstable indication signal changes, until the counter equals n-2, then pulled low, and the flag signal is output to the buffer control module as a switching control signal. The video valid judgment signal (sig_dect) latches the value of the unstable indication signal when the counter equals n, and uses it as a new video valid judgment signal to determine whether to output a normal or abnormal image. The video valid judgment signal lags the flag signal by two frames.

[0013] The value of the preset value n depends on the performance of the analog video decoder. The shorter the timing lock time after decoding, the smaller the value of n, and vice versa. In fixed applications, the value of n remains constant, and n is greater than the maximum settling time required for the decoder timing lock.

[0014] The cache control module connects the video switching control module, the video timing generation module, and the external memory, and is used to control the read and write operations of the external memory according to the flag signal. The external memory is a single static random access memory (SSRAM) chip. The cache control module divides the SSRAM into three cache regions, each cached with one complete video frame. The cache control module performs time-division multiplexing read and write operations on the SSRAM through write data FIFO and read data FIFO. It uses an intermediate clock higher than the input clock and output clock for the read and write operations of the read data FIFO and write data FIFO. Data read from the write data FIFO is written to the SSRAM, and data from the SSRAM is read out and written to the read data FIFO. The cache control module uses a first variable i and a second variable j to point to the write cache region and the read cache region, respectively, where i is cyclically incremented from 0 to 2, and j = (i + 2) mod 3, forming a stable cyclic read and write pattern of "reading the first variable, writing the first variable plus two and taking the modulo three".

[0015] When the flag signal goes high, the cache control module freezes the first variable i and the second variable j, keeping the read / write pointers unchanged, and continuously reads the video data of the cache area pointed to by the last frame read pointer before the switch; when the flag signal goes low, the loop read / write mode is restored, and the cache area where invalid data was written during the switch is refreshed with new valid video data.

[0016] The present invention also provides an FPGA-based method for smooth switching of multiple video streams in the system described above, comprising the following steps: Step S1: Use a local clock with the same frequency as the external video to determine the period of the input horizontal synchronization signal. When the horizontal synchronization period deviates from the normal range, an unstable indication signal is generated. Step S2: Perform logical processing based on the unstable indication signal and the field synchronization signal: When the unstable indication signal changes, start counting and generate a flag signal as a switching control signal; the flag signal is pulled high when the unstable indication signal changes, and pulled low when the count equals a preset value minus two; the count is accumulated according to the rising edge of the field synchronization signal when the flag signal is high, until the count reaches the preset value, at which point it is cleared and the flag signal is pulled low. Step S3: Freeze the read / write pointer of the external memory according to the flag signal, and continuously output the video data of the last complete frame before the switch; Step S4: When the count reaches a preset value, latch the value of the unstable indication signal as a new valid video judgment signal and restore the normal output of the new picture.

[0017] This invention detects the unstable state of the horizontal synchronization signal before and after video switching, using this detected signal as the basis for determining the switching operation. Upon detecting a switching event, the display refresh is immediately frozen, and the last complete frame of the image before the switching is repeatedly output until the new signal timing stabilizes, at which point the display output is seamlessly switched. This ensures a consistently stable display with smooth transitions, preventing jitter, tearing, or black screens.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention does not rely on front-end switching commands. It determines the occurrence of video switching entirely on the display side by passively detecting the period of the horizontal synchronization signal, making it suitable for application scenarios where the display cannot obtain switching commands.

[0019] 2. This invention freezes the memory read / write pointers during the switching process, continuously outputting the last complete frame of the image before the switch, thus avoiding the problems of screen tearing, jittering, or black screen caused by messy data being written to the memory due to unstable decoder timing during the switching process.

[0020] 3. This invention adopts a single SSRAM architecture with three regions for caching, which reduces pin and PCB routing resources and lowers costs; through the coordinated control of flag signals and video effective judgment signals, a smooth transition in the switching process is achieved.

[0021] 4. By setting a preset value n that matches the performance of the decoder, the present invention enables the system to flexibly adapt to different types of analog video decoders, thus achieving strong versatility. Attached Figure Description

[0022] Figure 1 This is a block diagram illustrating the application of smooth switching between multiple video streams in an embodiment of the present invention. Figure 2 This is a block diagram of the internal logic of the FPGA in an embodiment of the present invention; Figure 3 This is a timing diagram showing the transition from the presence to absence of external video in an embodiment of the present invention; Figure 4 This is a timing diagram showing the creation of external video from scratch in an embodiment of the present invention; Figure 5 This is a timing diagram of the switching between multiple external video streams in an embodiment of the present invention. Detailed Implementation

[0023] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0025] This invention provides an FPGA-based multi-channel video smooth switching system for use in airborne display scenarios. Figure 1As shown, multiple analog video signals (such as external video 1, external video 2, ..., external video n) are switched into a single signal by the multiplexer of the display processor and then sent to the video decoder of the display. After receiving the RGB data, horizontal synchronization signal (hsync), vertical synchronization signal (vsync), and data enable signal (den) output by the decoder, the FPGA works with the external SSRAM, video encoder, and LCD module to achieve smooth switching of multiple video signals.

[0026] As the main control chip, the FPGA's main function is to receive the decoded video data, judge the external video, and control the reading and writing of SSRAM based on the judgment result.

[0027] like Figure 2 As shown, the FPGA internal logic block diagram mainly includes four core modules: a video timing generation module, an external video detection module, a video switching control module, and an SSRAM three-frame buffer control module (i.e., a buffer control module). The external video detection module is connected to the video switching control module; the video timing generation module is connected to both the video switching control module and the SSRAM three-frame buffer control module; and the video switching control module is connected to the SSRAM three-frame buffer control module. Specifically: The video timing generation module uses the output video pixel clock for counting, generating the horizontal synchronization signal (hsync), vertical synchronization signal (vsync), and data enable signal (den) required for the output video. The generated timing signals are sent to the SSRAM three-frame buffer control module for data reading from the FIFO buffer; the generated vertical synchronization signal is sent to the video switching control module for frame counting; and after multiple frame-by-frame operations based on actual conditions, the data, along with the RGB data, is output to the external video encoder for encoding.

[0028] The external video detection module receives external video data and uses a local clock with the same frequency as the external video to determine the period of the horizontal synchronization signal. The judgment range is five clock cycles above or below the normal horizontal synchronization period—that is, if the horizontal synchronization period is greater than or less than five clock cycles of the normal period, the instability indicator signal sig_no is pulled high; otherwise, it is pulled low, and this signal is sent to the video switching control module.

[0029] The normal horizontal synchronization period refers to the standard period value of the horizontal synchronization signal specified by the input video standard format (such as PAL, NTSC, etc.). The upper and lower error of five clock cycles refers to the error tolerance of five clock cycles of the local clock. When the deviation between the measured horizontal synchronization period and the standard period value exceeds five local clock cycles, the horizontal synchronization signal is considered unstable.

[0030] The video switching control module performs logical processing based on the field synchronization signal vsync and the instability indication signal sig_no.

[0031] When the sig_no signal undergoes a transition (i.e., from stable to unstable or from unstable to stable), the switching signal sig_chg is pulled high. The counter cnt accumulates based on the rising edge of the field synchronization signal vsync while the sig_chg signal is high, until cnt reaches the preset value n, at which point cnt is cleared, and sig_chg is pulled low.

[0032] The flag signal is pulled high when sig_no transitions and pulled low when cnt equals n-2, at which point the flag signal is output to the SSRAM three-frame buffer control module. The value of n depends on the decoder's performance; the shorter the timing lock time after decoding, the smaller the value of n, and vice versa. Generally, the value of n remains constant in fixed applications.

[0033] During the counting period, the video validity judgment signal sig_dect is processed. When cnt equals n, sig_dect latches the value of sig_no and uses it as the new video validity judgment signal to determine whether the output is a normal image or another abnormal image (such as a black screen). sig_dect lags the flag signal by two frames, primarily to ensure that the previous video source's image is completely replaced by the new image in the buffer, avoiding the phenomenon of the image appearing and disappearing repeatedly, sometimes showing a frame from the previous video source.

[0034] like Figure 3 As shown, when the external video signal disappears (i.e., the video signal vanishes), sig_no transitions from low to high, flag is pulled high, and the switching signal sig_chg is also pulled high, and cnt starts counting. During the period when cnt accumulates from 0 to n-2, flag remains high, and the system continuously outputs the last frame before the switch. When the cnt count reaches n-2, flag goes low, but sig_dect has not yet been updated, and the system still operates with the old valid judgment signal; when cnt reaches n, the switching signal sig_chg goes low, and sig_dect latches the high level value of sig_no. At this point, it is determined that there is no valid video input, and a black screen or other abnormal image is output.

[0035] like Figure 4As shown, when the external video signal returns to normal (i.e., the video signal is restored), sig_no transitions from high to low, flag goes high, and the switching signal sig_chg also goes high, and cnt starts counting. During the period when cnt accumulates from 0 to n-2, flag remains high, and the system continuously outputs the last frame (black screen) before the switch (i.e., during the period without video). When the cnt count reaches n-2, flag goes low, but sig_dect has not yet been updated, and the system still operates with the old valid signal. When cnt reaches n, the switching signal sig_chg goes low, and sig_dect latches the low level value of sig_no. At this point, it is determined that there is valid video input, and the normal output image is restored. Since the new image is already stable, there will be no jitter or tearing during restoration.

[0036] During the initial stage of the switchover, when the cnt count is from 0 to n-2, and sig_dect is low and flag is high, data from the buffer area read at the rising edge of flag for n consecutive frames is used for screen display.

[0037] In practical applications, it is more often like Figure 5 The diagram illustrates the multi-channel external video switching process. During the switching period, the timing of the decoder input to the FPGA is unstable, causing sig_no to fluctuate continuously. Without processing, the SSRAM would be filled with messy data, and the video judgment signal would also fluctuate, resulting in screen tearing and flickering. The flag signal ensures that during the switching period, it consistently reads data from the buffer area pointed to by the read pointer of the last frame before the switch, and waits until the new video signal stabilizes before lowering it. sig_dect filters sig_no; the combined effect of these two signals maintains a stable output of the image during the switching period until the flag is lowered, smoothly transitioning to the new image.

[0038] The SSRAM three-frame buffer control module (buffer control module) is used to control the read and write operations of a single SSRAM chip. To reduce chip pin and PCB routing resources, only one SSRAM chip is used, divided into three buffer areas, with each area buffering one complete frame of video image.

[0039] Since only one SSRAM is used, read and write enable needs to be time-division multiplexed, requiring the use of a write data FIFO and a read data FIFO for data reading and writing. An intermediate clock higher than the input / output clock is needed for the read and write operations of the read data FIFO and write data FIFO. Data read from the write data FIFO is quickly written to the SSRAM, and then data from the SSRAM is quickly read and written to the read data FIFO.

[0040] To prevent read-write conflicts, the first variable i and the second variable j are used to point to the read and write cache areas respectively, where i is cyclically incremented from 0 to 2 and j = (i+2) mod 3, forming a stable "read i, write (i+2) mod 3" pattern.

[0041] To prevent the reading of messy data written to SSRAM during switching, the read / write loop is terminated by a flag signal output from the video switching control module. When the flag is high, the i signal and j signal remain unchanged, allowing the video data in the buffer area pointed to by the read pointer of the last frame before the switch to be read continuously during the switching period. After waiting for a certain period of time for the decoder to complete timing locking and stabilize the output, the flag is lowered, and the read / write pointer loop continues.

[0042] It should be noted that before re-entering the loop, it is necessary to wait for the buffer area where invalid data was written during the switching period to be refreshed with new valid video data. Therefore, the preset value n of the counter cnt is slightly longer than the maximum settling time required for the actual decoder timing lock.

[0043] like Figure 2 As shown, the SSRAM three-frame buffer control module is connected to the external SSRAM chip via a data address control bus. This data address control bus is a bidirectional bus used to transmit pixel data, read / write addresses, and control signals between the FPGA and the SSRAM, thereby controlling the read and write operations of the three buffer areas of the SSRAM.

[0044] At the FPGA output, the RGB data read from the SSRAM three-frame buffer control module, the video validity judgment signal sig_dect output from the video switching control module, and the preset 24-bit all-zero data (24'h000000, corresponding to a black screen) are input to a 2-to-1 data selector. This data selector is controlled by the sig_dect signal: when sig_dect is high (indicating a stable and valid video input), the data selector selects the RGB data read from the SSRAM and outputs it as the RGB_out signal to the external video encoder; when sig_dect is low (indicating no valid video input, such as signal loss or unstable timing during switching), the data selector selects 24'h000000, outputting a black screen. This mechanism ensures that during video switching or when the signal is abnormal, the monitor will not display screen tearing or glitches caused by messy data written to the SSRAM.

[0045] Based on the collaborative work of the above modules, the complete system workflow of this embodiment of the invention is as follows: First, the system is powered on and initialized, and the video timing generation module begins to generate various timing signals required for output video.

[0046] Under normal operating conditions, the external video detection module continuously monitors the period of the input horizontal synchronization signal. When the horizontal synchronization period is within the normal range, sig_no is low, the video switching control module does not initiate the switching process, and the system outputs the current video frame normally.

[0047] When an external video signal switches (whether from present to absent, absent to present, or multiple channels switching), the signal received by the analog video decoder changes, and its internal clock phase-locked loop and automatic gain control circuit need a certain amount of time to relock. During this period, the period of the horizontal synchronization signal output by the decoder will fluctuate. After the external video detection module detects that the horizontal synchronization period deviates from the normal range, it pulls sig_no high (or pulls it low), triggering the video switching control module to start the switching process.

[0048] Upon detecting a change in sig_no, the video switching control module immediately raises the flag and starts the counter cnt. The flag signal is transmitted to the SSRAM three-frame buffer control module, which immediately freezes the read and write pointers, stops writing new data to the SSRAM, and continuously reads data from the buffer area pointed to by the current read pointer, thus ensuring that the displayed image is always the complete image of the last frame before the switch, without tearing or black screen.

[0049] During the cnt counting period, regardless of how sig_no changes, flag remains high, the read / write pointer remains frozen, and the output screen remains unchanged. When the cnt count reaches n-2, flag goes low, but sig_dect has not yet been updated, and the system continues to operate with the old valid judgment signal. When the cnt count continues to reach n, sig_dect latches the current value of sig_no and updates it to the new valid video judgment signal. If the new signal has stabilized (sig_no is low), the system resumes normal reading, writing, and output of the new image; if the new signal has not stabilized (sig_no is high), it is determined that there is no valid video input, and a black screen is output.

[0050] Based on the above system, this invention also provides a method for smooth switching of multiple video streams based on FPGA, comprising the following steps: Step S1: The external video detection module uses a local clock with the same frequency as the external video to determine the period of the input horizontal synchronization signal. If the horizontal synchronization period deviates from the normal range (e.g., more than ±5 local clock cycles), it outputs a high-level unstable indicator signal sig_no. Step S2: The video switching control module monitors sig_no. When a transition occurs, it pulls the switching change signal sig_chg high and starts the counter cnt to accumulate based on the rising edge of the field synchronization signal vsync, while simultaneously pulling the flag signal high. The flag signal is pulled high when the unstable indicator signal transitions and pulled low when the count equals a preset value n-2. The count is accumulated based on the rising edge of the field synchronization signal when the flag signal is high, until the count reaches the preset value n, at which point it is cleared and the flag signal is pulled low. Step S3: The SSRAM three-frame buffer control module receives the raised flag signal, freezes the read and write pointers, and continuously reads and outputs the buffer area data pointed to by the last frame read pointer before the switch; Step S4: When the counter cnt accumulates to the preset value n, sig_no is latched as the new valid video judgment signal sig_dect, and the flag is pulled low. The buffer control module resumes the loop read and write mode, and completes the smooth switch to the new screen.

[0051] The preset value n is greater than the maximum stabilization time required for timing locking of the analog video decoder, and in step S2, the flag signal is pulled low in advance when cnt=n-2, so that sig_dect lags behind the flag by two frames.

[0052] Through the above mechanism, the embodiments of the present invention achieve smooth video switching that can be completed entirely autonomously on the display without relying on front-end switching commands.

[0053] It should be noted that: The choice of the preset value n directly affects the switching effect and response speed. The value of n should be determined based on the performance of the analog video decoder actually used.

[0054] The maximum settling time refers to the maximum time elapsed from the input signal switching to the output stable timing of an analog video decoder under the most severe operating conditions (including but not limited to input signal format switching, ambient temperature changes, power supply fluctuations, etc.). This maximum settling time can be determined as follows: at the instant the video switching occurs, continuously monitor the period of the horizontal sync signal output by the decoder, and record the time from when the horizontal sync period first deviates from the normal range to when the horizontal sync period remains stable within the normal range (i.e., N consecutive horizontal sync periods are within ±5 clock cycles of the normal period); repeat the test under various operating conditions, and take the maximum value as the maximum settling time of the decoder.

[0055] For decoders with short lock times (e.g., approximately 50ms), a smaller n value (e.g., n=3 or n=4) can be selected to shorten the switching transition time. For example, for a common 60Hz refresh rate video input, each frame is approximately 16.6ms long. With n=3, the corresponding freeze time is approximately 50ms, which matches a decoder with a fast lock. With n=4, it's approximately 66ms, leaving an appropriate margin. For decoders with longer lock times (e.g., approximately 200ms), a larger n value (e.g., n=8 or n=10) needs to be selected. The corresponding freeze time at 60Hz is approximately 133ms to 166ms. If the actual stabilization time of the decoder is long, the total duration corresponding to the n value should be slightly greater than the decoder's maximum stabilization time to avoid premature recovery and resulting image instability.

[0056] The principle for choosing the value of n is that the time represented by the frame number corresponding to n should be slightly greater than the maximum settling time required for the decoder to complete timing locking in the worst case. This ensures both the smoothness of the switching process and the ability for the system to recover to a normal display state as quickly as possible.

[0057] In practical applications, the settling time of decoders of the same model is relatively fixed, so once the value of n is determined, it can remain unchanged.

[0058] The FPGA-based multi-channel video smooth switching system and method described in this invention are particularly suitable for airborne display systems. In airborne environments, pilots need to frequently switch between multiple video sources (such as navigation screens, radar screens, infrared screens, etc.), requiring a high level of visual experience during the switching process. Using the technical solution of this invention, no modifications to existing multiplexers and displays are necessary; simply implementing the above logic in the FPGA achieves a smooth video switching effect.

[0059] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-channel video smooth switching system based on FPGA, characterized in that, Includes an FPGA and external memory connected to the FPGA; The FPGA internally includes: The video timing generation module is used to count according to the output video pixel clock and generate the horizontal synchronization signal, vertical synchronization signal and data enable signal required for the output video. The external video detection module is used to determine the period of the input horizontal synchronization signal using a local clock with the same frequency as the external video. When the horizontal synchronization period deviates from the normal range, it outputs an unstable indication signal. The video switching control module is connected to the external video detection module and the video timing generation module. It is used to perform logical processing based on the unstable indication signal and the field synchronization signal to generate a switching control signal and a video valid judgment signal. as well as A cache control module, connected to the video switching control module, the video timing generation module, and the external memory, is used to control the read and write operations of the external memory according to the switching control signal; The video switching control module starts counting when the unstable indication signal changes. During the counting period, it controls the buffer control module to freeze the read and write pointers according to the switching control signal to continuously output the video data of the last complete frame before the switching. When the count reaches a preset value, it updates the video validity judgment signal and restores the normal output of the new frame.

2. The system according to claim 1, characterized in that: The external video detection module pulls the instability indicator signal high when the horizontal synchronization period is greater than or less than five clock cycles of the normal period; otherwise, it pulls the instability indicator signal low.

3. The system according to claim 1, characterized in that: The video switching control module includes: A switching change signal generation unit is used to generate a switching change signal when the unstable indication signal changes abruptly. A counter unit is used to accumulate counts based on the rising edge of the field synchronization signal when the switching change signal is high. A flag signal generation unit is configured to pull the flag signal high when the unstable indication signal changes, and pull the flag signal low when the count equals a preset value minus two, wherein the flag signal is output to the buffer control module as the switching control signal; and A valid judgment signal generation unit is used to latch the value of the unstable indication signal when the count equals the preset value, and use it as the valid judgment signal for the video.

4. The system according to claim 3, characterized in that: The value of the preset value depends on the performance of the analog video decoder. The shorter the timing lock time after decoding by the analog video decoder, the smaller the value of the preset value, and vice versa. The preset value is greater than the maximum stabilization time required for timing locking of the analog video decoder.

5. The system according to claim 1, characterized in that: The cache control module uses a single static random access memory (SRAM) chip, which is divided into three cache regions, each of which caches one complete video frame. The cache control module performs time-division multiplexing read and write operations on the SRAM through write data FIFO and read data FIFO.

6. The system according to claim 5, characterized in that: The cache control module uses an intermediate clock higher than the input clock and the output clock to perform read and write operations on the read data FIFO and the write data FIFO. It writes the data read from the write data FIFO into the static random access memory, and then reads the data from the static random access memory into the read data FIFO. The cache control module uses a first variable and a second variable to point to the write cache area and the read cache area, respectively, forming a stable cyclic read and write mode of reading the first variable and writing the first variable by adding two and taking the modulo three.

7. The system according to claim 6, characterized in that: When the switching control signal goes high, the cache control module freezes the first variable and the second variable, keeping the read and write pointers unchanged, and continuously reads the video data of the cache area pointed to by the last frame read pointer before the switch. When the switching control signal is pulled low, the cyclic read / write mode is restored, and the buffer area where invalid data was written during the switching period is refreshed with new valid video data.

8. The system according to claim 1, characterized in that: The video valid judgment signal lags behind the switching control signal by two frames.

9. A method for smooth switching of multiple video streams based on FPGA, used in the system as described in any one of claims 1-8, characterized in that, Includes the following steps: Step S1: Use a local clock with the same frequency as the external video to determine the period of the input horizontal synchronization signal. When the horizontal synchronization period deviates from the normal range, an unstable indication signal is generated. Step S2: Perform logical processing based on the unstable indication signal and the field synchronization signal: When the unstable indication signal changes, start counting and generate a flag signal as a switching control signal; Step S3: Freeze the read / write pointer of the external memory according to the flag signal, and continuously output the video data of the last complete frame before the switch; Step S4: When the count reaches a preset value, latch the value of the unstable indication signal as a new valid video judgment signal and restore the normal output of the new picture.

10. The method according to claim 9, characterized in that: In step S2, the flag signal is pulled high when the unstable indication signal changes, and pulled low when the count equals a preset value minus two; the count is accumulated according to the rising edge of the field synchronization signal when the flag signal is high, until the count reaches the preset value, at which point it is cleared and the flag signal is pulled low; the preset value is greater than the maximum stabilization time required for timing lock of the analog video decoder.

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