Digital video bus physical layer system based on multi-channel adaptive rate and implementation method

Abstract

The application belongs to the technical field of avionics video transmission and relates to a digital video bus physical layer system based on a multi-channel adaptive rate and an implementation method thereof. The system comprises a reference clock generation unit, a multi-channel configuration unit and a multi-channel alignment unit. The reference clock generation unit is used for generating and outputting a multi-parallel reference clock signal. The channel configuration unit comprises a control unit, a link monitoring unit, a DRP dynamic configuration unit and a GTH transceiver unit. The application supports multiple digital video bus standard rates and custom high rates, has a large rate coverage range, can adapt to video transmission scenes with different bandwidth requirements through dynamic configuration, adopts a multi-channel grouping alignment architecture, can accurately eliminate clock deviation and link transmission delay difference between channels, ensures high consistency of the timing of multi-parallel video data, and effectively avoids problems such as picture tearing, row misalignment and frame asynchronization during multi-link transmission.

Description

Technical Field

[0001] This invention belongs to the field of avionics video transmission technology, specifically relating to a digital video bus physical layer system and its implementation method based on multi-channel adaptive rate. Background Technology

[0002] With the development of avionics technology, the resolution of cockpit displays is constantly improving, the number of camera acquisition channels is continuously increasing, and the synchronous transmission of high-resolution and high-frame-rate multi-channel parallel digital video bus signals has become a mainstream requirement.

[0003] Traditional digital video bus physical layer implementation schemes have several drawbacks: (1) Traditional physical layer schemes only support single rate configuration and cannot be compatible with avionics equipment of different generations and different rates. When the system upgrades equipment or expands functions, it often needs to redesign hardware circuits or recompile firmware, resulting in high development costs, long iteration cycles, and difficulty in adapting to complex avionics system environments with multiple devices coexisting. (2) Traditional physical layer solutions only support single link mode and cannot be compatible with video transmission requirements of different resolutions and frame rates. For low-resolution video, the single link bandwidth is excessive, resulting in resource waste; for high-resolution and high-bandwidth video, a single link cannot meet the transmission requirements and lacks flexible link aggregation capabilities. (3) The traditional physical layer has a fixed configuration mode and cannot be flexibly adjusted according to actual usage needs. It has weak link status monitoring capabilities, lacks built-in testing and self-testing mechanisms, and is difficult to debug and maintain. It is difficult to meet the requirements of high reliability and high maintainability of avionics systems.

[0004] The existing method for automatic bus link rate adaptation uses an FPGA high-speed serial transceiver and includes three parts: dynamic reconfiguration of the FPGA high-speed serial transceiver link rate, high-speed serial transceiver link rate polling, and digital video bus protocol end line rate reconfiguration. The specific implementation steps are as follows: configure the high-speed serial transceiver line rate; monitor the high-speed serial transceiver link status after a period of time; reconfigure the high-speed serial transceiver line rate to another line rate; detect and obtain the current line rate, fix the current configuration parameter information of the high-speed serial transceiver IP, and exit the high-speed serial transceiver link rate polling state; obtain the link line rate information and working status from the high-speed serial transceiver; based on the obtained link line rate information and status, estimate the working status of the ARINC818 protocol end and reconfigure the ARINC818 protocol end parameters to adapt to the needs of receiving different video resolutions.

[0005] While existing technologies have achieved automatic rate adaptation for single links, they still have significant technical shortcomings: (1) The rate support range is limited, only supporting four digital video bus link rates, which cannot cover the full rate range specified by the digital video bus protocol, nor does it support custom high rates, making it difficult to adapt to the bandwidth requirements of the new generation of high-resolution video transmission. (2) The function is incomplete. This solution only realizes the dynamic configuration of the digital video bus link rate, but does not realize the complete physical layer function of the digital video bus. It lacks complete physical layer capabilities such as accurate monitoring of link status, data validity verification and built-in testing. (3) It does not support multi-channel synchronous transmission. Existing technologies are only designed for single links, without multi-channel architecture or channel alignment and synchronization mechanisms. They cannot meet the needs of multi-channel parallel video transmission and multi-link aggregation transmission scenarios, and are difficult to support typical avionics applications such as cockpit multi-screen display and multi-camera synchronous acquisition. Summary of the Invention

[0006] To address the aforementioned technical problems, the present invention provides a solution. The present invention offers a digital video bus physical layer system and method based on multi-channel adaptive rate.

[0007] In a first aspect, the present invention provides a digital video bus physical layer system based on multi-channel adaptive rate, including a reference clock generation unit, a multi-channel configuration unit and a multi-channel alignment unit; The reference clock generation unit is used to receive multiple differential reference clocks from external input, generate multiple parallel reference clock signals and output them, providing a multi-frequency clock source for high-speed serial links; The channel configuration unit includes a control unit, a link monitoring unit, a DRP dynamic configuration unit, and a GTH transceiver unit. The control unit receives external configuration signals and outputs link status signals, configures the link rate, and monitors the link status. The link monitoring unit monitors the physical link status of the GTH transceiver in the GTH transceiver unit and the data format of the digital video bus transmitted on the link in real time, generating a link establishment status signal. The DRP dynamic configuration unit writes the corresponding parameters of the GTH transceiver and its CPLL through the dynamic reconfiguration bus to complete the non-compiled dynamic switching of the line rate. The GTH transceiver unit performs serial data encoding / decoding, serial-to-parallel conversion, and clock data recovery. The control unit is connected to each channel configuration unit and the link monitoring unit. The link monitoring unit is connected to each channel alignment unit. Each channel configuration unit connects to the clock output of the reference clock generation unit to independently receive rate configuration commands. It adjusts the transmission parameters of the GTH transceiver in real time through the dynamic reconfiguration interface, completes the dynamic switching of the digital video bus rate and data transmission and reception, and outputs link status signals and parallel received data. The hardware groups of the GTH transceiver are connected one-to-one with the channel configuration units, which are used to convert the transmitted and received data from serial to parallel through encoding and decoding. The channel alignment unit is connected to each channel configuration unit and is used to collect the received data and link status of each channel in groups by channel. It performs channel alignment through frame identifier detection and elastic buffering mechanism to eliminate clock deviation and transmission delay differences between channels and output time-synchronized multi-channel parallel video data.

[0008] Secondly, the implementation method of the physical layer system of a digital video bus based on multi-channel adaptive rate includes: The system receives multiple differential reference clocks from external input, generates multiple parallel reference clock signals and outputs them, providing a multi-frequency clock source for high-speed serial links; The system receives external configuration signals and outputs link status signals, configures the link rate, and monitors the link status. The system monitors the physical link status of the GTH transceiver and the data format of the digital video bus transmitted on the link in real time, generating a link establishment status signal. The system writes corresponding parameters to the GTH transceiver and its CPLL via a dynamic reconfiguration bus, completing the non-compiled dynamic switching of the line rate. The system completes serial data encoding / decoding, serial-to-parallel conversion, and clock data recovery. The system collects the received data and link status of each channel in groups by channel, and performs channel alignment through frame identifier detection and elastic buffering mechanism to eliminate clock deviation and transmission delay differences between channels, and outputs multi-channel parallel video data with synchronized timing.

[0009] In some alternative embodiments, the differential reference clock input ports of the hardware groups of different GTH transceivers are configured with clock parameters of different frequencies.

[0010] In some optional embodiments, each channel configuration unit further includes a test data generation unit; the test data generation unit controls the data path switching according to the externally input test enable signal, and generates a pseudo-random test sequence in test mode to replace service data and send it to the GTH transceiver for link bit error rate testing and link fault location during the link debugging phase.

[0011] Configuring the link rate includes: after the system reset, determining whether the auto-configuration enable signal is valid; if the auto-configuration enable signal is invalid, entering manual configuration mode, reading the externally input rate encoding value, configuring the parameters of the corresponding rate, and outputting the link status upon completion; if the auto-configuration enable signal is valid, selecting the preset initial link rate, completing the rate configuration, and then detecting the link handshake status; if the link handshake is successful, locking the current rate parameters, outputting the link status, and ending the rate negotiation process; if the link handshake is unsuccessful, switching to the next-order rate in the preset rate list, repeating the link rate configuration and link detection steps until the link handshake is successful or the preset negotiation timeout condition is reached.

[0012] In some optional embodiments, the corresponding parameters of the GTH transceiver and the CPLL within the GTH transceiver are calculated using the phase-locked loop output frequency formula and the linear rate formula, including: set up This is the output frequency of the phase-locked loop. For the reference clock input frequency, This is the first feedback frequency division coefficient of the phase-locked loop. This is the second feedback frequency division coefficient of the phase-locked loop. Let be the input frequency divider of the phase-locked loop (PLL), then the formula for the PLL output frequency is: ; set up For high-speed serial line rate, Let the transceiver output frequency division factor be denoted as , then the formula for the line rate of the GTH transceiver is: .

[0013] In some optional embodiments, the link monitoring unit generates link establishment status signals through the IDLE (idle state) primitive detection mechanism and the frame check detection mechanism respectively; when the IDLE primitive transmitted on the link is continuously detected, it is determined that the link establishment is complete; when the input ADVB frame format is detected to conform to the digital video bus protocol specification and the CRC check result is correct, it is determined that the link establishment is complete, thus confirming the link validity under the link service transmission state.

[0014] In some optional embodiments, the DRP dynamic configuration unit writes the corresponding parameters of the GTH transceiver and the CPLL in the GTH transceiver through the dynamic reconfiguration bus to complete the non-compilation dynamic switching of the line rate, including: The DRP dynamic configuration unit receives the target rate code and configuration enable signal transmitted by the control unit, and looks up the table to obtain the physical parameters of the GTH transceiver and the phase-locked loop configuration parameters corresponding to the target rate. The physical parameters and phase-locked loop configuration parameters of the GTH transceiver are written into the corresponding configuration register of the GTH transceiver via the DRP configuration bus. Set the phase-locked loop reset signal to perform a reset operation on the phase-locked loop in the GTH transceiver; The phase-locked loop (PLL) lock signal is continuously monitored. Once the PLL lock signal goes high, the core reset signal of the GTH transceiver is set to reset the serial transceiver unit of the GTH transceiver. The GTH transceiver reset completion signal is continuously monitored. Once the reset completion signal goes high, the marker line rate dynamic switching is completed.

[0015] In some optional embodiments, in the transmission path of the GTH transceiver, parallel service data is input to the GTH transceiver via the transmission data interface, and after encoding and parallel-to-serial conversion are completed in sequence, it is output in the form of differential serial signal; in the reception path of the GTH transceiver, the GTH transceiver receives the externally input differential serial signal, and after clock data recovery, serial-to-parallel conversion and decoding are completed in sequence, it outputs parallel received data to the link monitoring unit and the channel alignment unit.

[0016] In some optional embodiments, the system performs channel alignment through frame identifier detection and elastic buffering mechanism, including three working modes: a first working mode, a second working mode, and a third working mode. In the first working mode, the system directly transmits the received data from each single channel, outputting a total of 12 independent data channels in the first working mode; In the second working mode, the system outputs the received data from two adjacent links in the first working mode after synchronizing them, and outputs a total of six channels of data in the second working mode. In the third working mode, the system synchronizes the received data from the four links in the first working mode within the group and then outputs the data, resulting in a total output of three data streams in the third working mode.

[0017] The beneficial effects of this invention are: (1) This invention supports multiple digital video bus standard rates and custom high rates through the cross-hardware component reuse design of the reference clock and the DRP dynamic configuration mechanism. The rate coverage is large and it can be compatible with avionics equipment of different generations and different rate levels. When the system is upgraded or expanded, there is no need to modify the hardware circuit. It can be adapted to video transmission scenarios with different bandwidth requirements through dynamic configuration, which greatly reduces the system upgrade cost and shortens the product iteration cycle. It can adapt to the full scenario requirements from low-resolution monitoring video to high-resolution cockpit display. (2) The present invention adopts a multi-channel group alignment architecture. Through SOF identification detection, elastic buffering and phase calibration mechanism, it can accurately eliminate the clock deviation and link transmission delay difference between channels, ensure the high consistency of the timing of multi-channel parallel video data, and effectively avoid problems such as screen tearing, line misalignment and frame asynchrony that occur during multi-link transmission. (3) This invention realizes the complete physical layer function of digital video bus, and improves link stability; (4) The present invention adopts a modular and grouped architecture design. The reference clock generation unit, channel configuration unit and channel alignment unit are all standardized units, which can be smoothly expanded according to actual needs and can easily adapt to the multi-channel video parallel transmission scenario of multiple displays, multiple cameras and multiple sensors in avionics systems. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the digital video bus physical layer system based on multi-channel adaptive rate provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of the link rate configuration for the control unit; Figure 3 This is a schematic diagram of the link monitoring state transition; Figure 4 This is a flowchart of the dynamic reconfiguration process; Figure 5 This is a timing diagram of the four-link bonded transmission mode; Figure 6 This is a flowchart of the implementation method of the physical layer system of digital video bus based on multi-channel adaptive rate provided in Embodiment 2 of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Example 1 As an example, to address the problems existing in the prior art, this embodiment provides a digital video bus physical layer system based on multi-channel adaptive rate.

[0021] The implementation details of the system in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0022] As attached Figure 1 As shown, the digital video bus physical layer system based on multi-channel adaptive rate includes a reference clock generation unit, a multi-channel configuration unit, and a multi-channel alignment unit. The reference clock generation unit is used to receive multiple differential reference clocks from external input, generate multiple parallel reference clock signals and output them, providing a multi-frequency clock source for high-speed serial links; The channel configuration unit includes a control unit, a link monitoring unit, a DRP (Dynamic Reconfiguration Port) dynamic configuration unit, and a GTH transceiver unit. The control unit receives external configuration signals and outputs link status signals, configures the link rate, and monitors the link status. The link monitoring unit monitors the physical link status of the GTH (Gigabit Transceiver High-performance) transceiver in the GTH transceiver unit and the data format of the digital video bus transmitted on the link in real time, generating a link establishment status signal. The DRP dynamic configuration unit writes the corresponding parameters between the GTH transceiver and the CPLL (Channel Phase-Locked Loop) via the dynamic reconfiguration bus to complete the non-compiled dynamic switching of the line rate. The GTH transceiver unit performs serial data encoding / decoding, serial-to-parallel conversion, and clock data recovery. The control unit is connected to each channel configuration unit and the link monitoring unit. The link monitoring unit is connected to each channel alignment unit. Each channel configuration unit connects to the clock output of the reference clock generation unit to independently receive rate configuration commands. It adjusts the transmission parameters of the GTH transceiver in real time through the dynamic reconfiguration interface, completes the dynamic switching of the digital video bus rate and data transmission and reception, and outputs link status signals and parallel received data. The hardware groups of the GTH transceiver are connected one-to-one with the channel configuration units, which are used to convert the transmitted and received data from serial to parallel through encoding and decoding. The channel alignment unit is connected to each channel configuration unit and is used to collect the received data and link status of each channel in groups by channel. It performs channel alignment through frame identifier detection and elastic buffering mechanism to eliminate clock deviation and transmission delay differences between channels and output time-synchronized multi-channel parallel video data.

[0023] The reference clock generation includes: receiving multiple differential reference clocks from external input, generating multiple parallel reference clock signals and outputting them, providing a multi-frequency clock source for high-speed serial links.

[0024] In some alternative embodiments, the differential reference clock input ports of the hardware groups of different GTH transceivers are configured with clock parameters of different frequencies.

[0025] This embodiment utilizes the feature that the CPLL in the GTH transceiver can reuse the reference clock between adjacent banks (hardware components) to provide different frequency clock sources at the differential reference clock input ports of different banks. This provides multiple selectable input reference clock frequencies for each channel configuration unit, eliminating the need to configure a full-frequency clock source for each channel separately, and greatly simplifying the hardware clock circuit design.

[0026] The GTH transceiver is divided into hardware banks, each supporting two independent reference clock source inputs. It can also reuse reference clocks from adjacent upper banks (Bank-1) and lower banks (Bank+1). In this embodiment, differential reference clocks of 170MHz and 220MHz are input to the two reference clock input ports of Bank-1; differential reference clocks of 255MHz and 162MHz are input to the two reference clock input ports of the middle bank; and differential reference clocks of 170MHz and 200MHz are input to the two reference clock input ports of Bank+1. Through the inter-bank reference clock multiplexing mechanism, all channels in the middle bank can select reference clocks from the middle, upper, and lower banks, thereby obtaining reference clocks of various frequencies such as 170MHz, 220MHz, 255MHz, 162MHz, and 200MHz, covering the clock requirements of all target line rates.

[0027] The reference clock generation unit generates a parallel reference clock signal and distributes it to each channel. Each channel's GTH transceiver can select a target clock source from the above reference clocks via a multiplexer, input it to the CPLL for phase-locked loop frequency multiplication, and generate the internal operating clock required for the corresponding line rate.

[0028] Based on the physical layer link rates specified in digital bus protocols (such as ARINC818), and combined with custom high-speed requirements, this embodiment supports 11 line rates: 1.0625Gbps, 1.5Gbps, 1.62Gbps, 2.125Gbps, 2.5Gbps, 3.1875Gbps, 4.25Gbps, 5.0Gbps, 6.375Gbps, 8.5Gbps, and a custom 10Gbps. Using the CPLL output frequency calculation formula of the FPGA GTH transceiver and the GTH line rate calculation formula, the reference clock frequency and division parameters corresponding to each line rate can be calculated.

[0029] Specifically, the corresponding parameters of the GTH transceiver and its CPLL are calculated using the phase-locked loop output frequency formula and the linear rate formula, including: set up This is the output frequency of the phase-locked loop. For the reference clock input frequency, This is the first feedback frequency division coefficient of the phase-locked loop. This is the second feedback frequency division coefficient of the phase-locked loop. Let be the input frequency divider of the phase-locked loop (PLL), then the formula for the PLL output frequency is: ; set up For high-speed serial line rate, Let the transceiver output frequency division factor be denoted as , then the formula for the line rate of the GTH transceiver is: .

[0030] This embodiment supports all 11 line rates, requiring only five reference clock frequencies: 170MHz, 220MHz, 162MHz, 255MHz, and 200MHz. Combining the GTH's feature that each bank supports two reference clock inputs and can reuse reference clocks from adjacent banks, the reference clock architecture design in this embodiment can provide the reference clocks required for all 12 channels at all rates, without the need for additional clock chips, resulting in low hardware cost and high clock quality.

[0031] The channel rate adaptive configuration includes: the control unit receives external configuration signals and outputs link status signals, configures the link rate and monitors the link status; the link monitoring unit monitors the physical link status of the GTH transceiver and the data format of the digital video bus transmitted on the link in real time, and generates a link establishment status signal; the DRP dynamic configuration unit writes the corresponding parameters of the GTH transceiver and the CPLL in the GTH transceiver through the dynamic reconfiguration bus to complete the non-compiled dynamic switching of the line rate; and the GTH transceiver unit completes the encoding and decoding of serial data, serial-to-parallel conversion and clock data recovery.

[0032] This embodiment features 12 independent channel configuration units, each capable of independently performing ARINC818 physical layer rate configuration, link monitoring, and data transmission / reception functions. Each channel configuration unit comprises five sub-units: a control unit, a link monitoring unit, a test data generation unit, a DRP dynamic configuration unit, and a GTH transceiver unit.

[0033] The control unit is the core control component of each channel configuration unit. It is responsible for receiving configuration signals from external input and outputting corresponding link status signals, thereby realizing the functions of rate configuration scheduling, status management and link start / stop control for the entire channel.

[0034] The link rate configuration process for the control unit is as follows: Figure 2 As shown, the specific process steps are as follows: (1) After the system reset is completed, the control unit first checks the status of the automatic configuration enable signal; (2) If the automatic configuration enable signal is low, i.e., the automatic negotiation mode is off, then the manual configuration mode is entered. The manual configuration rate encoding value input externally is read, and the configuration command and target rate are sent to the DRP dynamic configuration unit to drive the DRP unit to complete the parameter configuration of the corresponding rate. After the configuration is completed, the link status signal is output. The manual configuration mode is mainly used at the transmitting end, where the system actively specifies the link transmission rate; (3) If the automatic configuration enable signal is high, i.e. the automatic negotiation mode is enabled, the automatic rate negotiation process will begin: S31: Select the preset initial link rate, usually starting from the lowest rate of 1.0625Gbps, or other initial rates can be set as needed; S32: Send a configuration command to the DRP dynamic configuration unit to complete the GTH parameter configuration for the current rate; S33: After configuration, continuously read the handshake success signal output by the link monitoring unit to detect the link handshake status; S34: If a handshake success signal is detected to be high, that is, the link handshake is successful, then lock all configuration parameters of the current rate, output the rate code and the link status signal of the handshake success, and end the rate negotiation process. S35: If a link handshake is not detected within the preset time, i.e. negotiation timeout, switch to the next rate level in the preset rate list and repeat steps S32 to S34 to poll all supported rate levels in turn until the link handshake is successful, or enter the error state after traversing all rates if the handshake is still unsuccessful.

[0035] The auto-negotiation mode is mainly used on the receiving end. It can automatically match the link rate of the sending device on the other end without the need for manual pre-configuration, which greatly improves the compatibility and ease of use of the device.

[0036] The core function of the link monitoring unit is to monitor the link status of the GTH transceiver in real time, as well as the ARINC818 data format transmitted on the link, generate a link establishment status signal indicating a successful handshake, and feed it back to the control unit and the corresponding channel alignment unit.

[0037] Given the unidirectional transmission characteristic of the ARINC818 protocol, the link monitoring unit in this embodiment makes link determination entirely based on the received data, without relying on additional bypass handshake signals, thus adapting to the unidirectional transmission mechanism of ARINC818.

[0038] In some optional embodiments, the link monitoring unit generates link establishment status signals through the IDLE primitive detection mechanism and the frame check detection mechanism respectively; when IDLE primitives transmitted on the link are continuously detected, the link establishment is determined to be complete; when the input ADVB (Avionics Digital Video Bus) frame format is detected to conform to the digital video bus protocol specification and the CRC check result is correct, the link establishment is determined to be complete, thus confirming the link validity under the link service transmission state.

[0039] Two independent link establishment determination mechanisms are adapted to different working states of the link, as detailed below: The first link establishment determination mechanism is the IDLE primitive detection mechanism: when the link is in an idle state, the ARINC818 protocol stipulates that IDLE idle primitives will be continuously transmitted on the link. When the link monitoring unit continuously detects a preset number of valid IDLE primitives, it determines that the physical link has been established and pulls the link establishment status signal high. This mechanism is suitable for connectivity confirmation during the link idle phase.

[0040] The second link establishment determination mechanism is a frame check detection mechanism: when the link is in service transmission state, ADVB video frame data is transmitted on the link. When the link monitoring unit detects that the input data conforms to the ADVB frame format specification and the CRC check result of the frame is correct, it determines that the link is in a valid working state and pulls the link establishment signal high. This mechanism is suitable for link validity confirmation during service transmission, and can effectively filter out occasional minor transmission errors on the link, avoiding frequent jitter in the link status.

[0041] The link monitoring unit implements the above-mentioned decision logic based on a finite state machine. The state machine mainly includes multiple states such as reset, IDLE detection, frame header detection, frame data verification, and link establishment. After system reset, it enters the reset state. After the reset is complete, it enters the IDLE detection state to start detecting IDLE primitives. If valid IDLE primitives are continuously detected, it jumps to the link establishment state. If a frame start identifier is detected in the link establishment state, it jumps to the frame header detection state to verify the frame format and CRC check. If the check passes, the link establishment state is maintained; if the check fails, it returns to the IDLE detection state to re-detect. Through this state machine mechanism, the link state switching is smooth, the anti-interference capability is strong, and it can stably adapt to various working states of the ARINC818 link. A state transition diagram is attached. Figure 3 As shown, the initial state S0 is the idle state. After the system is powered on or reset, it enters the global idle state by default and waits for the link signal. S1 is the frame idle wait state. After detecting the link idle primitive, it jumps to the S1 frame idle wait state and starts accumulating the idle character count. S2 is the frame start identification state. When the frame start identifier (SOF) is detected and the idle character counter value is greater than or equal to 6, it jumps to the S2 frame start identification state to confirm that a frame of data has officially started. S3 is the data reception state. After detecting the payload data (DATA), it jumps to the S3 frame valid data reception state and starts receiving video frame data byte by byte and accumulating the data count. S4 is the frame end verification state. When the frame end identifier (EOF) is detected and the valid data byte counter value is greater than 7, it jumps to the S4 frame end termination state to perform frame tail CRC verification. Return to S0: One frame reception is completed and it returns to idle. When the verification is successful and the number of valid video data bytes is greater than or equal to 535, it is confirmed that the whole frame has been received completely, and it jumps back to the S0 idle state to wait for the next frame.

[0042] In some optional embodiments, each channel configuration unit further includes a test data generation unit; the test data generation unit controls the data path switching according to the externally input test enable signal, and generates a pseudo-random test sequence in test mode to replace service data and send it to the GTH transceiver for link bit error rate testing and link fault location during the link debugging phase.

[0043] Configuring the link rate includes: after the system reset, determining whether the auto-configuration enable signal is valid; if the auto-configuration enable signal is invalid, entering manual configuration mode, reading the externally input rate encoding value, configuring the parameters of the corresponding rate, and outputting the link status upon completion; if the auto-configuration enable signal is valid, selecting the preset initial link rate, completing the rate configuration, and then detecting the link handshake status; if the link handshake is successful, locking the current rate parameters, outputting the link status, and ending the rate negotiation process; if the link handshake is unsuccessful, switching to the next-order rate in the preset rate list, repeating the link rate configuration and link detection steps until the link handshake is successful or the preset negotiation timeout condition is reached.

[0044] The function of the test data generation unit is to control the switching of the data path according to the test enable signal, generate a pseudo-random test sequence in test mode, and send it into the GTH transceiver instead of normal business data.

[0045] The test data generation unit is mainly used in link debugging mode and fault diagnosis scenarios. During equipment factory debugging, on-site installation debugging, or fault location, the test mode is activated, the transmitting end outputs a standard pseudo-random test sequence, and the receiving end performs bit error rate statistics on the received data. This allows for rapid determination of the link's transmission quality and location of faulty links and fault points, without relying on upper-layer video service data, significantly improving the efficiency of link debugging and maintenance.

[0046] In normal operating mode, when the test enable signal is low, the test data generation unit is not working, and the data path selects normal service data input to the GTH transceiver; when the test enable signal is high, the data path switches to the pseudo-random test sequence output by the test data generation unit and sends it to the GTH transceiver for transmission.

[0047] In some alternative embodiments, as shown in the appendix Figure 4 The flowchart shown illustrates the dynamic reconfiguration process. The DRP dynamic configuration unit writes the corresponding parameters of the GTH transceiver and its CPLL via the dynamic reconfiguration bus, completing the non-compiled dynamic switching of line rates, including: The DRP dynamic configuration unit receives the target rate code and configuration enable signal transmitted by the control unit, and looks up the table to obtain the physical parameters of the GTH transceiver and the phase-locked loop configuration parameters corresponding to the target rate. The physical parameters and phase-locked loop configuration parameters of the GTH transceiver are written into the corresponding configuration register of the GTH transceiver via the DRP configuration bus. Set the phase-locked loop reset signal to perform a reset operation on the phase-locked loop in the GTH transceiver; The phase-locked loop (PLL) lock signal is continuously monitored. Once the PLL lock signal goes high, the core reset signal of the GTH transceiver is set to reset the serial transceiver unit of the GTH transceiver. The system continuously monitors the GTH transceiver reset completion signal and waits for the reset completion signal to go high before marking the dynamic switching of the line rate.

[0048] The core function of the DRP (Dynamic Configuration Provider) unit is to enable dynamic reconfiguration of the GTH transceiver, allowing for online switching of link rates without recompiling the FPGA firmware. DRP is a configuration interface provided by the FPGA GTH transceiver, which can read and write the transceiver's internal configuration registers via a parallel bus to adjust the transceiver's operating parameters in real time.

[0049] The specific steps of the DRP dynamic configuration unit's workflow are as follows: (1) Receive the target rate encoding and configuration enable signal transmitted by the control unit; (2) Based on the target rate code, look up the preset parameter table and obtain the GTH physical configuration parameters and CPLL clock configuration parameters corresponding to the rate; (3) Write all configuration parameters sequentially into the corresponding configuration register of the GTH transceiver via the DRP configuration bus; (4) After all parameters are written, set the CPLLRESET signal to perform a reset operation on the CPLL phase-locked loop inside the GTH transceiver so that the new clock parameters take effect; (5) Continuously monitor the CPLLLOCK phase-locked loop locking signal and wait for the CPLL to complete phase-locking. When the CPLLLOCK signal goes high, it indicates that the phase-locked loop has stabilized and output the target frequency. (6) Set / reset signal: Performs a reset operation on the serial transceiver core of the GTH transceiver to make the new physical parameters take effect; (7) Continuously detect the reset completion signal. When the reset completion signal goes high, it indicates that the GTH transceiver has been reset and the entire line rate dynamic switching process has been completed. Return the configuration completion signal to the control unit.

[0050] Through the DRP dynamic configuration mechanism, all rate switching in this embodiment can be completed online without reloading the FPGA firmware or powering off and restarting the device. The rate switching speed is fast and the system availability is high.

[0051] The GTH transceiver unit is the core physical layer hardware for high-speed serial communication, responsible for transmitting and receiving serial data.

[0052] In some optional embodiments, in the transmission path of the GTH transceiver, parallel service data is input to the GTH transceiver via the transmission data interface, and after encoding and parallel-to-serial conversion are completed in sequence, it is output in the form of differential serial signal; in the reception path of the GTH transceiver, the GTH transceiver receives the externally input differential serial signal, and after clock data recovery, serial-to-parallel conversion and decoding are completed in sequence, it outputs parallel received data to the link monitoring unit and the channel alignment unit.

[0053] In this embodiment, in the data transmission path, parallel service data or test data is input into the GTH transceiver via the transmission interface. The transceiver first performs 8b / 10b encoding on the parallel data, converting 8-bit data into 10-bit encoding to ensure DC balance of the serial data stream, while providing sufficient transition edges for the receiver to recover the clock. After encoding, parallel-to-serial conversion is performed to convert the parallel data into a high-speed serial data stream, which is finally output to the transmission medium in the form of differential signals.

[0054] In the data receiving path, the GTH transceiver receives differential serial signals from the transmission medium. First, it extracts the synchronization clock from the serial data stream through the CDR clock data recovery circuit. Then, it performs serial-to-parallel conversion to convert high-speed serial data into low-speed parallel data. After 8b / 10b decoding, it restores the 10-bit encoding to 8-bit original data. Finally, it outputs parallel received data to the link monitoring unit and the channel alignment unit.

[0055] Channel alignment includes: collecting received data and link status of each channel in groups by channel, aligning channels through frame identifier detection and elastic buffering mechanism, eliminating clock deviation and transmission delay differences between channels, and outputting time-synchronized multi-channel parallel video data.

[0056] In some optional embodiments, the system performs channel alignment through frame identifier detection and elastic buffering mechanism, including three working modes: a first working mode, a second working mode, and a third working mode. In the first working mode, the system directly transmits the received data from each single channel, outputting a total of 12 independent data channels in the first working mode; In the second working mode, the system outputs the received data from two adjacent links in the first working mode after synchronizing them, and outputs a total of six channels of data in the second working mode. In the third operating mode, the system synchronizes the received data from the four links in the first operating mode within the group and then outputs the data, resulting in a total of three outputs in the third operating mode. This embodiment sets up three channel alignment units, grouped according to the hardware banks of the GTH. Each channel alignment unit is associated with a four-channel configuration unit corresponding to a GTH bank. This grouped alignment architecture can fully utilize the clock resources within the bank, achieving higher alignment accuracy, while also providing a clear architecture and facilitating expansion.

[0057] In this embodiment, the channel alignment unit supports three working modes: single-link independent transmission mode, dual-link bonded transmission mode, and four-link bonded transmission mode, which can be flexibly configured according to actual transmission bandwidth requirements. (1) Single-link independent transmission mode: The channel alignment unit does not perform data synchronization processing and directly outputs the video data received by each physical channel. In this mode, the twelve channels can operate independently and output twelve independent video data streams that do not interfere with each other. It is suitable for use scenarios that transmit twelve low-definition, low-bitrate video images at the same time. (2) Dual-link binding transmission mode: The channel alignment unit performs time synchronization processing on the data of two adjacent single links and outputs them in a unified manner. The two links are merged into a group, and the system outputs a total of six composite video data streams, which is suitable for transmitting medium-definition and medium-bitrate video images. (3) Four-link binding transmission mode: The channel alignment unit will synchronize and integrate the data of all four single links in the same group and output them in a unified manner. The four links are merged into one group, and the system outputs a total of three synthetic video data streams, which is suitable for transmitting ultra-high resolution, high refresh rate and ultra-high bit rate video images.

[0058] Taking the four-link bonded transmission mode as an example, the specific implementation mechanism of multi-channel synchronization alignment is explained in detail. The timing diagram of the four-link bonded transmission mode is attached. Figure 5 As shown, the Header is the frame header, lane represents the channel number, SOP (Start of Packet) indicates the start of the data packet, lane0reg1 represents register 1 of channel 0, lane0reg2 represents register 2 of channel 0, CRC (Cyclic Redundancy Check) indicates cyclic redundancy check, and DATA represents the payload data segment. Synchronization alignment in the four-link bonded transmission mode uses the SOF (Start to Frame) identifier of the ADVB frame as the synchronization reference. The output phase of each data path is adjusted through elastic buffering. The specific steps are as follows: (1) Link establishment waiting stage: The channel alignment unit continuously detects the handshake success signal of the 4 channels in the group. Only when the handshake success signal of all 4 channels is valid, that is, all links are established, will the synchronization alignment process be started. (2) SOF detection and data buffering: After the synchronization process starts, the channel alignment unit detects the SOF frame start identifier in the received data of the four channels in real time. At time T0, the channel alignment unit detects the SOF identifier input to link 3, records the SOF arrival time T0 of link 3, and starts the data register of link 3 to buffer the input data of link 3 frame by frame; at time T1, the channel alignment unit detects the SOF identifier input to link 0 and link 2; records the SOF arrival times T1 and T2 of link 0 and link 2 respectively, and starts the data register buffer of the corresponding channel; at time T3, the channel alignment unit detects the SOF identifier input to link 1, records the SOF arrival time T3 of link 1, and starts the data register buffer of link 1. (3) Synchronization reference time determination: After all the SOF identifiers of the four links in the group have been detected, the arrival time of the last SOF is marked as the synchronization reference time, that is, the T3 time in this embodiment is the synchronization end time. (4) Calculation of delay difference and number of registers: Calculate the time difference between the SOF arrival time and the synchronization reference time for each channel. This time difference is the additional registration time required for the data. Since the data is registered step by step in the parallel clock domain, the corresponding number of data registers can be obtained by dividing the time difference by the parallel clock cycle. For example, if the SOF arrival time of link 3 is T0 and the synchronization reference time is T3, then the time difference is T3-T0, and the corresponding number of registers is (T3-T0) / Tclk, where Tclk is the parallel clock cycle. (5) Data Alignment Output: Based on the calculated number of clock cycles for each channel, the corresponding number of clock cycles is read from its respective elastic buffer, and then combined bit by bit into a parallel data stream with a width of 4 channels, which is then output to the upper protocol layer. At this time, the data of the 4 channels are completely aligned at the output time, eliminating the transmission delay difference between links; (6) Real-time dynamic alignment: For each subsequent ADVB frame, the above process of SOF detection, time recording, delay calculation, and alignment output is repeated to achieve frame-by-frame dynamic synchronization alignment. This mechanism can track the drift of link delay in real time, ensure synchronization accuracy under long-term operation, and avoid the accumulation of link delay offset caused by temperature and voltage changes.

[0059] Through the aforementioned channel alignment mechanism, this embodiment can effectively eliminate clock skew and link delay differences between multiple channels, providing the upper ARINC818 protocol layer with completely consistent timing of multi-channel parallel video data, ensuring that the video images transmitted by multiple channels are complete and tear-free, and meeting the high reliability requirements of aviation video transmission.

[0060] In some optional embodiments, the corresponding parameters of the GTH transceiver and the CPLL within the GTH transceiver are calculated using the phase-locked loop output frequency formula and the linear rate formula, including: set up This is the output frequency of the phase-locked loop. For the reference clock input frequency, This is the first feedback frequency division coefficient of the phase-locked loop. This is the second feedback frequency division coefficient of the phase-locked loop. Let be the input frequency divider of the phase-locked loop (PLL), then the formula for the PLL output frequency is: ; set up For high-speed serial line rate, Let the transceiver output frequency division factor be denoted as , then the formula for the line rate of the GTH transceiver is: .

[0061] In some optional embodiments, the link monitoring unit generates link establishment status signals through the IDLE primitive detection mechanism and the frame check detection mechanism respectively; when IDLE primitives transmitted on the link are continuously detected, the link establishment is determined to be complete; when the input ADVB frame format is detected to conform to the digital video bus protocol specification and the CRC check result is correct, the link establishment is determined to be complete, thus confirming the link validity under the link service transmission state.

[0062] In some optional embodiments, the DRP dynamic configuration unit writes the corresponding parameters of the GTH transceiver and the CPLL in the GTH transceiver through the dynamic reconfiguration bus to complete the non-compilation dynamic switching of the line rate, including: The DRP dynamic configuration unit receives the target rate code and configuration enable signal transmitted by the control unit, and looks up the table to obtain the physical parameters of the GTH transceiver and the phase-locked loop configuration parameters corresponding to the target rate. The physical parameters and phase-locked loop configuration parameters of the GTH transceiver are written into the corresponding configuration register of the GTH transceiver via the DRP configuration bus. Set the phase-locked loop reset signal to perform a reset operation on the phase-locked loop in the GTH transceiver; The phase-locked loop (PLL) lock signal is continuously monitored. Once the PLL lock signal goes high, the core reset signal of the GTH transceiver is set to reset the serial transceiver unit of the GTH transceiver. The GTH transceiver reset completion signal is continuously monitored. Once the reset completion signal goes high, the marker line rate dynamic switching is completed.

[0063] This invention, through a cross-bank multiplexing design of the reference clock and a DRP dynamic configuration mechanism, supports 10 standard digital video bus rates and 1 custom high rate. This rate coverage is far greater than the four rates of existing technologies, ensuring compatibility with avionics equipment of different generations and rate levels. During system upgrades or expansions, no hardware circuitry modifications are required; dynamic configuration alone can adapt to video transmission scenarios with varying bandwidth requirements, significantly reducing system upgrade costs and shortening product iteration cycles. It can adapt to all scenarios, from low-resolution surveillance video to high-resolution cockpit displays.

[0064] This invention employs a multi-channel group alignment architecture, setting up independent channel alignment units at the bank level. Through SOF frame identifier detection, elastic buffering, and phase calibration mechanisms, it can accurately eliminate clock deviations and link transmission delay differences between channels, ensuring high timing consistency of multi-channel parallel video data. This effectively avoids problems such as screen tearing, line misalignment, and frame asynchrony that occur during multi-link transmission, fully meeting the stringent requirements of high reliability and high synchronization for aviation video transmission. It also supports three flexible link modes: X1, X2, and X4, dynamically aggregating link resources according to bandwidth requirements, balancing resource utilization and transmission capacity.

[0065] This invention implements complete digital video bus physical layer functionality, including dynamic rate switching, real-time link status monitoring, data validity verification, and automatic fault recovery. Link monitoring employs a dual-determination mechanism of IDLE primitives and ADVB frame CRC, adapting to unidirectional transmission characteristics while filtering out transient link errors, thus improving link stability. Simultaneously, a built-in test data generation unit supports link self-testing and bit error rate testing, enabling link fault location and performance verification without additional testing equipment, significantly reducing the difficulty and cost of system debugging and maintenance. Rate configuration supports both manual fixed configuration and automatic adaptive negotiation modes, satisfying both the fixed-rate output requirements of the transmitting end and the automatic adaptation rate requirements of the receiving end, offering high configuration flexibility.

[0066] This invention adopts a modular and grouped architecture design. The reference clock generation unit, channel configuration unit, and channel alignment unit are all standardized units, which can be smoothly expanded to 12 or more channels according to actual needs. It can easily adapt to multi-channel parallel video transmission scenarios with multiple displays, multiple cameras, and multiple sensors in avionics systems. The grouped alignment architecture also means that expansion does not require modification of the core synchronization logic; only the corresponding group's alignment unit needs to be added, providing good engineering scalability.

[0067] Example 2 The method employs the same principle as in Example 1, as shown in the appendix. Figure 6 As shown, this embodiment provides a method for implementing a digital video bus physical layer system based on multi-channel adaptive rate, including: the system receives multiple differential reference clocks from external input, generates multiple parallel reference clock signals and outputs them, providing a multi-frequency clock source for high-speed serial links.

[0068] A reference clock is fundamental to high-speed serial communication, and a stable and compatible reference clock is a prerequisite for supporting multi-rate transmission. In this step, the reference clock generation unit receives multiple differential reference clock signals from external input, generates multiple parallel reference clock signals, and outputs them to the GTH transceivers of each channel configuration unit, providing a stable reference clock source for high-speed serial communication.

[0069] The system receives external configuration signals and outputs link status signals, configures the link rate, and monitors the link status. The system monitors the physical link status of the GTH transceiver and the data format of the digital video bus transmitted on the link in real time, and generates a link establishment status signal. The system writes the corresponding parameters of the GTH transceiver and the CPLL in the GTH transceiver through the dynamic reconfiguration bus to complete the non-compiled dynamic switching of the line rate. The system completes the encoding and decoding of serial data, serial-to-parallel conversion, and clock data recovery.

[0070] The system collects the received data and link status of each channel in groups by channel, and performs channel alignment through frame identifier detection and elastic buffering mechanism to eliminate clock deviation and transmission delay differences between channels, and outputs multi-channel parallel video data with synchronized timing.

[0071] When transmitting a single video signal using multi-link bonding, differences in PCB trace lengths across channels and variations in transceiver delays can lead to inconsistent arrival times for the same data frame across different channels, resulting in inter-channel transmission delay differences. Without alignment, the inconsistent timing of the multiple data streams received by the upper protocol layer can cause video tearing, misalignment, and other anomalies. Therefore, this embodiment includes a channel alignment unit to eliminate delay differences between multiple channels and achieve data synchronization.

[0072] In some alternative embodiments, the differential reference clock input ports of the hardware groups of different GTH transceivers are configured with clock parameters of different frequencies.

[0073] In some optional embodiments, each channel configuration unit further includes a test data generation unit; the test data generation unit controls the data path switching according to the externally input test enable signal, and generates a pseudo-random test sequence in test mode to replace service data and send it to the GTH transceiver for link bit error rate testing and link fault location during the link debugging phase.

[0074] After the system reset is complete, it checks whether the auto-configuration enable signal is valid. If the auto-configuration enable signal is invalid, it enters manual configuration mode, reads the externally input rate encoding value, configures the parameters corresponding to the rate, and outputs the link status upon completion. If the auto-configuration enable signal is valid, it selects the preset initial link rate, completes the rate configuration, and then checks the link handshake status. If the link handshake is successful, it locks the current rate parameters, outputs the link status, and ends the rate negotiation process. If the link handshake is unsuccessful, it switches to the next rate in the preset rate list and repeats the link rate configuration and link detection steps until the link handshake is successful or the preset negotiation timeout condition is met.

[0075] In some optional embodiments, the corresponding parameters of the GTH transceiver and the CPLL within the GTH transceiver are calculated using the phase-locked loop output frequency formula and the linear rate formula, including: set up This is the output frequency of the phase-locked loop. For the reference clock input frequency, This is the first feedback frequency division coefficient of the phase-locked loop. This is the second feedback frequency division coefficient of the phase-locked loop. Let be the input frequency divider of the phase-locked loop (PLL), then the formula for the PLL output frequency is: ; set up For high-speed serial line rate, Let the transceiver output frequency division factor be denoted as , then the formula for the line rate of the GTH transceiver is: .

[0076] In some optional embodiments, the link monitoring unit generates link establishment status signals through the IDLE primitive detection mechanism and the frame check detection mechanism respectively; when IDLE primitives transmitted on the link are continuously detected, the link establishment is determined to be complete; when the input ADVB frame format is detected to conform to the digital video bus protocol specification and the CRC check result is correct, the link establishment is determined to be complete, thus confirming the link validity under the link service transmission state.

[0077] In some optional embodiments, the DRP dynamic configuration unit writes the corresponding parameters of the GTH transceiver and the CPLL in the GTH transceiver through the dynamic reconfiguration bus to complete the non-compilation dynamic switching of the line rate, including: The DRP dynamic configuration unit receives the target rate code and configuration enable signal transmitted by the control unit, and looks up the table to obtain the physical parameters of the GTH transceiver and the phase-locked loop configuration parameters corresponding to the target rate. The physical parameters and phase-locked loop configuration parameters of the GTH transceiver are written into the corresponding configuration register of the GTH transceiver via the DRP configuration bus. Set the phase-locked loop reset signal to perform a reset operation on the phase-locked loop in the GTH transceiver; The phase-locked loop (PLL) lock signal is continuously monitored. Once the PLL lock signal goes high, the core reset signal of the GTH transceiver is set to reset the serial transceiver unit of the GTH transceiver. The GTH transceiver reset completion signal is continuously monitored. Once the reset completion signal goes high, the marker line rate dynamic switching is completed.

[0078] In some optional embodiments, in the transmission path of the GTH transceiver, parallel service data is input to the GTH transceiver via the transmission data interface, and after encoding and parallel-to-serial conversion are completed in sequence, it is output in the form of differential serial signal; in the reception path of the GTH transceiver, the GTH transceiver receives the externally input differential serial signal, and after clock data recovery, serial-to-parallel conversion and decoding are completed in sequence, it outputs parallel received data to the link monitoring unit and the channel alignment unit.

[0079] In some optional embodiments, the system performs channel alignment through frame identifier detection and elastic buffering mechanism, including three working modes: a first working mode, a second working mode, and a third working mode. In the first working mode, the system directly transmits the received data from each single channel, outputting a total of 12 independent data channels in the first working mode; In the second working mode, the system outputs the received data from two adjacent links in the first working mode after synchronizing them, and outputs a total of six channels of data in the second working mode. In the third working mode, the system synchronizes the received data from the four links in the first working mode within the group and then outputs the data, resulting in a total output of three data streams in the third working mode.

[0080] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A digital video bus physical layer system based on multi-channel adaptive rate, characterized in that, It includes a reference clock generation unit, a multi-channel configuration unit, and a multi-channel alignment unit; The reference clock generation unit is used to receive multiple differential reference clocks from external input, generate multiple parallel reference clock signals and output them, providing a multi-frequency clock source for high-speed serial links; The channel configuration unit includes a control unit, a link monitoring unit, a DRP dynamic configuration unit, and a GTH transceiver unit. The control unit receives external configuration signals and outputs link status signals, configures the link rate, and monitors the link status. The link monitoring unit monitors the physical link status of the GTH transceiver in the GTH transceiver unit and the data format of the digital video bus transmitted on the link in real time, generating a link establishment status signal. The DRP dynamic configuration unit writes the corresponding parameters of the GTH transceiver and its CPLL through the dynamic reconfiguration bus to complete the non-compiled dynamic switching of the line rate. The GTH transceiver unit performs serial data encoding / decoding, serial-to-parallel conversion, and clock data recovery. The control unit is connected to each channel configuration unit and the link monitoring unit. The link monitoring unit is connected to each channel alignment unit. Each channel configuration unit connects to the clock output of the reference clock generation unit to independently receive rate configuration commands. It adjusts the transmission parameters of the GTH transceiver in real time through the dynamic reconfiguration interface, completes the dynamic switching of the digital video bus rate and data transmission and reception, and outputs link status signals and parallel received data. The hardware groups of the GTH transceiver are connected one-to-one with the channel configuration units, which are used to convert the transmitted and received data from serial to parallel through encoding and decoding. The channel alignment unit is connected to each channel configuration unit and is used to collect the received data and link status of each channel in groups by channel. It performs channel alignment through frame identifier detection and elastic buffering mechanism to eliminate clock deviation and transmission delay differences between channels and output time-synchronized multi-channel parallel video data.

2. The digital video bus physical layer system based on multi-channel adaptive rate according to claim 1, characterized in that, Different GTH transceivers have their hardware groups configured with different frequency clock parameters for their differential reference clock input ports.

3. The digital video bus physical layer system based on multi-channel adaptive rate according to claim 1, characterized in that, Each channel configuration unit also includes a test data generation unit; the test data generation unit controls the data path switching according to the externally input test enable signal, and generates a pseudo-random test sequence in test mode to replace the service data and send it to the GTH transceiver for link error rate testing and link fault location during the link debugging phase.

4. A method for implementing a digital video bus physical layer system based on multi-channel adaptive rate, characterized in that, include: The system receives multiple differential reference clocks from external input, generates multiple parallel reference clock signals and outputs them, providing a multi-frequency clock source for high-speed serial links; The system receives external configuration signals and outputs link status signals, configures the link rate, and monitors the link status. The system monitors the physical link status of the GTH transceiver and the data format of the digital video bus transmitted on the link in real time, and generates a link establishment status signal; the system writes the corresponding parameters of the GTH transceiver and the CPLL in the GTH transceiver through the dynamic reconfiguration bus to complete the non-compiled dynamic switching of the line rate; the system completes the encoding and decoding of serial data, serial-to-parallel conversion and clock data recovery. The system collects the received data and link status of each channel in groups by channel, and performs channel alignment through frame identifier detection and elastic buffering mechanism to eliminate clock deviation and transmission delay differences between channels, and outputs multi-channel parallel video data with synchronized timing.

5. The method for implementing a digital video bus physical layer system based on multi-channel adaptive rate according to claim 4, characterized in that, Configuring the link rate includes: after the system reset, determining whether the auto-configuration enable signal is valid; if the auto-configuration enable signal is invalid, entering manual configuration mode, reading the externally input rate encoding value, configuring the parameters of the corresponding rate, and outputting the link status upon completion; if the auto-configuration enable signal is valid, selecting the preset initial link rate, completing the rate configuration, and then detecting the link handshake status; if the link handshake is successful, locking the current rate parameters, outputting the link status, and ending the rate negotiation process; if the link handshake is unsuccessful, switching to the next-order rate in the preset rate list, repeating the link rate configuration and link detection steps until the link handshake is successful or the preset negotiation timeout condition is reached.

6. The method for implementing a digital video bus physical layer system based on multi-channel adaptive rate according to claim 4, characterized in that, The corresponding parameters of the GTH transceiver and its CPLL are calculated using the phase-locked loop output frequency formula and the linear rate formula, including: set up This is the output frequency of the phase-locked loop. For the reference clock input frequency, This is the first feedback frequency division coefficient of the phase-locked loop. This is the second feedback frequency division coefficient of the phase-locked loop. Let be the input frequency divider of the phase-locked loop (PLL), then the formula for the PLL output frequency is: ; set up For high-speed serial line rate, Let the transceiver output frequency division factor be denoted as , then the formula for the line rate of the GTH transceiver is: .

7. The method for implementing a digital video bus physical layer system based on multi-channel adaptive rate according to claim 4, characterized in that, The system generates link establishment status signals through IDLE primitive detection mechanism and frame check detection mechanism respectively; when IDLE primitives transmitted on the link are continuously detected, the link establishment is determined to be complete; when the input ADVB frame format is detected to conform to the digital video bus protocol specification and the CRC check result is correct, the link establishment is determined to be complete, thus confirming the link validity under the service transmission state of the adaptation link.

8. The method for implementing a digital video bus physical layer system based on multi-channel adaptive rate according to claim 4, characterized in that, The system dynamically reconfigures the bus to write corresponding parameters between the GTH transceiver and the CPLL in the GTH transceiver, completing the non-compilation dynamic switching of line rates, including: The system looks up the physical parameters of the GTH transceiver and the phase-locked loop configuration parameters corresponding to the link rate by looking up a table based on the link rate and the auto-configuration enable signal. The physical parameters and phase-locked loop configuration parameters of the GTH transceiver are written into the corresponding configuration register of the GTH transceiver via the DRP configuration bus. Set the phase-locked loop reset signal to perform a reset operation on the phase-locked loop in the GTH transceiver; The phase-locked loop (PLL) lock signal is continuously monitored. Once the PLL lock signal goes high, the core reset signal of the GTH transceiver is set to reset the serial transceiver unit of the GTH transceiver. The GTH transceiver reset completion signal is continuously monitored. Once the reset completion signal goes high, the marker line rate dynamic switching is completed.

9. The method for implementing a digital video bus physical layer system based on multi-channel adaptive rate according to claim 4, characterized in that, In the transmission path of the GTH transceiver, parallel service data is input to the GTH transceiver via the transmission data interface. After encoding and parallel-to-serial conversion are completed sequentially, it is output in the form of a differential serial signal. In the reception path of the GTH transceiver, the GTH transceiver receives the externally input differential serial signal. After clock data recovery, serial-to-parallel conversion and decoding are completed sequentially, it outputs parallel received data to the link monitoring unit and the channel alignment unit.

10. The method for implementing a digital video bus physical layer system based on multi-channel adaptive rate according to claim 4, characterized in that, The system performs channel alignment through frame identifier detection and elastic buffering mechanism, including three working modes: first working mode, second working mode and third working mode. In the first working mode, the system directly transmits the received data from each single channel, outputting a total of 12 independent data channels in the first working mode; In the second working mode, the system outputs the received data from two adjacent links in the first working mode after synchronizing them, and outputs a total of six channels of data in the second working mode. In the third working mode, the system synchronizes the received data from the four links in the first working mode within the group and then outputs the data, resulting in a total output of three data streams in the third working mode.

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