Method, apparatus and storage medium for processing video content

Abstract

The present disclosure provides a method, an apparatus and a storage medium for processing video content. The method can include receiving a bitstream including video content, determining whether a first signal associated with the video content satisfies a given condition, and in response to determining that the first signal satisfies the given condition, disabling a cross-component adaptive loop filter (CCALF) process and a chroma adaptive loop filter (ALF) process.

Description

[0001] This application is a divisional application of an international application filed in China. The original application was filed on May 24, 2021, with application number "202180033009.0" and titled "Method and Apparatus for Processing Video Content" (international application number PCT / US2021 / 033941, titled "Method and Apparatus for Processing VideoContent").

[0002] Cross-references to related applications

[0003] This disclosure claims priority to U.S. Provisional Application No. 63 / 028.615, filed May 22, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0004] This disclosure generally relates to video processing, and more specifically, to methods and apparatus for processing video content using advanced syntactic cleanup of VVC. Background Technology

[0005] Video is a set of still images (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, video can be compressed before storage or transmission and then decompressed before display. The compression process is usually called encoding, and the decompression process is usually called decoding. There are various video coding formats that use standardized video coding techniques, the most common being prediction, transform, quantization, entropy coding, and loop filtering. Video coding standards, such as the High Efficiency Video Coding (HEVC / H.265) standard, the Universal Video Coding (VVC / H.266) standard, and the Audio Video Coding Standard (AVS) standard, specify specific video coding formats and are developed by standardization organizations. As more and more advanced video coding technologies are adopted in video standards, the coding efficiency of new video coding standards is also increasing. Summary of the Invention

[0006] Embodiments of this disclosure provide a method and apparatus for video content processing. The method may include: receiving a bitstream containing video content; determining whether a first signal associated with the video content satisfies a given condition; and, in response to determining that the first signal satisfies the given condition, disabling a Cross Component Adaptive Loop Filter (CCALF) process and a Chroma Adaptive Loop Filter (ALF) process.

[0007] The apparatus may include a memory storing an instruction set; and one or more processors configured to execute the instruction set to cause the apparatus to perform: receiving a bitstream including video content; determining whether a first signal associated with the video content satisfies a given condition; and, in response to determining that the first signal satisfies the given condition, disabling the Cross Component Adaptive Loop Filter (CCALF) process and the Chroma Adaptive Loop Filter (ALF) process.

[0008] Embodiments of this disclosure also provide a non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a computer to cause the computer to perform a method for processing video content, the method comprising: receiving a bitstream containing the video content; determining whether a first signal associated with the video content satisfies a given condition; and disabling a cross-component adaptive loop filter (CCALF) process and a chroma adaptive loop filter (ALF) process in response to determining that the first signal satisfies the given condition.

[0009] Embodiments of this disclosure also provide a method and apparatus for processing video content. The method may include: receiving a bitstream comprising video content; determining whether a first signal associated with the video content satisfies a given condition; and, in response to determining that the first signal satisfies the given condition, disabling correlated quantization (DQ) and symbolic data hiding (SDH) for at least one stripe.

[0010] The apparatus may include a memory storing an instruction set; and one or more processors configured to execute the instruction set to cause the apparatus to perform: receiving a bitstream including video content; determining whether a first signal associated with the video content satisfies a given condition; and disabling correlated quantization (DQ) and symbolic data hiding (SDH) for at least one stripe in response to determining that the first signal satisfies the given condition.

[0011] Embodiments of this disclosure also provide a non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a computer to cause the computer to perform a method for processing video content, the method comprising: receiving a bitstream including the video content; determining whether a first signal associated with the video content satisfies a given condition; and disabling correlated quantization (DQ) and symbolic data hiding (SDH) for at least one stripe in response to determining that the first signal satisfies the given condition.

[0012] Embodiments of this disclosure also provide an apparatus for processing video content, comprising: a first receiving module for receiving a bitstream including video content; a first processing module for determining whether a first signal associated with the video content satisfies a given condition; and, in response to determining that the first signal satisfies the given condition, disabling the Cross Component Adaptive Loop Filter (CCALF) process and the Chroma Adaptive Loop Filter (ALF) process.

[0013] Embodiments of this disclosure also provide an apparatus for processing video content, comprising: a second receiving module for receiving a bitstream including video content; a second processing module for determining whether a first signal associated with the video content satisfies a given condition; and, in response to determining that the first signal satisfies the given condition, disabling correlated quantization (DQ) and symbolic data hiding (SDH) for at least one stripe.

[0014] Embodiments of this disclosure also provide a storage medium product used for storing bit streams generated by the apparatus as described above. Attached Figure Description

[0015] The following detailed description and accompanying drawings illustrate embodiments and aspects of this disclosure. The various features shown in the figures are not drawn to scale.

[0016] Figure 1 A schematic diagram illustrating the structure of an example video sequence consistent with some embodiments of this disclosure is shown.

[0017] Figure 2A A schematic diagram illustrating an exemplary encoding process of a hybrid video encoding system consistent with some embodiments of this disclosure is shown.

[0018] Figure 2B A schematic diagram of another exemplary encoding process for a hybrid video encoding system consistent with some embodiments of this disclosure is shown.

[0019] Figure 3A A schematic diagram illustrating an exemplary decoding process of a hybrid video coding system consistent with some embodiments of this disclosure is shown.

[0020] Figure 3B A schematic diagram of another exemplary decoding process of a hybrid video coding system consistent with some embodiments of this disclosure is shown.

[0021] Figure 4 A block diagram of an exemplary apparatus for encoding or decoding video is shown, consistent with some embodiments of this disclosure.

[0022] Figure 5 A flowchart illustrating an exemplary method for processing video content, consistent with some embodiments of the present invention, is shown.

[0023] Figure 6 An exemplary sequence parameter set syntax structure consistent with some embodiments of the present invention is shown.

[0024] Figure 7 An exemplary image header syntax structure consistent with some embodiments of the present invention is shown.

[0025] Figure 8 An exemplary strip header syntax structure consistent with some embodiments of the present invention is shown.

[0026] Figure 9 An exemplary image parameter set syntax structure consistent with some embodiments of the present invention is shown.

[0027] Figure 10 An exemplary image header syntax structure consistent with some embodiments of the present invention is shown.

[0028] Figure 11 An exemplary strip header syntax structure consistent with some embodiments of the present invention is shown.

[0029] Figure 12 A flowchart illustrating an exemplary method for processing video content, consistent with some embodiments of the present invention, is shown.

[0030] Figure 13 An exemplary sequence parameter set syntax structure consistent with some embodiments of the present invention is shown.

[0031] Figure 14 An exemplary strip header syntax structure consistent with some embodiments of the present invention is shown.

[0032] Figure 15 Exemplary general constraint syntax structures consistent with some embodiments of the present invention are shown.

[0033] Figure 16A -H illustrates an exemplary sequence parameter set syntax structure consistent with some embodiments of the present invention.

[0034] Figure 17A -F illustrates an exemplary image header syntax structure consistent with some embodiments of the present invention.

[0035] Figure 18A -E illustrates an exemplary strip header syntax structure consistent with some embodiments of the present invention. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, and unless otherwise stated, the same numbers in different drawings denote the same or similar elements. The embodiments set forth in the following description of the exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with aspects of the invention as described in the appended claims. Specific aspects of this disclosure are described below in more detail. In case of conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall prevail.

[0037] The Joint Video Experts Group (JVET) of the ITU-T Video Coding Experts Group (ITU-T VCEG) and the ISO / IEC Moving Picture Experts Group (ISO / IEC MPEG) is currently developing the Universal Video Coding (VVC / H.266) standard. The VVC standard aims to double the compression efficiency of its predecessor, the High Efficiency Video Coding (HEVC / H.265) standard. In other words, VVC aims to achieve the same subjective quality as HEVC / H.265 using half the bandwidth.

[0038] To achieve the same subjective quality as HEVC / H.265 using half the bandwidth, JVET has been developing techniques beyond HEVC using the Joint Exploratory Model (JEM) reference software. With the incorporation of coding techniques into JEM, JEM achieves higher coding performance than HEVC.

[0039] The VVC standard has recently been established and continues to include more coding techniques that provide better compression performance. VVC is based on the same hybrid video coding system used in modern video compression standards such as HEVC, H.264 / AVC, MPEG2, H.263, etc.

[0040] Video is a set of still images (or “frames”) arranged chronologically to store visual information. Video capture devices (e.g., cameras) can be used to capture and store these images chronologically, and video playback devices (e.g., televisions, computers, smartphones, tablets, video players, or any end-user terminal with a display capability) can be used to display such images chronologically. Furthermore, in some applications, video capture devices can transmit captured video in real time to video playback devices (e.g., computers with monitors), such as for surveillance, conferencing, or live streaming.

[0041] To reduce the storage space and transmission bandwidth required for such applications, video can be compressed before storage and transmission, and decompressed before display. Compression and decompression can be implemented in software by a processor (e.g., a processor in a general-purpose computer) or dedicated hardware. The module used for compression is typically called an "encoder," and the module used for decompression is typically called a "decoder." Encoders and decoders can be collectively referred to as a "codec." Encoders and decoders can be implemented as any of a variety of suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders can include circuits such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders can include program code, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process embedded in a computer-readable medium. Video compression and decompression can be implemented using various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, H.26x series, etc. In some applications, a codec can decompress video from a first encoding standard and recompress the decompressed video using a second encoding standard; in this case, the codec can be called a "transcoder."

[0042] Video encoding processes identify and retain useful information that can be used to reconstruct an image, while ignoring information that is not important for reconstruction. If the ignored, unimportant information cannot be fully reconstructed, this encoding process can be called "lossy." Otherwise, it can be called "lossless." Most encoding processes are lossy, a trade-off made to reduce required storage space and transmission bandwidth.

[0043] Useful information about the image being encoded (referred to as the "current image") includes changes relative to a reference image (e.g., a previously encoded and reconstructed image). These changes can include variations in pixel position, brightness, or color, with positional changes being of primary interest. The positional changes of a set of pixels representing an object can reflect the object's movement between the reference and current images.

[0044] An image encoded without referencing another image (i.e., it is its own reference image) is called an "I-image". An image is called a "P-image" if some or all of its blocks (e.g., blocks typically representing portions of a video image) are predicted using intra-frame prediction or inter-frame prediction (e.g., single prediction) with a reference image. An image is called a "B-image" if at least one block in the image is predicted using two reference images (e.g., bidirectional prediction).

[0045] This disclosure relates to methods and apparatus for processing video content consistent with the aforementioned video coding standards.

[0046] Figure 1 The structure of an example video sequence 100 according to some embodiments of the present disclosure is shown. The video sequence 100 may be live video or captured and archived video. The video 100 may be real video, computer-generated video (e.g., computer game video), or a combination thereof (e.g., real video with augmented reality effects). The video sequence 100 may be input from a video capture device (e.g., a camera), a video archive containing previously captured video (e.g., a video file stored on a storage device), or a video feed interface (e.g., a video broadcast transceiver) receiving video from a video content provider.

[0047] like Figure 1 As shown, video sequence 100 may include a series of images arranged temporally along a time axis, including images 102, 104, 106, and 108. Images 102-106 are consecutive, and there are more images between images 106 and 108. Figure 1 In this diagram, image 102 is an I-image, and its reference image is image 102 itself. Image 104 is a P-image, and its reference image is image 102, as indicated by the arrow. Image 106 is a B-image, and its reference images are images 104 and 108, as indicated by the arrow. In some embodiments, the reference image of an image (e.g., image 104) may not immediately precede or follow the image. For example, the reference image of image 104 may be an image preceding image 102. It should be noted that the reference images of images 102-106 are merely examples, and this disclosure does not limit the embodiments of the reference images to specific cases. Figure 1 The example shown.

[0048] Typically, due to the computational complexity of encoding and decoding tasks, video codecs do not encode or decode the entire image at once. Instead, they can segment the image into basic segments and encode or decode the image segment by segment. Such basic segments are referred to in this disclosure as basic processing units (“BPUs”). For example, Figure 1Structure 110 illustrates an example structure of an image (e.g., any one of images 102-108) from video sequence 100. In structure 110, the image is divided into 4×4 basic processing units, whose boundaries are shown as dashed lines. In some embodiments, the basic processing unit may be referred to as a “macroblock” in some video coding standards (e.g., MPEG series, H.261, H.263, or H.264 / AVC), or as a “coding tree unit” (“CTU”) in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing units in the image can have variable sizes, such as 128×128, 64×64, 32×32, 16×16, 4×8, 16×32, or any arbitrary shape and size of pixels. The size and shape of the basic processing units for the image can be chosen based on a balance between coding efficiency and the level of detail to be preserved in the basic processing units. The CTU is the largest block unit, which can include up to 128 × 128 luma samples (plus corresponding chroma samples depending on the chroma format). The CTU can be further divided into coding units (CUs) using quadtrees, binary trees, ternary trees, or combinations thereof.

[0049] A basic processing unit can be a logical unit that may include a set of different types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color image may include a luminance component (Y) representing achromatic luminance information, one or more chrominance components (e.g., Cb and Cr) representing color information, and associated syntactic elements, where the luminance and chrominance components may have the same basic processing unit size. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luminance and chrominance components may be referred to as “code tree blocks” (“CTBs”). Any operation performed on a basic processing unit may be repeated on each of its luminance and chrominance components.

[0050] Video encoding involves multiple operational stages, examples of which are shown in... Figure 2A-2B and Figures 3A-3BAs shown in the diagram. For each stage, the size of the basic processing unit may still be too large to process, and therefore can be further divided into segments referred to herein as "basic processing subunits". In some embodiments, the basic processing subunit may be referred to as a "block" in some video coding standards (e.g., MPEG series, H.261, H.263, or H.264 / AVC), or as a "coding unit" ("CU") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The size of the basic processing subunit may be the same as or smaller than the basic processing unit. Similar to the basic processing unit, the basic processing subunit is also a logical unit that may include a set of different types of video data (e.g., Y, Cb, Cr, and related syntax elements) stored in computer memory (e.g., in a video frame buffer). Any operation performed on a basic processing subunit may be repeated for each of its luminance and chrominance components. It should be noted that this division can be further refined as needed for processing. It should also be noted that different stages may use different schemes to divide the basic processing units.

[0051] For example, in the pattern determination phase (examples of which are in...) Figure 2B As shown in the diagram, the encoder can decide which prediction mode to use for a basic processing unit (e.g., intra-image prediction or inter-image prediction), but the basic processing unit may be too large to make such a decision. The encoder can divide the basic processing unit into multiple basic processing subunits (e.g., CUs as in H.265 / HEVC or H.266 / VVC) and determine the prediction type for each individual basic processing subunit.

[0052] For another example, in the prediction phase (the example is in...) Figure 2A-2B As shown in the diagram, the encoder can perform prediction operations at the level of a basic processing subunit (e.g., CU). However, in some cases, the basic processing subunit may still be too large to handle. The encoder can further divide the basic processing subunit into smaller segments (e.g., referred to as "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC), at which prediction operations can be performed.

[0053] For another example, in the transformation phase (the example of which is in...) Figure 2A-2BAs shown in the diagram, the encoder can perform transform operations on residual basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder can further divide the basic processing subunits into smaller segments (e.g., referred to as "transform blocks" or "TBs" in H.265 / HEVC or H.266 / VVC), at which transform operations can be performed. It should be noted that the partitioning scheme of the same basic processing subunit can differ between the prediction and transform phases. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transform blocks of the same CU can have different sizes and numbers.

[0054] exist Figure 1 In structure 110, the basic processing unit 112 is further divided into 3×3 basic processing sub-units, the boundaries of which are shown by dashed lines. Different basic processing units of the same image can be divided into basic processing sub-units with different schemes.

[0055] In some implementations, to provide parallel processing and fault tolerance for video encoding and decoding, an image can be divided into multiple regions for processing. This allows the encoding or decoding process for a single region of the image to be independent of information from any other region. In other words, each region of the image can be processed independently. By doing so, the codec can process different regions of the image in parallel, thereby improving encoding efficiency. Furthermore, when data in one region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same image without relying on the corrupted or lost data, thus providing fault tolerance. In some video coding standards, images can be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two types of regions: "slices" and "tiles." It should also be noted that different images in a video sequence 100 can have different partitioning schemes for dividing the image into multiple regions.

[0056] For example, in Figure 1 In the diagram, structure 110 is divided into three regions 114, 116, and 118, whose boundaries are shown as solid lines within structure 110. Region 114 comprises four basic processing units. Each of regions 116 and 118 comprises six basic processing units. It should be noted that... Figure 1 The basic processing unit, basic processing subunit, and region of structure 110 are merely examples, and this disclosure does not limit its embodiments.

[0057] Figure 2A A schematic diagram of an example encoding process 200A consistent with embodiments of this disclosure is shown. For example, the encoding process 200A can be performed by an encoder. Figure 2AAs shown, the encoder can encode the video sequence 202 into a video bitstream 228 according to process 200A. (And...) Figure 1 Similar to video sequence 100, video sequence 202 may include a set of images arranged in chronological order (referred to as "original images"). Similar to... Figure 1 In structure 110, each raw image of video sequence 202 can be divided into basic processing units, basic processing subunits, or regions by the encoder for processing. In some embodiments, the encoder can perform process 200A on each raw image of video sequence 202 at the basic processing unit level. For example, the encoder can perform process 200A iteratively, wherein the encoder can encode a basic processing unit in one iteration of process 200A. In some embodiments, the encoder can perform process 200A in parallel on regions (e.g., regions 114-118) of each raw image of video sequence 202.

[0058] exist Figure 2A In this process, the encoder feeds the basic processing units (referred to as "raw BPUs") of the original image of video sequence 202 to prediction stage 204 to generate prediction data 206 and predicted BPUs 208. The encoder can subtract the predicted BPUs 208 from the raw BPUs to generate residual BPUs 210. The encoder can feed the residual BPUs 210 to transform stage 212 and quantization stage 214 to generate quantized transform coefficients 216. The encoder can feed the prediction data 206 and quantized transform coefficients 216 to binary encoding stage 226 to generate video bitstream 228. Components 202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 can be referred to as the "forward path". During process 200A, after quantization stage 214, the encoder can feed the quantized transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate reconstructed residual BPUs 222. The encoder can add the reconstructed residual BPU222 to the predicted BPU208 to generate a prediction reference 224, which is used in the prediction stage 204 of the next iteration of process 200A. Components 218, 220, 222, and 224 of process 200A can be referred to as the "reconstruction path". The reconstruction path can be used to ensure that the encoder and decoder use the same reference data for prediction.

[0059] The encoder can iteratively execute process 200A to encode each raw BPU of the original image (in the forward path) and generate a prediction reference 224 for encoding the next raw BPU of the original image (in the reconstruction path). After encoding all raw BPUs of the original image, the encoder can continue to encode the next image in the video sequence 202.

[0060] Referring to process 200A, the encoder may receive a video sequence 202 generated by a video capture device (e.g., a camera). As used herein, the term "receive" may refer to any action of receiving, inputting, acquiring, retrieving, obtaining, reading, accessing, or otherwise inputting data.

[0061] In prediction phase 204, during the current iteration, the encoder can receive the original BPU and prediction reference 224, and perform prediction operations to generate prediction data 206 and a predicted BPU 208. Prediction reference 224 can be generated from the reconstruction path of a previous iteration of process 200A. The purpose of prediction phase 204 is to reduce information redundancy by extracting prediction data 206, which can be used to reconstruct the original BPU into the predicted BPU 208 from prediction data 206 and prediction reference 224.

[0062] Ideally, the predicted BPU208 should be identical to the original BPU. However, due to non-ideal prediction and reconstruction operations, the predicted BPU208 is typically slightly different from the original BPU. To record this difference, after generating the predicted BPU208, the encoder can subtract it from the original BPU to generate the residual BPU210. For example, the encoder can subtract the pixel values ​​(e.g., grayscale or RGB values) of the predicted BPU208 from the corresponding pixel values ​​of the original BPU. Each pixel of the residual BPU210 can have a residual value, which is the result of this subtraction between the corresponding pixel of the original BPU and the predicted BPU208. Compared to the original BPU, the predicted data 206 and the residual BPU 210 can have fewer bits, but they can be used to reconstruct the original BPU without significant quality degradation. Therefore, the original BPU is compressed.

[0063] To further compress the residual BPU210, in the transform stage 212, the encoder can reduce its spatial redundancy by decomposing the residual BPU210 into a set of two-dimensional “fundamental patterns,” each of which is associated with “transform coefficients.” The fundamental patterns can have the same size (e.g., the size of the residual BPU210). Each fundamental pattern can represent a frequency component of the residual BPU210 (e.g., the frequency of brightness variations). No fundamental pattern can be reproduced from any combination of any other fundamental patterns (e.g., a linear combination). In other words, the decomposition decomposes the variations of the residual BPU210 into the frequency domain. This decomposition is analogous to the discrete Fourier transform of a function, where the fundamental patterns are analogous to the fundamental functions of the discrete Fourier transform (e.g., trigonometric functions), and the transform coefficients are analogous to the coefficients associated with the fundamental functions.

[0064] Different transform algorithms can use different base modes. Various transform algorithms, such as discrete cosine transform, discrete sine transform, etc., can be used in transform stage 212. The transform in transform stage 212 is reversible. That is, the encoder can recover the residual BPU210 through the inverse operation of the transform (called the "inverse transform"). For example, to recover the pixels of the residual BPU210, the inverse transform could be to multiply the value of the corresponding pixel in the base mode by the corresponding correlation coefficient and sum the products to produce a weighted sum. For video coding standards, both the encoder and decoder can use the same transform algorithm (and therefore the same base mode). Therefore, the encoder may only record the transform coefficients, from which the decoder can reconstruct the residual BPU210 without receiving the base mode from the encoder. Compared to the residual BPU210, the transform coefficients can have fewer bits, but they can be used to reconstruct the residual BPU210 without significantly degrading the quality. Therefore, the residual BPU210 is further compressed.

[0065] The encoder can further compress the transform coefficients in the quantization stage 214. During the transform process, different fundamental modes can represent different frequencies of change (e.g., brightness change frequencies). Since the human eye is generally better at recognizing low-frequency changes, the encoder can ignore information about high-frequency changes without causing a significant degradation in decoding quality. For example, in the quantization stage 214, the encoder can generate quantized transform coefficients 216 by dividing each transform coefficient by an integer value (called a "quantization scaling factor") and rounding the quotient to its nearest integer. After such an operation, some transform coefficients of high-frequency fundamental modes can be converted to zero, and transform coefficients of low-frequency fundamental modes can be converted to smaller integers. The encoder can ignore the zero-valued quantized transform coefficients 216, further compressing the transform coefficients through this operation. The quantization process is also reversible, where the quantized transform coefficients 216 can be reconstructed into transform coefficients in the inverse operation of quantization (called "inverse quantization").

[0066] Because the encoder ignores the remainder of such division during rounding operations, quantization stage 214 can be lossy. Typically, quantization stage 214 can cause the greatest information loss in process 200A. The greater the information loss, the fewer bits the quantization transform coefficients 216 may require. To obtain different levels of information loss, the encoder can use different values ​​of the quantization parameters or any other parameters of the quantization process.

[0067] In the binary encoding stage 226, the encoder may encode the prediction data 206 and the quantized transform coefficients 216 using binary encoding techniques (e.g., entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless or lossy compression algorithm). In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the encoder may encode other information in the binary encoding stage 226, such as the prediction mode used in the prediction stage 204, the parameters of the prediction operation, the transform type in the transform stage 212, the parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bitrate control parameters), etc. The encoder may use the output data of the binary encoding stage 226 to generate a video bitstream 228. In some embodiments, the video bitstream 228 may be further packaged for network transmission.

[0068] Referring to the reconstruction path of process 200A, in the inverse quantization stage 218, the encoder can perform inverse quantization on the quantized transform coefficients 216 to generate reconstructed transform coefficients. In the inverse transform stage 220, the encoder can generate reconstructed residual BPU 222 based on the reconstructed transform coefficients. The encoder can add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a prediction reference 224 that will be used in the next iteration of process 200A.

[0069] It should be noted that other variations of process 200A can be used to encode video sequence 202. In some embodiments, the various stages of process 200A may be performed by the encoder in different orders. In some embodiments, one or more stages of process 200A may be combined into a single stage. In some embodiments, a single stage of process 200A may be divided into multiple stages. For example, transform stage 212 and quantization stage 214 may be combined into a single stage. In some embodiments, process 200A may include additional stages. In some embodiments, process 200A may be omitted. Figure 2A One or more stages in the process.

[0070] Figure 2B A schematic diagram of another example encoding process 200B consistent with embodiments of this disclosure is shown. Process 200B can be modified from process 200A. For example, process 200B can be used by an encoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared to process 200A, the forward path of process 200B additionally includes a mode determination stage 230 and divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044. The reconstruction path of process 200B additionally includes a loop filter stage 232 and a buffer 234.

[0071] Generally, prediction techniques can be divided into two categories: spatial prediction and temporal prediction. Spatial prediction (e.g., intra-image prediction or "intra-frame prediction") can use pixels from one or more coded neighboring BPUs in the same image to predict the current BPU. That is, the prediction reference 224 in spatial prediction can include neighboring BPUs. Spatial prediction can reduce the inherent spatial redundancy of images. Temporal prediction (e.g., inter-image prediction or "inter-frame prediction") can use regions from one or more coded images to predict the current BPU. That is, the prediction reference 224 in temporal prediction can include coded images. Temporal prediction can reduce the inherent temporal redundancy of images.

[0072] In reference process 200B, during the forward path, the encoder performs prediction operations in spatial prediction phase 2042 and temporal prediction phase 2044. For example, in spatial prediction phase 2042, the encoder may perform intra-frame prediction. For the original BPU of the image being encoded, prediction reference 224 may include one or more adjacent BPUs that have been encoded (in the forward path) and reconstructed (in the reconstruction path) in the same image. The encoder can generate the predicted BPU 208 by extrapolating adjacent BPUs. Extrapolation techniques may include, for example, linear extrapolation or interpolation, polynomial extrapolation or interpolation, etc. In some embodiments, the encoder may perform extrapolation at the pixel level, such as by extrapolating the value of the corresponding pixel for each pixel of the predicted BPU 208. The adjacent BPUs used for extrapolation may be located in various orientations relative to the original BPU, such as in the vertical direction (e.g., at the top of the original BPU), the horizontal direction (e.g., to the left of the original BPU), the diagonal direction (e.g., at the lower left, lower right, upper left, or upper right of the original BPU), or any orientation defined in the video coding standard used. For intra-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the neighboring BPUs used, the size of the neighboring BPUs used, extrapolation parameters, and the orientation of the neighboring BPUs used relative to the original BPU.

[0073] In another example, during the temporal prediction phase 2044, the encoder can perform inter-frame prediction. For the original BPU of the current image, the prediction reference 224 can include one or more images (referred to as "reference images") that have been encoded (in the forward path) and reconstructed (in the reconstruction path). In some embodiments, the reference images can be encoded and reconstructed on a BPU-by-BPU basis. For example, the encoder can add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a reconstructed BPU. When all reconstructed BPUs of the same image are generated, the encoder can generate a reconstructed image as the reference image. The encoder can perform a "motion estimation" operation to search for matching regions within the range of the reference image (referred to as a "search window"). The position of the search window in the reference image can be determined based on the position of the original BPU in the current image. For example, the search window can be centered at a position in the reference image that has the same coordinates as the original BPU in the current image and can be extended outward by a predetermined distance. When the encoder (e.g., by using a pixel recursive algorithm, block matching algorithm, etc.) identifies a region in the search window that is similar to the original BPU, the encoder can determine such a region as a matching region. The matching region can have a different size than the original BPU (e.g., less than, equal to, greater than, or different in shape). This is because the reference image and the current image are temporally separated on the time axis (e.g., as...). Figure 1 As shown), the matching region can be considered to have "moved" to the original BPU's location over time. The encoder can record the direction and distance of this movement as a "motion vector." When using multiple reference images (e.g., such as...), Figure 1 When working with image 106 in the image, the encoder can search for a matching region for each reference image and determine its associated motion vector. In some embodiments, the encoder can assign weights to the pixel values ​​of the matching regions of each matching reference image.

[0074] Motion estimation can be used to identify various types of motion, such as translation, rotation, scaling, etc. For inter-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the matching region, the motion vector associated with the matching region, the number of reference images, the weights associated with the reference images, etc.

[0075] To generate the predicted BPU208, the encoder can perform a "motion compensation" operation. Motion compensation can be used to reconstruct the predicted BPU208 based on the predicted data 206 (e.g., motion vectors) and the predicted reference 224. For example, the encoder can move a matching region of the reference image according to the motion vectors, where the encoder can predict the original BPU of the current image. When using multiple reference images (e.g., such as...), Figure 1In image 106), the encoder can move the matching regions of the reference image according to their respective motion vectors and average pixel values. In some embodiments, if the encoder has assigned weights to the pixel values ​​of the matching regions of the respective matching reference images, the encoder can add the weighted sums of the pixel values ​​of the moved matching regions.

[0076] In some embodiments, inter-frame prediction can be unidirectional or bidirectional. Unidirectional inter-frame prediction can use one or more reference images in the same temporal direction relative to the current image. For example, Figure 1 Image 104 in the example is a unidirectional inter-frame prediction image, where the reference image (e.g., image 102) precedes image 104. Bidirectional inter-frame prediction can use one or more reference images in two temporal directions relative to the current image. For example, Figure 1 Image 106 in the image is a bidirectional inter-frame prediction image, wherein reference images (e.g., images 104 and 108) are located in two time directions relative to image 104.

[0077] Referring again to the forward path of process 200B, after spatial prediction stage 2042 and temporal prediction stage 2044, in mode determination stage 230, the encoder can select a prediction mode (e.g., one of intra-frame prediction or inter-frame prediction) for the current iteration of process 200B. For example, the encoder can perform rate-distortion optimization techniques, where the encoder selects a prediction mode based on the bit rate of the candidate prediction modes and the distortion of the reference image reconstructed under the candidate prediction modes to minimize the value of the cost function. Based on the selected prediction mode, the encoder can generate the corresponding predicted BPU 208 and prediction data 206.

[0078] In the reconstruction path of process 200B, if intra-prediction mode is selected in the forward path, the encoder can directly feed prediction reference 224 to spatial prediction stage 2042 for later use (e.g., for extrapolating the next BPU of the current image) after generating prediction reference 224 (e.g., the current BPU encoded and reconstructed in the current image). The encoder can feed prediction reference 224 to loop filter stage 232, where it can apply loop filters to prediction reference 224 to reduce or eliminate distortions (e.g., block artifacts) introduced during the encoding of prediction reference 224. The encoder can apply various loop filter techniques in loop filter stage 232, such as deblocking, sample adaptive offset, adaptive loop filtering, etc. The loop-filtered reference image can be stored in buffer 234 (or "decoded image buffer") for later use (e.g., as an inter-frame prediction reference image for future images of video sequence 202). The encoder can store one or more reference images in buffer 234 for use in temporal prediction stage 2044. In some embodiments, the encoder may encode the parameters of the loop filter (e.g., the loop filter strength), as well as the quantized transform coefficients 216, the prediction data 206, and other information in the binary encoding stage 226.

[0079] Figure 3A A schematic diagram of an example decoding process 300A consistent with embodiments of this disclosure is shown. Process 300A may be corresponding to Figure 2A The compression process 200A in the decompression process is described. In some embodiments, process 300A can be similar to the reconstruction path of process 200A. The decoder can decode the video bitstream 228 into video stream 304 according to process 300A. Video stream 304 can be very similar to video sequence 202. However, due to information loss during compression and decompression (e.g., Figure 2A-2B In the quantization phase 214, video stream 304 typically differs from video sequence 202. Similar to processes 200A and 200B in the figure, the decoder can perform process 300A at the basic processing unit (BPU) level for each image encoded in video bitstream 228. For example, the decoder can perform process 300A iteratively, where the decoder can decode the basic processing unit in one iteration of process 300A. In some embodiments, the decoder can perform process 300A in parallel for regions (e.g., regions 114-118) of each image encoded in video bitstream 228.

[0080] exist Figure 3AIn this process, the decoder can feed a portion of the video bitstream 228 associated with a basic processing unit (referred to as an "encoded BPU") of the encoded image to the binary decoding stage 302. In the binary decoding stage 302, the decoder can decode this portion into prediction data 206 and quantized transform coefficients 216. The decoder can feed the quantized transform coefficients 216 to the inverse quantization stage 218 and the inverse transform stage 220 to generate a reconstructed residual BPU 222. The decoder can feed the prediction data 206 to the prediction stage 204 to generate a predicted BPU 208. The decoder can add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a prediction reference 224. In some embodiments, the prediction reference 224 can be stored in a buffer (e.g., a decoded image buffer in computer memory). The decoder can feed the prediction reference 224 to the prediction stage 204 to perform a prediction operation in the next iteration of process 300A.

[0081] The decoder can iteratively execute process 300A to decode each encoded BPU of the encoded image and generate a prediction reference 224 for decoding the next encoded BPU of the encoded image. After decoding all encoded BPUs of the encoded image, the decoder can output the image to video stream 304 for display and continue decoding the next encoded image in video bitstream 228.

[0082] In binary decoding stage 302, the decoder can perform the inverse operation of the binary encoding technique used by the encoder (e.g., entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless compression algorithm). In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the decoder can decode other information in binary decoding stage 302, such as the prediction mode, parameters of the prediction operation, transform type, parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bitrate control parameters), etc. In some embodiments, if the video bitstream 228 is transmitted over the network in packets, the decoder can unpack it before feeding the video bitstream 228 to binary decoding stage 302.

[0083] Figure 3B A schematic diagram of another example decoding process 300B consistent with embodiments of this disclosure is shown. Process 300B can be modified from process 300A. For example, process 300B can be used by a decoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared to process 300A, process 300B further divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044, and further includes a loop filter stage 232 and a buffer 234.

[0084] In process 300B, for the encoded basic processing unit (referred to as the "current BPU") of the encoded image being decoded (referred to as the "current image"), the prediction data 206 decoded by the decoder from the binary decoding stage 302 can include various types of data depending on the prediction mode used by the encoder to encode the current BPU. For example, if the encoder uses intra-frame prediction to encode the current BPU, the prediction data 206 can include a prediction mode indicator (e.g., a flag value) indicating intra-frame prediction, parameters for the intra-frame prediction operation, etc. Parameters for the intra-frame prediction operation can include, for example, the positions (e.g., coordinates) of one or more neighboring BPUs used as references, the sizes of neighboring BPUs, extrapolation parameters, the orientations of neighboring BPUs relative to the original BPU, etc. For another example, if the encoder uses inter-frame prediction to encode the current BPU, the prediction data 206 can include a prediction mode indicator (e.g., a flag value) indicating inter-frame prediction, parameters for the inter-frame prediction operation, etc. The parameters of the inter-frame prediction operation may include, for example, the number of reference images associated with the current BPU, the weights associated with each reference image, the positions (e.g., coordinates) of one or more matching regions in each reference image, and one or more motion vectors associated with each matching region.

[0085] Based on the prediction mode indicator, the decoder can decide whether to perform spatial prediction (e.g., intra-frame prediction) in the spatial prediction phase 2042 or temporal prediction (e.g., inter-frame prediction) in the temporal prediction phase 2044. Figure 2B The details of performing this spatial or temporal prediction are described in [the previous section], and will not be repeated below. After performing this spatial or temporal prediction, the decoder can generate the predicted BPU208. For example... Figure 3A The decoder can add the predicted BPU 208 and the reconstructed residual BPU 222 to generate a prediction reference 224.

[0086] In process 300B, the decoder can feed prediction reference 224 to spatial prediction stage 2042 or temporal prediction stage 2044 to perform prediction operations in the next iteration of process 300B. For example, if the current BPU is decoded using intra-frame prediction in spatial prediction stage 2042, the decoder can directly feed prediction reference 224 to spatial prediction stage 2042 for later use (e.g., for extrapolating the next BPU of the current image) after generating prediction reference 224 (e.g., the decoded current BPU). If the current BPU is decoded using inter-frame prediction in temporal prediction stage 2044, the decoder can feed prediction reference 224 to loop filter stage 232 to reduce or eliminate distortion (e.g., block artifacts) after generating prediction reference 224 (e.g., a reference image where all BPUs have been decoded). Figure 2B The described method applies a loop filter to prediction reference 224. The loop-filtered reference image can be stored in buffer 234 (e.g., a decoded image buffer in computer memory) for later use (e.g., as an inter-frame prediction reference image used as a future encoded image for video bitstream 228). The decoder can store one or more reference images in buffer 234 for use in the temporal prediction stage 2044. In some embodiments, the prediction data may also include parameters of the loop filter (e.g., loop filter strength). In some embodiments, the prediction data includes parameters of the loop filter when the prediction mode indicator of prediction data 206 indicates that inter-frame prediction is used to encode the current BPU.

[0087] Figure 4 This is a block diagram of an example apparatus 400 for encoding or decoding video, consistent with embodiments of this disclosure. Figure 4 As shown, device 400 may include processor 402. When processor 402 executes the instructions described herein, device 400 may become a dedicated machine for video encoding or decoding. Processor 402 may be any type of circuit capable of manipulating or processing information. For example, processor 402 may include any combination of any number of central processing units (or “CPU”), graphics processing units (or “GPU”), neural processing units (“NPU”), microcontroller units (“MCU”), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), application-specific integrated circuits (ASICs), etc. In some embodiments, processor 402 may also be a group of processors grouped into individual logic components. For example, such as Figure 4As shown, processor 402 may include multiple processors, including processor 402a, processor 402b and processor 402n.

[0088] The device 400 may also include a memory 404 configured to store data (e.g., a set of instructions, computer code, intermediate data, etc.). For example, as Figure 4 As shown, the stored data may include program instructions (e.g., program instructions for implementing stages in processes 200A, 200B, 300A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). Processor 402 can access the program instructions and the data for processing (e.g., via bus 410) and execute the program instructions to perform operations or control on the data for processing. Memory 404 may include a high-speed random access memory device or a non-volatile memory device. In some embodiments, memory 404 may include any combination of any number of random access memories (RAM), read-only memories (ROM), optical discs, magnetic disks, hard disks, solid-state drives, flash drives, secure digital cards (SD cards), memory sticks, compact flash (CF) cards, etc. Memory 404 may also be a group of memories grouped into a single logical component. Figure 4 (Not shown in the image).

[0089] Bus 410 may be a communication device for transmitting data between components within device 400, such as an internal bus (e.g., CPU-memory bus), an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect Fast Port), etc.

[0090] For ease of explanation and without ambiguity, processor 402 and other data processing circuitry are collectively referred to as "data processing circuitry" in this disclosure. Data processing circuitry can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. Furthermore, data processing circuitry can be a single, independent module, or it can be wholly or partially integrated into any other component of device 400.

[0091] The device 400 may also include a network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, intranet, local area network, mobile communication network, etc.). In some embodiments, the network interface 406 may include any combination of any number of network interface controllers (NICs), radio frequency (RF) modules, repeaters, transceivers, modems, routers, gateways, wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near field communication (“NFC”) adapters, cellular network chips, etc.

[0092] In some embodiments, the device 400 may optionally include a peripheral interface 408 to provide connectivity to one or more peripheral devices. Figure 4 As shown, peripheral devices may include, but are not limited to, cursor control devices (e.g., mouse, touchpad, or touchscreen), keyboards, displays (e.g., cathode ray tube displays, liquid crystal displays, or light-emitting diode displays), video input devices (e.g., cameras or input interfaces coupled to video files), etc.

[0093] It should be noted that the video codec (e.g., the codec for executing processes 200A, 200B, 300A, or 300B) can be implemented as any combination of any software or hardware modules in device 400. For example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more software modules of device 400, such as program instructions that can be loaded into memory 404. As another example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more hardware modules of device 400, such as dedicated data processing circuitry (e.g., FPGA, ASIC, NPU, etc.).

[0094] In VVC, an adaptive loop filter (ALF) with block-based filter adaptation is applied. For the luma component, one of 25 filters is selected for each 4×4 block based on the direction and activity of the local gradient. In addition to the ALF, the cross-component adaptive loop filter (CCALF) is also used in VVC draft 9. The CCALF filter is designed to operate in parallel with the luma ALF.

[0095] VVC supports three types of Adaptive Parameter Set (APS) Network Abstraction Layer (NAL) units, such as ALF_APS, LMCS_APS, and SCALING_APS. The filter coefficients for the ALF and CCALF processes are indicated in the ALF_APS. Up to 25 sets of luminance ALF filter coefficients and limiting indexes, and up to 8 sets of chrominance ALF filter coefficients and limiting indexes can be indicated in one ALF_APS. Additionally, up to 4 sets of CCALF filter coefficients for the Cb component and up to 4 sets of CCALF filter coefficients for the Cr component can be indicated.

[0096] In VVC Draft 9, two residual coding methods are provided: (a) Regular Residual Coding (RRC) and (b) Transform Skip Residual Coding (TSRC). These residual coding methods are specified in the specification as "residual_coding" and "residual_ts_coding". VVC Draft 9 allows Transform Skip (TS) and Block Differential Pulse Code Modulation (BDPCM) blocks to select either RRC or TSRC under specific conditions. If the slice level flag slice_ts_residual_coding_disabled_flag is equal to 0, then the blocks encoded in TS and BDPCM modes for that slice are TSRC. If the slice level flag slice_ts_residual_coding_disabled_flag is equal to 1, then the TS and BDPCM encoded blocks for that slice are RRC.

[0097] The current VVC design has shortcomings in the no_aps_constraint_flag syntactic element, the no_tsrc_constraint_flag syntactic element, and the syntactic order. This disclosure provides several proposed methods, such as updating the definitions of syntactic elements and updating the syntax table, to address these shortcomings.

[0098] The first drawback concerns the `no_aps_constraint_flag` syntax element. Current VVC designs have several constraint flags indicated in the SPS. These constraint flags (e.g., the `no_aps_constraint_flag` syntax element) can be used to define configuration files for deactivating certain encoding tools. The `no_aps_constraint_flag` syntax element specifies the presence of APS NAL cells in the bitstream. The semantics of `no_aps_constraint_flag` are as follows.

[0099] The syntax element `no_aps_constraint_flag` equal to 1 specifies that there are no NAL units in OlsInScope whose `nuh_unit_type` is equal to `PREFIX_APS_NUT` or `SUFFIX_APS_NUT`, and that `sps_lmcs_enabled_flag` and `sps_scaling_list_enabled_flag` can both be equal to 0. A syntax element `no_aps_constraint_flag` equal to 0 does not impose this constraint.

[0100] As mentioned above, VVC supports three types of APS NAL units, such as ALF_APS, LMCS_APS, and SCALING_APS. From the semantic definition of no_aps_constraint_flag above, it can be seen that if the no_aps_constraint_flag syntactic element is equal to 1, then the encoding tools LMCS and scaling lists are disabled by setting sps_lmcs_enabled_flag and sps_scaling_list_enabled_flag to 0. However, in the current VVC design, ALF and CCALF can still be enabled even if no APS is indicated (i.e., no_APS_constraint_flag equals 1).

[0101] In the current VVC design, the Luminance ALF procedure can be enabled without sending an APS because VVC allows a fixed / default filter bank for the Luminance ALF. However, there is no such fixed / default filter bank for the Chroma ALF and CCALF procedures. Therefore, it can be asserted that the Chroma ALF and CCALF procedures cannot be performed without specifying the filter bank via an APS.

[0102] In the proposed approach, both the chroma ALF and CCALF procedures are disabled when no APS is indicated (i.e., no_APS_constraint_flag equals 1). Methods for disabling the chroma ALF and CCALF procedures include updating the definition of the no_aps_constraint_flag syntax element and introducing new flags. These methods address the aforementioned shortcomings and provide better code efficiency.

[0103] Figure 5 This is a flowchart of an exemplary method for processing video content, consistent with some embodiments of the present invention. The method can be performed by a decoder (e.g., via...). Figure 3A Process 300A or Figure 3B The 300B) is executed or is performed by a device (e.g., Figure 4 The device 400) is executed by one or more software or hardware components. For example, a processor (e.g., Figure 4 The processor 402 can execute Figure 5 The method described in the embodiments. In some embodiments, the method may be implemented by a computer program product contained in a computer-readable medium and includes components developed by a computer (e.g., Figure 4 The device 400 executes computer-executable instructions such as program code.

[0104] Figure 5 The method may include the following steps.

[0105] In step 501, the decoder receives a bitstream including video content (e.g., via...). Figure 3A Process 300A or Figure 3B (300B).

[0106] In step 502, it is determined whether a first signal associated with the video content satisfies a given condition. In some embodiments, this determination includes determining whether the first signal indicates the presence of an Adaptive Parameter Set (APS) Network Abstraction Layer (NAL) unit in the received bitstream. For example, it is determined whether the no_aps_constraint_flag syntax element is equal to 1, because a no_aps_constraint_flag syntax element equal to 1 indicates the absence of an APS NAL unit.

[0107] In step 503, in response to determining that the first signal satisfies a given condition, the Cross Component Adaptive Loop Filter (CCALF) process and the Chromaticity Adaptive Loop Filter (ALF) process are disabled. As described above, the CCALF and Chromaticity ALF processes are disabled if the no_aps_constraint_flag syntax element is equal to 1.

[0108] In some embodiments, the CCALF process can be disabled at the sequence level. The definition of the no_aps_constraint_flag syntax element can be updated by including sps_ccalf_enabled_flag (sps_ccalf_enabled_flag). A no_aps_constraint_flag syntax element equal to 1 indicates that sps_ccalf_enabled_flag can be equal to 0. A sps_ccalf_enabled_flag syntax element equal to 0 indicates that the CCALF process is disabled and not applied to the decoding of images in CLVS associated with video content in the received bitstream. In some embodiments, if the no_aps_constraint_flag syntax element is equal to 1, the value of sps_ccalf_enabled_flag can be equal to 0. If the no_aps_constraint_flag syntax element is equal to 0, no such constraint is imposed.

[0109] In some embodiments, disabling the chroma ALF process at the stripe level can be achieved by updating the definition of the `no_aps_constraint_flag` syntax element. The definition of the `no_aps_constraint_flag` syntax element can be updated by including `sh_alf_cb_flag` (sh_alf_cb_flag), `sh_alf_cr_flag` (sh_alf_cr_flag), and `sh_num_alf_aps_ids_luma` (sh_num_alf_aps_ids_luma). For example, setting the `no_aps_constraint_flag` syntax element to 1 specifies that the values ​​of `sh_alf_cb_flag`, `sh_alf_cr_flag`, and `sh_num_alf_aps_ids_luma` for all stripes in OlsInScope can be equal to 0. Setting the value of `sh_num_alf_aps_ids_luma` to 0 uses the fixed / default filter bank of the luma ALF process. In some embodiments, if the no_aps_constraint_flag syntax element is equal to 1, then the sh_alf_cb_flag, sh_alf_cr_flag, and sh_num_alf_aps_ids_luma syntax elements are equal to 0. If the no_aps_constraint_flag syntax element is equal to 0, then no such constraint is imposed.

[0110] In some embodiments, the chroma ALF process can be disabled at the image level rather than the strip level. The definition of the no_aps_constraint_flag syntax element can be updated by including ph_alf_cb_flag (ph_alf_cb_flag), ph_alf_cr_flag (ph_alf_cr_flag), and ph_num_alf_aps_ids_luma (ph_num_alf_aps_ids_luma). For example, setting the no_aps_constraint_flag syntax element to 1 can specify that the values ​​of ph_alf_cb_flag, ph_alf_cr_flag, and ph_num_alf_aps_ids_luma for all strips in OlsInScope can be equal to 0. Setting the value of ph_num_alf_aps_ids_luma to 0 uses the fixed / default filter bank of the luma ALF process. In some embodiments, if the no_aps_constraint_flag syntax element is equal to 1, then the ph_alf_cb_flag, ph_alf_cr_flag, and ph_num_alf_aps_ids_luma syntax elements are equal to 0. If the no_aps_constraint_flag syntax element is equal to 0, then no such constraint is imposed.

[0111] As described above, the chroma ALF process can be disabled at the stripe header level by updating the definition of the no_aps_constraint_flag syntax element. In some embodiments, the chroma ALF process can be controlled by providing a signal in the bitstream.

[0112] In some embodiments, the method may further include providing a second signal for controlling the chroma ALF process at the image parameter set (PPS) level, sequence parameter set (SPS) level, image header (PH) level, or slice header (SH) level. The second signal may be an SPS level flag or a PPS level flag.

[0113] The image header conveys information about a specific image and contains common information about all stripes belonging to the same image. The SPS contains sequence-level information shared by all images in the entire Coding Layer Video Sequence (CLVS), providing an overall picture of what the bitstream contains and how the information in the bitstream is used. The SPS level is higher than PH and SH, and the SPS level flag can be used to control the chroma ALF process at the SPS, PH, or SH level.

[0114] Similarly, PPS contains syntactic elements related to CLVS. The PPS level is higher than PH and SH. The PPS level flag can be used to control the chroma ALF process at the PPS level, PH level, or SH level.

[0115] In some embodiments, SPS level flags (e.g., `sps_chroma_alf_enabled_flag`) are used to control the ALF process for the chroma components. For example, an SPS_chroma_alf_enabled_flag (sps_chroma_alf_enabled_flag) syntax element equal to 0 can specify that the adaptive loop filter is disabled and not applied to the decoding of the chroma components of the image in CLVS. An SPS_chroma_alf_enabled_flag syntax element equal to 1 can specify that the adaptive loop filter is enabled and can be applied to the decoding of the chroma components of the image in CLVS. When it is not present, the value of `sps_chroma_alf_enabled_flag` is inferred to be equal to 0. It is understood that while this example provides various results based on elements being 0 or 1, it is worth noting that the indication of 0 and 1 is a design choice and the results of this syntax element and other syntax elements can be reversed (e.g., an SPS_chroma_alf_enabled_flag syntax element equal to 0 can specify that the adaptive loop filter is enabled).

[0116] Figure 6-8 Example sequence parameter sets (SPS), picture headers (PH), and stripe headers (SH) syntax tables for the proposed method are shown. The proposed changes can be implemented in the VVC specification as well as in other video coding techniques.

[0117] like Figure 6 As shown, the proposed flag `sps_chroma_alf_enabled_flag` (e.g., element 601) is conditionally indicated when `sps_alf_enabled_flag` (the `sps_alf_enabled_flag`) equals 1 and `ChromaArrayType` != 0 (the chroma array type != 0). Furthermore, the flag `sps_ccalf_enabled_flag` (e.g., element 602) is also conditionally indicated when `sps_alf_enabled_flag` equals 1 and `ChromaArrayType` != 0.

[0118] Figure 7The syntax element ph_alf_aps_id_luma[i] (ph_alf_aps_id_luminance[i]) is introduced, which specifies the aps_adaptation_parameter_set_id (aps_adaptation_parameter_set_id) of the i-th ALF APS referenced by the luminance component of the strip associated with PH. When the ph_alf_aps_id_luma[i] syntax element exists, the following applies: The value of alf_luma_filter_signal_flag (alf_luminance_filter_signal_flag) of the APS NAL cell whose –aps_params_type (aps_params_type) is equal to ALF_APS and whose aps_adaptation_parameter_set_id is equal to ph_alf_aps_id_luma[i] can be equal to 1.

[0119] The TemporalId (time ID) of the APS NAL cell whose –aps_params_type is equal to ALF_APS and aps_adaptation_parameter_set_id is equal to ph_alf_aps_id_luma[i] can be less than or equal to the TemporalId of the image associated with PH.

[0120] – When ChromaArrayType equals 0, the value of aps_chroma_present_flag (aps_chroma_present_flag) of the APS NAL cell where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals ph_alf_aps_id_luma[i] can be equal to 0.

[0121] – When sps_ccalf_enabled_flag equals 0, the values ​​of alf_cc_cb_filter_signal_flag (alf_cc_cb_filter_signal_flag) and alf_cc_cr_filter_signal_flag (alf_cc_cr_filter_signal_flag) of the APS NAL cell where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals ph_alf_aps_id_luma[i] can be equal to 0.

[0122] – Furthermore, in some embodiments of this disclosure, when sps_chroma_alf_enabled_flag equals 0, the value of alf_chroma_filter_signal_flag of the APS NAL unit where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals ph_alf_aps_id_luma[i] can be equal to 0, such as Figure 7 Element 701 is shown.

[0123] Figure 8 The syntax element sh_alf_aps_id_luma[i] (sh_alf_aps_id_luminance[i]) is introduced, where sh_alf_aps_id_luma[i] specifies the aps_adaptation_parameter_set_id of the i-th ALF APS referenced by the luminance component of the strip. When sh_alf_enabled_flag (sh_alf_enabled_flag) is equal to 1 and sh_alf_aps_id_luma[i] does not exist, the value of sh_alf_aps_id_luma[i] is inferred to be equal to the value of ph_alf_aps_id_luma[i]. When sh_alf_aps_id_luma[i] exists, the following applies: The TemporalId of the APS NAL cell whose –aps_params_type is equal to ALF_APS and aps_adaptation_parameter_set_id is equal to sh_alf_aps_id_luma[i] can be less than or equal to the TemporalId of the encoded stripe NAL cell.

[0124] The value of alf_luma_filter_signal_flag for the APS NAL cell whose –aps_params_type is equal to ALF_APS and aps_adaptation_parameter_set_id is equal to sh_alf_aps_id_luma[i] can be equal to 1.

[0125] – When ChromaArrayType equals 0, the value of aps_chroma_present_flag of the APS NAL cell where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals sh_alf_aps_id_luma[i] can be equal to 0.

[0126] – When sps_ccalf_enabled_flag equals 0, the values ​​of alf_cc_cb_filter_signal_flag and alf_cc_cr_filter_signal_flag of the APS NAL unit where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals sh_alf_aps_id_luma[i] can be equal to 0.

[0127] – Furthermore, in some embodiments of this disclosure, when When sps_chroma_alf_enabled_flag equals 0, the value of alf_chroma_filter_signal_flag in the APS NAL unit where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals sh_alf_aps_id_luma[i] can be equal to 0, such as Figure 8 Element 801 is shown in the table.

[0128] In some embodiments, by means of Figure 6-8 The new SPS-level flag `sps_chroma_alf_enabled_flag` syntax element is introduced, which can update the definition of `no_aps_constraint_flag`. For example, a `no_aps_constraint_flag` syntax element equal to 1 indicates that there are no NAL units in OlsInScope with `nuh_unit_type` equal to `PREFIX_APS_NUT` or `SUFFIX_APS_NUT`, and that `sps_chroma_alf_enabled_flag` (in...) Figure 6-8 Introduced in elements 601, 701, and 801), sps_ccalf_enabled_flag (in Figure 6-8 The elements 602, 702, and 802 (introduced in [reference to scaling parameters]) and `sps_lmcs_enabled_flag` and `sps_scaling_list_enabled_flag` can both be equal to 0. In some embodiments, if the `no_aps_constraint_flag` syntax element is equal to 1, then the value of `sh_num_alf_aps_ids_luma` for all stripes in OlsInScope can be equal to 0. If the `no_aps_constraint_flag` syntax element is equal to 0, no such constraint is imposed.

[0129] In some embodiments, a second signal (e.g., a PPS level flag) may also be introduced to control the chroma ALF process at the PPS, PH, or SH levels. For example, a PPS level flag (e.g., PPS_chroma_alf_enabled_flag) can be used to control the ALF process for the chroma components. A syntax element of pps_chroma_alf_enabled_flag (pps_chroma_alf_enabled_flag) equal to 0 can specify that the adaptive loop filter is disabled and not applied to the decoding of the chroma components of the image at the reference PPS. A syntax element of pps_chroma_alf_enabled_flag equal to 1 can specify that the adaptive loop filter is enabled and can be applied to the decoding of the chroma components of the image at the reference PPS. When it does not exist, the value of the pps_chroma_alf_enabled_flag syntax element is inferred to be equal to 0. Understandably, while this example provides various results based on elements being 0 or 1, it is also understandable that the indication of 0 and 1 is a design choice and that the results of this syntax element can be reversed with those of other syntax elements (e.g., the pps_chroma_alf_enabled_flag syntax element being equal to 0 can specify that the adaptive loop filter is enabled).

[0130] Figure 9-11 Example image parameter set (PPS), image header (PH), and stripe header (SH) syntax tables for the proposed method are shown. The following proposed changes can be implemented in the VVC specification as well as in other video coding techniques.

[0131] like Figure 9 As shown in element 901, the proposed flag pps_chroma_alf_enabled_flag is conditionally indicated when pps_chroma_tool_offsets_present_flag (pps_chroma_tool_offsets_present_flag) is equal to 1.

[0132] Figure 10 The syntax element ph_alf_aps_id_luma[i] is introduced, which specifies the aps_adaptation_parameter_set_id of the i-th ALF APS referenced by the luminance component of the strip associated with ph. When ph_alf_aps_id_luma[i] exists, the following applies: The value of alf_luma_filter_signal_flag for the APS NAL cell whose –aps_params_type is equal to ALF_APS and aps_adaptation_parameter_set_id is equal to ph_alf_aps_id_luma[i] can be equal to 1.

[0133] The TemporalId of the APS NAL cell whose –aps_params_type is equal to ALF_APS and aps_adaptation_parameter_set_id is equal to ph_alf_aps_id_luma[i] can be less than or equal to the TemporalId of the image associated with PH.

[0134] – When ChromaArrayType equals 0, the value of aps_chroma_present_flag of the APS NAL cell where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals ph_alf_aps_id_luma[i] can be equal to 0.

[0135] – When sps_ccalf_enabled_flag equals 0, the values ​​of alf_cc_cb_filter_signal_flag and alf_cc_cr_filter_signal_flag of the APS NAL unit where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals ph_alf_aps_id_luma[i] can be equal to 0.

[0136] – Furthermore, in some embodiments of this disclosure, when pps_chroma_alf_enabled_flag equals 0, the value of alf_chroma_filter_signal_flag of the APS NAL unit where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals ph_alf_aps_id_luma[i] can be equal to 0, such as Figure 10 Element 1001 is shown in the table.

[0137] Figure 11The syntax element `ph_alf_aps_id_luma[i]` is introduced, which specifies the `aps_adaptation_parameter_set_id` of the i-th ALF APS referenced by the luminance component of the strip associated with the PH. When `ph_alf_aps_id_luma[i]` exists, the following applies: The syntax element `sh_alf_aps_id_luma[i]` specifies the `aps_adaptation_parameter_set_id` of the i-th ALF APS referenced by the luminance component of the strip. When `sh_alf_enabled_flag` equals 1 and `sh_alf_aps_id_luma[i]` does not exist, the value of `sh_alf_aps_id_luma[i]` is inferred to be equal to the value of `ph_alf_aps_id_luma[i]`. When `sh_alf_aps_id_luma[i]` exists, the following applies: The TemporalId of the APS NAL cell whose –aps_params_type is equal to ALF_APS and aps_adaptation_parameter_set_id is equal to sh_alf_aps_id_luma[i] can be less than or equal to the TemporalId of the encoded stripe NAL cell.

[0138] The value of alf_luma_filter_signal_flag for the APS NAL cell whose –aps_params_type is equal to ALF_APS and aps_adaptation_parameter_set_id is equal to sh_alf_aps_id_luma[i] can be equal to 1.

[0139] – When ChromaArrayType equals 0, the value of aps_chroma_present_flag of the APS NAL cell where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals sh_alf_aps_id_luma[i] can be equal to 0.

[0140] – When sps_ccalf_enabled_flag equals 0, the values ​​of alf_cc_cb_filter_signal_flag and alf_cc_cr_filter_signal_flag of the APS NAL unit where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals sh_alf_aps_id_luma[i] can be equal to 0.

[0141] – Furthermore, in some embodiments of this disclosure, when pps_chroma_alf_enabled_flag equals 0, the value of alf_chroma_filter_signal_flag of the APS NAL unit where aps_params_type equals ALF_APS and aps_adaptation_parameter_set_id equals sh_alf_aps_id_luma[i] can be equal to 0, such as Figure 11 Element 1101 is shown.

[0142] In some embodiments, by means of Figure 9-11 The new PPS level flag pps_chroma_alf_enabled_flag syntax element is introduced, which can update the definition of no_aps_constraint_flag. For example, a no_aps_constraint_flag syntax element equal to 1 indicates that there are no NAL units in OlsInScope with nuh_unit_type equal to PREFIX_aps_NUT or SUFFIX_aps_NUT, and pps_chroma_alf_enabled_flag (in...) Figure 9-11 Introduced in elements 901, 1001, and 1101), sps_ccalf_enabled_flag (in Figure 9-11 The elements 902, 1002, and 1102 (introduced in the standard syntax) and `sps_lmcs_enabled_flag` and `sps_scaling_list_enabled_flag` can both be equal to 0. In some embodiments, if the `no_aps_constraint_flag` syntax element is equal to 1, then the value of `sh_num_alf_aps_ids_luma` for all stripes in OlsInScope can be equal to 0. If the `no_aps_constraint_flag` syntax element is equal to 0, no such constraint is imposed.

[0143] In some embodiments, semantic constraints are applied to `no_aps_constraint_flag` to disable ALF and CCALF. For example, a syntax element of `no_aps_constraint_flag` equal to 1 can specify that there are no NAL units in OlsInScope with `nuh_unit_type` equal to `PREFIX_APS_NUT` or `SUFFIX_APS_NUT`, and `sps_alf_enabled_flag`, `sps_ccalf_enabled_flag`, `sps_lmcs_enabled_flag`, and `sps_scaling_list_enabled_flag` can all be equal to 0. In some embodiments, if the syntax element of `no_aps_constraint_flag` is equal to 1, then the values ​​of `sps_alf_enabled_flag`, `sps_ccalf_enabled_flag`, `sps_lmcs_enabled_flag`, and `sps_scaling_list_enabled_flag` can all be 0. If the syntax element of `no_aps_constraint_flag` is equal to 0, no such constraint is applied.

[0144] The second flaw in the current VVC design relates to disabling Transform Skip Residual Coding (TSRC). Disabling TSRC is prevented in either of the following two cases.

[0145] In the first scenario, enabling Dependency Quantization (DQ) or Symbolic Data Hiding (SDH) for stripes can prevent TSRC disabling.

[0146] In the second case, flags associated with TSRC constraints can be used to prevent TSRC from being disabled.

[0147] This will address both of the above situations so that TSRC can be disabled when needed.

[0148] In the first case, enabling DQ or SDH for the stripe can prevent TSRC from being disabled. Specifically, according to the stripe header syntax of the current VVC design, the TSRC disable flag (i.e., sh_ts_residual_coding_disabled_flag) is set to 0 when either the stripe-level DQ flag (i.e., sh_dep_quant_used_flag) or the stripe-level SDH flag (i.e., sh_sign_data_hiding_used_flag) is equal to 1.

[0149] Setting the `sh_dep_quant_used_flag` syntax element to 0 disables TSRC. According to the definition of the `sh_dep_quant_used_flag` syntax element, setting the `sh_ts_residual_coding_disabled_flag` syntax element to 0 specifies that the `residual_ts_coding()` syntax structure is used to parse the residual samples of the transform skip block for the current slice. Additionally, setting the `sh_dep_quant_used_flag` syntax element to 1 specifies that correlated quantization is used for the current slice. Setting the `sh_sign_data_hiding_used_flag` syntax element to 1 specifies that sign bit hiding is used for the current slice. Disabling TSRC requires both the `sh_dep_quant_used_flag` and `sh_sign_data_hiding_used_flag` syntax elements to 0. Enabling DQ or SDH for a stripe can prevent TSRC from disabling it.

[0150] In the second case, TSRC disabling can be disabled using the `no_tsrc_constraint_flag` syntax element by setting the TSRC disable flag to 0. Specifically, a `no_tsrc_constraint_flag` syntax element equal to 1 specifies that `sh_ts_residual_coding_disabled_flag` can be equal to 0. A `no_tsrc_constraint_flag` syntax element equal to 0 does not impose such a constraint. As mentioned above, a `sh_ts_residual_coding_disabled_flag` syntax element equal to 0 specifies that the `residual_ts_coding()` syntax structure is used to parse the residual samples of the transform skip blocks of the current stripe. If the `sh_ts_residual_coding_disabled_flag` syntax element is set to 0, TSRC is enabled.

[0151] In traditional VVC video coding design, for a given stripe, TSRC can be disabled if all of the following conditions are met (e.g., sh_ts_residual_coding_disabled_flag is 1): – Related quantization (DQ) is disabled (sh_dep_quant_used_flag==0), and – Symbolic data hiding (SDH) is disabled (sh_sign_data_hiding_used_flag==0) Disabling both DQ and SDH will disable TSRC, while enabling either DQ or SDH will prevent TSRC from being disabled.

[0152] In some embodiments of this disclosure, constraints are applied to the no_tsrc_constraint_flag syntax element to disable certain features, such as TSRC. For example, the following embodiments are proposed to disable the following two combinations.

[0153] –no_tsrc_constraint_flag is equal to 1, and DQ is enabled. –no_tsrc_constraint_flag equals 1, and SDH is enabled.

[0154] The proposed method is provided to address situations where TSRC is disabled. In some embodiments of the invention, constraints are applied to the `no_tsrc_constraint_flag` syntax element and syntax elements related to DQ and SDH to disable TSRC. The current syntax elements are updated to provide TSRC disabling functionality, thereby improving code efficiency.

[0155] For example, Figure 12 This is a flowchart of an exemplary method for processing video content, consistent with some embodiments of this disclosure. The method can be performed by a decoder (e.g., via...). Figure 3A Process 300A or Figure 3B 300B) or by means of a device (e.g., Figure 4 The device 400) is executed by one or more software or hardware components. For example, a processor (e.g., Figure 4 The processor 402 can execute the method. In some embodiments, the method can be implemented by a computer program product contained in a computer-readable medium and including components developed by a computer (e.g., processor 402). Figure 4 The device 400 executes computer-executable instructions such as program code. The method may include the following steps.

[0156] In step 1201, the bitstream including video content is received by, for example, a decoder.

[0157] In step 1202, it is determined whether a first signal associated with the video content satisfies a given condition. The first signal may be the no_tsrc_constraint_flag syntax element. In some embodiments, it is determined whether the no_tsrc_constraint_flag syntax element is equal to 1.

[0158] In step 1203, in response to determining that the first signal satisfies a given condition, correlated quantization (DQ) and symbolic data hiding (SDH) are disabled for at least one stripe. For example, when it is determined that the no_tsrc_constraint_flag syntax element is equal to 1, DQ and SDH are disabled for at least one stripe.

[0159] In some embodiments, the method may further include disabling Transform Skip Residual Coding (TSRC) for at least one stripe in response to determining that a first signal satisfies a given condition. For example, the TSRC disable flag is set to 1 when the no_tsrc_constraint_flag syntax element is determined to be equal to 1.

[0160] In some embodiments, DQ and SDH can be disabled at the SPS or SH level. In some embodiments, DQ and SDH can be disabled for all stripes.

[0161] At the SPS level, disabling DQ and SDH applies to all stripes. In some embodiments, the definition of the no_tsrc_constraint_flag syntax element can be updated using constraints associated with the SPS-level DQ and SDH syntax elements. In some embodiments, the definition of the SPS-level DQ and SDH syntax elements can be updated using constraints associated with the no_tsrc_constraint_flag syntax element. In some embodiments, the SPS syntax can be updated using conditional signaling between the no_tsrc_constraint_flag syntax element and the SPS-level DQ and SDH syntax elements.

[0162] At the SH level, the definition of the `no_tsrc_constraint_flag` syntax element can be updated using constraints associated with the SH level DQ and SDH syntax elements of all stripes. In some embodiments, the definition of the SH level DQ and SDH syntax elements of a stripe can be updated using constraints associated with the `no_tsrc_constraint_flag` syntax element, where DQ and SDH disabling is applied to that stripe. In some embodiments, the SH syntax can be updated using conditional signaling between the `no_tsrc_constraint_flag` syntax element and the SH level DQ and SDH syntax elements of the stripe, where DQ and SDH disabling is applied to that stripe. As described above, at the SH level, DQ and SDH disabling can be applied to all stripes or a given stripe.

[0163] The following proposed changes can be made to the VVC specification or implemented in other video coding technologies.

[0164] In some embodiments, semantic constraints are applied to `no_tsrc_constraint_flag` to disable DQ and SDH at the SPS level. Therefore, the proposed semantic changes to `no_tsrc_constraint_flag` below can be made to the VVC specification and can also be implemented in other video coding technologies. For example, setting the `no_tsrc_constraint_flag` syntax element to 1 can specify that `sh_ts_residual_coding_disabled_flag` can be equal to 1 and `sps_dep_quant_enabled_flag` and `sps_sign_data_hiding_enabled_flag` can both be equal to 0. In some embodiments, if the `no_tsrc_constraint_flag` syntax element is equal to 1, then the `sh_ts_residual_coding_disabled_flag` syntax element, the `sps_dep_quant_enabled_flag` syntax element, and the `sps_sign_data_hiding_enabled_flag` syntax element are equal to 0. If the no_tsrc_constraint_flag syntax element is equal to 0, no such constraint is imposed. At the SPS level, disabling DQ and SDH applies to all stripes.

[0165] In some embodiments, semantic constraints are applied to `no_tsrc_constraint_flag` to disable DQ and SDH in all slices of CLVS. Therefore, the proposed semantic changes to `no_tsrc_constraint_flag` below can be made to the VVC specification and can also be implemented in other video coding technologies. For example, setting the syntax element of `no_tsrc_constraint_flag` to 1 can specify that `sh_ts_residual_coding_disabled_flag` is equal to 1 for all slices. 1Furthermore, both `sh_dep_quant_used_flag` and `sh_sign_data_hiding_used_flag` can be equal to 0. In some embodiments, if the `no_tsrc_constraint_flag` syntax element is equal to 1, then the `sh_ts_residual_coding_disabled_flag`, `sh_dep_quant_used_flag`, and `sh_sign_data_hiding_used_flag` syntax elements are equal to 0. If the `no_tsrc_constraint_flag` syntax element is equal to 0, then no such constraint is imposed.

[0166] In some embodiments, semantic constraints are applied to `sps_dep_quant_enabled_flag` and `sps_sign_data_hiding_enabled_flag` to disable DQ and SDH at the SPS level. The proposed semantic changes to `sps_dep_quant_enabled_flag` and `sps_sign_data_hiding_enabled_flag` can be made to the VVC specification or implemented in other video coding techniques. For example, a syntax element of `sps_dep_quant_enabled_flag` equal to 0 can specify that correlated quantization is disabled and not used to reference the image of the SPS. A syntax element of `sps_dep_quant_enabled_flag` equal to 1 can specify that correlated quantization is enabled and can be used to reference the image of the SPS. In some embodiments, the value of `sps_dep_quant_enabled_flag` can be equal to 0 when the value of `no_tsrc_constraint_flag` is equal to 1. For example, a syntax element of `sps_sign_data_hiding_enabled_flag` equal to 0 specifies that sign bit hiding is disabled and not used to reference the image of the SPS. The `sps_sign_data_hiding_enabled_flag` syntax element being equal to 1 indicates that sign bit hiding is enabled and can be used to reference the image of the SPS. When `sps_sign_data_hiding_enabled_flag` is not present, it is inferred to be equal to 0. In some embodiments, the value of `sps_sign_data_hiding_enabled_flag` can be equal to 0 when the value of `no_tsrc_constraint_flag` is equal to 1. DQ and SDH can be disabled at the SPS level for all stripes based on the updated definitions of the `sps_dep_quant_enabled_flag` and `sps_sign_data_hiding_enabled_flag` syntax elements.

[0167] In some embodiments, semantic constraints are applied to stripe-level DQ flags (e.g., sh_dep_quant_used_flag) and SDH flags (e.g., sh_sign_data_hiding_used_flag). For example, a sh_dep_quant_used_flag syntax element equal to 0 can specify that the correlated quantization is not used for the current stripe. A sh_dep_quant_used_flag syntax element equal to 1 can specify that the correlated quantization is used for the current stripe. When sh_dep_quant_used_flag does not exist, it is inferred to be equal to 0. In some embodiments, the value of sh_dep_quant_used_flag can be equal to 0 when the value of no_tsrc_constraint_flag is equal to 1. For example, a sh_sign_data_hiding_used_flag syntax element equal to 0 can specify that the sign bit hiding is not used for the current stripe. A sh_sign_data_hiding_used_flag syntax element equal to 1 can specify that the sign bit hiding is used for the current stripe. When sh_sign_data_hiding_used_flag does not exist, it is inferred to be equal to 0. In some embodiments, when the value of no_tsrc_constraint_flag is equal to 1, the value of sh_sign_data_hiding_used_flag can be equal to 0. DQ and SDH can be disabled for the current stripe at the SH level.

[0168] In the following embodiments of this disclosure, conditional signaling for disabling TSRC can be used to update the SPS syntax table. In some embodiments, conditional signaling for disabling TSRC can be used to update the SH syntax table.

[0169] At the SPS or SH level, SDH can be enabled when DQ is disabled, according to the SPS and SH syntax tables. To prevent a disabled DQ from enabling SDH, a first signal is used to disable SDH after DQ is disabled. In some embodiments, in response to determining that the first signal satisfies a given condition, it is determined whether DQ is disabled for the at least one stripe, and in response to DQ being disabled, SDH is disabled for the at least one stripe. For example, it is determined whether DQ is disabled when the no_tsrc_constraint_flag syntax element is equal to 1. When it is determined that DQ is disabled, SDH is disabled.

[0170] In some embodiments, the SPS syntax table is updated to disable TSRC for all stripes. Figure 13The SPS syntax table for the proposed method is shown. For example, `sps_dep_quant_enabled_flag` and `sps_sign_data_hiding_enabled_flag` are conditionally indicated when `no_tsrc_constraint_flag` is not equal to 0. The following proposed changes to the SPS syntax table can be made to the VVC specification and can also be implemented in other video coding techniques. For example, as... Figure 13 As shown in elements 1301 and 1302, the syntax "!no_tsrc_constraint_flag" is added. When the no_tsrc_constraint_flag syntax element is equal to 1, the value of "!no_tsrc_constraint_flag" is equal to 0, and the value of sps_dep_quant_enabled_flag is set to 0. The sps_dep_quant_enabled_flag syntax element being equal to 0 specifies that correlated quantization is disabled for all stripes at the SPS level. In element 1302, when the no_tsrc_constraint_flag syntax element is equal to 1, the value of "!no_tsrc_constraint_flag" is equal to 0, and even if "!sps_dep_quant_enabled_flag" is equal to 1, the value of sps_sign_data_hiding_enabled_flag is still set to 0. The sps_sign_data_hiding_enabled_flag syntax element being equal to 0 specifies that sign data hiding is disabled for all stripes at the SPS level.

[0171] As mentioned earlier, if both DQ and SDH are disabled for a given stripe, then TSRC for that stripe can be disabled. Since both DQ and SDH are disabled for all stripes, TSRC is disabled for all stripes.

[0172] In some embodiments, the SH syntax table is updated to disable TSRC for stripes. Figure 14 The SH syntax table for the proposed method is shown. For example, when no_tsrc_constraint_flag equals 0, it conditionally indicates the stripe level DQ sh_dep_quant_used_flag and SDH sh_sign_data_hiding_used_flag. Figure 14As shown in elements 1401 and 1402, the syntax includes "!no_tsrc_constraint_flag". When the no_tsrc_constraint_flag syntax element is equal to 1, the sh_dep_quant_used_flag syntax element is set to 0. As shown in element 1402, when the no_tsrc_constraint_flag syntax element is equal to 1, even if the value of "!sh_sign_data_hiding_used_flag" is 1, the sh_sign_data_hiding_used_flag syntax element is still set to 0. Since sh_ts_residual_coding_disabled_flag is conditionally indicated when both the sh_dep_quant_used_flag and sh_sign_data_hiding_used_flag syntax elements are equal to 0, the sh_ts_residual_coding_disabled_flag syntax element is set to 1.

[0173] In some embodiments, semantic constraints are applied to `no_tsrc_constraint_flag` to disable transform skip mode. For example, setting the syntax element of `no_tsrc_constraint_flag` to 1 can specify that `sps_transform_skip_enabled_flag` and `sh_ts_residual_coding_disabled_flag` can be equal to 0. In some embodiments, if the syntax element of `no_tsrc_constraint_flag` is equal to 1, then the syntax element of `sps_transform_skip_enabled_flag` is equal to 0. If the syntax element of `no_tsrc_constraint_flag` is equal to 0, then no such constraint is imposed.

[0174] In some embodiments, the general constraint syntax is updated by removing the `no_tsrc_constraint_flag` syntax element. It should be noted that disabling DQ or SDH may impact coding efficiency. If transform skipping is disabled at the SPS level, TSRC can be disabled. The constraint flag `no_transform_skip_constraint_flag` can be used to disable transform skipping mode. The `no_transform_skip_constraint_flag` syntax element equal to 1 specifies that transform skipping mode is disabled. When the `no_transform_skip_constraint_flag` syntax element equals 1, TSRC is implicitly disabled because there is no transform skipping mode. Therefore, the functionality of `no_tsrc_constraint_flag` overlaps with that of `no_transform_skip_constraint_flag`. To disable TSRC, the `no_tsrc_constraint_flag` syntax element can be removed from the example general constraint syntax, such as... Figure 15 As shown, the no_transform_skip_constraint_flag syntax element can be used without disabling DQ and SDH.

[0175] The third flaw in the current VVC design is the syntax order. For example, in VVC Draft 9, the syntax order is not modular. In the SPS syntax table, the syntax related to transformations is scattered in different locations. In the image header (PH) and strip header (SH), some syntax elements of the loop filter are located at the top of the syntax table, while others are located at the bottom.

[0176] In some embodiments, such as Figure 16A As shown in -H, the syntactic elements of the SPS syntax table are ordered such that all syntactic elements related to transformations are grouped together. This is related to the maximum transformation size (e.g., Figure 16C Element 1601 in the transformation skip (e.g., Figure 16D Element 1602 in the data) and multiple transform sets (MTS) (e.g., Figure 16D Element 1603 in the middle) and low-frequency non-separable transform (LFNST) (e.g., Figure 16D The syntactic elements related to element 1604 in the example SPS syntax table are indicated sequentially. Similarly, sps_lmcs_enabled_flag (e.g., Figure 16D Element 1605 in the table is indicated immediately after the `sps_ccalf_enabled_flag` instruction. Syntactic elements marked with a strikethrough are the positions of the syntactic elements before reordering.

[0177] In some embodiments, the image header (PH) syntax is reordered, such as Figure 17A As shown in -F. For example, the image header (PH) syntax elements associated with SAO and the deblocking process are indicated immediately after the ALF and LMCS related syntax is indicated, such as... Figure 17B Elements 17011 and 17012 in -C are shown. The syntax elements marked with strikethrough are the positions of the syntax elements before reordering.

[0178] In some embodiments, such as Figure 18A As shown in -E, the stripe head (SH) syntax is reordered. For example, stripe head syntax elements related to SAO and the deblocking process (e.g., Figure 18B Element 1801 in the syntax table is indicated immediately after the relevant ALF and LMCS syntax. Syntactic elements marked with a strikethrough are the positions of the syntactic elements before reordering. It is understood that the above embodiments can be combined during implementation.

[0179] In some embodiments, a non-transitory computer-readable storage medium including instructions is also provided, and these instructions can be executed by a device (e.g., the disclosed encoder and decoder) to perform the methods described above. Common forms of non-transitory media include, for example, floppy disks, collapsible disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, PROMs and EPROMs, FLASH-EPROMs or any other flash memory, NVRAM, caches, registers, any other memory chips or cartridges and their network versions. The device may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.

[0180] In some embodiments, an apparatus for processing video content is provided, comprising: The first receiving module is used to receive a bitstream including video content; A first processing module is configured to determine whether a first signal associated with the video content satisfies a given condition; and In response to determining that the first signal satisfies the given condition, the Cross Component Adaptive Loop Filter (CCALF) process and the Chromaticity Adaptive Loop Filter (ALF) process are disabled.

[0181] In some embodiments, the first processing module is specifically used for: Determine whether the first signal indicates the presence of an Adaptive Parameter Set (APS) network abstraction layer (NAL) unit in the received bit stream.

[0182] In some embodiments, the first processing module is further configured to provide a second signal for controlling the chroma ALF process at the image parameter set level, sequence parameter set level, image head level, or strip head level.

[0183] In some embodiments, the second signal indicates whether the chroma ALF process is enabled during the decoding of the chroma components of an image in a coding layer video sequence (CLVS) associated with the video content.

[0184] In some embodiments, an apparatus for processing video content is provided, comprising: The second receiving module is used to receive a bitstream including video content; The second processing module is configured to determine whether a first signal associated with the video content satisfies a given condition; and In response to determining that the first signal satisfies the given condition, correlated quantization (DQ) and symbolic data hiding (SDH) are disabled for at least one stripe.

[0185] In some embodiments, the second processing module is further configured to disable Transform Skip Residual Code (TSRC) for at least one strip in response to determining that the first signal satisfies the given condition.

[0186] In some embodiments, the second processing module is further configured to disable the TSRC for the at least one stripe in response to the DQ and SDH being disabled for the at least one stripe.

[0187] In some embodiments, the second processing module is specifically used for: In response to determining that the first signal satisfies the given condition, for the at least one stripe, the DQ and the SDH are disabled at the stripe header level, image header level, or sequence parameter set level.

[0188] In some embodiments, the second processing module is further specifically used for: In response to determining that the first signal satisfies the given condition, it is determined whether the DQ is disabled for the at least one stripe. In response to the DQ being disabled, the SDH is disabled for the at least one stripe.

[0189] In some embodiments, a computer program product is provided, including a computer program that, when executed by a processor, implements the method as described above.

[0190] In some embodiments, a storage medium product is provided that is used to store a bit stream generated by performing the method described above.

[0191] It should be noted that relational terms in this document, such as “first” and “second”, are used only to distinguish one entity or operation from another, and do not require or imply any actual relationship or order between these entities or operations. Furthermore, the words “including,” “having,” “containing,” and other similar forms are intended to have the same meaning and are open-ended, as one or more items following any of these words do not imply an exhaustive list of those items or are limited to only the listed items.

[0192] As used herein, unless otherwise specified, the term "or" includes all possible combinations unless impractical. For example, if a database is stated to include A or B, then unless explicitly stated or impractical, the database may include A, or B, or A and B. As a second example, if a database is stated to include A, B, or C, then unless explicitly stated or impractical, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0193] It is understood that the above embodiments can be implemented by hardware or software (program code) or a combination of hardware and software. If implemented by software, it can be stored in the above-described computer-readable medium. When executed by a processor, the software can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, software, or a combination of hardware and software. Those skilled in the art will also understand that multiple of the above modules / units can be combined into one module / unit, and each of the above modules / units can be further divided into multiple sub-modules / sub-units.

[0194] In the foregoing description, embodiments have been described with reference to numerous specific details that may vary with different implementations. Certain adjustments and modifications may be made to the described embodiments. Other embodiments will be apparent to those skilled in the art in light of the description and practice of the invention disclosed herein. This description and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims. The order of steps shown in the figures is also for illustrative purposes only and is not intended to be limited to any particular order of steps. Therefore, those skilled in the art will understand that these steps may be performed in a different order while implementing the same method.

[0195] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terms are used, they are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A video decoding method, comprising: Receive the bitstream associated with the video content; Decode the first signal from the encoded information of the bit stream; Based on the first signal, determine whether there is an APS NAL unit in the bit stream; as well as In response to determining that the APS NAL unit is absent in the bitstream, the chroma ALF process is disabled. The process of disabling the chroma ALF includes decoding one or more stripe-level flags that indicate the disabling of chroma ALF, and disabling the chroma ALF process based on the decoded values ​​of the one or more stripe-level flags.

2. The method of claim 1, wherein the one or more strip-level flags comprise: The first band level marker for the chromaticity ALF process corresponding to the chromaticity component Cb, and the second band level marker for the chromaticity ALF process corresponding to the chromaticity component Cr.

3. The method of claim 1, wherein the decoded value of the one or more strip-level flags is equal to 0 for all one or more images in the coding layer video sequence associated with the video content.

4. The method of claim 1, further comprising: In response to determining that the APS NAL unit is not present in the bitstream, a luminance ALF process is performed using a predetermined set of filters.

5. The method of claim 4, wherein performing the luminance ALF process using the predetermined filter set further comprises: Decode the third band-level flag from the encoded information of the bitstream; as well as The luminance ALF process is performed based on the decoded value of the third band level flag.

6. The method of claim 5, wherein the decoded value of the third band-level flag is equal to 0 for all of one or more images in the coding layer video sequence associated with the video content.

7. The method of claim 1, wherein the first signal is a flag, and the method further comprises: In response to the flag having a value equal to 1, it is determined that the APS NAL unit is not present in the received bit stream.

8. A video encoding method, comprising: The first signal is encoded into a bitstream associated with the video content, the first signal indicating the presence of an APS NAL unit in the bitstream; as well as In response to the absence of the APS NAL unit in the bitstream, the chroma ALF process is disabled, and one or more stripe-level flags are encoded into the bitstream, the one or more stripe-level flags indicating that chroma ALF is disabled.

9. The method of claim 8, wherein the one or more stripe-level flags comprise: The first band level marker for the chromaticity ALF process corresponding to the chromaticity component Cb, and the second band level marker for the chromaticity ALF process corresponding to the chromaticity component Cr.

10. The method of claim 8, further comprising: Set the value of the one or more strip-level flags to 0 for all of one or more images in the coding layer video sequence associated with the video content.

11. The method of claim 8, further comprising: In response to the absence of the APS NAL unit in the bitstream, a luminance ALF process is performed using a predetermined set of filters.

12. The method of claim 11, wherein performing the luminance ALF process using the predetermined filter set further comprises: The third strip-level flag associated with the luminance ALF process is encoded into the bitstream.

13. The method of claim 12, further comprising: Set the value of the third band-level flag to 0 for all of one or more images in the coding layer video sequence associated with the video content.

14. The method of claim 8, wherein the first signal is a flag, and the method further comprises: In response to the absence of the APS NAL unit in the bitstream, the value of the flag is set to equal to 1.

15. A method for storing a bitstream associated with video content, the method comprising: The bitstream is generated, and the bitstream includes: A first signal indicating the absence of APS NAL units in the bitstream; and One or more stripe-level flags that indicate the disabling of the chroma ALF process; and The bitstream is stored in a non-transitory computer-readable medium.

16. The method of claim 15, wherein the one or more stripe-level flags comprise: The first band level marker for the chromaticity ALF process corresponding to the chromaticity component Cb, and the second band level marker for the chromaticity ALF process corresponding to the chromaticity component Cr.

17. The method of claim 15, further comprising: Set the value of the one or more strip-level flags to 0 for all of one or more images in the coding layer video sequence associated with the video content.

18. The method of claim 15, further comprising: The luminance ALF process is performed using a predefined set of filters.

19. The method of claim 18, wherein the generated bitstream further includes a third stripe-level flag associated with the luminance ALF process.

20. The method of claim 19, further comprising: Set the value of the third band-level flag to 0 for all of one or more images in the coding layer video sequence associated with the video content.

Images