Image compression method, device and terminal equipment

Abstract

The application is suitable for the field of image processing technology, and provides an image compression method, device and terminal equipment, the method comprises the following steps: in response to an image compression instruction, performing block processing on a current image frame to obtain a plurality of image units; controlling a plurality of logical operation circuits to perform parallel compression processing on the plurality of image units to obtain a plurality of compressed image units, wherein each logical operation circuit is used for compression processing of one or more image units; and performing splicing processing on the plurality of compressed image units to obtain a compressed image frame corresponding to the current image frame. By using the above technical scheme, the parallel compression processing of the image units is performed by using a plurality of parallelly connected logical operation circuits in the DSP core, thereby effectively solving the problem that the real-time performance is limited in the prior art, and greatly improving the image compression efficiency.

Description

Technical Field

[0001] This application belongs to the field of image processing technology, and in particular relates to an image compression method, apparatus and terminal equipment. Background Technology

[0002] In the field of digital image processing, image compression algorithms are a widely used standard technology, and their optimization work has long focused on general-purpose central processing units, graphics processing units, and multi-core digital signal processor (DSP) platforms.

[0003] In existing solutions, researchers have developed a method based on eight DSP cores to implement operations such as parallel discrete cosine transform, and combined it with a lookup table mechanism to complete the core compression process.

[0004] However, such schemes are prone to congestion in allocating image block tasks and data interaction between cores, which limits real-time performance during image compression and reduces the efficiency of image compression. Summary of the Invention

[0005] This application provides an image compression method, apparatus, and terminal device, which can effectively solve the problem of limited real-time performance in the prior art and greatly improve image compression efficiency.

[0006] In a first aspect, embodiments of this application provide an image compression method applied to a terminal device. The DSP core of the DSP processor in the terminal device is configured with multiple parallel-connected logic operation circuits. The method includes: In response to an image compression command, the current image frame is segmented to obtain multiple image units; Multiple logic operation circuits are controlled to perform parallel compression processing on multiple image units to obtain multiple compressed image units, wherein each logic operation circuit is used to compress one or more image units. Multiple compressed image units are stitched together to obtain a compressed image frame corresponding to the current image frame.

[0007] In one possible implementation of the first aspect, multiple logic operation circuits are controlled to perform parallel compression processing on multiple image units to obtain multiple compressed image units, including: Output discrete cosine transform instructions to multiple logic operation circuits, so as to control multiple logic operation circuits based on discrete cosine transform instructions, and perform discrete cosine transform processing on multiple image units in parallel to obtain multiple transformed image units corresponding to multiple image units. Output quantization instructions to multiple logic operation circuits to control multiple logic operation circuits based on quantization instructions, and perform quantization processing on multiple transformed image units in parallel to obtain multiple quantized image units corresponding to multiple image units; Output position arrangement instructions to multiple logic operation circuits, so as to control multiple logic operation circuits based on position arrangement instructions, and perform position arrangement processing on multiple quantized image units in parallel to obtain multiple arranged image units corresponding to multiple image units; The encoding instructions are output to multiple logic operation circuits to control the multiple logic operation circuits based on the encoding instructions, and to perform position encoding processing on multiple arranged image units in parallel to obtain multiple compressed image units corresponding to the multiple image units.

[0008] In one possible implementation of the first aspect, multiple logic circuits are controlled based on discrete cosine transform instructions to perform discrete cosine transform processing on multiple image units in parallel, resulting in multiple transformed image units corresponding to the multiple image units, including: Each logic operation circuit is controlled by a discrete cosine transform instruction. Based on the set parameter vector, each row or column of pixels in the image unit corresponding to each logic operation circuit is processed by discrete cosine transform in turn to obtain the transformed image unit corresponding to each logic operation circuit. The transformed image units corresponding to all logic operation circuits are determined as multiple transformed image units corresponding to multiple image units.

[0009] In one possible implementation of the first aspect, each image unit has 8 rows and 8 columns, and correspondingly, the number of vector elements in the parameter vector is set to 11. Based on a set parameter vector, discrete cosine transform is applied sequentially to each row or column of pixels in the image unit corresponding to each logic operation circuit to obtain the transformed image unit corresponding to each logic operation circuit, including: Obtain the set parameter vector c[0,…,10] and the pixel data pic[0,…,7] of each row of pixels in the image unit corresponding to each logic operation circuit; Multiple addition and subtraction operations are performed on the pixel data pic[0,…,7] to obtain the first intermediate value x01, the second intermediate value x11, the third intermediate value x21, the fourth intermediate value x31, the fifth intermediate value x41, the sixth intermediate value x51, the seventh intermediate value x61, and the eighth intermediate value x71, where x01=pic[0]+pic[7], x11=pic[1]+pic[6], x21=pic[2]+pic[5], x31=pic[3]+pic[4], x41=pic[3]-pic[4], x51=pic[2]-pic[5], x61=pic[1]-pic[6], and x71=pic[0]-pic[7]. Perform the first operation on vector elements c[0], the first intermediate value, the second intermediate value, the third intermediate value, and the fourth intermediate value to obtain the transformed pixel data dct[0]. The second operation is performed on the vector elements c[0], the first intermediate value, the second intermediate value, the third intermediate value and the fourth intermediate value to obtain the transformed pixel data dct[4]; Perform a third operation on vector element c[1], vector element c[2], first intermediate value, second intermediate value, third intermediate value and fourth intermediate value to obtain the transformed pixel data dct[2]; The fourth operation is performed on vector element c[1], vector element c[3], first intermediate value, second intermediate value, third intermediate value and fourth intermediate value to obtain the transformed pixel data dct[6]; The fifth operation is performed on vector element c[1], vector element c[7], the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[5]; The sixth operation is performed on vector elements c[1], c[4], c[6], c[8], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[1]. The seventh operation is performed on vector elements c[1], c[4], c[6], c[9], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[7]. The eighth operation is performed on vector elements c[1], c[4], c[5], c

[10] , the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[3]. The transformed pixel data dct[0,…,7] is determined as the transformed pixel data of each row of pixels in the image unit corresponding to each logic operation circuit; Based on the transformed pixel data corresponding to all rows of pixels, the transformed image unit corresponding to each logic operation circuit is determined.

[0010] In one possible implementation of the first aspect, multiple logic operation circuits are controlled based on quantization instructions to perform quantization processing on multiple transformed image units in parallel, resulting in multiple quantized image units corresponding to the multiple image units, including: Based on the quantization instructions, each logic operation circuit is controlled to determine the target brightness quantization matrix and the target color difference quantization matrix corresponding to the current image frame. The target brightness quantization matrix is ​​used to perform brightness quantization processing on the transformed image unit corresponding to each logic operation circuit, and the target color difference quantization matrix is ​​used to perform color difference quantization processing on the transformed image unit corresponding to each logic operation circuit. Each logic operation circuit is controlled, and the image data of the transformed image unit corresponding to each logic operation circuit is divided bitwise with the target brightness quantization matrix to obtain the first operation result. Each logic operation circuit is controlled to perform a bitwise division operation on the first operation result and the target color difference quantization matrix to obtain the quantized image unit corresponding to each logic operation circuit. The quantized image units corresponding to all logic operation circuits are determined as multiple quantized image units corresponding to multiple image units.

[0011] In one possible implementation of the first aspect, determining the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame includes: Obtain the pixel distribution parameters and historical shaping coefficients of the target historical image frame, where the target historical image frame is the image frame before the current image frame; Calculate the current shaping coefficient of the current image frame based on pixel distribution parameters and historical shaping coefficients; The standard luminance quantization matrix and the standard chrominance quantization matrix are quantized using the current shaping coefficients to obtain the target luminance quantization matrix and the target chrominance quantization matrix.

[0012] In one possible implementation of the first aspect, the target historical image frame includes a first historical image frame and a second historical image frame, the first historical image frame being an image frame preceding the current image frame, the second historical image frame being an image frame preceding the first historical image frame, and the pixel distribution parameters including a first root mean square error and a first signal-to-noise ratio of the first historical image frame, and a second root mean square error and a second signal-to-noise ratio of the second historical image frame. Based on pixel distribution parameters and historical shaping coefficients, the current shaping coefficient of the current image frame is calculated, including: Based on the first root mean square error, the first signal-to-noise ratio, the second root mean square error, and the second signal-to-noise ratio, the historical shaping coefficients are corrected to obtain the current shaping coefficients of the current image frame.

[0013] In one possible implementation of the first aspect, determining the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame includes: Get the current integer coefficients input by the user; The standard luminance quantization matrix and the standard chrominance quantization matrix are shaped using the current shaping coefficients to obtain the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame.

[0014] Secondly, embodiments of this application provide an image compression device configured in a terminal device. The DSP core of the DSP processor in the terminal device is configured with multiple parallel-connected logic operation circuits. The device includes: The slicing module is used to slice the current image frame into multiple image units in response to image compression commands; The parallel compression module is used to control multiple logic operation circuits to perform parallel compression processing on multiple image units to obtain multiple compressed image units. Each logic operation circuit is used to compress one or more image units. The stitching module is used to stitch together multiple compressed image units to obtain a compressed image frame corresponding to the current image frame.

[0015] Thirdly, embodiments of this application provide a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method as described in any of the first aspects.

[0016] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as described in any of the first aspects.

[0017] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute any of the methods described in the first aspect above.

[0018] This application provides an image compression method, apparatus, and terminal device. The method includes: responding to an image compression command, segmenting a current image frame into multiple image units; controlling multiple logic operation circuits to perform parallel compression processing on the multiple image units to obtain multiple compressed image units, wherein each logic operation circuit is used to compress one or more image units; and stitching the multiple compressed image units together to obtain a compressed image frame corresponding to the current image frame. By utilizing the above technical solution and employing multiple parallel-connected logic operation circuits in the DSP core to perform parallel compression processing on image units, the problem of limited real-time performance in the prior art is effectively solved, and image compression efficiency is greatly improved. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of an image compression method provided in an embodiment of this application; Figure 2 This is a schematic flowchart of an image compression method provided in another embodiment of this application; Figure 3 This is a structural block diagram of an image compression device provided in one embodiment of this application; Figure 4 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Detailed Implementation

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0025] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0027] It should be noted that the information collection process (such as image acquisition process) / feature extraction process involved in this application is performed with the user's knowledge and permission. That is, the information collection process / feature extraction process complies with the requirements of laws and regulations and does not constitute an act that harms the public interest.

[0028] Image compression can be categorized into lossless compression and lossy compression based on whether information is lost during the compression process and whether there are discrepancies between the compressed and original images. Lossless compression refers to compression without sacrificing image quality. It optimizes file storage by using algorithms to represent redundant information, allowing for complete file restoration without affecting the file content. Generally, because lossless compression only removes redundant information from image data and can accurately restore the original image, it cannot achieve very high compression ratios. Lossy compression, on the other hand, sacrifices image quality by removing irrelevant information. Therefore, decompression can only approximate the original image; its high compression ratio comes at the cost of image quality.

[0029] Currently, most optimization efforts for image compression algorithms focus on general-purpose CPUs, GPUs, and multi-core DSP platforms. For example, an image compression implementation based on an 8-core DSP chip completes the core image compression process by utilizing parallel Discrete Cosine Transform (DCT) on a multi-core DSP.

[0030] However, most of these solutions are highly compatible with specific hardware models, and changing the hardware platform requires large-scale rewriting of the solutions and programs, resulting in high porting costs. Furthermore, when using multi-core DSPs in parallel, congestion can easily occur in image block task allocation and inter-core data interaction, leading to transmission delays during image processing. In addition, frame drops are common in high frame rate scenarios, indicating room for improvement in real-time performance and energy efficiency. Therefore, researching and implementing a highly optimized image compression method for DSP platforms with a Single Instruction Multiple Data (SIMD) instruction architecture is of great significance for promoting the development of embedded image systems.

[0031] Figure 1 This is a flowchart illustrating an image compression method according to an embodiment of this application. It is intended as an example and not a limitation. This method can be applied to terminal devices. The DSP core in the DSP processor of the terminal device is configured with multiple parallel-connected logic operation circuits, such as... Figure 1 As shown, the method includes: S101. In response to the image compression command, the current image frame is segmented to obtain multiple image units.

[0032] It is understood that the DSP processor in this embodiment, as the core computing unit, has an internal DSP core designed to contain multiple independent logic operation circuits. These logic operation circuits are configured to be connected in parallel, meaning they can execute different computing tasks simultaneously, thereby significantly improving the efficiency of image processing. For example, the DSP core can contain multiple general-purpose arithmetic logic units, which are configured to independently receive and process data to achieve parallel computing. As another implementation, the DSP core can integrate multiple hardware accelerators specifically designed for particular image processing operations, with each accelerator acting as a logic operation circuit capable of processing image data in parallel.

[0033] When a terminal device receives an image compression command triggered externally or internally, it will initiate a segmentation process on the current image frame to be processed, such as dividing a complete image frame into several smaller, independently processable image units. For example, an image frame with a resolution of 1920*1080 pixels can be divided into multiple image units according to a fixed size (e.g., 8*8 pixels or 16*16 pixels).

[0034] S102. Control multiple logic operation circuits to perform parallel compression processing on multiple image units to obtain multiple compressed image units, wherein each logic operation circuit is used to compress one or more image units.

[0035] After the image segmentation process is complete, the generated image units are assigned to multiple parallel-connected logic circuits within the DSP core. Each logic circuit can independently execute a compression algorithm on one or more image units assigned to it. For example, image units can be assigned sequentially to available logic circuits, with each circuit processing one unit before receiving the next. Alternatively, a simple load balancing strategy can be employed, distributing the image units evenly across the logic circuits, with each circuit responsible for compressing all the image units assigned to it.

[0036] For example, a 1280*720 pixel image frame can be divided into 14,400 8*8 image units. After the segmentation process is completed, the 14,400 image units are allocated to multiple parallel-connected logic operation circuits in the DSP core. Assume the DSP core is configured with 8 logic operation circuits. This method controls these 8 logic operation circuits to perform parallel compression processing on the 14,400 image units. Each logic operation circuit can independently receive and process the image units allocated to it. For example, a simple static allocation strategy can be used, distributing the 14,400 image units evenly among the 8 logic operation circuits, with each circuit handling 1,800 image units. After receiving its allocated image units, each logic operation circuit independently executes an image compression algorithm, such as a compression process based on discrete cosine transform and quantization, thereby converting the original image units into compressed image units. Because multiple logic operation circuits work simultaneously, the compression processing of image units is performed in parallel, significantly reducing the overall compression time.

[0037] S103. Perform stitching processing on multiple compressed image units to obtain a compressed image frame corresponding to the current image frame.

[0038] After all image units have been compressed in parallel, the resulting compressed image units need to be reassembled to form a complete compressed image frame. This stitching process ensures that the structure and order of the original image frame are restored. For example, each compressed image unit can be placed in its corresponding position in the final compressed image frame based on its original position information. Alternatively, the stitching process can simply arrange all compressed image units sequentially in a preset order to form the final compressed image frame.

[0039] This embodiment provides an image compression method that utilizes multiple parallel-connected logic operation circuits in the DSP core to perform parallel compression processing on image units, effectively solving the problem of limited real-time performance in the prior art and greatly improving image compression efficiency.

[0040] Figure 2 This is a flowchart illustrating an image compression method according to another embodiment of this application. This embodiment further optimizes the parallel compression processing of multiple image units by controlling multiple logic operation circuits to obtain multiple compressed image units as follows: Outputting discrete cosine transform instructions to multiple logic operation circuits to control the circuits and perform parallel discrete cosine transform processing on multiple image units, resulting in multiple transformed image units corresponding to the multiple image units; outputting quantization instructions to multiple logic operation circuits to control the circuits and perform parallel quantization processing on multiple transformed image units, resulting in multiple quantized image units corresponding to the multiple image units; outputting position arrangement instructions to multiple logic operation circuits to control the circuits and perform parallel position arrangement processing on multiple quantized image units, resulting in multiple arranged image units corresponding to the multiple image units; and outputting encoding instructions to multiple logic operation circuits to control the circuits and perform parallel position encoding processing on multiple arranged image units, resulting in multiple compressed image units corresponding to the multiple image units. Figure 2 As shown, the method includes: S201. In response to the image compression command, the current image frame is segmented to obtain multiple image units.

[0041] S202: Output discrete cosine transform instructions to multiple logic operation circuits, so as to control multiple logic operation circuits based on discrete cosine transform instructions, and perform discrete cosine transform processing on multiple image units in parallel to obtain multiple transformed image units corresponding to multiple image units.

[0042] Unlike existing multi-core parallel processing methods, this embodiment primarily uses a single instruction to drive multiple parallel logic circuits to perform parallel processing operations on multiple image units. This embodiment further refines the compression processing operation into multiple sub-processing operations. By sequentially outputting different instructions, it drives multiple parallel logic circuits to execute different sub-processing operations on multiple image units, thereby obtaining multiple compressed image units.

[0043] Discrete cosine transform (DCT) is a core step in image compression, used to convert image data from the spatial domain to the frequency domain, facilitating subsequent quantization and encoding.

[0044] Parallel processing means that multiple logic circuits simultaneously perform DCT on their respective image units, significantly improving processing speed. For example, a Discrete Cosine Transform (DCT) instruction can be generated for each logic circuit and sent to the corresponding logic circuit via an internal bus or dedicated signal line. Alternatively, the logic circuit may have a pre-built hardware implementation or firmware program for the DCT algorithm. When it receives an external DCT instruction, it activates its internal DCT processing module to perform the operation on the assigned image unit data.

[0045] This embodiment does not limit the specific process of discrete cosine transform (DCT). For example, each logic operation circuit can be controlled based on DCT instructions, and DCT can be applied to each row or column of pixels in the image unit corresponding to each logic operation circuit sequentially based on a set parameter vector to obtain the transformed image unit corresponding to each logic operation circuit. Then, the transformed image units corresponding to all logic operation circuits are determined as multiple transformed image units corresponding to multiple image units. Alternatively, this embodiment can also directly output the transformed image unit corresponding to each image unit by configuring a neural network model.

[0046] It should be noted that, due to the high symmetry of the DCT transform, it can be optimized into matrix operations in practical code applications. In this embodiment, the two input parameter matrices are transposes of each other, and parameter matrix A is a symmetric matrix. Since parameter matrix A can be obtained by the cosine formula, the parameters in parameter matrix A have cosine characteristics. Therefore, this embodiment can obtain an improved fast discrete cosine transform (FDCT) by decomposing matrix operations.

[0047] As a feasible implementation, when each image unit is an 8*8 image block, that is, each image unit has 8 rows and 8 columns, the number of vector elements in the parameter vector is set to 11; the specific discrete cosine transform processing can include: Obtain the set parameter vector c[0,…,10] and the pixel data pic[0,…,7] of each row of pixels in the image unit corresponding to each logic operation circuit; Multiple addition and subtraction operations are performed on the pixel data pic[0,…,7] to obtain the first intermediate value x01, the second intermediate value x11, the third intermediate value x21, the fourth intermediate value x31, the fifth intermediate value x41, the sixth intermediate value x51, the seventh intermediate value x61, and the eighth intermediate value x71, where x01=pic[0]+pic[7], x11=pic[1]+pic[6], x21=pic[2]+pic[5], x31=pic[3]+pic[4], x41=pic[3]-pic[4], x51=pic[2]-pic[5], x61=pic[1]-pic[6], and x71=pic[0]-pic[7]. Perform the first operation on vector elements c[0], the first intermediate value, the second intermediate value, the third intermediate value, and the fourth intermediate value to obtain the transformed pixel data dct[0]. The second operation is performed on the vector elements c[0], the first intermediate value, the second intermediate value, the third intermediate value and the fourth intermediate value to obtain the transformed pixel data dct[4]; Perform a third operation on vector element c[1], vector element c[2], first intermediate value, second intermediate value, third intermediate value and fourth intermediate value to obtain the transformed pixel data dct[2]; The fourth operation is performed on vector element c[1], vector element c[3], first intermediate value, second intermediate value, third intermediate value and fourth intermediate value to obtain the transformed pixel data dct[6]; The fifth operation is performed on vector element c[1], vector element c[7], the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[5]; The sixth operation is performed on vector elements c[1], c[4], c[6], c[8], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[1]. The seventh operation is performed on vector elements c[1], c[4], c[6], c[9], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[7]. The eighth operation is performed on vector elements c[1], c[4], c[5], c

[10] , the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[3]. The transformed pixel data dct[0,…,7] is determined as the transformed pixel data of each row of pixels in the image unit corresponding to each logic operation circuit; Based on the transformed pixel data corresponding to all rows of pixels, the transformed image unit corresponding to each logic operation circuit is determined.

[0048] In a specific implementation, pixel data pic[0,…,7] represents the grayscale or color component values ​​of 8 pixels in a row of the image unit to be processed. By performing specific addition and subtraction operations on the pixel data, complex multiplication operations can be effectively decomposed and transformed into simpler addition and subtraction operations, thereby significantly reducing the complexity of subsequent calculations. For example, operations such as x01=pic[0]+pic[7] combine the pixel values ​​at symmetrical positions, laying the foundation for the subsequent butterfly operation structure. These addition and subtraction operations can be completed in parallel within the logic operation circuit through a dedicated array of adders and subtractors.

[0049] Subsequently, instead of performing complex matrix multiplication directly, the logic operation circuit cleverly decomposes and combines the original pixel data pic[0,…,7] into eight intermediate values ​​x01 to x71 through multiple sets of addition and subtraction operations. These intermediate values ​​are carefully designed to simplify subsequent multiplication operations. Next, the logic operation circuit uses these intermediate values ​​and specific vector elements c[0] to c

[10] in the set parameter vector to calculate the transformed pixel data dct[0] to dct[7] through a series of eight predefined operations (the first operation to the eighth operation).

[0050] Each operation typically involves multiplication and addition / subtraction operations, used to combine preset vector elements (such as c[0]) with previously calculated intermediate values ​​(such as x01, x11, x21, x31, x41). This combination operation can be implemented in the logic operation circuit through multipliers, adders and subtractors. The order and combination of these combination operations are the core of the fast discrete cosine transform algorithm. By reducing the number of multiplications required and optimizing the data flow, the computational efficiency is greatly improved. Furthermore, the specific architecture of the combination operation can be configured according to actual needs. For example, pic[0,…,7] is a row of pixel data in the image unit, dct[0,…,7] is the pixel data after FDCT transformation of each row of pixel data, and the parameter vector c

[11] is set to [0.35355339,0.707106781,0.27059805,0.653281482,0.382683432,0.541196100,1.306562965,0.449988111,0.254897789,1.281457724,0.300672443].

[0051] To facilitate the explanation of the principle, this application uses an image frame size of 512*512 bytes as an example. A width of 512 bytes is exactly the length of one SIMD instruction, and a single operation corresponds to exactly one line of image data. The specific FDCT transformation process can be described as follows: (1) Based on the channel to which the image data belongs, the DCT transform parameter table (i.e. the parameter vector) is moved from the ARM side to the DMA, and all data is loaded into V0.

[0052] (2) Transfer 16 lines of image data from the ARM side to the DMA at once.

[0053] (3) Load 128 uint8 (i.e. 128 bytes) of input pixel values ​​into vector register V1 at once.

[0054] (4) Expand the data in register V0, changing the data from uint8 to 32-bit float, store the data in V2 and V3, and save it in MR1 (i.e. 512 bytes).

[0055] (5) Repeat steps 3 and 4 until there are 8×512 bytes of data in MR1.

[0056] (6) Read 8×512 bytes of data from MR1 into V4, perform FDCT transformation, that is, use the DCT transformation parameter table data V0, and perform a series of multiplication and addition operations based on V0 and V4, while simultaneously performing calculations on 128 pixels. The specific pseudocode for performing a series of multiplication and addition operations based on V0 and V4 is as follows: float x01,x11,x21,x31,x41,x51,x61,x71; float x0,x1,x2,x3; x01 = pic[0] + pic[7]; x11 = pic[1] + pic[6]; x21 = pic[2] + pic[5]; x31 = pic[3] + pic[4]; x41 = pic[3] - pic[4]; x51 = pic[2] - pic[5]; x61 = pic[1] - pic[6]; x71 = pic[0] - pic[7]; x0 = x01 + x31; x1 = x11 + x21; x2 = x11 - x21; x3 = x01 - x31; dct[0]=c[0]*(x0+x1); dct[4]=c[0]*(x0-x1); x2 = c[1]*(x2+x3); dct[2]=c[2]*(x2+x3); dct[6]=c[3]*(x3-x2); x0 = x41 + x51; x1 = x51 + x61; x2 = x61 + x71; x3 = c[4]*(x0-x2); x41=c[5]*x0+x3; x51 = c[1] * x1; x61=c[6]*x2+x3; x1 = x51 + x71; x3 = x71 - x51; dct[5]=c[7]*(x41+x3); dct[1]=c[8]*(x1+x61); dct[7]=c[9]*(x1-x61); dct[3]=c

[10] *(x3-x41).

[0057] By combining the dct[0] to dct[7] components obtained from the above eight operations, a complete one-dimensional discrete cosine transform result of the row of pixels can be formed. These results represent the energy distribution of the row of pixels in the frequency domain. Then, by repeating the above process for all rows in the image unit, the transformed image unit of the image unit can be obtained.

[0058] It should be noted that when performing DCT transformation using matrix operations on each 8*8 image unit, 128 parameters are required, and the entire algorithm requires 4096 multiplication operations and 896 addition operations. However, when using the improved FDCT transformation in this embodiment, only 11 parameters are required for each 8*8 image unit block, and the entire algorithm requires 208 multiplication operations and 464 addition operations. It is evident that the improved FDCT implementation significantly reduces the computational load. Furthermore, through the 16 logic operation circuits configured in the DSP chip, FDCT transformations of 16 image blocks can be performed simultaneously, greatly improving image compression performance. Based on this, the step-by-step, structured computational method of this embodiment enables the originally computationally intensive Discrete Cosine Transform to be efficiently implemented in the hardware logic operation circuits, fully utilizing the advantages of parallel processing to accelerate the entire image compression process.

[0059] S203. Output quantization instructions to multiple logic operation circuits to control multiple logic operation circuits based on quantization instructions, and perform quantization processing on multiple transformed image units in parallel to obtain multiple quantized image units corresponding to multiple image units.

[0060] Quantization can be considered as the process of mapping continuous values ​​of a signal to a finite number of discrete amplitudes, achieving a many-to-one mapping of signal values. In image and video coding, the transform coefficients of a signal after FDCT often have a large dynamic range. Quantizing the transform coefficients can effectively reduce the range of signal values ​​and achieve better compression results.

[0061] In this embodiment, multiple logic operation circuits can be controlled to simultaneously perform quantization operations on their respective transformed image units based on quantization instructions. For example, the quantization instruction may include quantization parameters or an index pointing to a preset quantization table, and the logic operation circuits perform division and rounding operations on the frequency coefficients of the transformed image units according to these parameters or tables. Alternatively, the logic operation circuits may have a built-in programmable quantization module, which can be configured to perform quantization behavior based on received quantization instructions, such as adjusting the quantization step size or selecting different quantization matrices.

[0062] Understandably, quantization matrices typically employ uniform quantization, while this application allows for the use of different quantization step sizes for transform coefficients at different locations. For example, taking advantage of the human eye's insensitivity to high-frequency details in images and videos, a larger quantization step size can be used for high-frequency coefficients, while a smaller quantization step size can be used for low-frequency components. This can improve the subjective quality of images or videos while maintaining a certain compression ratio.

[0063] In a specific implementation, multiple logic operation circuits are controlled based on quantization instructions to perform quantization processing on multiple transformed image units in parallel, resulting in multiple quantized image units corresponding to the multiple image units, including: Based on the quantization instructions, each logic operation circuit is controlled to determine the target brightness quantization matrix and the target color difference quantization matrix corresponding to the current image frame. The target brightness quantization matrix is ​​used to perform brightness quantization processing on the transformed image unit corresponding to each logic operation circuit, and the target color difference quantization matrix is ​​used to perform color difference quantization processing on the transformed image unit corresponding to each logic operation circuit. Each logic operation circuit is controlled, and the image data of the transformed image unit corresponding to each logic operation circuit is divided bitwise with the target brightness quantization matrix to obtain the first operation result. Each logic operation circuit is controlled to perform a bitwise division operation on the first operation result and the target color difference quantization matrix to obtain the quantized image unit corresponding to each logic operation circuit. The quantized image units corresponding to all logic operation circuits are determined as multiple quantized image units corresponding to multiple image units.

[0064] The quantization matrix is ​​a two-dimensional numerical table used in the quantization step of image compression. Its core function is to weight the frequency coefficients after discrete cosine transform based on the differences in human eye sensitivity to different frequency components, thereby effectively removing visual redundancy information. Specifically, the target luminance quantization matrix is ​​used to process the luminance (y) component of the image, while the target chrominance quantization matrix is ​​used to process the chrominance (cb, cr) components. This differentiated processing is based on the physiological characteristic that the human eye is more sensitive to changes in luminance than to changes in chrominance. Therefore, a relatively coarser quantization of the chrominance component can be performed to achieve a higher compression ratio while maintaining acceptable visual quality. These quantization matrices can be pre-set as industry standard matrices (such as the luminance / chrominance quantization table defined in the JPEG standard), or they can be dynamically generated and adjusted based on the specific content of the current image frame, user-defined compression quality requirements, or by analyzing the statistical characteristics of the image (such as texture complexity and noise level).

[0065] The specific quantization compression process can include: First, based on the channel to which the image data belongs, the corresponding quantization parameter table (i.e., the target luminance quantization matrix or the target chrominance quantization matrix) is transferred from the ARM side to the DMA, and all data is loaded into V0. Then, 16 transformed image units are transferred from the ARM side to the DMA at once; 128 float (i.e., 512 bytes) of input pixel values ​​are loaded into the vector register V1 at once. Next, a bitwise division operation can be performed between V0 and V1 to achieve simultaneous compression of 128 pixels; steps 3 and 4 are repeated until all image units in the DMA are processed, and steps 2-5 are continued. After all logic operation circuits have completed quantization, their respective quantized image units can be combined to form complete quantized image data, providing input for subsequent encoding steps. Based on this, through this step-by-step, component (luminance and chrominance) quantization strategy, and by utilizing the parallel processing capabilities of multiple logic operation circuits, image data can be quantized efficiently and specifically, ensuring that while achieving a high compression ratio, the visual quality of the image is preserved to the maximum extent.

[0066] In some embodiments, determining the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame includes: Obtain the pixel distribution parameters and historical shaping coefficients of the target historical image frame, where the target historical image frame is the image frame before the current image frame; Calculate the current shaping coefficient of the current image frame based on pixel distribution parameters and historical shaping coefficients; The standard luminance quantization matrix and the standard chrominance quantization matrix are quantized using the current shaping coefficients to obtain the target luminance quantization matrix and the target chrominance quantization matrix.

[0067] In this context, the target historical image frame refers to image frames that have been processed before the current image frame. This could be the frame immediately preceding the current frame, or several earlier frames. Pixel distribution parameters can be parameters describing the statistical characteristics of image pixels, reflecting the degree of image distortion or quality. For example, pixel distribution parameters may include the root mean square error (RMSE), which quantifies the degree of image distortion; or the signal-to-noise ratio (SNR), which reflects the image's quality level. Furthermore, pixel distribution parameters can also be other statistical quantities such as image variance, average brightness, and contrast.

[0068] Historical shaping coefficients refer to the coefficients used in the quantization matrix shaping process of previous image frames. For example, historical shaping coefficients can be shaping coefficients calculated from the previous image frame, shaping coefficients obtained by averaging multiple historical frames of data, or coefficients adjusted based on historical image quality feedback.

[0069] The standard luminance quantization matrix and standard chrominance quantization matrix can be predefined, universal quantization matrices, such as the 8x8 luminance quantization matrix recommended in the JPEG standard. and color difference quantization matrix Alternatively, a pre-trained or optimized base quantization matrix can be used, depending on the specific application scenario. For example... , .

[0070] Specifically, when calculating the current shaping coefficient of the current image frame based on pixel distribution parameters and historical shaping coefficients, the aim is to predict or deduce the shaping coefficient of the current frame based on historical data and current image characteristics. Specifically, a pre-defined lookup table can be used to perform a lookup operation based on the obtained pixel distribution parameters and historical shaping coefficients to obtain the corresponding current shaping coefficient. Alternatively, a machine learning model can be used, taking the pixel distribution parameters and historical shaping coefficients as input, and outputting the current shaping coefficient through a trained model. Furthermore, algorithms such as weighted averaging and linear interpolation can be used to calculate the current shaping coefficient by combining the changing trends of historical shaping coefficients and pixel distribution parameters.

[0071] Next, the element values ​​of the standard quantization matrix can be adjusted according to the current shaping coefficients to achieve shaping of the standard quantization matrix. For example, each element of the standard quantization matrix can be multiplied with the current shaping coefficients, or other scaling operations can be performed. Alternatively, a non-linear transformation can be applied to the standard quantization matrix based on the current shaping coefficients, such as through table lookup or function mapping. Or, the standard quantization matrix can be adaptively adjusted based on the current shaping coefficients, for example, by adjusting high-frequency or low-frequency components to different degrees. Building upon this, by introducing the analysis of historical image frames and comprehensively considering the changing trends of image content and historical compression experience, the quantization matrix can more accurately reflect the characteristics of the current image frame. This allows for more refined and optimized quantization processing based on the actual content of the current image frame, thus ensuring image quality while enabling the entire image compression method to better adapt to the characteristics of different image content, avoiding the poor compression effect that may result from a fixed quantization matrix.

[0072] In some embodiments, the target historical image frame includes a first historical image frame and a second historical image frame. The first historical image frame is an image frame preceding the current image frame, and the second historical image frame is an image frame preceding the first historical image frame. The pixel distribution parameters include a first root mean square error and a first signal-to-noise ratio (SNR) of the first historical image frame, and a second root mean square error and a second SNR of the second historical image frame. Based on the pixel distribution parameters and historical shaping coefficients, the current shaping coefficient of the current image frame is calculated, including: correcting the historical shaping coefficients according to the first root mean square error, the first SNR, the second root mean square error, and the second SNR to obtain the current shaping coefficient of the current image frame.

[0073] In this scenario, assuming the current image frame is the Nth frame, the first historical image frame can be N-1 frames, and the second historical image frame can be N-2 frames. Alternatively, in some scenarios, the first and second historical image frames can be selected at a set interval, such as the first historical image frame being Nk frames and the second historical image frame being N-2k frames.

[0074] The root mean square error (RMSE) reflects the degree of image distortion, while the signal-to-noise ratio (SNR) measures the relative strength of the image signal and noise. By acquiring these parameters from the first and second historical image frames, the trend of image quality changes over time can be captured. The first RMSE and the first SNR can be calculated based on the raw data of the first historical image frame and some reference data (e.g., data after preliminary compression or processing). For example, if the pixel data of the first historical image frame is... The pixel data after image compression of the first historical image frame is Let M be the number of pixels in the first historical image frame, then the first root mean square error... First signal-to-noise ratio in, This represents the average power of the signal.

[0075] In specific implementations, historical shaping coefficients can be adjusted based on the quality metrics of historical image frames to better adapt them to the characteristics of the current image frame. One correction method involves designing an adaptive algorithm that uses historical shaping coefficients as a benchmark and incorporates a first root mean square error (RMSE), a first signal-to-noise ratio (SNR), a second RMSE, and a second SNR as inputs. The algorithm then outputs the corrected current shaping coefficients through weighted averaging, trend prediction, or machine learning models. Another correction method involves pre-setting a lookup table or a set of rules. Based on the changing trends of RMSE and SNR in historical frames, new shaping coefficients are selected from the lookup table or calculated according to the rules. For example, if both RMSE and SNR are decreasing, the shaping coefficients can be increased to improve the compression ratio.

[0076] For example, in this embodiment, the interval can be 60 frames, first based on the first root mean square error. First signal-to-noise ratio Second root mean square error Second signal-to-noise ratio The process involves loading the previously obtained historical shaping coefficients Qvalue_0, calculating the current shaping coefficients, and then calculating the quantization matrix used for the current image frame based on the current shaping coefficients. The specific calculation process may include: calculating Qvalue = Qvalue_0 * ( If Qvalue < 50, then continue to set the current integer coefficient Qvalue = 5000 / Qvalue; otherwise, set the current integer coefficient Qvalue = 200 - Qvalue * 2. Next, perform integer processing on each element Qy[i][j] in the standard luminance quantization matrix to obtain Qnew[i][j] = Qy[i][j] * Qvalue + 50) * 0.01. The integer processing of the standard chrominance quantization matrix is ​​similar to that of the standard luminance quantization matrix, and will not be elaborated further here. Based on this, when determining the target luminance quantization matrix and target chrominance quantization matrix corresponding to the current image frame, this application no longer relies solely on the pixel distribution parameters and historical shaping coefficients of a single historical image frame. Instead, it introduces richer time-series information. By acquiring historical quality indicators from multiple historical image frames, the system can gain a more comprehensive understanding of the dynamic trends of the image sequence and perform correction processing on the historical shaping coefficients. This results in more accurate current shaping coefficients for the current image frame, making the obtained target luminance quantization matrix and target chrominance quantization matrix more adaptive. Consequently, in subsequent parallel quantization processing, it can more effectively balance the compression ratio and image quality, avoiding over-compression or quality loss due to inaccurate quantization parameters.

[0077] In some embodiments, determining the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame includes: Get the current integer coefficients input by the user; The standard luminance quantization matrix and the standard chrominance quantization matrix are shaped using the current shaping coefficients to obtain the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame.

[0078] In specific implementations, the preset standard luminance quantization matrix and standard chrominance quantization matrix can be adjusted or modified according to the user's wishes to adapt to different compression requirements. One implementation method is to use the current shaping coefficient as a scaling factor and perform a series of operations with each element in the standard quantization matrix to obtain a new quantization matrix. Another implementation method is to perform a nonlinear transformation on the standard quantization matrix based on the current shaping coefficient through methods such as table lookup or nonlinear function mapping to achieve more refined or specific curve quality control.

[0079] For example, the user-inputted current integer coefficient Qvalue ranges from [1, 100]. If Qvalue < 50, the current integer coefficient Qvalue is set to 5000 / Qvalue; otherwise, Qvalue is set to 200 - Qvalue * 2. Then, each element Qy[i][j] in the standard luminance quantization matrix is ​​shaped to obtain Qnew[i][j] = Qy[i][j] * Qvalue + 50) * 0.01. The shaping of the standard chrominance quantization matrix is ​​similar to that of the standard luminance quantization matrix and will not be elaborated further here. Based on this, by introducing the user-inputted current integer coefficient, the user can intuitively adjust the compression quality, solving the problem of lack of direct control over compression quality or excessive algorithm complexity in certain scenarios. This ensures that while maintaining efficient compression, the compression ratio and image quality can be flexibly balanced according to actual application needs, providing a direct and flexible control mechanism for the quantization stage in the image compression process.

[0080] S204. Output position arrangement instructions to multiple logic operation circuits to control multiple logic operation circuits based on the position arrangement instructions, and perform position arrangement processing on multiple quantized image units in parallel to obtain multiple arranged image units corresponding to multiple image units.

[0081] Understandably, by observing the quantized image units, it can be found that there are a large number of 0s in the lower right corner. Through the position arrangement processing in this step, the 0s can be arranged in a continuous order.

[0082] In this step, multiple logic circuits can be controlled simultaneously to perform arrangement operations on their respective quantized image units using position arrangement instructions. For example, the position arrangement instructions can specify a specific scan path or arrangement algorithm, and the logic circuits can then rearrange the quantized image units into a one-dimensional data stream according to the specified order. Alternatively, the logic circuits can include a data rearrangement unit that, upon receiving the position arrangement instructions, rearranges the input data according to a preset arrangement pattern.

[0083] For example, this embodiment can perform position arrangement processing based on a mapping table using a zigzag scanning method. Considering that in actual hardware implementation, the output pixel positions of the zigzag scan cannot be clearly defined, which is not conducive to simplifying it to a table lookup operation, this embodiment first performs an inverse operation on the mapping table Z to obtain... Then, during the zigzag scanning process, the table can be directly used as a reference. Locate the data following the original FDCT and update the image data.

[0084] in, , .

[0085] The specific parallel position arrangement process may include: first, according to the channel to which the image data belongs, mapping the table... The data is transferred from the ARM side to the DMA and loaded into V0. Then, 16 quantized image units are transferred from the ARM side to the DMA at once. 128 float (512 bytes) of input pixel values ​​are loaded into vector register V1. Subsequently, based on V1, the data in V0 is mapped to obtain V2, with the 128 pixels undergoing a lookup operation simultaneously. Steps 3 and 4 can then be repeated until all image data in the DMA is processed, and steps 2-5 can continue.

[0086] S205. Output encoding instructions to multiple logic operation circuits to control multiple logic operation circuits based on the encoding instructions, and perform position encoding processing on multiple arranged image units in parallel to obtain multiple compressed image units corresponding to multiple image units.

[0087] Positional encoding (usually referring to entropy encoding, such as Huffman coding or arithmetic coding) is the final step in the compression process. By performing lossless encoding on the arranged data sequence, data redundancy can be further removed. Parallel positional encoding can refer to multiple logic circuits simultaneously performing encoding operations on their respective arranged image units. For example, encoding instructions can specify the encoding type (e.g., Huffman coding, arithmetic coding) or provide an encoding table, allowing the encoder within the logic circuit to perform variable-length encoding on the arranged data according to the instructions. Alternatively, the logic circuit can integrate a configurable entropy encoder, thereby selecting or loading different encoding tables based on received encoding instructions and efficiently encoding the input data.

[0088] The specific parallel compression encoding process may include: first, transferring 16 arranged image units from the ARM side to the DMA at once; loading 64×16 float input pixel values ​​into the vector register V0 at once; performing lossless compression on the encoding of each 64 pixels, omitting redundant information in continuous storage (for example, the original data is 1111 1112 3333, which becomes 12 21 34 after run-length encoding), and performing parallel processing on the 16 8×8 image units; then repeating steps 2 and 3 until all image data in the DMA has been processed, and then continuing with steps 1-4 to complete the position encoding processing of all arranged image units.

[0089] S206. Perform stitching processing on multiple compressed image units to obtain a compressed image frame corresponding to the current image frame.

[0090] This embodiment provides an image compression method that decomposes the image compression process into four core sub-steps: discrete cosine transform, quantization, position arrangement, and encoding. The main control unit sequentially outputs specific instructions for these sub-steps to multiple logic operation circuits, enabling each logic operation circuit to collaboratively complete each stage of image compression. This ensures smooth data flow and maximizes processing efficiency, thereby effectively solving the problems of low efficiency and difficulty in guaranteeing quality in traditional parallel compression.

[0091] As can be seen from the above description, the image compression method of this embodiment introduces a single instruction multiple data stream instruction set architecture into the digital signal processor, divides the image frame into several image units, and uses each image unit as a basis, so that the DSP can complete the parallel processing of multiple image units in a single instruction cycle. It has the advantages of low power consumption, high real-time performance and excellent computing density, and provides new possibilities for the efficient implementation of computationally intensive algorithms.

[0092] Experiments have shown that, compared with conventional algorithm implementations, this embodiment successfully deployed the image compression algorithm in a DSP environment, resulting in a significant improvement in compression efficiency.

[0093] Corresponding to the image compression method in the above embodiments, Figure 3 This is a structural block diagram of an image compression device provided in one embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0094] Reference Figure 3 The device includes: The slicing module 301 is used to slice the current image frame into multiple image units in response to an image compression command. The parallel compression module 302 is used to control multiple logic operation circuits to perform parallel compression processing on multiple image units to obtain multiple compressed image units, wherein each logic operation circuit is used to compress one or more image units. The stitching module 303 is used to stitch together multiple compressed image units to obtain a compressed image frame corresponding to the current image frame.

[0095] This embodiment provides an image compression device that, in response to an image compression command, segments the current image frame into multiple image units using a segmentation module. A parallel compression module controls multiple logic operation circuits to perform parallel compression processing on these image units, resulting in multiple compressed image units. Each logic operation circuit is used to compress one or more image units. A stitching module stitches the compressed image units together to obtain a compressed image frame corresponding to the current image frame. This device, by utilizing multiple parallel-connected logic operation circuits in a DSP core to perform parallel compression processing on image units, effectively solves the problem of limited real-time performance in existing technologies and significantly improves image compression efficiency.

[0096] Optionally, the parallel compression module includes: The first output unit is used to output discrete cosine transform instructions to multiple logic operation circuits, so as to control multiple logic operation circuits based on the discrete cosine transform instructions, and perform discrete cosine transform processing on multiple image units in parallel to obtain multiple transformed image units corresponding to multiple image units. The second output unit is used to output quantization instructions to multiple logic operation circuits, so as to control multiple logic operation circuits based on quantization instructions, and perform quantization processing on multiple transformed image units in parallel to obtain multiple quantized image units corresponding to multiple image units. The third output unit is used to output position arrangement instructions to multiple logic operation circuits, so as to control multiple logic operation circuits based on the position arrangement instructions, and perform position arrangement processing on multiple quantized image units in parallel to obtain multiple arranged image units corresponding to multiple image units. The fourth output unit is used to output encoding instructions to multiple logic operation circuits, so as to control multiple logic operation circuits based on the encoding instructions, and perform position encoding processing on multiple arranged image units in parallel to obtain multiple compressed image units corresponding to multiple image units.

[0097] Optionally, the first output unit includes: The transformation subunit is used to control each logic operation circuit based on the discrete cosine transform instruction. Based on the set parameter vector, the discrete cosine transform is performed on each row or column of pixels in the image unit corresponding to each logic operation circuit to obtain the transformed image unit corresponding to each logic operation circuit. The sub-unit is determined to identify multiple transformed image units corresponding to multiple image units for all logic operation circuits.

[0098] Optionally, each image unit has 8 rows and 8 columns, and correspondingly, the number of vector elements in the parameter vector is set to 11. The transformation subunit is specifically used for: Obtain the set parameter vector c[0,…,10] and the pixel data pic[0,…,7] of each row of pixels in the image unit corresponding to each logic operation circuit; Multiple addition and subtraction operations are performed on the pixel data pic[0,…,7] to obtain the first intermediate value x01, the second intermediate value x11, the third intermediate value x21, the fourth intermediate value x31, the fifth intermediate value x41, the sixth intermediate value x51, the seventh intermediate value x61, and the eighth intermediate value x71, where x01=pic[0]+pic[7], x11=pic[1]+pic[6], x21=pic[2]+pic[5], x31=pic[3]+pic[4], x41=pic[3]-pic[4], x51=pic[2]-pic[5], x61=pic[1]-pic[6], and x71=pic[0]-pic[7]. Perform the first operation on vector elements c[0], the first intermediate value, the second intermediate value, the third intermediate value, and the fourth intermediate value to obtain the transformed pixel data dct[0]. The second operation is performed on the vector elements c[0], the first intermediate value, the second intermediate value, the third intermediate value and the fourth intermediate value to obtain the transformed pixel data dct[4]; Perform a third operation on vector element c[1], vector element c[2], first intermediate value, second intermediate value, third intermediate value and fourth intermediate value to obtain the transformed pixel data dct[2]; The fourth operation is performed on vector element c[1], vector element c[3], first intermediate value, second intermediate value, third intermediate value and fourth intermediate value to obtain the transformed pixel data dct[6]; The fifth operation is performed on vector element c[1], vector element c[7], the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[5]; The sixth operation is performed on vector elements c[1], c[4], c[6], c[8], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[1]. The seventh operation is performed on vector elements c[1], c[4], c[6], c[9], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[7]. The eighth operation is performed on vector elements c[1], c[4], c[5], c

[10] , the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[3]. The transformed pixel data dct[0,…,7] is determined as the transformed pixel data of each row of pixels in the image unit corresponding to each logic operation circuit; Based on the transformed pixel data corresponding to all rows of pixels, the transformed image unit corresponding to each logic operation circuit is determined.

[0099] Optionally, the second output unit includes: The first determining unit is used to control each logic operation circuit based on the quantization instruction to determine the target brightness quantization matrix and the target color difference quantization matrix corresponding to the current image frame. The target brightness quantization matrix is ​​used to perform brightness quantization processing on the transformed image unit corresponding to each logic operation circuit, and the target color difference quantization matrix is ​​used to perform color difference quantization processing on the transformed image unit corresponding to each logic operation circuit. The first arithmetic unit is used to control each logic operation circuit and perform a bitwise division operation between the image data of the transformed image unit corresponding to each logic operation circuit and the target brightness quantization matrix to obtain the first operation result. The second arithmetic unit is used to control each logic operation circuit, and to perform a bitwise division operation on the first operation result and the target color difference quantization matrix to obtain the quantized image unit corresponding to each logic operation circuit. The second determining unit is used to determine the quantized image units corresponding to all logic operation circuits as multiple quantized image units corresponding to multiple image units.

[0100] Optionally, the first determining unit includes: The acquisition sub-unit is used to acquire the pixel distribution parameters and historical shaping coefficients of the target historical image frame, where the target historical image frame is the image frame before the current image frame; The computational subunit is used to calculate the current shaping coefficient of the current image frame based on pixel distribution parameters and historical shaping coefficients; The shaping sub-unit is used to shape the standard luminance quantization matrix and the standard chrominance quantization matrix using the current shaping coefficients, respectively, to obtain the target luminance quantization matrix and the target chrominance quantization matrix.

[0101] Optionally, the target historical image frame includes a first historical image frame and a second historical image frame. The first historical image frame is an image frame before the current image frame, and the second historical image frame is an image frame before the first historical image frame. The pixel distribution parameters include the first root mean square error and the first signal-to-noise ratio of the first historical image frame, and the second root mean square error and the second signal-to-noise ratio of the second historical image frame. The computational subunit is specifically used for: Based on the first root mean square error, the first signal-to-noise ratio, the second root mean square error, and the second signal-to-noise ratio, the historical shaping coefficients are corrected to obtain the current shaping coefficients of the current image frame.

[0102] Optionally, the first determining unit is specifically used for: Get the current integer coefficients input by the user; The standard luminance quantization matrix and the standard chrominance quantization matrix are shaped using the current shaping coefficients to obtain the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame.

[0103] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0104] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0105] Figure 4 This is a schematic diagram of the structure of a terminal device provided in one embodiment of this application, as shown below. Figure 4 As shown, the terminal device 500 of this embodiment includes: at least one processor 502 ( Figure 4 (Only one is shown in the image) A processor, a memory 501, and a computer program 503 stored in the memory 501 and executable on at least one processor 502, wherein the processor 502 executes the computer program 503 to implement the steps in any of the above-described image compression method embodiments.

[0106] Terminal device 500 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. This terminal device may include, but is not limited to, a processor 502 and a memory 501. Those skilled in the art will understand that... Figure 4 This is merely an example of terminal device 500 and does not constitute a limitation on terminal device 500. It may include more or fewer components than shown in the figure, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0107] The processor 502 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0108] In some embodiments, memory 501 may be an internal storage unit of terminal device 500, such as a hard disk or memory of terminal device 500. In other embodiments, memory 501 may be an external storage device of terminal device 500, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on terminal device 500. Furthermore, memory 501 may include both internal and external storage units of terminal device 500. Memory 501 is used to store operating system, applications, boot loader, data, and other programs, such as program code for computer programs. Memory 501 can also be used to temporarily store data that has been output or will be output.

[0109] This application also provides a computer-readable storage medium storing a computer program, which, when executed by processor 502, can implement the steps in the above-described method embodiments.

[0110] This application provides a computer program product that, when run on a terminal device, enables the terminal device to implement the steps described in the various method embodiments.

[0111] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by the processor 502, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable storage medium can include at least: any entity or device capable of carrying computer program code to a device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0112] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0113] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] In the embodiments provided in this application, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0115] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An image compression method, characterized in that, Applied to a terminal device, wherein the DSP core of the DSP processor of the terminal device is configured with multiple parallel-connected logic operation circuits, the method includes: In response to an image compression command, the current image frame is segmented to obtain multiple image units; Multiple logic operation circuits are controlled to perform parallel compression processing on multiple image units to obtain multiple compressed image units, wherein each logic operation circuit is used to compress one or more image units; Multiple compressed image units are stitched together to obtain a compressed image frame corresponding to the current image frame.

2. The image compression method as described in claim 1, characterized in that, The control of multiple logic operation circuits to perform parallel compression processing on multiple image units to obtain multiple compressed image units includes: Output discrete cosine transform instructions to multiple logic operation circuits, so as to control multiple logic operation circuits based on the discrete cosine transform instructions, and perform discrete cosine transform processing on multiple image units in parallel to obtain multiple transformed image units corresponding to multiple image units; A quantization instruction is output to multiple logic operation circuits to control the multiple logic operation circuits based on the quantization instruction, and to perform quantization processing on multiple transformed image units in parallel to obtain multiple quantized image units corresponding to the multiple image units. Output position arrangement instructions to multiple logic operation circuits to control multiple logic operation circuits based on the position arrangement instructions, and perform position arrangement processing on multiple quantized image units in parallel to obtain multiple arranged image units corresponding to multiple image units; The encoding instructions are output to multiple logic operation circuits to control the multiple logic operation circuits based on the encoding instructions, and to perform position encoding processing on the multiple arranged image units in parallel to obtain multiple compressed image units corresponding to the multiple image units.

3. The image compression method as described in claim 2, characterized in that, The method of controlling multiple logic circuits based on the discrete cosine transform instruction to perform discrete cosine transform processing on multiple image units in parallel, thereby obtaining multiple transformed image units corresponding to the multiple image units, includes: Based on the discrete cosine transform instruction, each logic operation circuit is controlled, and based on the set parameter vector, each row of pixels or each column of pixels in the image unit corresponding to each logic operation circuit is sequentially subjected to discrete cosine transform processing to obtain the transformed image unit corresponding to each logic operation circuit. The transformed image units corresponding to all the logic operation circuits are determined as multiple transformed image units corresponding to multiple image units.

4. The image compression method as described in claim 3, characterized in that, Each image unit has 8 rows and 8 columns, and correspondingly, the set parameter vector has 11 vector elements. The step of performing discrete cosine transform on each row or column of pixels in the image unit corresponding to each logic operation circuit based on a set parameter vector to obtain the transformed image unit corresponding to each logic operation circuit includes: Obtain the set parameter vector c[0,…,10] and the pixel data pic[0,…,7] of each row of pixels in the image unit corresponding to each logic operation circuit; Multiple addition and subtraction operations are performed on the pixel data pic[0,…,7] to obtain the first intermediate value x01, the second intermediate value x11, the third intermediate value x21, the fourth intermediate value x31, the fifth intermediate value x41, the sixth intermediate value x51, the seventh intermediate value x61, and the eighth intermediate value x71, where x01=pic[0]+pic[7], x11=pic[1]+pic[6], x21=pic[2]+pic[5], x31=pic[3]+pic[4], x41=pic[3]-pic[4], x51=pic[2]-pic[5], x61=pic[1]-pic[6], and x71=pic[0]-pic[7]. Perform a first operation on vector element c[0], the first intermediate value, the second intermediate value, the third intermediate value and the fourth intermediate value to obtain the transformed pixel data dct[0]. A second operation is performed on vector element c[0], the first intermediate value, the second intermediate value, the third intermediate value and the fourth intermediate value to obtain the transformed pixel data dct[4]; A third operation is performed on vector element c[1], vector element c[2], the first intermediate value, the second intermediate value, the third intermediate value and the fourth intermediate value to obtain the transformed pixel data dct[2]. A fourth operation is performed on vector element c[1], vector element c[3], the first intermediate value, the second intermediate value, the third intermediate value and the fourth intermediate value to obtain the transformed pixel data dct[6]; The fifth operation is performed on vector element c[1], vector element c[7], the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[5]; A sixth operation is performed on vector elements c[1], c[4], c[6], c[8], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[1]. A seventh operation is performed on vector elements c[1], c[4], c[6], c[9], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[7]. The eighth operation is performed on vector elements c[1], c[4], c[5], c[10], the fifth intermediate value, the sixth intermediate value, the seventh intermediate value and the eighth intermediate value to obtain the transformed pixel data dct[3]. The transformed pixel data dct[0,…,7] is determined as the transformed pixel data of each row of pixels in the image unit corresponding to each logic operation circuit; Based on the transformed pixel data corresponding to all row pixels, the transformed image unit corresponding to each of the logic operation circuits is determined.

5. The image compression method as described in claim 2, characterized in that, The method of controlling multiple logic operation circuits based on the quantization instruction to perform quantization processing on multiple transformed image units in parallel, thereby obtaining multiple quantized image units corresponding to the multiple image units, includes: Based on the quantization instruction, each of the logic operation circuits is controlled to determine the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame. The target luminance quantization matrix is ​​used to perform luminance quantization processing on the transformed image unit corresponding to each of the logic operation circuits, and the target chrominance quantization matrix is ​​used to perform chrominance quantization processing on the transformed image unit corresponding to each of the logic operation circuits. Each of the logic operation circuits is controlled to perform a bitwise division operation between the image data of the transformed image unit corresponding to each logic operation circuit and the target brightness quantization matrix to obtain a first operation result; Each logic operation circuit is controlled to perform a bitwise division operation on the first operation result and the target color difference quantization matrix to obtain the quantized image unit corresponding to each logic operation circuit. The quantized image units corresponding to all the logic operation circuits are determined as multiple quantized image units corresponding to multiple image units.

6. The image compression method as described in claim 5, characterized in that, Determining the target luminance quantization matrix and target chrominance quantization matrix corresponding to the current image frame includes: Obtain the pixel distribution parameters and historical shaping coefficients of the target historical image frame, wherein the target historical image frame is the image frame preceding the current image frame; Based on the pixel distribution parameters and the historical shaping coefficients, calculate the current shaping coefficient of the current image frame; The standard luminance quantization matrix and the standard chrominance quantization matrix are shaped using the current shaping coefficients to obtain the target luminance quantization matrix and the target chrominance quantization matrix.

7. The image compression method as described in claim 6, characterized in that, The target historical image frame includes a first historical image frame and a second historical image frame. The first historical image frame is an image frame before the current image frame, and the second historical image frame is an image frame before the first historical image frame. The pixel distribution parameters include the first root mean square error and the first signal-to-noise ratio of the first historical image frame, and the second root mean square error and the second signal-to-noise ratio of the second historical image frame. The step of calculating the current shaping coefficient of the current image frame based on the pixel distribution parameters and the historical shaping coefficients includes: The historical shaping coefficients are corrected based on the first root mean square error, the first signal-to-noise ratio, the second root mean square error, and the second signal-to-noise ratio to obtain the current shaping coefficients of the current image frame.

8. The image compression method as described in claim 5, characterized in that, Determining the target luminance quantization matrix and target chrominance quantization matrix corresponding to the current image frame includes: Get the current integer coefficients input by the user; The standard luminance quantization matrix and the standard chrominance quantization matrix are shaped using the current shaping coefficients to obtain the target luminance quantization matrix and the target chrominance quantization matrix corresponding to the current image frame.

9. An image compression device, characterized in that, Configured in a terminal device, wherein the DSP core of the DSP processor of the terminal device is configured with multiple parallel-connected logic operation circuits, the device includes: The slicing module is used to slice the current image frame into multiple image units in response to image compression commands; A parallel compression module is used to control multiple logic operation circuits to perform parallel compression processing on multiple image units to obtain multiple compressed image units, wherein each logic operation circuit is used to compress one or more of the image units; The stitching module is used to stitch together multiple compressed image units to obtain a compressed image frame corresponding to the current image frame.

10. A terminal device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it causes the terminal device to implement the method as described in any one of claims 1-8.

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