Method, device and medium for three-dimensional model compression and decoding based on GPU acceleration

Abstract

The application discloses a kind of based on GPU acceleration three-dimensional model compression and decoding method, equipment and medium, the method includes: based on the topological structure and geometric distribution of three-dimensional model, three-dimensional model is divided into several independent sub-model blocks;Based on GPU parallel computing architecture, the topological information, geometric information and texture information of each sub-model block are compressed in coordination, and are packaged into compressed package;Based on UDP protocol, the compressed package of each sub-model block is transmitted in parallel, and dynamic bandwidth allocation is carried out according to the transmission priority of sub-model block;While receiving the compressed package of each sub-model block, the receiving end starts GPU parallel decoding and real-time rendering based on dynamic voltage frequency adjustment technology, and optimizes the working frequency of GPU.The application realizes three-dimensional model full-process GPU acceleration, significantly reduces loading delay, and considers compression ratio and model fidelity.

Description

Technical Field

[0001] This invention relates to the field of 3D model technology, and more specifically, to a GPU-accelerated 3D model compression and decoding method, device, and medium. Background Technology

[0002] With the rapid development of 3D technology, the application of large models (millions of vertices or more) is becoming increasingly widespread. These models contain massive amounts of geometric, topological, and textural information, resulting in enormous data volumes and posing significant challenges to storage, transmission, and real-time rendering. In practical applications, the loading latency of large models directly impacts user experience, especially in scenarios with extremely high real-time requirements such as VR / AR and cloud rendering. Excessive loading latency can lead to issues like screen stuttering and dizziness, severely hindering application deployment.

[0003] Currently, 3D model compression technology is mainly divided into GPU-based compression algorithms and GPU-assisted compression algorithms. GPU-based compression algorithms (such as those based on mesh generation, vector quantization, and texture compression) are limited by the serial execution characteristics of traditional GPU compression schemes, resulting in low compression efficiency and difficulty in meeting the fast compression requirements of large models. Most existing GPU-based compression technologies are only used for parallel compression of geometric information, failing to achieve full-process GPU acceleration for compression, decoding, and rendering, and lacking a block compression and transmission mechanism designed for large models, thus failing to solve the problem of excessively high loading latency for large models.

[0004] Meanwhile, existing decoding and rendering processes mostly follow a serial mode of "complete decoding first, then overall rendering," meaning that rendering cannot begin until the entire model is decoded. This prevents the decoding and rendering processes from being parallelized, further exacerbating loading latency. Furthermore, existing technologies suffer from poor coordination between compression algorithms and decoding / rendering, lacking an effective synchronization scheduling mechanism. This makes it difficult to achieve seamless integration between decoding and rendering, and the compression process does not fully consider the topological correlation and geometric redundancy characteristics of large models, resulting in a trade-off between compression ratio and model fidelity.

[0005] Therefore, designing a GPU-accelerated end-to-end solution to achieve efficient compression and fast transmission of large models, as well as parallel execution of decoding and rendering, significantly reducing loading latency while ensuring model fidelity, has become a pressing technical problem to be solved. Summary of the Invention

[0006] To overcome the technical problems of low compression efficiency, high loading latency, inability to perform decoding and rendering in parallel, and difficulty in balancing compression ratio and fidelity in existing technologies for large 3D models, this invention provides a GPU-accelerated 3D model compression and decoding method, device, and medium, which realizes efficient compression and transmission of 3D models, simultaneous decoding and rendering, significantly reduces loading latency, and balances compression ratio and model fidelity.

[0007] The technical solution of this invention is as follows:

[0008] In a first aspect, the present invention provides a GPU-accelerated method for compressing and decoding three-dimensional models, characterized by comprising the following steps:

[0009] Based on the topology and geometric distribution of the 3D model, the 3D model is divided into several independent sub-model blocks. Each sub-model block contains complete topological information, geometric information and texture information, and the size of the sub-model block is adapted to the parallel processing capability of the GPU.

[0010] Based on the GPU parallel computing architecture, the topological, geometric, and texture information of each sub-model block is collaboratively compressed and packaged into a compressed file;

[0011] Based on the UDP protocol, the compressed packets of each sub-model block are transmitted in parallel, and dynamic bandwidth is allocated according to the transmission priority of the sub-model blocks.

[0012] While receiving the compressed packages of each of the sub-model blocks, the receiving end starts GPU parallel decoding and real-time rendering;

[0013] The GPU's operating frequency is optimized based on dynamic voltage and frequency adjustment technology.

[0014] As a preferred embodiment of the present invention, in the process of dividing the three-dimensional model into several independent sub-model blocks, adaptive partitioning is performed based on the curvature characteristics and vertex density of the three-dimensional model. The block boundary set is determined by minimizing the sum of the products of the curvature of all vertices on the block boundary and the distance from the vertex to the candidate block boundary.

[0015] Among them, the candidate block boundary is all possible block boundaries, the curvature of the vertex reflects the degree of model bending at the vertex, and the distance from the vertex to the candidate boundary is the shortest distance between the vertex and the boundary.

[0016] As a preferred embodiment of the present invention, the mathematical model for determining the block boundaries is as follows:

[0017]

[0018] in, For the set of partition boundaries, For candidate block boundaries, Let v be the curvature of vertex v. Let v be the distance from vertex v to the candidate boundary.

[0019] As a preferred embodiment of the present invention, the GPU-based parallel computing architecture collaboratively compresses the topological, geometric, and texture information of each sub-model block and encapsulates it into a compressed package, including:

[0020] Topology information compression: Based on GPU and edge weight calculation model, construct the vertex spanning tree and triangle spanning tree of the sub-model block, and perform run-length encoding on the vertex spanning tree and the triangle spanning tree;

[0021] Geometric information compression: Based on the GPU's single instruction stream multiple data stream architecture, the geometric information is compressed in parallel;

[0022] Texture information compression: Based on the GPU's texture processing unit, each texture block of the texture information is compressed in parallel, and the encoding mode selection of the texture block is optimized;

[0023] Compressed package encapsulation: The compressed topological, geometric, and texture information of each sub-model block, as well as auxiliary information, are encapsulated into an independent compressed package.

[0024] As a preferred embodiment of the present invention, the edge weight calculation model is as follows:

[0025]

[0026] in, Let be the weight of the i-th edge. Let i be the midpoint of the i-th edge. Generate the root node of the tree from the vertices. This is the curvature weighting coefficient. The curvature of the edge midpoint is given; based on the edge weight, the edge set is traversed in parallel by the GPU to determine the splitting edge and generate the vertex spanning tree and triangle spanning tree.

[0027] As a preferred embodiment of the present invention, the compression processing of the geometric information includes:

[0028] A vertex coordinate prediction model is constructed based on the topological correlation of the vertex spanning tree;

[0029] The optimal prediction coefficients and offsets are determined by minimizing the sum of squared prediction errors.

[0030] An adaptive quantization step size is used to quantize the prediction error;

[0031] The quantized prediction error is then entropy encoded.

[0032] As a preferred embodiment of the present invention, the transmission priority calculation formula for the sub-model block is as follows:

[0033]

[0034] in, The transmission priority of the j-th sub-model block is... The visibility coefficient of the sub-model block. This refers to the size of the sub-model block compressed package. and These are the weighting coefficients. .

[0035] As a preferred embodiment of the present invention, the receiving end, while receiving the compressed packages of each of the sub-model blocks, initiates GPU parallel decoding and real-time rendering, including:

[0036] Compressed package reception and parsing: The receiving end receives the compressed packages of each of the sub-model blocks in parallel through multi-threading, parses the header information of the compressed package, determines the ID and compression parameters of the sub-model block, and sends the data body of the compressed package into the GPU decoding buffer;

[0037] GPU parallel decoding: Based on the multi-threaded architecture of GPU, parallel entropy decoding is performed on the compressed data body of each sub-model block;

[0038] Decoding and rendering synchronization scheduling: Design a GPU synchronization scheduling model to adjust the synchronization deviation between decoding and rendering of each sub-model block;

[0039] Sub-block rendering and stitching: The rendering results of each sub-model block are stitched together to form a complete model image; during the stitching process, a smooth transition is performed based on the topological information of the block boundaries, and the rendering priority of the sub-model blocks is dynamically adjusted according to the changes in the user's perspective, with priority given to rendering the sub-model blocks in the visible area.

[0040] In a second aspect, the present invention provides an electronic device, comprising:

[0041] At least one processor; and,

[0042] A memory communicatively connected to the at least one processor; wherein,

[0043] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the GPU-accelerated 3D model compression and decoding method described above.

[0044] Thirdly, the present invention provides a computer-readable storage medium, including a data storage area and a program storage area, wherein the data storage area stores created data and the program storage area stores a computer program; wherein, when the computer program is executed by a processor, it implements the GPU-accelerated three-dimensional model compression and decoding method described above.

[0045] According to the above-described solution, the beneficial effects of this invention are as follows:

[0046] 1. The entire process is based on GPU parallel acceleration, which greatly improves the compression speed of 3D models;

[0047] 2. By adopting a simultaneous decoding and rendering mechanism, the serial mode of first fully decoding and then rendering the whole model is broken, which effectively reduces the loading delay of 3D models and enables the loading of large models with millions of vertices in seconds.

[0048] 3. By using adaptive block partitioning, optimized prediction model, and adaptive quantization strategy, the problem of excessive loading delay of 3D model was solved;

[0049] 4. By dynamically adjusting the GPU frequency, the GPU power consumption is effectively reduced while ensuring real-time performance;

[0050] 5. It is compatible with large models of different sizes and various GPU architectures (CUDA, OpenCL, Vulkan), and can be widely used in multiple fields such as metaverse, VR / AR, 3D games, and industrial design visualization. Attached Figure Description

[0051] Figure 1 This is a flowchart illustrating a GPU-accelerated 3D model compression and decoding method according to an embodiment of the present invention.

[0052] Figure 2 for Figure 1 A detailed flowchart of step S2 is shown below;

[0053] Figure 3 for Figure 1 A detailed flowchart of step S4 is shown below;

[0054] Figure 4 This is a schematic diagram of a GPU-accelerated 3D model compression and decoding device according to an embodiment of the present invention;

[0055] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0056] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0057] It should be noted that the terms "comprising" and "having," and any variations thereof, in the specification and claims of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0058] like Figure 1 As shown, one embodiment of the present invention provides a GPU-accelerated method for compressing and decoding 3D models, characterized by comprising the following steps:

[0059] Step S1, Model Block Preprocessing: Based on the topology and geometric distribution of the 3D model, the 3D model is divided into several independent sub-model blocks. Each sub-model block contains complete topological, geometric, and texture information, and the size of the sub-model block is adapted to the parallel processing capability of the GPU.

[0060] Specifically, in the process of dividing the 3D model into several independent sub-model blocks, adaptive partitioning is performed based on the curvature characteristics and vertex density of the 3D model. The block boundary set is determined by minimizing the sum of the products of the curvature of all vertices on the block boundary and the distance from that vertex to the candidate block boundary. The candidate block boundary is all possible block boundaries. The curvature of a vertex reflects the degree of model curvature at that vertex, and the distance from a vertex to the candidate boundary is the shortest distance between the vertex and the boundary. The mathematical model for determining the block boundaries is shown below:

[0061]

[0062] in, For the set of partition boundaries, For candidate block boundaries, Let v be the curvature of vertex v. Let v be the distance from vertex v to the candidate boundary. This mathematical model ensures that the block boundaries avoid the high-curvature, detail-rich regions of the model, reducing the impact of block division on model fidelity. At the same time, it ensures that the size of each sub-model block is uniform, adapting to GPU thread scheduling and solving the problems of detail distortion and uneven GPU load caused by traditional uniform block division.

[0063] Step S2, GPU-accelerated sub-block compression: Based on the GPU parallel computing architecture, the topology, geometry, and texture information of each sub-model block are collaboratively compressed and packaged into a compressed file. Since each sub-model block corresponds to a GPU thread block, the compression process of topology, geometry, and texture information is executed in parallel, significantly improving compression efficiency.

[0064] Specifically, such as Figure 2As shown, the steps for GPU-accelerated sub-block compression are as follows:

[0065] Step S201, Topology Information Compression: Based on the GPU and edge weight calculation model, construct the vertex spanning tree and triangle spanning tree of the sub-model block, and perform run-length encoding on the vertex spanning tree and triangle spanning tree to complete the topology information compression. The edge weight calculation model is as follows:

[0066]

[0067] in, Let be the weight of the i-th edge. Let i be the midpoint of the i-th edge. Generate the root node of the tree from the vertices. This is the curvature weighting coefficient (range 0.1-0.3). Let be the curvature of the midpoint of the edge. After obtaining the weight of each edge based on the edge weight calculation model, the edge set is traversed in parallel by the GPU to determine the splitting edges, thereby generating the vertex spanning tree and triangle spanning tree. The introduction of a curvature factor in the edge weight calculation model improves compression accuracy.

[0068] Step S202, Geometric Information Compression: Based on the GPU's Single Instruction Multiple Data (SIMD) architecture, geometric information such as vertex coordinates and normal vectors is compressed in parallel. The specific compression process is as follows:

[0069] First, based on the topological relationships of the vertex spanning tree, a vertex coordinate prediction model is constructed:

[0070]

[0071] in, Let n be the predicted coordinates of the nth vertex. For prediction coefficients, The coordinates of the k ancestor vertices of the nth vertex. The offset is calculated by minimizing the sum of squared prediction errors ( Determine the optimal prediction coefficients. and offset Subsequently, an adaptive quantization step size was used to quantize the prediction error:

[0072]

[0073] in, For prediction error, To quantize the step size, it is adaptively adjusted based on the model's detail complexity (in regions with rich detail). Values ​​range from 0.001 to 0.005, representing a flat region. (Values ​​range from 0.01 to 0.05). Finally, entropy encoding (Huffman coding) is performed on the quantized prediction error to complete the geometric information compression.

[0074] Step S203, Texture Information Compression: Based on the GPU's texture processing unit, each texture block of texture information is compressed and processed in parallel, optimizing the encoding mode selection of texture blocks, reducing texture data redundancy, and ensuring texture fidelity.

[0075] Step S204, Compressed Package Encapsulation: The topological, geometric, and texture information of each sub-model block, as well as auxiliary information such as block index and compression parameters, are encapsulated into an independent compressed package; each compressed package contains a header (block ID, data length, compression parameters) and a data body (various types of compressed information), which facilitates parallel processing during subsequent transmission and decoding.

[0076] Step S3, Parallel Transmission of Compressed Packets: Based on the UDP protocol, the compressed packets of each sub-model block are transmitted in parallel, and dynamic bandwidth allocation is performed according to the transmission priority of the sub-model blocks (sub-blocks in visible areas have higher priority, and sub-blocks in invisible areas have lower priority). The formula for calculating the transmission priority of the sub-model blocks is as follows:

[0077]

[0078] in, The transmission priority of the j-th sub-model block is... This is the visibility coefficient of the sub-model block (1 for visible areas, 0.5 for semi-visible areas, and 0.1 for invisible areas). This refers to the size of the sub-model block compressed package. and These are the weighting coefficients. ( (The value is typically 0.7-0.8). This transmission priority calculation formula enables priority transmission of sub-model blocks in the visible area, further reducing loading latency.

[0079] Step S4, GPU-accelerated sub-block decoding and rendering: While receiving the compressed packages of each sub-model block, the receiving end starts GPU parallel decoding and real-time rendering to achieve simultaneous reception, decoding and rendering.

[0080] Specifically, such as Figure 3 As shown, the steps for GPU-accelerated sub-block decoding and rendering are as follows:

[0081] Step S401, Compressed Packet Reception and Parsing: The receiving end receives the compressed packets of each sub-model block in parallel through multi-threading, parses the packet header information of the compressed packet, determines the ID of the sub-model block, compression parameters, etc., and sends the data body of the compressed packet into the GPU decoding buffer.

[0082] Step S402, GPU Parallel Decoding: Based on a multi-threaded GPU architecture, parallel entropy decoding is performed on the compressed data of each sub-model block, corresponding to the reverse process of the compression stage: the quantized prediction error is obtained through entropy decoding, and the original prediction error is recovered through inverse quantization, combined with the prediction model to recover vertex coordinates; the spanning tree encoding is decoded to recover the vertex spanning tree and triangle spanning tree, reconstructing the topology; the texture compressed data is decoded to recover the texture image. During the decoding process, a dynamic GPU thread scheduling mechanism is adopted, allocating decoding threads according to the receiving progress of the compressed package and the GPU load to ensure that the decoding efficiency is synchronized with the receiving progress.

[0083] Step S403, Decoding and Rendering Synchronization Scheduling: Design a GPU synchronization scheduling model to adjust the synchronization deviation between decoding and rendering of each sub-model block, achieving seamless integration of decoding and rendering. The GPU synchronization scheduling model is designed as follows:

[0084]

[0085] in, For synchronization deviation, This represents the decoding time for the sub-model block. This is the rendering time for the previous sub-model block. When ( When the synchronization threshold (value is 1~2ms) is reached, the GPU adjusts the number of decoding threads or the rendering frame rate to ensure that the decoded sub-model blocks can immediately enter the rendering process, avoiding decoding wait or rendering idle.

[0086] Step S404, Sub-block rendering and stitching: The rendering results of each sub-model block are stitched together into a complete model image. During the stitching process, based on the topological information of the block boundaries, a smooth transition is performed to eliminate stitching marks and ensure the integrity and consistency of the rendered image. At the same time, the rendering priority of the sub-model blocks is dynamically adjusted according to changes in the user's perspective, prioritizing the rendering of sub-model blocks in the visible area to further optimize rendering efficiency.

[0087] Step S5, GPU load optimization: To ensure efficient and stable operation of the entire compression, decoding, and rendering process, the GPU's operating frequency is optimized based on Dynamic Voltage Frequency Scaling (DVFS) technology to balance processing efficiency and energy consumption.

[0088] Specifically, the objective function for optimizing the GPU's operating frequency is as follows:

[0089]

[0090] in, For GPU operating frequency, This refers to the total processing time. Set the target processing time (based on the application scenario). As time weight, As energy consumption weight, GPU power consumption ( Where A is the activity factor, C is the capacitance, and V is the voltage. (This refers to standby power). By optimizing this objective function, the optimal GPU operating frequency is determined, thereby reducing power consumption while ensuring real-time performance.

[0091] This embodiment presents a GPU-accelerated 3D model compression and decoding method that achieves full-process GPU acceleration for 3D model block compression, parallel transmission, and simultaneous decoding and rendering. It breaks the serial mode of full decoding followed by overall rendering by employing a simultaneous decoding and rendering mechanism, effectively reducing 3D model loading latency and enabling second-level loading of large models with millions of vertices. Through adaptive block division, optimized prediction models, and adaptive quantization strategies, it solves the problem of excessively high 3D model loading latency. Dynamic GPU frequency adjustment effectively reduces GPU power consumption while ensuring real-time performance. It is adaptable to large models of different sizes and various GPU architectures (CUDA, OpenCL, Vulkan), and can be widely applied in multiple fields such as metaverse, VR / AR, 3D games, and industrial design visualization.

[0092] like Figure 4 As shown, one embodiment of the present invention provides a GPU-accelerated 3D model compression and decoding device, comprising:

[0093] Block preprocessing module 1 is used to divide the 3D model into several independent sub-model blocks based on the topology and geometric distribution of the 3D model. Each sub-model block contains complete topological, geometric and texture information, and the size of the sub-model block is adapted to the parallel processing capability of the GPU.

[0094] GPU compression module 2 is used to collaboratively compress the topological, geometric, and texture information of each sub-model block based on the GPU parallel computing architecture, and encapsulate it into a compressed package;

[0095] Parallel transmission module 3 is used to transmit the compressed packets of each sub-model block in parallel based on the UDP protocol, and to dynamically allocate bandwidth according to the transmission priority of the sub-model blocks.

[0096] GPU decoding and rendering module 4 is used to start GPU parallel decoding and real-time rendering while receiving the compressed package of each sub-model block at the receiving end, so as to realize simultaneous reception, decoding and rendering.

[0097] Load Optimization Module 5: Used to optimize the GPU's operating frequency and balance processing efficiency and energy consumption based on dynamic voltage and frequency adjustment technology.

[0098] The GPU-accelerated 3D model compression and decoding device provided in this application embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, so it will not be described again here.

[0099] Figure 5 This is a schematic diagram of the electronic device that implements the GPU-accelerated three-dimensional model compression and decoding method of the present invention.

[0100] The electronic device may include a processor 10, a memory 11, a communication bus 12 and a communication interface 13, and may also include a computer program stored in the memory 11 and capable of running on the processor 10, such as a GPU-accelerated 3D model compression and decoding program.

[0101] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (GPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., executing GPU-accelerated 3D model compression and decoding programs) and calls data stored in the memory 11 to perform various functions of the electronic device and process data.

[0102] The memory 11 includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of an electronic device, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. Furthermore, the memory 11 can include both internal and external storage units of the electronic device. The memory 11 can be used not only to store application software and various types of data installed on the electronic device, such as the code of a GPU-accelerated 3D model compression and decoding program, but also to temporarily store data that has been output or will be output.

[0103] The communication bus 12 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0104] Communication interface 13 is used for communication between the aforementioned electronic device and other devices, including a network interface and a user interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, Bluetooth interface, etc.), typically used to establish communication connections between the electronic device and other electronic devices. The user interface may be a display, an input unit (such as a keyboard), and optionally, a standard wired or wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device and to display a visual user interface.

[0105] Figure 5 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 5 The structure shown does not constitute a limitation on the electronic device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0106] For example, a power supply, although not shown, may also include a power source (such as a battery) to power various components. Preferably, the power supply can be logically connected to at least one processor 10 via a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power sources, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be elaborated further here.

[0107] It should be understood that the embodiments are for illustrative purposes only and are not limited to this structure in the scope of the patent application.

[0108] The memory 11 in the electronic device stores a GPU-accelerated 3D model compression and decoding program, which is a combination of multiple computer programs.

[0109] For the specific implementation method of the above computer program by processor 10, please refer to Figure 1 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0110] Furthermore, if the modules / units integrated into an electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, a computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, and read-only memory (ROM).

[0111] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following functions: Figure 1 The flowchart illustrates the GPU-accelerated 3D model compression and decoding method.

[0112] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0113] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0115] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0116] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the invention. No appended diagram markings in the claims should be construed as limiting the scope of the claims.

[0117] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0118] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0119] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0120] The present invention has been described above with reference to the accompanying drawings. Obviously, the implementation of the present invention is not limited to the above-described manner. Any improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other situations without modification, are all within the protection scope of the present invention.

Claims

1. A GPU-accelerated method for compressing and decoding 3D models, characterized in that, Includes the following steps: Based on the topology and geometric distribution of the 3D model, the 3D model is divided into several independent sub-model blocks. Each sub-model block contains complete topological information, geometric information and texture information, and the size of the sub-model block is adapted to the parallel processing capability of the GPU. Based on the GPU parallel computing architecture, the topological, geometric, and texture information of each sub-model block is collaboratively compressed and packaged into a compressed file; Based on the UDP protocol, the compressed packets of each sub-model block are transmitted in parallel, and dynamic bandwidth is allocated according to the transmission priority of the sub-model blocks. While receiving the compressed packages of each of the sub-model blocks, the receiving end starts GPU parallel decoding and real-time rendering; The GPU's operating frequency is optimized based on dynamic voltage and frequency adjustment technology.

2. The GPU-accelerated 3D model compression and decoding method according to claim 1, characterized in that, In the process of dividing the 3D model into several independent sub-model blocks, adaptive partitioning is performed based on the curvature features and vertex density of the 3D model. The block boundary set is determined by minimizing the sum of the products of the curvature of all vertices on the block boundary and the distance from that vertex to the candidate block boundary. Among them, the candidate block boundary is all possible block boundaries, the curvature of the vertex reflects the degree of model bending at the vertex, and the distance from the vertex to the candidate boundary is the shortest distance between the vertex and the boundary.

3. The GPU-accelerated 3D model compression and decoding method according to claim 2, characterized in that, The mathematical model for determining the block boundaries is as follows: ； in, For the set of partition boundaries, For candidate block boundaries, Let v be the curvature of vertex v. Let v be the distance from vertex v to the candidate boundary.

4. The GPU-accelerated 3D model compression and decoding method according to claim 1, characterized in that, The GPU-based parallel computing architecture collaboratively compresses the topological, geometric, and texture information of each sub-model block and encapsulates it into a compressed package, including: Topology information compression: Based on GPU and edge weight calculation model, construct the vertex spanning tree and triangle spanning tree of the sub-model block, and perform run-length encoding on the vertex spanning tree and the triangle spanning tree; Geometric information compression: Based on the GPU's single instruction stream multiple data stream architecture, the geometric information is compressed in parallel; Texture information compression: Based on the GPU's texture processing unit, each texture block of the texture information is compressed in parallel, and the encoding mode selection of the texture block is optimized; Compressed package encapsulation: The compressed topological, geometric, and texture information of each sub-model block, as well as auxiliary information, are encapsulated into an independent compressed package.

5. The GPU-accelerated 3D model compression and decoding method according to claim 4, characterized in that, The edge weight calculation model is as follows: ； in, Let be the weight of the i-th edge. Let i be the midpoint of the i-th edge. Generate the root node of the tree from the vertices. This is the curvature weighting coefficient. The curvature of the edge midpoint is given; based on the edge weight, the edge set is traversed in parallel by the GPU to determine the splitting edge and generate the vertex spanning tree and triangle spanning tree.

6. The GPU-accelerated 3D model compression and decoding method according to claim 4, characterized in that, The compression process of the geometric information includes: A vertex coordinate prediction model is constructed based on the topological correlation of the vertex spanning tree; The optimal prediction coefficients and offsets are determined by minimizing the sum of squared prediction errors. An adaptive quantization step size is used to quantize the prediction error; The quantized prediction error is then entropy encoded.

7. The GPU-accelerated 3D model compression and decoding method according to claim 1, characterized in that, The formula for calculating the transmission priority of the sub-model block is as follows: ； in, The transmission priority of the j-th sub-model block is... The visibility coefficient of the sub-model block. This refers to the size of the sub-model block compressed package. and These are the weighting coefficients. .

8. The GPU-accelerated 3D model compression and decoding method according to claim 1, characterized in that, While receiving the compressed packages of each of the sub-model blocks, the receiving end initiates GPU parallel decoding and real-time rendering, including: Compressed package reception and parsing: The receiving end receives the compressed packages of each of the sub-model blocks in parallel through multi-threading, parses the header information of the compressed package, determines the ID and compression parameters of the sub-model block, and sends the data body of the compressed package into the GPU decoding buffer; GPU parallel decoding: Based on the multi-threaded architecture of GPU, parallel entropy decoding is performed on the compressed data body of each sub-model block; Decoding and rendering synchronization scheduling: Design a GPU synchronization scheduling model to adjust the synchronization deviation between decoding and rendering of each sub-model block; Sub-block rendering and stitching: The rendering results of each sub-model block are stitched together to form a complete model image; during the stitching process, a smooth transition is performed based on the topological information of the block boundaries, and the rendering priority of the sub-model blocks is dynamically adjusted according to the changes in the user's perspective, with priority given to rendering the sub-model blocks in the visible area.

9. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the GPU-accelerated 3D model compression and decoding method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing computer-executable instructions, characterized in that, It includes a data storage area and a program storage area. The data storage area stores the created data, and the program storage area stores the computer program. When the computer program is executed by the processor, it implements the GPU-accelerated three-dimensional model compression and decoding method as described in any one of claims 1 to 8.

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