A method for a video self-loop output to be compatible with a video decode output interface

Abstract

The application relates to a method for making a video self-loop output compatible with a video decoding output interface, comprising the following steps: powering on a video processing device; a video processing module of the video processing device detecting and identifying a mode selection signal, wherein the mode selection signal is 0 corresponding to a video self-loop output mode and the mode selection signal is 1 corresponding to a video decoding output mode; the video processing module configuring a first chip according to the identified mode selection signal, controlling the first chip to complete two-alternative output of a video stream, and the first chip outputting a video data stream to a second chip or to a video coding and decoding module for processing; and the video processing module configuring the second chip according to the identified mode selection signal, controlling the second chip to complete two-alternative input of the video stream, and the second chip receiving a raw video data stream directly transmitted by the first chip or receiving a video data stream processed by the video coding and decoding module.

Description

Technical Field

[0001] This invention relates to the fields of video processing and integrated circuit design technology, and specifically to a method for video self-loop output and video decoding output interface compatibility. Background Technology

[0002] In the development and application of integrated circuits for video encoding and decoding, video conversion, and video processing equipment, the equipment typically has two requirements: conventional video decoding output and internal video loop-through output. Video decoding output is used to output the decoded standard video data stream to an external display device, while video loop-through output is mostly used for device self-testing, function debugging, performance verification, and firmware upgrades. Existing traditional solutions set up independent physical interfaces and dedicated signal paths for the two output functions, separately allocate dedicated pins, and plan PCB traces. This not only occupies a lot of chip I / O resources, increases chip area and hardware production costs, but also increases the difficulty of circuit board wiring and the number of PCB layers, which is not conducive to the miniaturization and high-density integration of the equipment. Moreover, mode switching often relies on external jumpers, physical switches, and other operations, making the switching process cumbersome and the debugging inconvenience poor. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method that is compatible with video self-loop output and video decoding output interfaces, in order to overcome the shortcomings of the prior art.

[0004] The technical solution of this invention to solve the above-mentioned technical problems is as follows: A method for video self-loop output and video decoding output interface compatibility, comprising the following steps: Power on the video processing equipment; The video processing module of the video processing equipment detects and identifies the mode selection signal, where a mode selection signal of 0 corresponds to the video self-loop output mode, and a mode selection signal of 1 corresponds to the video decoding output mode. The video processing module configures the first chip based on the identified mode selection signal, controls the first chip to complete the two-way video stream output, and sends the video data stream output by the first chip to the second chip or to the video encoding and decoding module for processing.

[0005] The video processing module configures the second chip based on the identified mode selection signal and controls the second chip to complete the two-input video stream selection. The second chip receives the raw video data stream directly transmitted by the first chip or the video data stream processed by the video codec module.

[0006] The beneficial effects of adopting the technical solution of this invention are as follows: This invention completes the video data stream routing switch by linking the first chip and the second chip through the video processing module. It realizes both video self-loop output and video decoding output functions in a time-division manner through the same set of hardware paths. It eliminates the need to design independent hardware links and output interfaces for the two working modes, which can save chip I / O pin resources, reduce PCB layout space, reduce the complexity of device hardware design and the overall production cost, and improve device integration. The path can be automatically switched by simply relying on software to identify the mode selection signal, without the need for manual operation of external switches and jumpers, simplifying the device self-testing and debugging process. At the same time, the two video data streams have regular transmission paths and low signal loss. The self-loop mode can completely retain the original video signal for hardware link verification, and the decoding mode can standardize the video signal to adapt to various display terminals, taking into account both debugging scenarios and regular business output needs, ensuring stable video transmission and good picture output effect under different working modes.

[0007] Furthermore, the first chip and its peripheral circuits form a video interface splitter circuit, which includes a video input channel, a video loopback output channel, and a video output channel.

[0008] The advantages of adopting the above-mentioned further solution are that it uses the first chip and peripheral circuits to form an integrated video interface 1-to-2 circuit, integrating three types of transmission paths: video input channel, video loop-through output channel, and video output channel. It eliminates the need for additional independent signal distribution devices, simplifies the design of the overall peripheral hardware circuit and PCB layout, and reduces signal loss and electromagnetic interference caused by signal conversion. The chip's native multi-channel switching capability enables hardware splitting of the two video data streams. The signal path can be flexibly switched according to the working mode. One path enables the original video direct loop-through debugging, while the other path connects to the video codec module to achieve service decoding output. One set of hardware circuits simultaneously carries both debugging and normal service transmission links, reusing hardware resources, effectively saving chip pins, reducing material costs, and improving the overall hardware integration and video signal transmission stability.

[0009] Furthermore, the video processing module of the video processing device detects and identifies the mode selection signal by: when the video processing module identifies the mode selection signal as 0, sending a control command to the video interface splitter circuit to establish a video loopback path; when the video processing module identifies the mode selection signal as 1, sending a control command to the video interface splitter circuit to connect the video data stream to the decoding link.

[0010] The beneficial effect of adopting the above-mentioned further solution is that the video processing module identifies the mode selection signal with different levels and sends corresponding control commands to the video interface splitter circuit to switch the video transmission path. When the signal is 0, a direct self-loop path without the participation of the decoding unit is quickly established. When the signal is 1, it automatically switches to the decoding link. The entire path switching is completed by software commands, without the need for manual toggling of external switches or modification of hardware jumpers. The mode switching response speed is fast and the degree of automation is high.

[0011] Furthermore, the establishment of the video self-loop path includes: connecting the video input channel and the video self-loop output channel, wherein the input video data stream does not pass through the video encoding and decoding module and is directly output in a loop.

[0012] The beneficial effect of adopting the above-mentioned further solution is that it directly connects the video input channel and the video self-loop output channel, allowing the input video data stream to bypass the video codec module and directly loop back to output, eliminating the decoding and encoding processing steps, greatly reducing the computational load of the video processing module and the codec unit, reducing the transmission delay and image quality loss caused by multi-level signal processing, completely restoring the original input video data stream, and facilitating accurate verification of hardware link integrity and verification of interface transmission performance.

[0013] Furthermore, the step of connecting the video data stream to the decoding link includes: switching the video input channel to the video codec module, and then transmitting the input video data to the video output channel after processing by the video codec module.

[0014] The beneficial effect of adopting the above-mentioned further solution is that by switching the video input channel to the video codec module, the raw video data stream is uniformly handed over to the video codec module to complete the standardization processing such as decoding and format adaptation before being sent to the video output channel. This can standardize the input video signal and output a standard video stream that is compatible with various external display devices, meeting the routine business needs of the device for daily video playback, image output, etc. By completing signal processing through an independent decoding link, the video signal transmission is stable and the terminal compatibility is strong, which can ensure smooth and clear picture under normal business scenarios and effectively improve the video output quality and usage compatibility of the device during normal operation.

[0015] Furthermore, the control of the first chip to complete the two-to-one video stream output specifically includes: the video processing module configuring the multiplexer inside the first chip to perform route selection on the video data stream decoupled from the first chip.

[0016] The advantages of adopting the above-mentioned further solution are that by configuring the video processing module with the built-in multiplexer of the first chip to perform routing selection for the video data stream after decoupling from the chip, the video stream path switching is realized by relying on the chip's built-in hardware path, without the need to add additional external switching switches or discrete signal switching circuits, simplifying the external PCB wiring structure and reducing the cost and failure points caused by additional hardware; the hardware-level switching response speed is fast and the signal transmission loss is small, which can accurately split the original video data stream according to the current working mode, and adapt to the two paths of self-loop direct transmission and back-end decoding processing respectively, ensuring stable and reliable video signal transmission in both working modes.

[0017] Furthermore, when the device is in video loop-through output mode, the first chip is controlled to directly transmit the decoupled video data stream to the second chip; when the device is in video decoding output mode, the first chip is controlled to transmit the decoupled video data stream to the video encoding / decoding module for decoding processing.

[0018] The beneficial effects of adopting the above-mentioned further solution are that, according to the current working mode of the device, the first chip is controlled to perform targeted distribution of the decoupled video data stream. In the self-loop mode, the original video data stream is sent directly to the second chip, bypassing the video codec module, reducing the image quality attenuation and transmission delay caused by multi-level signal processing, and completely preserving the characteristics of the original video signal, which facilitates accurate verification of whether the input and output hardware links are intact. In the decoding mode, the data stream is sent to the video codec module for standardized decoding processing, which can provide a regular and clean video source for back-end business output, ensuring smooth and clear display. The two data streams are split on demand through the first chip, with a simple path and less signal interference. One set of hardware can be compatible with both debugging self-test and normal business output scenarios, with strong hardware reusability, effectively reducing the overall hardware design cost.

[0019] Furthermore, the control of the second chip to complete the two-way input of the video stream specifically includes: the video processing module configuring the input selection switch built into the second chip to switch the video data stream receiving source of the second chip.

[0020] The advantages of adopting the above-mentioned further solution are that by configuring the input selection switch built into the second chip through the video processing module to switch the input source of the video data stream, the internal selection of the two video sources is completed through the chip's native hardware, eliminating the need for additional external analog switches and discrete signal switching components. This simplifies the external PCB wiring and reduces signal attenuation and electromagnetic interference caused by multi-stage conversion. This control logic can work in conjunction with the front-end signal splitter chip to receive the original direct video data stream and the encoded / decoded post-processed video data stream in a time-division multiplexing manner, and share the same set of output circuits for external output. This achieves hardware multiplexing of the two service links, reducing material costs and saving main control pin resources. At the same time, mode switching is completed by hardware switches, with fast response speed, and the video output signal is stable and continuous in both working modes.

[0021] Furthermore, when the device is in video loop-out output mode, the second chip receives the raw video data stream from the first chip and outputs it externally; when the device is in video decoding output mode, the second chip receives the video data stream processed by the video encoding and decoding module and converts it into a video stream for external output.

[0022] The beneficial effects of adopting the above-mentioned further solution are that when the device switches to the video loop-out output mode, the second chip directly receives the complete original video data stream output by the first chip and outputs it externally, completely preserving the original signal without secondary processing loss. This allows for direct verification of the integrity of the entire hardware transmission link. When the device switches to the video decoding output mode, the second chip receives the video data regulated by the video encoding and decoding module and converts it into a standard video stream for output, adapting to various external display terminals. Both modes share the same second chip and the same external output interface, eliminating the need to configure two separate sets of output hardware. This reduces the material costs of chips, connectors, and PCB wiring, lowering the overall hardware cost. The front and rear chips are synchronously controlled and switched by the video processing module, resulting in rapid path switching response and less signal transfer interference. A single hardware architecture simultaneously accommodates two usage scenarios: hardware debugging and self-testing, and routine video service output. This significantly improves the device's integration and versatility.

[0023] Furthermore, powering on the video processing device includes: connecting the video processing device to a power socket and connecting it to the debugging and maintenance port to supply DC12V power to the device.

[0024] The beneficial effect of adopting the above-mentioned further solution is that by using a unified DC12V power supply and a corresponding debugging and maintenance port for synchronous power-on, it can stably ensure that the equipment's working power supply and standby power supply are synchronously and reliably powered on, providing a stable working voltage for the first chip, the second chip, and core video processing chips such as the CPU, avoiding video path switching failures caused by abnormal voltage. At the same time, the debugging and maintenance port can output the equipment power-on log in real time, which makes it easier for developers to quickly judge the overall power-on status, promptly troubleshoot power supply and hardware link anomalies, and improve the efficiency of equipment debugging and fault diagnosis. Attached Figure Description

[0025] Figure 1 This is a flowchart illustrating a method for a video self-loop output and video decoding output interface compatible with an embodiment of the present invention. Detailed Implementation

[0026] The principles and features of the present invention are described below. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0029] It should be noted that similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," "inner," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship in which the product of the invention is usually placed, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0030] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0031] like Figure 1 As shown, this embodiment of the invention provides a method for video self-loop output and video decoding output interface compatibility, including the following steps: Power on the video processing equipment.

[0032] The video processing module of the video processing equipment detects and identifies the mode selection signal, where a mode selection signal of 0 corresponds to the video self-loop output mode, and a mode selection signal of 1 corresponds to the video decoding output mode.

[0033] The video processing module configures the first chip based on the detected mode selection signal, controlling the first chip to perform a two-way video stream output. The video data stream output by the first chip is sent to the second chip or to the video codec module for processing. Preferably, the first chip is an LT86102 and the second chip is an LT8641uxe. The video processing module identifies the device's mode selection signal in real time and configures the registers of the LT86102 first chip via the I2C communication bus according to two different working scenarios: self-loop output mode and decoding output mode. The LT86102 chip integrates a signal decoupling unit and a programmable multiplexer switch, which can perform signal shaping, clock repair, and data decoupling processing on the incoming raw video data stream, and perform precise routing according to the configuration instructions. When the self-loop output mode is detected, the first chip directly transmits the decoupled raw video data stream to the LT8641uxe second chip, forming a direct transmission link; when the decoding output mode is detected, the first chip switches the routing of the video data stream and sends it to the video codec module for decoding, format adaptation, and other standardization processing.

[0034] The video processing module configures the second chip based on the identified mode selection signal and controls the second chip to complete the two-to-one input of the video stream. The second chip receives the raw video data stream directly transmitted by the first chip or receives the video data stream processed by the video codec module.

[0035] The beneficial effects of adopting the technical solution of this invention are as follows: This invention completes the video data stream routing switch by linking the first chip and the second chip through the video processing module. It realizes both video self-loop output and video decoding output functions in a time-division manner through the same set of hardware paths. It eliminates the need to design independent hardware links and output interfaces for the two working modes, which can save chip I / O pin resources, reduce PCB layout space, reduce the complexity of device hardware design and the overall production cost, and improve device integration. The path can be automatically switched by simply relying on software to identify the mode selection signal, without the need for manual operation of external switches and jumpers, simplifying the device self-testing and debugging process. At the same time, the two video data streams have regular transmission paths and low signal loss. The self-loop mode can completely retain the original video signal for hardware link verification, and the decoding mode can standardize the video signal to adapt to various display terminals, taking into account both debugging scenarios and regular business output needs, ensuring stable video transmission and good picture output effect under different working modes.

[0036] Furthermore, the first chip and its peripheral circuits form a video interface splitter circuit, which includes a video input channel, a video loopback output channel, and a video output channel. The video input channel corresponds to the HDMI receiver trace of the first chip and the external HDMI input socket, used to access the external raw HDMI video data stream and complete differential impedance matching and signal reception. The video loopback output channel corresponds to the first transmit output port trace of the LT86102, directly connected to the input pin of the LT8641uxe, forming a direct loopback link without going through the video codec module. The video output channel corresponds to the second transmit output port trace of the LT86102, connected to the input of the video codec module, providing the raw video data source for the decoding service link.

[0037] The advantages of adopting the above-mentioned further solution are that it uses the first chip and peripheral circuits to form an integrated video interface 1-to-2 circuit, integrating three types of transmission paths: video input channel, video loop-through output channel, and video output channel. It eliminates the need for additional independent signal distribution devices, simplifies the design of the overall peripheral hardware circuit and PCB layout, and reduces signal loss and electromagnetic interference caused by signal conversion. The chip's native multi-channel switching capability enables hardware splitting of the two video data streams. The signal path can be flexibly switched according to the working mode. One path enables the original video direct loop-through debugging, while the other path connects to the video codec module to achieve service decoding output. One set of hardware circuits simultaneously carries both debugging and normal service transmission links, reusing hardware resources, effectively saving chip pins, reducing material costs, and improving the overall hardware integration and video signal transmission stability.

[0038] Furthermore, the video processing module of the video processing device detects and identifies the mode selection signal by: when the video processing module identifies the mode selection signal as 0, sending a control command to the video interface splitter circuit to establish a video loopback path; when the video processing module identifies the mode selection signal as 1, sending a control command to the video interface splitter circuit to connect the video data stream to the decoding link. The video processing module has a built-in central processing unit (CPU), which performs mode recognition, chip register configuration, and control command issuance. The CPU establishes communication with the first chip constituting the video interface splitter circuit through the device's internal I2C communication bus, encapsulates the register configuration parameters of the corresponding mode into control commands, and issues them to the LT86102. The path switching is achieved by rewriting the chip's internal routing register. The entire process is controlled by software logic, without any manual switching structures such as hardware jumpers or mechanical switches.

[0039] The beneficial effect of adopting the above-mentioned further solution is that the video processing module identifies the mode selection signal with different levels and sends corresponding control commands to the video interface splitter circuit to switch the video transmission path. When the signal is 0, a direct self-loop path without the participation of the decoding unit is quickly established. When the signal is 1, it automatically switches to the decoding link. The entire path switching is completed by software commands, without the need for manual toggling of external switches or modification of hardware jumpers. The mode switching response speed is fast and the degree of automation is high.

[0040] Furthermore, establishing the video loopback path includes connecting the video input channel and the video loopback output channel, whereby the input video data stream bypasses the video encoding / decoding module and is directly output in a loopback manner. Channel switching control is achieved through a video interface splitter circuit composed of the first chip. When the device operates in video loopback output mode, the video processing module issues a configuration command to control the multi-path routing switch within the first chip to complete channel switching, directly connecting the video input channel and the video loopback output channel in the hardware circuit to form an independent, direct-through video transmission link.

[0041] The beneficial effect of adopting the above-mentioned further solution is that it directly connects the video input channel and the video self-loop output channel, allowing the input video data stream to bypass the video codec module and directly loop back to output, eliminating the decoding and encoding processing steps, greatly reducing the computational load of the video processing module and the codec unit, reducing the transmission delay and image quality loss caused by multi-level signal processing, completely restoring the original input video data stream, and facilitating accurate verification of hardware link integrity and verification of interface transmission performance.

[0042] Furthermore, connecting the video data stream to the decoding link includes: switching the video input channel to the video codec module; the input video data is processed by the video codec module before being transmitted to the video output channel. Link switching is achieved through the programmable multiplexing function of the first chip. When the device is identified as being in video decoding output mode, the video processing module, by configuring the internal multiplexer of the first chip, disconnects the direct path between the input channel and the loopback output channel, and directionally switches the video input channel to the input branch of the video codec module, so that all externally input raw video data streams are imported into the video codec module.

[0043] The beneficial effect of adopting the above-mentioned further solution is that by switching the video input channel to the video codec module, the raw video data stream is uniformly handed over to the video codec module to complete the standardization processing such as decoding and format adaptation before being sent to the video output channel. This can standardize the input video signal and output a standard video stream that is compatible with various external display devices, meeting the routine business needs of the device for daily video playback, image output, etc. By completing signal processing through an independent decoding link, the video signal transmission is stable and the terminal compatibility is strong, which can ensure smooth and clear picture under normal business scenarios and effectively improve the video output quality and usage compatibility of the device during normal operation.

[0044] Furthermore, the control of the first chip to perform a two-way video stream output specifically includes: the video processing module configuring the multiplexer inside the first chip to perform routing selection on the video data stream decoupled from the first chip. The first chip has a built-in programmable hardware multiplexer with one input and two independent output branches, corresponding to a self-loop direct path and a decoding processing path, respectively. The video processing module reads and writes the internal routing register of the LT86102 via the I2C bus, and can switch the multiplexer's conducting branches by modifying the register configuration value, thus completing the two-way video data stream splitting at the hardware level.

[0045] The advantages of adopting the above-mentioned further solution are that by configuring the video processing module with the built-in multiplexer of the first chip to perform routing selection for the video data stream after decoupling from the chip, the video stream path switching is realized by relying on the chip's built-in hardware path, without the need to add additional external switching switches or discrete signal switching circuits, simplifying the external PCB wiring structure and reducing the cost and failure points caused by additional hardware; the hardware-level switching response speed is fast and the signal transmission loss is small, which can accurately split the original video data stream according to the current working mode, and adapt to the two paths of self-loop direct transmission and back-end decoding processing respectively, ensuring stable and reliable video signal transmission in both working modes.

[0046] Furthermore, when the device is in video loop-through output mode, the first chip is controlled to directly transmit the decoupled video data stream to the second chip; when the device is in video decoding output mode, the first chip is controlled to transmit the decoupled video data stream to the video encoding / decoding module for decoding processing.

[0047] The beneficial effects of adopting the above-mentioned further solution are that, according to the current working mode of the device, the first chip is controlled to perform targeted distribution of the decoupled video data stream. In the self-loop mode, the original video data stream is sent directly to the second chip, bypassing the video codec module, reducing the image quality attenuation and transmission delay caused by multi-level signal processing, and completely preserving the characteristics of the original video signal, which facilitates accurate verification of whether the input and output hardware links are intact. In the decoding mode, the data stream is sent to the video codec module for standardized decoding processing, which can provide a regular and clean video source for back-end business output, ensuring smooth and clear display. The two data streams are split on demand through the first chip, with a simple path and less signal interference. One set of hardware can be compatible with both debugging self-test and normal business output scenarios, with strong hardware reusability, effectively reducing the overall hardware design cost.

[0048] Furthermore, the control of the second chip to perform a two-way video stream input specifically includes: the video processing module configuring the input selection switch built into the second chip to switch the video data stream receiving source of the second chip. The LT8641uxe is a multi-input HDMI output converter chip with an integrated programmable input selection switch. The hardware provides two independent video input ports, which respectively connect to the raw video data stream directly transmitted from the LT86102 and the video data stream processed by the video encoding / decoding module. The video processing module establishes register communication with the LT8641uxe via the I2C bus, and issues corresponding configuration commands according to the current operating mode of the entire device to rewrite the conduction channel of the input selection switch, thereby dynamically switching the video data stream receiving source of the chip.

[0049] The advantages of adopting the above-mentioned further solution are that by configuring the input selection switch built into the second chip through the video processing module to switch the input source of the video data stream, the internal selection of the two video sources is completed through the chip's native hardware, eliminating the need for additional external analog switches and discrete signal switching components. This simplifies the external PCB wiring and reduces signal attenuation and electromagnetic interference caused by multi-stage conversion. This control logic can work in conjunction with the front-end signal splitter chip to receive the original direct video data stream and the encoded / decoded post-processed video data stream in a time-division multiplexing manner, and share the same set of output circuits for external output. This achieves hardware multiplexing of the two service links, reducing material costs and saving main control pin resources. At the same time, mode switching is completed by hardware switches, with fast response speed, and the video output signal is stable and continuous in both working modes.

[0050] Furthermore, when the device is in video loop-through output mode, the second chip receives the raw video data stream from the first chip and outputs it externally; when the device is in video decoding output mode, the second chip receives the video data stream processed by the video encoding and decoding module and converts it into a video stream for external output.

[0051] The beneficial effects of adopting the above-mentioned further solution are that when the device switches to the video loop-out output mode, the second chip directly receives the complete original video data stream output by the first chip and outputs it externally, completely preserving the original signal without secondary processing loss. This allows for direct verification of the integrity of the entire hardware transmission link. When the device switches to the video decoding output mode, the second chip receives the video data regulated by the video encoding and decoding module and converts it into a standard video stream for output, adapting to various external display terminals. Both modes share the same second chip and the same external output interface, eliminating the need to configure two separate sets of output hardware. This reduces the material costs of chips, connectors, and PCB wiring, lowering the overall hardware cost. The front and rear chips are synchronously controlled and switched by the video processing module, resulting in rapid path switching response and less signal transfer interference. A single hardware architecture simultaneously accommodates two usage scenarios: hardware debugging and self-testing, and routine video service output. This significantly improves the device's integration and versatility.

[0052] Furthermore, powering on the video processing device includes: connecting the video processing device to a power socket and connecting it to the debugging and maintenance port to supply DC12V power to the device.

[0053] The beneficial effect of adopting the above-mentioned further solution is that by using a unified DC12V power supply and a corresponding debugging and maintenance port for synchronous power-on, it can stably ensure that the equipment's working power supply and standby power supply are synchronously and reliably powered on, providing a stable operating voltage for core video processing chips such as LT86102, LT8641uxe, and CPU, avoiding video path switching failures caused by abnormal voltage. At the same time, the debugging and maintenance port can output the equipment power-on log in real time, which makes it easier for developers to quickly judge the overall power-on status, promptly troubleshoot power supply and hardware link anomalies, and improve the efficiency of equipment debugging and fault diagnosis.

[0054] Preferably, the complete execution flow is as follows: Connect the device to the power socket, connect the debugging and maintenance port, connect the whole machine to a stable DC 12V power supply, and power on the video processing module, LT86102, LT8641uxe, and video codec module in sequence. Print the power-on log through the debugging and maintenance port to confirm that the hardware power supply is normal.

[0055] The video processing module has a built-in CPU that can acquire the mode selection signal level in real time. If the detected level is 0, it is determined that the video self-loop output mode has been entered. The CPU sends a control command to the video interface 1-to-2 circuit composed of LT86102 to establish a direct self-loop path. If the detected level is 1, it is determined that the video decoding output mode has been entered. A command is sent to switch the input channel to the video encoding and decoding module.

[0056] The CPU configures the internal multiplexer of the LT86102 via the I2C bus to route the video data stream after decoupling from the input HDMI signal: in loopback mode, the data stream is directly forwarded to the LT8641uxe; in decoding mode, the data stream is forwarded to the video codec module to complete decoding and format conversion.

[0057] The CPU synchronously configures the LT8641uxe's ​​internal input selection switch to switch the data receiving source: in loopback mode, it receives the raw data stream from the LT86102 and directly outputs the HDMI image; in decoding mode, it receives the video stream processed by the encoding / decoding module, re-encodes it, and converts it into a standard HDMI signal for external output.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for video self-loop output and video decoding output interface compatibility, characterized in that, Includes the following steps: Power on the video processing equipment; The video processing module of the video processing equipment detects and identifies the mode selection signal, where a mode selection signal of 0 corresponds to the video self-loop output mode, and a mode selection signal of 1 corresponds to the video decoding output mode. The video processing module configures the first chip based on the identified mode selection signal, controls the first chip to complete the two-to-one output of the video stream, and sends the video data stream output by the first chip to the second chip or to the video encoding and decoding module for processing. The video processing module configures the second chip based on the identified mode selection signal and controls the second chip to complete the two-to-one input of the video stream. The second chip receives the raw video data stream directly transmitted by the first chip or receives the video data stream processed by the video codec module.

2. The method for video self-loop output and video decoding output interface compatibility according to claim 1, characterized in that, The first chip and its peripheral circuits form a video interface splitter circuit, which includes a video input channel, a video loopback output channel, and a video output channel.

3. The method for compatible video self-loop output and video decoding output interfaces according to claim 2, characterized in that, The video processing module of the video processing device detects and identifies the mode selection signal by: when the video processing module identifies the mode selection signal as 0, sending a control command to the video interface splitter circuit to establish a video loopback path; when the video processing module identifies the mode selection signal as 1, sending a control command to the video interface splitter circuit to connect the video data stream to the decoding link.

4. The method for compatible video self-loop output and video decoding output interfaces according to claim 3, characterized in that, The establishment of the video self-loop path includes: connecting the video input channel and the video self-loop output channel, wherein the input video data stream does not pass through the video encoding and decoding module and is directly output in a loop.

5. The method for video self-loop output and video decoding output interface compatibility according to claim 3, characterized in that, The step of connecting the video data stream to the decoding link includes: switching the video input channel to the video encoding / decoding module, and then transmitting the input video data to the video output channel after processing by the video encoding / decoding module.

6. The method for compatible video self-loop output and video decoding output interfaces according to claim 1, characterized in that, The control of the first chip to complete the two-way video stream output specifically includes: the video processing module configuring the multiplexer inside the first chip to perform routing selection on the video data stream after decoupling from the first chip.

7. The method for video self-loop output and video decoding output interface compatibility according to claim 1, characterized in that, When the device is in video loop-through output mode, the first chip is controlled to directly transmit the decoupled video data stream to the second chip; when the device is in video decoding output mode, the first chip is controlled to transmit the decoupled video data stream to the video encoding / decoding module for decoding processing.

8. The method for video self-loop output and video decoding output interface compatibility according to claim 1, characterized in that, The control of the second chip to complete the two-way input of video stream specifically includes: the video processing module configuring the input selection switch built into the second chip to switch the video data stream receiving source of the second chip.

9. The method for video self-loop output and video decoding output interface compatibility according to claim 1, characterized in that, When the device is in video loop-through output mode, the second chip receives the raw video data stream from the first chip and outputs it externally; when the device is in video decoding output mode, the second chip receives the video data stream processed by the video encoding and decoding module and converts it into a video stream for external output.

10. The method for video self-loop output and video decoding output interface compatibility according to claim 1, characterized in that, Powering on the video processing equipment includes: connecting the video processing equipment to a power socket and connecting it to the debugging and maintenance port to supply DC12V power to the equipment.

Images