A dual mode gain control system and method for a framing camera

Abstract

The application belongs to the technical field of photoelectric imaging, and specifically discloses a dual-mode gain control system and method for a framing camera, which comprises a reference voltage module, a plurality of high-voltage conversion modules, a voltage detection module, a control module, a plurality of fine adjustment modules and an image acquisition module. The reference voltage module generates a common reference control voltage. The high-voltage conversion modules respectively convert the reference voltage into MCP working voltages of corresponding channel image intensifiers. The voltage detection module collects the MCP voltages of the channels and outputs feedback. The control module is internally provided with a plurality of PID controllers, generates an adjusting amount according to the feedback and a target deviation, and controls the fine adjustment modules to independently fine tune the output voltages of the high-voltage conversion modules of the channels. The image acquisition module acquires response images of the channels under standard excitation. The control module has two modes, i.e., a calibration mode and a closed-loop mode. In the calibration mode, the voltage is iteratively compensated according to the consistency deviation of the response images, and the target value is updated. In the closed-loop mode, the PID is controlled by the target value to maintain the consistency of the voltages of the channels. The application can improve the consistency of the gains of the channels of the multi-channel framing camera.

Description

Technical Field

[0001] This application belongs to the field of optoelectronic imaging technology, and more specifically, relates to a dual-mode gain control system and method for a framing camera. Background Technology

[0002] A 4-frame camera achieves nanosecond-level time-resolved transient recording by simultaneously imaging with multiple image intensifiers. A typical 4-frame camera system includes four image intensifiers, four CMOS cameras, and a corresponding optical beam splitter system. In existing technology, the gain control of the four image intensifiers suffers from the following problems: Due to differences in the manufacturing process of MCPs (microchannel plates) (channel diameter, length, secondary electron emission coefficient, etc.), even when the same microchannel plate voltage is applied, the actual gain of the four image intensifiers varies by 10% to 20%; simultaneously, the four independent high-voltage power supplies experience temperature drift (50~100 ppm / °C) and load variations, resulting in voltage deviations of 1% to 2% after prolonged operation, corresponding to gain deviations of 7% to 18%. Both of these problems lead to inconsistent brightness across the four frame images.

[0003] Therefore, how to achieve consistency in the gain of each channel in a multi-channel image intensifier framing camera is a problem that urgently needs to be solved. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide a dual-mode gain control system and method for a framing camera, which can achieve the consistency of gain of each channel of a multi-channel image intensifier framing camera.

[0005] To achieve the above objectives, in a first aspect, this application provides a dual-mode gain control system for a framing camera, the system comprising multiple imaging channels, each imaging channel including an image intensifier, comprising: The reference voltage module is used to generate a common reference control voltage to establish a unified basic level for each imaging channel; Multiple high-voltage conversion modules, each corresponding to an imaging channel, are used to convert the reference control voltage into the microchannel plate operating voltage of the image intensifier of that channel. The voltage detection module is used to collect the actual voltage of the microchannel plate in each imaging channel and output the corresponding feedback quantity. The control module has multiple built-in PID controllers, each corresponding to an imaging channel, which is used to generate adjustment based on the deviation between the feedback value of the channel and the target value. Multiple fine-tuning modules, each corresponding to an imaging channel, are used to independently fine-tune the output voltage of the high-voltage conversion module of that channel in response to the adjustment amount of that channel; The image acquisition module is used to acquire the response images of each imaging channel under standard excitation; The control module has a calibration mode and a closed-loop control mode: In calibration mode, the control module iteratively back-calculates the voltage compensation amount required for each imaging channel based on the consistency deviation of the response image of each imaging channel, and updates the target value of each imaging channel according to the iteration result; In closed-loop control mode, the control module uses the updated target value as the control target of each PID controller to maintain the consistency of the microchannel plate voltage of each imaging channel.

[0006] As a further preferred embodiment, the PID controller has a control cycle of 1ms and adjusts the control frequency based on the feedback value. With target value deviation Calculate the adjustment amount, the deviation The formula for calculation is: = -

[0007] The adjustment amount The positional PID algorithm is used for calculation, and the formula is as follows:

[0008] in, This refers to the imaging channel number. For proportional gain, For integral gain, For differential gain, This represents the deviation from the previous control cycle; When the adjustment amount Δ When the preset limit value is reached, the PID controller pauses integral accumulation.

[0009] As a further preferred embodiment, in calibration mode, the control module drives the image acquisition module to synchronously acquire multiple frames of images from each imaging channel under standard excitation, and calculates the average grayscale value of the region of interest in each channel image. The calculation formula is: Where M×N is the number of pixels in the region of interest. The coordinates in the i-th channel image The pixel grayscale value at that location; The average of the grayscale values ​​of all channels As a benchmark, the calculation formula is: = ,in , , , This corresponds to the average grayscale value of each channel; Calculate the deviation of each channel The calculation formula is: = ； when deviation When the absolute value of the difference from the value 1 is greater than or equal to 2%, the control module reverse-calculates the microchannel board voltage compensation amount for that channel and adjusts the output voltage of the corresponding high-voltage conversion module through the fine-tuning module. After waiting for the voltage to stabilize, the image is re-acquired, and the above process is repeated until all channels are | - 1 | Less than 2%.

[0010] As a further preferred embodiment, the control module stores a gain voltage mapping table for each imaging channel. The gain voltage mapping table is generated by calibrating each channel in a preset voltage step within the rated operating voltage range of the microchannel board and by using piecewise linear interpolation. The gain voltage mapping table includes a forward table and a reverse table. The forward table uses the microchannel plate voltage as the reference. Output gain value for index The inverted table uses the gain value To index the output microchannel board voltage value ; In calibration mode, the control module adjusts the calibration parameters based on the deviation. The target voltage of each imaging channel is calculated by reverse-engineering the reverse table. The formula for calculating the target voltage is:

[0011] in, It is a reverse mapping function. The current gain value of the channel is given; the control module determines the voltage compensation amount based on the difference between the target voltage and the current voltage.

[0012] As a further preferred embodiment, an overexposure protection module is also included. This module comprises a dual-redundant photoelectric detection unit and a high-speed comparator. The dual-redundant photoelectric detection unit is located at the incident end of the image intensifier and is used to convert light signals into electrical signals. The input of the high-speed comparator is connected to the output of the dual-redundant photoelectric detection unit, and is used to directly shut down the gating of the microchannel board via hardware bypass when the illuminance exceeds a preset threshold, with a shutdown time of less than 50 ns. The output of the dual-redundant photoelectric detection unit is judged by the high-speed comparator and then subjected to AND logic determination; protection is triggered only when both photoelectric detection units confirm that the illuminance exceeds the limit. The control module has a built-in three-level protection state machine, including a normal state, a warning state, and a dangerous state. When the dual-redundant photoelectric detection unit detects that the illuminance exceeds the first threshold and the duration exceeds a preset time, the state machine switches from the normal state to the warning state, and the control module reduces the microchannel board voltage. When the illuminance exceeds the second threshold or the high-speed comparator is triggered, the state machine switches from the warning state to the dangerous state, and the control module shuts down the microchannel board gating through hardware bypass. When the illuminance drops below the hysteresis value of the second threshold and the duration exceeds a preset time, the state machine switches to the recovery state and gradually recovers to the normal state.

[0013] As a further preferred embodiment, the voltage detection module includes multiple voltage divider sampling networks and a four-channel synchronous analog-to-digital converter. Each voltage divider sampling network is connected to the output terminal of a high-voltage conversion module. The input terminal of the four-channel synchronous analog-to-digital converter is connected to the output terminal of each voltage divider sampling network, and is used to synchronously acquire the analog feedback voltage of each channel and convert it into a digital quantity for output to the control module.

[0014] As a further preferred embodiment, the high-voltage conversion module includes a push-pull converter and a linear adjustment transistor. The push-pull converter is used to boost the input DC voltage to the DC bus voltage. The linear adjustment transistor is connected between the output terminal of the push-pull converter and the power supply terminal of the image intensifier microchannel board, and is driven by an error amplifier to stabilize the DC bus voltage to the microchannel board operating voltage corresponding to the reference control voltage.

[0015] As a further preferred embodiment, the fine-tuning module includes a digital-to-analog converter, an attenuation operational amplifier, and a superimposed resistor. The output terminal of the digital-to-analog converter is connected to the input terminal of the attenuation operational amplifier, and the output terminal of the attenuation operational amplifier is connected to the non-inverting input terminal of the error amplifier in the corresponding high-voltage conversion module through the superimposed resistor, so as to superimpose the adjustment amount onto the control terminal of the high-voltage conversion module in the form of a voltage.

[0016] As a further preferred embodiment, the image acquisition module includes a standard uniform light source and multiple cameras. The standard uniform light source is positioned in front of the incident window of the framing camera to provide uniform illumination. Each camera corresponds to an imaging channel, which is used to synchronously acquire the response images of each channel when the standard uniform light source is turned on and output them to the control module.

[0017] Secondly, this application provides a dual-mode gain control method for a framing camera, employing the system described in any one of the above-mentioned methods, comprising the following steps: A common reference control voltage is generated by the reference voltage module, and then converted into the microchannel plate operating voltage of the image intensifier of each imaging channel by multiple high voltage conversion modules. The voltage detection module collects the actual voltage of the microchannel plate of each imaging channel and outputs the corresponding feedback quantity to the control module. The control module uses a 1ms control cycle and generates adjustment amounts based on the deviation between the feedback amount of each channel and the target value through multiple PID controllers. The output voltage of each high-voltage conversion module is independently fine-tuned through multiple fine-tuning modules to form a closed-loop negative feedback control. In calibration mode, the image acquisition module acquires the response images of each imaging channel under standard excitation. The control module calculates the consistency deviation of the response images of each channel, iteratively back-calculates the voltage compensation amount required for each imaging channel based on the consistency deviation, and updates the target value of each channel. In closed-loop control mode, the control module uses the updated target value as the control target of each PID controller to maintain the consistency of the microchannel plate voltage of each imaging channel.

[0018] The beneficial effects of this application are as follows: (1) A unified basic level is established for each channel by using a common reference voltage module, and the output voltage of each high voltage conversion module is independently fine-tuned by combining the independent fine-tuning modules of each channel. At the same time, the voltage compensation amount is iteratively back-calculated based on the consistency deviation of the response image of each channel by the calibration mode of the control module and the target value of each channel is updated. In the closed-loop control mode, the updated target value is used as the control target of each PID controller. This effectively solves the problems of inconsistent actual gain of each channel due to the difference in the manufacturing process of the microchannel board and voltage deviation due to the temperature drift of the high voltage power supply and the load change in the prior art. It realizes the consistency of gain of each channel of the multi-channel frame camera and the balance of image brightness. (2) A dual-layer control architecture combining a shared high-precision digital-to-analog converter and multiple independent fine-tuning digital-to-analog converters was adopted to achieve high-precision equalization of MCP voltage ±1mV, with corresponding gain consistency of less than ±1% and image grayscale consistency of less than ±2%; (3) It achieves fully automatic calibration and operation without manual intervention. The calibration parameters are automatically loaded when the machine is turned on, and the protection state is automatically entered when there is an abnormality. (4) By adopting dual redundant photoelectric detection combined with hardware bypass fast shutdown mechanism, the overexposure protection response time is less than 50ns, and the system reliability is improved. Attached Figure Description

[0019] Figure 1 This is a global architecture diagram of the 4-channel framing camera dual-mode gain control system provided in an embodiment of this application; Figure 2 This is a block diagram of the negative feedback closed-loop control of MCP voltage real-time equalization control provided in the embodiments of this application. In the figure, the solid line represents the forward path and the dashed line represents the feedback path. Figure 3This is a diagram of the high-voltage module topology and voltage divider sampling circuit provided in the embodiments of this application; Figure 4 This is a state machine diagram of the calibration process provided in an embodiment of this application; Figure 5 This is a comparison curve of the voltage deviation of the four MCP voltages before and after the real-time equalization mode is turned on, provided in the embodiments of this application; Figure 6 This is the convergence curve of the four-way grayscale deviation during the automatic calibration mode iteration process provided in the embodiments of this application; Figure 7 This is a timing diagram for protection against sudden strong light provided in an embodiment of this application; wherein, (a) is a system architecture block diagram and (b) is a timing comparison diagram; Figure 8 This is a waveform diagram of an MCP turn-off time of less than 50ns provided in the embodiments of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] This application provides a dual-mode gain control system for a frame-segment camera, including a real-time MCP voltage equalization subsystem for mode A and an automatic gain consistency calibration subsystem for mode B, as well as an overexposure protection subsystem integrated therein.

[0022] The MCP real-time voltage equalization subsystem in Mode A includes: a shared high-precision DAC module for outputting a unified reference control voltage for the four high-voltage modules; and four independent high-voltage modules for... Converts to MCP voltage from 0 to 1000V; a 4-channel voltage divider sampling network (1:199) is used to reduce the MCP high voltage to a feedback voltage of 0 to 5V. 4-channel synchronous ADC (ADS131M04, 24-bit), used for synchronous sampling of 4 channels. The FPGA control core incorporates four independent PID controllers to calculate voltage deviations in each channel and output fine-tuning control values; it also includes four 16-bit fine-tuning DACs to output compensation voltage ΔV to the fine-tuning terminals of each high-voltage module. The FPGA control core is configured to receive four... The digital quantity is used to calculate the deviation from the target voltage, and the PID algorithm outputs four independent fine-tuning quantities ΔV to form a closed-loop negative feedback control.

[0023] The automatic gain consistency calibration subsystem for Mode B includes: a standard uniform light source module for providing uniform illumination, positioned in front of the incident window of the framing camera; four CMOS cameras for synchronously acquiring images from the standard light source; an FPGA image processing module for calculating the gray-scale mean values ​​G1 to G4 of the ROI regions in the four images; a calibration algorithm module for inferring the MCP voltage compensation amount based on the gray-scale deviation, iterating to ensure that the gray-scale mean deviation of the four images is less than 2%; and a non-volatile memory (EEPROM) for storing the calibration parameter set. The calibration system is linked to the real-time equalization subsystem, and the calibration results are used to update the reference parameters for real-time equalization.

[0024] Regarding the dual-mode collaborative control logic, the FPGA control core is equipped with a mode selection switch: during normal imaging, it operates in mode A (real-time equalization), with a control cycle of less than 1ms; during power-on self-test or periodic maintenance, it operates in mode B (automatic calibration), typically taking about 5s; after replacing the image tube, the complete calibration process is re-executed.

[0025] The overexposure protection subsystem includes: a dual-redundant photoelectric detection module (PD+TIA) located at the incident end of the image intensifier; a high-speed comparator (TLV3501) with a response time of less than 50ns, which directly shuts down the MCP gate via hardware bypass; and an FPGA state machine configured with three protection levels (Normal→Warning→Danger→Recovery). The overexposure protection subsystem shares the FPGA control core with the gain control subsystem, automatically pausing gain adjustment and prioritizing protection in case of an anomaly.

[0026] Compared with the prior art, the beneficial effects of this application include: (1) Dual-mode complementarity: real-time equalization solves the voltage drift problem, automatic calibration solves the MCP process difference problem, and the two complement each other to achieve full-link gain consistency; (2) High precision: MCP voltage consistency is ±1mV, corresponding to gain consistency of less than ±1%; image grayscale consistency is less than ±2%; (3) Fully automatic: no manual intervention is required, calibration parameters are automatically loaded when the machine is turned on, and abnormalities are automatically protected; (4) High reliability: dual redundant detection plus hardware fast protection improves system reliability.

[0027] The following are specific embodiments provided in this application: (1) System hardware architecture This embodiment uses a 4-channel split-frame camera system as an example for illustration.

[0028] Reference Figure 1 The 4-channel split-frame camera dual-mode gain control system includes optical links, detection links, control links, and execution links.

[0029] In the optical link, the incident light is split into 4 paths by a beam splitter (98:2 splitting ratio), which enter 4 image intensifiers (including photocathode, MCP and phosphor screen) respectively, and then through relay optics, finally reach 4 CMOS sensors.

[0030] In the detection chain, 2% of the sampled light passes through a dual-redundant PD (main detection + redundant detection) → TIA transimpedance amplifier → low-pass filter → 4-channel synchronous ADC.

[0031] In the control link, the FPGA control core (Zynq-7000) integrates three major functional modules: (a) overexposure protection module (high-speed comparator interrupt + state machine); (b) MCP voltage equalization module (4-channel PID controller); (c) gain calibration module (image grayscale calculation + LUT generation).

[0032] In the execution chain: (a) the electronic gating uses a high-speed MOSFET to turn off the high voltage of the MCP cathode, with a response of less than 50ns; (b) the high voltage fine-tuning uses 4 independent fine-tuning DACs (16bit), with a resolution of less than 0.5mV.

[0033] (2) Mode A: MCP voltage real-time equalization (a) Shared DAC reference source design The high-precision DAC uses the AD5791 (20-bit, ±1 LSB INL, ±0.05 ppm / °C temperature drift), whose reference voltage is provided by an LTZ1000 ultra-stable reference source of 5.00000V, buffered by an ADR4550 and input to the REFP / REFN pins of the AD5791. The output of the AD5791 is filtered by a second-order active low-pass filter. = 10Hz, ADA4522 buffer) to eliminate quantization noise, then through precision operational amplifier (OPA189, low noise) It drives 4 high-voltage modules.

[0034] DAC output Range 0~5V, corresponding to MCP voltage 0~1000V, theoretical resolution: ΔV = The theoretical resolution at the MCP end is approximately 0.95mV after being amplified 200 times by the high-voltage module, with a voltage of approximately 4.77μV.

[0035] (b) High-voltage module topology design Each high-voltage module adopts a hybrid architecture of push-pull DC-DC boost and linear regulation, such as Figure 3 As shown. The front-end push-pull converter (switching frequency 100kHz, transformer turns ratio 1:50) boosts the +12V input to 1200V, which is then rectified by a voltage doubler to obtain approximately 1200V DC bus. The rear-end linear regulator (IRFBG30, = 1000V, = 5.5Ω) Driven by an error amplifier (OPA189), the 1200V bus voltage is regulated to 0~1000V output. The regulating tube operates in the linear region, and the output ripple is less than 10m. .

[0036] Regarding the feedback network, the high-voltage output is obtained after a 1:199 voltage divider. (0~5V), inverting input of the input error amplifier; shared with the DAC The input to the non-inverting input forms a local voltage closed loop. The ΔV of the fine-tuning DAC is superimposed on the non-inverting input of the error amplifier via a 10kΩ resistor, achieving global fine-tuning.

[0037] (c) Design of voltage divider sampling network The voltage divider network uses a high-precision metal glass glaze resistor (R1 = 19.9MΩ, accuracy 0.1%, temperature drift 25ppm / °C, withstand voltage 3kV) in series with a metal film resistor (R2 = 100KΩ, accuracy 0.1%, temperature drift 15ppm / °C). Voltage divider ratio. .

[0038] Regarding protection design: (i) A Zener diode (1.2V) is connected in parallel between R1 and R2 to prevent... Overvoltage damages the ADC; (ii) a 10kΩ current-limiting resistor and a TVS diode (1.5V) are connected in series at the input. For temperature compensation, a matching resistor is used to... (The temperature drift coefficients are similar), the overall temperature drift is less than 50 ppm / °C, and the partial pressure ratio change is less than 0.25% within the working range of 0~50°C.

[0039] (d) ADC synchronous sampling timing The ADC uses an ADS131M04 (24-bit, Δ-Σ, 4-channel synchronous sampling), with key parameters including: sampling rate 32kSPS / ch; input range ±1.2V (differential); INL: ±2 ppm; inter-channel crosstalk less than -120dB.

[0040] In the synchronous sampling mechanism, all four channels use the same clock (SCLK=8MHz) and start signal (START) to ensure that all four channels... The time difference is frozen at the same moment to eliminate measurement errors.

[0041] The sampling timing is as follows: (i) The FPGA sends a START pulse (width greater than 2 SCLK cycles); (ii) The 4 modulators inside the ADC start integration simultaneously; (iii) After 3 conversion cycles (approximately 93μs@32kSPS), DRDY goes low; (iv) The FPGA reads 4 channels of 24-bit data via SPI; (v) The above process is repeated, and 4 channels are sampled synchronously every 1ms.

[0042] (e) FPGA PID algorithm implementation The PID algorithm is implemented in the FPGA as a fixed-point number (24-bit signed integer) with a control cycle of 1ms.

[0043] Deviation calculation: = - ,in The calibration results are provided by the calibration system (Mode B results) or set directly by the host computer.

[0044] PID output (positional):

[0045] Parameter tuning: = 0.5 (proportional gain, fast response); = 0.01 (Integral gain, to eliminate steady-state error, accumulated every 1ms); =0.001 (differential gain, suppressing overshoot).

[0046] Regarding resistance to integral saturation, when Δ When the fine-tuning DAC reaches full scale (±5V corresponds to ±10mV MCP voltage), integration is paused to prevent saturation oscillation. Regarding output limiting, Δ... Limited to ±10mV (MCP end), corresponding to a fine-tuned DAC output of ±50mV.

[0047] (f) Fine-tuning DAC output design The fine-tuning DAC uses a DAC8564 (16-bit, 4-channel, SPI interface) with an output range of 0~5V. The output is attenuated to 0~1V by a precision operational amplifier (OPA189, gain=0.2) and then superimposed to the non-inverting input of the high-voltage module error amplifier through a 10kΩ resistor.

[0048] Resolution calculation: fine-tuning = The voltage is approximately 76.3 μV, which is attenuated by 0.2 times to 15.3 μV. When superimposed on the high-voltage module (gain 200 times), it is 3.05 mV (MCP end). The actual effective resolution is approximately 1 mV, which meets the ±1 mV control target.

[0049] (g) Closed-loop bandwidth and stability The system open-loop transfer function is ,in = 200 (high voltage module gain). = 1 (Local closed loop has been compensated). = (Voltage divider network) = 1 (digital normalization). Variable (determined by PID parameters) = 200 (fine-tune DAC → high voltage module gain).

[0050] The closed-loop bandwidth is approximately 100Hz (determined by the PID integral time constant), significantly higher than the MCP voltage drift rate (less than 1Hz), ensuring steady-state tracking accuracy. The phase margin is greater than 45° (through...). (Differential term compensation), the system is stable and oscillates-free.

[0051] Figure 2 The negative feedback closed-loop control path of Mode A is shown in detail, including the setting terminal (G_target target gain setting → common reference DAC AD5791 output). The system includes a high-voltage output terminal (4 independent high-voltage modules 0~1000V → MCP1~MCP4), a feedback sampling terminal (4 voltage divider network 1:199 → 4-channel synchronous ADC ADS131M04), a control terminal (FPGA 4 independent PID controllers), and a feedback terminal (4 fine-tuning DAC 16bit → ΔV1~ΔV4 feedback to the high-voltage module fine-tuning terminal).

[0052] (3) Mode B: Automatic Gain Consistency Calibration (a) Trigger calibration Calibration trigger conditions include: power-on self-test, regular maintenance (every 24 hours), and replacement of the image tube.

[0053] (b) Initialization FPGA turns on a standard uniform light source and sets the initial MCP voltage. = 600V.

[0054] (c) Image acquisition Simultaneously trigger 4-channel CMOS exposure, acquire N=10 frames of images, and transmit them to the FPGA DDR buffer.

[0055] (d) Gray-scale calculation The FPGA reads image data and calculates the average grayscale value of each ROI region (center 80% region, excluding edge vignetting): ,in =1,2,3,4, M×N is the number of ROI pixels.

[0056] (e) Deviation Calculation Calculate the average grayscale of the 4 channels: = Calculate the deviation for each channel: = .

[0057] (f) Voltage compensation calculation Check the gain-voltage LUT (factory calibrated, stored in FPGA BRAM): = f( ). Calculate the target voltage:

[0058] Calculate the fine-tuning amount: Δ = - .

[0059] Regarding the construction of the gain-voltage LUT, a voltage-point step scanning method is adopted. Within the rated operating voltage range of the MCP (400V~1000V), discrete calibration nodes are set in 10V steps, totaling 61 calibration nodes across the entire range. For the low-voltage segment (400V~600V) with strong gain nonlinearity, the step size is increased to 5V to improve the lookup accuracy in the low-gain range. At each voltage node, after the high-voltage power supply stabilizes for 100ms, the actual voltage value at the MCP terminal is acquired using a 6.5-digit high-precision digital voltmeter to correct the inherent output deviation of the high-voltage module. Based on the voltage-gain data from the discrete calibration nodes, a piecewise linear interpolation algorithm is used to generate a continuous gain-voltage mapping table with a resolution of 1mV. The LUT adopts a bidirectional index structure: the forward table uses the MCP voltage as the index and outputs the corresponding relative gain value; the reverse table uses the relative gain value as the index and outputs the corresponding MCP voltage value. The four image intensifiers correspond to four independent LUTs, which are stored in independent address spaces of the FPGA BRAM to avoid data crosstalk between channels.

[0060] (g) Iterative convergence judgment If all | - 1.0|<2%, proceed to step (h); otherwise, apply Δ Wait 10ms for the voltage to stabilize, then return to step (c). The typical number of convergence attempts is 3 to 5, and a single calibration takes about 5 seconds.

[0061] (h) Storing LUTs The calibration parameters are written into the EEPROM, and the parameter group structure is shown in Table 1.

[0062] Table 1 EEPROM calibration parameter group data structure

[0063] The CRC check adopts the CRC-16 / CCITT-FALSE standard algorithm, adapted to the parallel implementation of FPGA hardware logic. The specific parameters and calculation rules are as follows: (i) Generator polynomial G(x)=x¹ 6 +x¹²+x 5 +1 corresponds to the hexadecimal value 0x1021; (ii) initial value 0xFFFF; (iii) input rule: input in MSB first order, without bit reversal; (iv) output rule: no final XOR processing, directly output 16-bit check value. During calibration writing, the FPGA first calculates the CRC16 value of the first 14 bytes, and then writes the check value to the address 0x0E~0x0F; during parameter loading, the first 14 bytes are read again to calculate the CRC, and compared with the stored check value. If they match, the check is considered successful.

[0064] The backup handling procedure after verification failure is as follows: (i) Read retry: Automatically reread the complete parameter block of the corresponding address of EEPROM, retrying up to 3 times to eliminate occasional verification failures caused by I2C communication interference and reading timing errors; (ii) Degrade and load default parameters: If the verification still fails after 3 retries, it is determined that the calibration parameters are corrupted, and the FPGA automatically loads the factory-preset default parameter group (V_base is set to the typical operating voltage of 600V, all 4 Delta_V are set to 0, and the calibration valid position is set to 0); (iii) Abnormal status reporting: Set the calibration in the FPGA internal register. (iv) Functional degradation operation: The real-time equalization system (mode A) can still work normally in closed loop, but the 4-channel gain consistency only guarantees voltage level accuracy and does not guarantee image gray level consistency; if the device is connected to a standard uniform light source, it can automatically trigger a complete mode B calibration process to regenerate valid parameters; (v) Safety protection: During the verification failure, it is forbidden to output voltage commands exceeding the rated range to the high voltage module to avoid MCP overvoltage damage to the image intensifier due to incorrect parameters.

[0065] (i) Verify loading Read EEPROM data, verify CRC, load into FPGA BRAM, and update the V_target parameter of real-time equalization.

[0066] Figure 4 The complete state machine flow of Mode B is demonstrated, including 8 states: IDLE (idle standby), INIT (initialization), ACQUIRE (image acquisition), CALC (grayscale calculation), ADJUST (voltage adjustment), CHECK (convergence check), STORE (storage LUT), and DONE (calibration complete). Calibration is triggered by power-on self-test, periodic maintenance, or replacement of the image tube. Figure 5 The curves show the voltage deviation of the four MCP voltages before and after the real-time balancing mode is enabled. Figure 6 This is the convergence curve of the four-channel grayscale deviation during the automatic calibration mode iteration process.

[0067] (4) Overexposure protection implementation method (a) Design of dual-redundant photoelectric detection module The photodiode selected is Hamamatsu S1336-5BQ (silicon PIN, spectral response 320~1100nm, junction capacitance less than 20pF, response time less than 1μs).

[0068] Dual redundancy configuration: (i) Main detection channel: PD1→TIA1 (OPA657, transimpedance gain 1MΩ, bandwidth 100MHz); (ii) Redundant detection channel: PD2→TIA2 (OPA657, transimpedance gain 1MΩ, bandwidth 100MHz).

[0069] The sampling position is a beam splitter (98:2 splitting ratio) placed in front of the image intensifier's incident window, directing 2% of the light energy to the dual photodiodes (PDs). The two PDs are placed at a 90° angle to avoid crosstalk.

[0070] Regarding the interlocking logic, the main detection and redundant detection outputs are compared by a high-speed comparator and then ANDed: protection is triggered only when both channels confirm that the illuminance exceeds the standard, thus preventing single-point false triggering.

[0071] (b) High-speed comparator and threshold setting The high-speed comparator uses the TI TLV3501 (push-pull output, propagation delay 4.5ns, rise time 1.5ns). The threshold source is a precision resistor divider network (R3=10kΩ, R4=1kΩ, temperature drift less than 25ppm / °C), powered by a +5V reference source, generating a 5V threshold voltage, corresponding to an illuminance of approximately 100 lux.

[0072] Comparator inputs: The non-inverting input is the TIA output voltage (proportional to illuminance); the inverting input is the threshold voltage (5V). Output logic: When the TIA output is greater than 5V, the comparator outputs a high level (5V), directly driving the MCP gate shutdown circuit.

[0073] (c) MCP gated shutdown circuit (hardware bypass) The gated circuit uses a PMOS+NMOS complementary switch: (i) PMOS (IRF9Z24N, VDS=-60V, ID=-9.3A) is used for periodic switching in PWM mode; (ii) NMOS (IRFZ24N, VDS=60V, ID=17A) is used for low impedance path in normally open DC mode; (iii) cathode normally open holding resistor R_hold=10MΩ.

[0074] High-speed shutdown path: Comparator output (5V) → Level shifting (opto-isolation + high-speed MOSFET driver) → Directly pull down the gates of PMOS and NMOS → The high voltage at the MCP cathode is cut off in less than 50 ns. This path completely bypasses the FPGA, does not go through ADC sampling and software judgment, and ensures nanosecond-level response.

[0075] (d) Detailed Design of FPGA State Machine State definition: (i) STATE_NORMAL (0x00): Normal operation, MCP gating is turned on; (ii) STATE_WARNING (0x01): Illuminance is greater than 50 lux, reduce MCP gain; (iii) STATE_DANGER (0x02): Illuminance is greater than 100 lux, turn off MCP gating; (iv) STATE_RECOVERY (0x03): Illuminance decreases, perform stepwise recovery.

[0076] The state transition conditions are as follows: NORMAL→WARNING: The condition is (PD1>TH_L1) AND (PD2>TH_L1) AND (duration greater than 100 μs); Action: The FPGA reduces the MCP voltage by 10% and decreases the duty cycle to 50%.

[0077] WARNING→DANGER: The condition is (PD1>TH_L2) OR (PD2>TH_L2) OR (hardware comparator triggered); Action: Immediately turn off MCP gating (the hardware path takes less than 50 ns), and the FPGA records the event.

[0078] DANGER→RECOVERY: The condition is (PD1<TH_L2_HYST) AND (PD2<TH_L2_HYST) AND (duration greater than 50 ms); Action: Restore MCP gating, and finally restore the gain.

[0079] RECOVERY→NORMAL: The condition is that the illuminance of all channels < TH_L1_HYST (80% of TH_L1); Action: Restore normal imaging, and the MCP equalization system restarts.

[0080] Threshold parameters: TH_L1 (warning) is 50 lux (corresponding to a TIA output of 2.5V); TH_L2 (danger) is 100 lux (corresponding to a TIA output of 5V, comparator threshold 5V); Hysteresis window: TH_L1_HYST=0.8×TH_L1, TH_L2_HYST=0.5×TH_L2.

[0081] (e) Coordination with the MCP equilibrium system Automatic pause in case of abnormality: When the state machine enters WARNING or above, the FPGA automatically pauses the PID integral accumulation of the MCP voltage equalization, keeps the current output unchanged, and avoids voltage regulation in the protection state, which may cause system instability.

[0082] Automatic restart after recovery: When the state machine returns to the NORMAL state, the FPGA resumes PID calculations and reloads the calibration parameters from the EEPROM to ensure gain consistency after recovery.

[0083] Figure 7 The system demonstrates the protection timing under sudden strong light. The upper part is a system architecture block diagram (optical link + detection link + protection architecture + FPGA control core + execution output), and the lower part is a timing comparison diagram (the left side is the power-on process, and the right side is the sudden strong light shutdown process, with the time node of electronic gating shutdown less than 50ns marked). Figure 8 The waveform diagram shows the MCP turn-off time of less than 50ns (47.6ns).

[0084] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A dual-mode gain control system for a framing camera, the system comprising multiple imaging channels, each imaging channel including an image intensifier, characterized in that, include: The reference voltage module is used to generate a common reference control voltage to establish a unified basic level for each imaging channel; Multiple high-voltage conversion modules, each corresponding to an imaging channel, are used to convert the reference control voltage into the microchannel plate operating voltage of the image intensifier of that channel. The voltage detection module is used to collect the actual voltage of the microchannel plate in each imaging channel and output the corresponding feedback quantity. The control module has multiple built-in PID controllers, each corresponding to an imaging channel, which is used to generate adjustment based on the deviation between the feedback value of the channel and the target value. Multiple fine-tuning modules, each corresponding to an imaging channel, are used to independently fine-tune the output voltage of the high-voltage conversion module of that channel in response to the adjustment amount of that channel; The image acquisition module is used to acquire the response images of each imaging channel under standard excitation; The control module has a calibration mode and a closed-loop control mode: In calibration mode, the control module iteratively back-calculates the voltage compensation amount required for each imaging channel based on the consistency deviation of the response image of each imaging channel, and updates the target value of each imaging channel based on the iteration result. In closed-loop control mode, the control module uses the updated target value as the control target of each PID controller to maintain the consistency of the microchannel plate voltage of each imaging channel.

2. The dual-mode gain control system for a framing camera as described in claim 1, characterized in that, The PID controller operates on a 1ms control cycle, based on the feedback quantity. With target value deviation Calculate the adjustment amount, the deviation The formula for calculation is: The adjustment amount Δ The positional PID algorithm is used for calculation, and the formula is as follows: in, This refers to the imaging channel number. For proportional gain, For integral gain, For differential gain, This represents the deviation from the previous control cycle; When the adjustment amount Δ When the preset limit value is reached, the PID controller pauses integral accumulation.

3. The dual-mode gain control system for a framing camera as described in claim 1, characterized in that, In calibration mode, the control module drives the image acquisition module to synchronously acquire multiple frames of images from each imaging channel under standard excitation, and calculates the average grayscale value of the region of interest in each channel image. The calculation formula is: Where M×N is the number of pixels in the region of interest. Let be the pixel gray value at coordinates (m, n) in the i-th channel image; The average of the grayscale values ​​of all channels As a benchmark, the calculation formula is: = ,in , , , This corresponds to the average grayscale value of each channel; Calculate the deviation of each channel The calculation formula is: = ; when deviation When the absolute value of the difference from the value 1 is greater than or equal to 2%, the control module reverse-calculates the microchannel board voltage compensation amount for that channel and adjusts the output voltage of the corresponding high-voltage conversion module through the fine-tuning module. After waiting for the voltage to stabilize, the image is re-acquired, and the above process is repeated until all channels are | - 1 | Less than 2%.

4. The dual-mode gain control system for a framing camera as described in claim 3, characterized in that, The control module stores a gain voltage mapping table for each imaging channel. The gain voltage mapping table is generated by calibrating each channel in a preset voltage step within the rated operating voltage range of the microchannel board and by piecewise linear interpolation. The gain voltage mapping table includes a forward table and a reverse table. The forward table uses the microchannel plate voltage as the reference. Output gain value for index The inverted table uses the gain value To index the output microchannel board voltage value ; In calibration mode, the control module adjusts the calibration parameters based on the deviation. The target voltage of each imaging channel is calculated by reverse-engineering the reverse table. The formula for calculating the target voltage is: in, It is a reverse mapping function. The current gain value of the channel is given; the control module determines the voltage compensation amount based on the difference between the target voltage and the current voltage.

5. The dual-mode gain control system for a framing camera as described in claim 1, characterized in that, It also includes an overexposure protection module, which comprises a dual-redundant photoelectric detection unit and a high-speed comparator. The dual-redundant photoelectric detection unit is located at the incident end of the image intensifier and is used to convert light signals into electrical signals. The input end of the high-speed comparator is connected to the output end of the dual-redundant photoelectric detection unit and is used to directly shut down the gating of the microchannel board through hardware bypass when the illuminance is detected to exceed a preset threshold, with a shutdown time of less than 50ns. The output of the dual-redundant photoelectric detection unit is judged by the high-speed comparator and then subjected to AND logic determination. Protection is triggered only when both photoelectric detection units confirm that the illuminance exceeds the standard. The control module has a built-in three-level protection state machine, including a normal state, a warning state, and a dangerous state. When the dual-redundant photoelectric detection unit detects that the illuminance exceeds the first threshold and the duration exceeds a preset time, the state machine switches from the normal state to the warning state, and the control module reduces the microchannel board voltage. When the illuminance exceeds the second threshold or the high-speed comparator is triggered, the state machine switches from the warning state to the dangerous state, and the control module shuts down the microchannel board gating through hardware bypass. When the illuminance drops below the hysteresis value of the second threshold and the duration exceeds a preset time, the state machine switches to the recovery state and gradually recovers to the normal state.

6. The dual-mode gain control system for a framing camera as described in claim 1, characterized in that, The voltage detection module includes multiple voltage divider sampling networks and a four-channel synchronous analog-to-digital converter. Each voltage divider sampling network is connected to the output of a high-voltage conversion module. The input of the four-channel synchronous analog-to-digital converter is connected to the output of each voltage divider sampling network, and is used to synchronously acquire the analog feedback voltage of each channel and convert it into a digital quantity for output to the control module.

7. The dual-mode gain control system for a framing camera as described in claim 1, characterized in that, The high-voltage conversion module includes a push-pull converter and a linear adjustment transistor. The push-pull converter is used to boost the input DC voltage to the DC bus voltage. The linear adjustment transistor is connected between the output terminal of the push-pull converter and the power supply terminal of the image intensifier microchannel board. It is driven by an error amplifier and is used to stabilize the DC bus voltage to the microchannel board operating voltage corresponding to the reference control voltage.

8. The dual-mode gain control system for a framing camera as described in claim 1, characterized in that, The fine-tuning module includes a digital-to-analog converter, an attenuation operational amplifier, and a superimposed resistor. The output of the digital-to-analog converter is connected to the input of the attenuation operational amplifier. The output of the attenuation operational amplifier is connected to the non-inverting input of the error amplifier in the corresponding high-voltage conversion module through the superimposed resistor, so as to superimpose the adjustment amount as a voltage onto the control terminal of the high-voltage conversion module.

9. The dual-mode gain control system for a framing camera as described in claim 1, characterized in that, The image acquisition module includes a standard uniform light source and multiple cameras. The standard uniform light source is positioned in front of the incident window of the frame-mounted camera to provide uniform illumination. Each camera corresponds to an imaging channel, which is used to synchronously acquire the response images of each channel when the standard uniform light source is turned on and output them to the control module.

10. A dual-mode gain control method for a framing camera, employing the system described in any one of claims 1 to 9, characterized in that, Includes the following steps: A common reference control voltage is generated by the reference voltage module, and then converted into the microchannel plate operating voltage of the image intensifier of each imaging channel by multiple high voltage conversion modules. The voltage detection module collects the actual voltage of the microchannel plate of each imaging channel and outputs the corresponding feedback quantity to the control module. The control module uses a 1ms control cycle and generates adjustment amounts based on the deviation between the feedback amount of each channel and the target value through multiple PID controllers. The output voltage of each high-voltage conversion module is independently fine-tuned through multiple fine-tuning modules to form a closed-loop negative feedback control. In calibration mode, the image acquisition module acquires the response images of each imaging channel under standard excitation. The control module calculates the consistency deviation of the response images of each channel, iteratively back-calculates the voltage compensation amount required for each imaging channel based on the consistency deviation, and updates the target value of each channel. In closed-loop control mode, the control module uses the updated target value as the control target of each PID controller to maintain the consistency of the microchannel plate voltage of each imaging channel.

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