Solid-state imaging device

Abstract

Embodiments of the present application provide a solid-state imaging device. The solid-state imaging device includes a pixel array. The pixel array includes N×M pixel units. Each of the N×M pixel units includes at least one pixel. Each pixel unit further includes an amplifier transistor, a floating diffusion node, a selection transistor, and a first capacitor, wherein a gate of the amplifier transistor is coupled to the floating diffusion node, a first terminal of the amplifier transistor is coupled to a power supply voltage, a second terminal of the amplifier transistor is coupled to a first terminal of the selection transistor, a second terminal of the selection transistor is coupled to an output terminal, and the first capacitor is coupled between the floating diffusion node and the second terminal of the amplifier transistor. Due to the Miller effect, the solid-state imaging device provided by the present application can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance.

Description

Technical Field

[0001] This application relates to the field of electronic engineering, and more specifically, to a solid-state imaging device. Background Technology

[0002] Due to the high spatial resolution and small form factor of camera systems, there is a strong need to reduce pixel size. However, small pixel size inherently reduces readout noise performance because the main source of readout noise is the amplifier transistors within the pixel unit, and the noise is inversely proportional to the pixel unit size. Therefore, it is crucial to improve the readout noise generated by the amplifier transistors within the pixel unit. Summary of the Invention

[0003] This application provides a solid-state imaging device that can improve the signal-to-noise ratio of solid-state imaging devices.

[0004] In a first aspect, embodiments of this application provide a solid-state imaging device including a pixel array. The pixel array includes N×M pixel units, where N is a positive integer and M is a positive integer. Each pixel unit includes at least one pixel. Each pixel unit further includes an amplifier transistor, a floating diffusion node, a selection transistor, and a first capacitor, wherein the gate of the amplifier transistor is coupled to the floating diffusion node, a first terminal of the amplifier transistor is coupled to a power supply voltage, a second terminal of the amplifier transistor is coupled to a first terminal of the selection transistor, the second terminal of the selection transistor is coupled to an output terminal, and the first capacitor is coupled between the floating diffusion node and the second terminal of the amplifier transistor.

[0005] For example, when the amplifier transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor, the first terminal of the amplifier transistor is the drain, and the second terminal is the source. When the amplifier transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor, the first terminal is the source, and the second terminal is the drain. Similarly, when the selector transistor is an NMOS transistor, the first terminal is the drain, and the second terminal is the source. When the selector transistor is a PMOS transistor, the first terminal is the source, and the second terminal is the drain.

[0006] Due to the Miller effect, the solid-state imaging device provided in this application can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance. Because the amplifier with a larger width / length (W / L) ratio has a higher transconductance (gm), the frame rate becomes higher compared to conventional configurations at similar readout noise levels.

[0007] In one possible design of the first aspect, each pixel unit further includes a first connection component and a second connection component, wherein the first connection component includes a first wire and at least one first contact, the first contact connecting the gate of the amplifier transistor to the first wire, the first wire being connected to the floating diffusion node; the second connection component includes a second wire and at least one second contact, the second contact connecting the second terminal of the amplifier transistor to the second wire; and the first capacitor is coupled between the first wire and the second wire.

[0008] In one possible design of the first aspect, the at least one first contact is connected to a first segment of the first wire, the first segment of the first wire extending from the at least one first contact along a first direction, a second segment of the first wire extending from the first segment of the first wire along a second direction, a third segment of the first wire extending from the second segment of the first wire along the first direction, and the floating diffusion node is connected to the third segment of the first wire, the first direction being perpendicular to the second direction.

[0009] In one possible design of the first aspect, a fourth segment of the first conductor extends from the first segment of the first conductor along a third direction, wherein the third direction is opposite to the first direction; and / or the second segment of the first conductor includes at least one V-shaped segment.

[0010] This design allows for high capacitance between the floating diffusion node and the first terminal of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0011] In one possible design of the first aspect, the at least one second contact is connected to a first segment of the second wire, the first segment of the second wire extending from the at least one second contact along the first direction, and a second segment of the second wire extending from the first segment of the second wire along the second direction; or the at least one second contact is connected to the first segment of the second wire, the first segment of the second wire extending from the at least one second contact along the second direction.

[0012] This design allows for high capacitance between the floating diffusion node and the first terminal of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0013] In one possible design of the first aspect, the third segment of the second conductor extends from the at least one second contact in a third direction, and / or the second segment of the second conductor includes at least one V-shaped segment.

[0014] This design allows for high capacitance between the floating diffusion node and the first terminal of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0015] In one possible design of the first aspect, the second conductor further includes a covering segment, wherein the at least one first contact and / or the floating diffusion node is covered by the covering segment.

[0016] This design allows for high capacitance between the floating diffusion node and the first terminal of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0017] In one possible design of the first aspect, the second conductor further includes at least one protruding segment, wherein the protruding segment extends from at least one of the other segments of the second conductor.

[0018] This design allows for high capacitance between the floating diffusion node and the first terminal of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0019] In one possible design of the first aspect, each pixel unit further includes: at least one third connection component, wherein the at least one third connection component is stacked on the first connection component; and / or at least one fourth connection component, wherein the at least one fourth connection component is stacked on the second connection component.

[0020] This design allows for high capacitance between the floating diffusion node and the first terminal of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0021] In one possible design of the first aspect, a portion of the conductor of one of the at least three third connecting components is located above a portion of the conductor of one of the at least four fourth connecting components; or a portion of the conductor of one of the at least four fourth connecting components is located above a portion of the conductor of one of the at least three third connecting components.

[0022] This design allows for high capacitance between the floating diffusion node and the first terminal of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0023] In one possible design of the first aspect, each pixel unit further includes a second capacitor, which is a vertical metal-insulator-metal (MIM) capacitor coupled between the wires of the third connection component and the wires of the fourth connection component.

[0024] In one possible design of the first aspect, each pixel unit further includes a shielding component, wherein the shielding component shields the second terminal of the amplifier transistor and the second connection component. The shielding component can improve the voltage stability of the first terminal of the amplifier transistor.

[0025] In one possible design of the first aspect, the shielding component is coupled to a reference node, wherein the reference node is one of the following: a power supply voltage (VDD) node in each pixel unit, a ground voltage (VSS) node in each pixel unit, an output voltage (Vout) node in each pixel unit, the gate of a dual conversion gain transistor in each pixel unit, the gate of a reset transistor in each pixel unit, or the gate of the select transistor in each pixel unit.

[0026] In one possible design of the first aspect, the shielding component is a control row line.

[0027] In one possible design of the first aspect, each pixel unit includes a first active region and a second active region, wherein the amplifier transistor is located in the first active region and the selection transistor is located in the second active region. Due to the Miller effect, this design can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance.

[0028] In one possible design of the first aspect, each pixel unit further includes a fifth connection component and a sixth connection component, wherein the fifth connection component includes a fifth wire and at least one fifth contact, the fifth contact connecting the gate of the amplifier transistor to the fifth wire, and the fifth wire connecting to the floating diffusion node; the sixth connection component includes a sixth wire, at least one sixth contact, and at least one seventh contact, the sixth contact connecting the second terminal of the amplifier transistor to the sixth wire, and the seventh contact connecting the first terminal of the selection transistor to the sixth wire; the first capacitance is coupled between the fifth wire and the sixth wire. Due to the Miller effect, this design can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance.

[0029] In one possible design of the first aspect, each pixel unit further includes a third capacitor, the sixth connection component includes a first segment and a second segment, the first segment being connected to the second terminal of the amplifier transistor via the sixth contact, the second segment being connected to the first terminal of the selection transistor via the seventh contact, the first capacitor being coupled between the first segment and the fifth connection component, and the third capacitor being coupled between the second segment and the fifth connection component.

[0030] In one possible design of the first aspect, at least one of the following components has an additional layer: the second terminal of the amplifier transistor, the first terminal of the amplifier transistor, the channel of the amplifier transistor, or the selection transistor, wherein the additional layer is an n-type layer or a p-type layer. Due to the Miller effect, this design can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance.

[0031] In one possible design of the first aspect, the second terminal of the amplifier transistor is deeper than the first terminal of the amplifier transistor. Due to the Miller effect, this design can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance.

[0032] In one possible design of the first aspect, the amplifier transistor has source / drain sidewalls with high dielectric constant, or there is an interlayer dielectric layer with high dielectric constant between the second terminal of the amplifier transistor and the gate of the amplifier transistor.

[0033] In one possible design of the first aspect, the amplifier transistor has an embedded portion on the channel edge side.

[0034] Secondly, embodiments of this application provide an electronic device. The electronic device includes the solid-state imaging device designed according to the first aspect or any possible design of the first aspect. Attached Figure Description

[0035] Figure 1 A schematic diagram of an electronic device is shown.

[0036] Figure 2 This is a block diagram illustrating an example configuration of a CMOS image sensor according to some embodiments of this application.

[0037] Figure 3 Pixel units according to some embodiments provided in this application are shown.

[0038] Figure 4 It corresponds to Figure 3 The circuit diagram of pixel unit 300 is shown.

[0039] Figure 5 A cross-sectional view of pixel unit 300 is shown.

[0040] Figure 6 The wires and contacts corresponding to capacitor 371 are shown.

[0041] Figure 7 Another possible design for the first conductor is shown.

[0042] Figure 8 Another possible design for the first conductor is shown.

[0043] Figure 9 Another possible design for the second conductor is shown.

[0044] Figure 10 Another possible design for the second conductor is shown.

[0045] Figure 11 Another possible design for the second conductor is shown.

[0046] Figure 12 Another possible design for the second conductor is shown.

[0047] Figure 13 Another possible design for the second conductor is shown.

[0048] Figure 14 The pixel units provided in some embodiments of this application are shown.

[0049] Figure 15 The pixel units provided in some embodiments of this application are shown.

[0050] Figure 16 The pixel units provided in some embodiments of this application are shown.

[0051] Figure 17 The pixel units provided in some embodiments of this application are shown.

[0052] Figure 18 The pixel units provided in some embodiments of this application are shown.

[0053] Figure 19 The pixel units provided in some embodiments of this application are shown.

[0054] Figure 20 The pixel units provided in some embodiments of this application are shown.

[0055] Figure 21 The pixel units provided in some embodiments of this application are shown.

[0056] Figure 22 The pixel units provided in some embodiments of this application are shown.

[0057] Figure 23The pixel units provided in some embodiments of this application are shown.

[0058] Figure 24 The pixel units provided in some embodiments of this application are shown.

[0059] Figure 25 The pixel units provided in some embodiments of this application are shown.

[0060] Figure 26 The pixel units provided in some embodiments of this application are shown.

[0061] Figure 27 The pixel units provided in some embodiments of this application are shown.

[0062] Figure 28 The pixel units provided in some embodiments of this application are shown.

[0063] Figure 29 The pixel units provided in some embodiments of this application are shown.

[0064] Figure 30 The pixel units provided in some embodiments of this application are shown.

[0065] Figure 31 The pixel units provided in some embodiments of this application are shown.

[0066] Figure 32 The pixel units provided in some embodiments of this application are shown.

[0067] Figure 33 An amplifier transistor according to some embodiments of this application is shown.

[0068] Figure 34 An amplifier transistor according to some embodiments of this application is shown.

[0069] Figure 35 An amplifier transistor according to some embodiments of this application is shown.

[0070] Figure 36 An amplifier transistor according to some embodiments of this application is shown.

[0071] Figure 37 An amplifier transistor according to some embodiments of this application is shown.

[0072] Figure 38 An amplifier transistor according to some embodiments of this application is shown.

[0073] Figure 39 An amplifier transistor according to some embodiments of this application is shown.

[0074] Figure 40An amplifier transistor according to some embodiments of this application is shown.

[0075] Figure 41 An amplifier transistor according to some embodiments of this application is shown.

[0076] Figure 42 An amplifier transistor according to some embodiments of this application is shown.

[0077] Figure 43 A cross-sectional view of an image sensor according to some embodiments of this application is shown.

[0078] Figure 44 A schematic diagram of a solid-state imaging device according to an embodiment of this application is shown.

[0079] Figure 45 A block diagram illustrating an exemplary configuration of an imaging device is shown, which is an electronic device to which the present technology is applied.

[0080] Figure 46 An example of the technology of the image sensor applied in this application is shown.

[0081] Figure 47 A block diagram illustrating an exemplary schematic configuration of a vehicle control system is shown. Detailed Implementation

[0082] The technical solution of this application will now be described with reference to the accompanying drawings.

[0083] The terms "first," "second," etc., used below are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated. Therefore, the features defined by "first" and "second" may explicitly or implicitly include one or more features.

[0084] In the embodiments of this application, "at least one" refers to one or more, and "multiple" refers to two or more. The term "and / or" describes the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three cases: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "OR" relationship between associated objects. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of one or more items. For example, at least one of a, b, and c can indicate: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be singular or plural.

[0085] Figure 1 A schematic diagram of an electronic device is shown. (For example...) Figure 1As shown, electronic device 100 can be a terminal device. This terminal device can be a mobile phone, tablet computer, laptop computer, augmented reality (AR) device, virtual reality (VR) device, vehicle terminal, digital camera, digital camcorder, action camera, security camera, etc. Electronic device 100 may include a processor 110, external memory interface 120, internal memory 121, universal serial bus (USB) interface 130, charging management module 140, power management module 141, battery 142, communication module 150, audio module 160, camera module 170, camera lens 171, solid-state imaging device 172, display screen 180, etc. Communication module 150 may include a wireless communication module and / or a mobile communication module.

[0086] It is understood that the illustrative structure of the embodiments of this application does not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, combine some components, split some components, or arrange the components in different ways. For example, if the electronic device 100 is a security camera, it may not include a display screen 180; if the electronic device 100 is a laptop computer, it may also include a keyboard, speakers, microphone, etc. The components shown in the figures can be implemented by hardware, software, or a combination of software and hardware.

[0087] Processor 110 may include one or more processing units. For example, processor 110 may include a general-purpose processor, application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, memory, video codec, digital signal processor (DSP), and / or neural network processing unit (NPU), etc. Different processing units may be independent components or integrated into one or more processors.

[0088] Memory may also be located in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache. The memory may store instructions or data used or cyclically used by the processor 110. If the processor 110 needs to use the instruction or data again, the processor 110 can directly retrieve the instruction or data from the memory to avoid repeated access and reduce the processor 110's waiting time, thereby improving system efficiency.

[0089] In some embodiments, the processor 110 may include one or more interfaces. These interfaces may be integrated circuit (I2C) interfaces, inter-integrated circuit sound (I2S) interfaces, pulse code modulation (PCM) interfaces, universal asynchronous receiver / transmitter (UART) interfaces, mobile industry processor interfaces (MIPI), general-purpose input / output (GPIO) interfaces, universal serial bus (USB) interfaces, etc.

[0090] The charging management module 140 is used to receive charging input from the charger. The charger can be a wireless charger or a wired charger. In some embodiments where the charger is a wired charger, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some embodiments where the charger is a wireless charger, the charging management module 140 can receive charging input from the wireless charger via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also supply power to the electronic device via the power management module 141.

[0091] The power management module 141 is used to connect to the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, internal memory 121, external memory, display screen 180, camera lens 171, and communication module 150, etc. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may also be located in the same component.

[0092] The wireless communication function of electronic device 100 can be implemented through antenna 1, antenna 2, communication module 150, modem processor and baseband processor, etc.

[0093] In other embodiments, the communication module 150 may include a wireless communication module. The wireless communication module can provide wireless communication solutions for the electronic device 100, such as wireless local area network (WLAN) (e.g., wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC) technology, infrared (IR) technology, long term evolution (LTE), fifth generation (5G) systems, new radio (NR) systems, future communication systems, etc.

[0094] Electronic device 100 implements display functions through a GPU, display screen 180, application processor, etc. The GPU is a microprocessor used for image processing and connects to the display screen 180 and the application processor. The GPU is used for mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs and executes program instructions to generate or modify display information.

[0095] The display screen 180 is used to display images, videos, etc. The display screen 180 includes a display panel. This display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Mini-LED, a Micro-LED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include one or more display screens 180.

[0096] Electronic device 100 can perform shooting functions through camera module 170, video codec, GPU, display screen 180, application processor, etc.

[0097] The camera module 170 is used to acquire still images or videos. The camera lens 171 can be used to acquire light signals corresponding to the object being photographed in the scene. The solid-state imaging device 172, also known as an "image sensor," can be a charge-coupled device (CCD) sensor or a complementary metal-oxide-semiconductor (CMOS) sensor. The solid-state imaging device 172 can be used to convert the light signals passing through the lens 171 into electrical signals, perform analog-to-digital (A / D) conversion on the electrical signals, and output the corresponding digital signals.

[0098] Digital signal processors (DSPs) are used to process digital signals, and in addition to processing digital image signals, they can also process other digital signals. For example, when electronic device 100 performs frequency selection, the DSP is used to perform Fourier transforms on the frequency energy, etc.

[0099] Video codecs are used to compress or decompress digital video. Electronic device 100 may support one or more video codecs. In this way, electronic device 100 can play or record video in various encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG 2, MPEG 3, and MPEG 4.

[0100] The external storage interface 120 can be used to connect external storage cards such as micro SD cards to expand the storage capacity of the electronic device 100. The external storage card communicates with the processor 110 through the external storage interface 120 to realize data storage functions, such as storing music, video and other files on the external storage card.

[0101] Internal memory 121 can be used to store computer executable program code, which includes instructions. Processor 110 executes the instructions stored in internal memory 121 to perform various functional applications and data processing of electronic device 100. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function (e.g., voice playback function or image playback function), etc. The data storage area may store data created when using electronic device 200 (e.g., audio data and address book), etc. In addition, internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage, flash memory, or universal flash storage (UFS).

[0102] Figure 2 This is a block diagram illustrating configuration examples of a CMOS image sensor (CIS) according to some embodiments of this application. The CMOS image sensor 200 can be... Figure 1 The image sensor 172 shown.

[0103] like Figure 2 As shown, the CMOS image sensor 200 includes a pixel array section 210, an analog-to-digital converter (ADC) group 220, a digital signal horizontal transmission circuit 230, a row selection circuit 240, and a digital-to-analog converter (DAC) device 250 that serves as a ramp signal generator.

[0104] The pixel array portion 210 is formed by arranging pixel units 211 in a matrix. Each pixel unit in the pixel array portion 210 may include two or more pixels.

[0105] The ADC group 220 has single-slope ADCs (SS ADCs) arranged in multiple columns, each of which includes a comparator 221, a counter 222, and a latch 223.

[0106] Comparator 221 compares a reference voltage Vslop with an analog signal obtained from the pixels in each row line via the vertical signal line LSGN. The reference voltage Vslop is obtained by gradually changing the reference voltage generated by DAC 250, which is a ramp waveform (RAMP).

[0107] Counter 222 counts the comparison time of comparator 221.

[0108] The ADC group 220 has an n-bit digital signal conversion function. The ADC group 220 is configured for each vertical signal line (column line) and forms a column-parallel ADC block.

[0109] For example, the output of each latch 223 is connected to a digital signal horizontal transmission circuit 230 with a width of 2n bits.

[0110] In ADC group 220, comparators 221 in each column compare an analog signal (the potential of the vertical output line (VOL)) with a reference voltage Vslop (a ramp waveform with a certain slope and linear variation).

[0111] At this time, counters 222, which are set in each column in a similar manner to comparator 221, are running, and the specific potential Vslop of the ramp waveform RAMP and the counter value change one-to-one, thereby converting the potential (analog signal) VSL of the vertical signal line into a digital signal.

[0112] Changes in the reference voltage Vslop translate into changes in time. Time is counted at regular intervals (clock) and converted into digital values.

[0113] Then, when the analog electrical signal VSL intersects with the reference voltage Vslop, the output of comparator 221 is inverted to stop the input clock of counter 222, thereby completing the AD conversion.

[0114] After the aforementioned AD conversion cycle ends, the digital signal horizontal transmission circuit 230 inputs the data held by the latch 223 to the signal processing circuit. Figure 2 (not shown), and generate a two-dimensional image.

[0115] Figure 3 Pixel units according to some embodiments provided in this application are shown. Pixel unit 300 is... Figure 2 Any pixel unit in the pixel array portion 210 shown.

[0116] See Figure 3Pixel unit 300 includes four pixels: pixel P310, pixel P320, pixel P330, and pixel 340. Each of these four pixels includes a photoelectric conversion element and a corresponding transmission gate transistor (TX). The photoelectric conversion element can be a photodiode, phototransistor, etc. The photodiode can be a phototransistor, photogate, pinned photodiode, organic photodiode, quantum dot, etc. The photoelectric conversion element is used to perform photoelectric conversion from incident light to a charge (electron) quantity corresponding to the incident light quantity. The transmission gate transistor is connected between the photoelectric conversion element and the floating diffusion (FD) node. A transmission signal TRG, serving as a control signal, is provided to the gate of the transmission gate transistor via the TX line (LTX). The transmission gate transistor is used to transfer the electrons acquired by the photoelectric conversion element to the FD node under the influence of the transmission signal TRG. The FD node receives and stores the electrons. One end of the photoelectric conversion component is coupled to the end of the transmission gate transistor, while the other end of the photoelectric conversion component is coupled to a first ground voltage (VSS1). VSS1 can be ground voltage or negative voltage, ranging from –5.0V to 0V.

[0117] See Figure 3 Pixel P310 includes a photoelectric conversion element PD311 and a transmission gate transistor TX312; pixel P320 includes a photoelectric conversion element PD321 and a transmission gate transistor TX322; pixel P330 includes a photoelectric conversion element PD331 and a transmission gate transistor TX332; and pixel P340 includes a photoelectric conversion element PD341 and a transmission gate transistor TX342.

[0118] The pixel unit 300 also includes a reset transistor 351, a dual conversion gain transistor 352, and a selection transistor 354.

[0119] The reset transistor 351 can be a transistor used to reset the potential of the FD node to the potential of the first power supply voltage (VDD1). Therefore, the gate of the reset transistor 351 can be referred to as the reset gate. A reset signal is provided to the reset gate as a control signal.

[0120] A dual conversion gain transistor 352 is connected between the reset transistor 351 and the FD node. The dual conversion gain transistor 352 can be a transistor used to enable pixel units to operate in two different gain modes: low conversion gain (LCG) mode and high conversion gain (HCG) mode. The high conversion gain mode is suitable for low-light conditions, improving sensitivity to weak light signals and enhancing image quality in low-light environments. The low conversion gain mode is suitable for strong light conditions to avoid signal saturation and ensure accurate capture of image information even in strong light. The dual conversion gain transistor 352 is controlled by a dual conversion gain signal. The dual conversion gain transistor 352 can be connected between the reset transistor 351 and the FD node, or between VDD1 and the FD node, to achieve high dynamic range by combining the two gain modes.

[0121] The FD node is connected to the gate of amplifier transistor 353. Amplifier transistor 353 and select transistor 354 are connected in series. Select transistor 354 can be connected to amplifier transistor 353. In some embodiments, select transistor 354 can be connected between the second power supply voltage (VDD2) and amplifier transistor 353. Current source I column A connection is made between the selection transistor 354 and the second ground voltage (VSS2). VSS2 can be ground voltage or a negative voltage, ranging from –5.0V to 0V. Both the amplifier transistor 353 and the selection transistor 354 can be transistors. A selection signal, serving as a control signal, is provided to the gate of the selection transistor 354, causing the selection transistor 354 to conduct. When the selection transistor 354 is on, the amplifier transistor 353 amplifies the potential of the FD node and outputs a voltage corresponding to that potential to the output signal line (i.e., the vertical signal line (VSL)).

[0122] Due to the Miller effect, the solid-state imaging device provided in this application can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance. Because the amplifier with a larger width / length (W / L) ratio has a higher transconductance (gm), the frame rate becomes higher compared to conventional configurations at similar readout noise levels.

[0123] The transistors mentioned in this application (i.e., transmission gate transistors, reset transistors, double-conversion gain transistors, amplifier transistors, and select transistors) can be NMOS transistors or PMOS transistors. In some embodiments, all transistors are NMOS transistors. In other embodiments, all transistors are PMOS transistors. In still other embodiments, some transistors can be NMOS transistors, while others are PMOS transistors. For convenience, in the following embodiments, it is assumed that the transistors are NMOS transistors. When an NMOS transistor is replaced with a PMOS transistor, the connection relationships can be adjusted accordingly. For example, in the following embodiments, the amplifier transistor is an NMOS transistor, and the source of the amplifier transistor is coupled to a capacitor. If the amplifier transistor is a PMOS transistor, then the terminal coupled to the capacitor is the drain of the amplifier transistor.

[0124] Figure 4 It corresponds to Figure 3 The circuit diagram of pixel unit 300 is shown.

[0125] In some embodiments, capacitor 355 is coupled to the node between reset transistor 351 and dual-conversion-gain transistor 352. Capacitor 355 may be made of pn junction capacitors, oxide-semiconductor (MOS) capacitors, metal-oxide-metal (MOM) capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, dynamic random access memory (DRAM), magnetoresistive random access memory (MRAM), other types of on-chip memory, or combinations thereof. In high-illuminance mode, the FD node is electrically connected to capacitor 355. For example, in high-illuminance mode, overflow charge from the photoelectric conversion element is not discharged but is retained using an extended full-well capacity. The extended full-well capacity allows for a relatively small potential change at the FD node compared to the amount of overflow charge. For example, in high-illuminance mode, the conversion gain is reduced. This is achieved by activating the dual-conversion gain control signal to be supplied to the solid-state imaging device, thereby turning on the dual-conversion gain transistor 352. In this case, the dual-conversion gain transistor 352 can remain on at all times when operating in high-illuminance mode.

[0126] See Figure 4The pixel unit 300 also includes a capacitor 371. The capacitor 371 is coupled between the FD node and the amplifier transistor 353. For example, the capacitor 371 may be coupled between the FD node and the source of the amplifier transistor 353.

[0127] As mentioned earlier, the connection relationships can be adjusted accordingly when an NMOS transistor is replaced with a PMOS transistor. In some embodiments, for convenience, the terms "first terminal" and "second terminal" can be used to refer to the drain and source of the transistor. For example, a transistor may include three terminals: a gate, a first terminal, and a second terminal. When the transistor is an NMOS transistor, the first terminal is the drain and the second terminal is the source; when the transistor is a PMOS transistor, the first terminal is the source and the second terminal is the drain.

[0128] by Figure 4 For example, the gate of amplifier transistor 353 is coupled to the FD node, the first terminal of amplifier transistor 353 is coupled to VDD2, the second terminal of amplifier transistor 353 is coupled to the second terminal of select transistor 354, and the first terminal of select transistor 354 is coupled to the output terminal of pixel unit 300 (i.e., coupled to VSL). Furthermore, capacitor 371 is coupled between the FD node and the second terminal of amplifier transistor 353. When amplifier transistor 353 is an NMOS transistor, the first terminal of amplifier transistor 353 is the drain of amplifier transistor 353, and the second terminal of amplifier transistor 353 is the source of amplifier transistor 353; when amplifier transistor 353 is a PMOS transistor, the first terminal of amplifier transistor 353 is the source of amplifier transistor 353, and the second terminal of amplifier transistor 353 is the drain of amplifier transistor 353. Similarly, when the selection transistor 354 is an NMOS transistor, the first terminal of the selection transistor 354 is the drain of the selection transistor 354, and the second terminal of the selection transistor 354 is the source of the selection transistor 354; when the selection transistor 354 is a PMOS transistor, the first terminal of the selection transistor 354 is the source of the selection transistor 354, and the second terminal of the selection transistor 354 is the drain of the selection transistor 354.

[0129] Figure 5 A cross-sectional view of pixel unit 300 is shown.

[0130] Pixel unit 300 also includes a first connecting component and a second connecting component. Each connecting component includes a wire (also referred to as a metal layer) and a contact. For example, the first connecting component includes a wire 361 and a contact 362. Figure 5As shown, contact 362 connects the gate of amplifier transistor 353 to wire 361. Wire 361 is connected to the gate of amplifier transistor 353 via contact 362. Wire 361 is connected to the FD node. In other words, the FD node is coupled to the gate of amplifier transistor 353 via wire 361 and contact 362. A second connection assembly includes wire 363 and contact 364. Contact 364 connects the source of amplifier transistor 353 to wire 363. Capacitor 371 is coupled between wire 361 and wire 363.

[0131] Figure 6 The wires and contacts corresponding to capacitor 371 are shown.

[0132] See Figure 6 The conductor 361 comprises three segments: segment 601, segment 602, and segment 603. Contact 362 is connected to segment 601, which extends from contact 362 along a first direction. Segment 602 extends from segment 601 along a second direction, and segment 603 extends from segment 602 along the first direction. An FD node is connected to segment 603.

[0133] In some embodiments, the first direction is perpendicular to the second direction. In other words, the angle between the first direction and the second direction is 90°. In other embodiments, the angle between the first direction and the second direction may not be equal to 90°. For example, the angle between the first direction and the second direction may be 80° to 100°. Yet another example is that the angle between the first direction and the second direction may be 75° to 105°.

[0134] Figure 6 One possible design for conductor 361 is shown. Besides... Figure 6 Besides the possible designs shown, conductor 361 has other possible designs.

[0135] Figure 7 Another possible design for wire 361 is shown.

[0136] Figure 7 The wire 361 shown includes segments 701, 702, 703, and 704. The configuration of segments 701 to 703 is the same as that of segments 601 to 604. For example, contact 362 is connected to segment 701, which extends from contact 362 along a first direction. Segment 702 extends from segment 701 along a second direction, and segment 703 extends from segment 702 along the first direction. An FD node is connected to segment 703.

[0137] Figure 7 The conductor 361 shown also includes a segment 704 that extends from the first direction of the conductor 361 along a third direction. The third direction is opposite to the first direction.

[0138] Similarly, in some embodiments, the first direction is perpendicular to the second direction. In other words, the angle between the first direction and the second direction is 90°. In other embodiments, the angle between the first direction and the second direction may not be equal to 90°. For example, the angle between the first direction and the second direction may be 80° to 100°. Yet another example is that the angle between the first direction and the second direction may be 75° to 105°.

[0139] For convenience, in some embodiments, conductor 361 may be referred to as the first conductor, segments 601 and 701 may be referred to as the first segment of the first conductor, segments 602 and 702 may be referred to as the second segment of the first conductor, segments 603 and 703 may be referred to as the third segment of the first conductor, and segment 704 may be referred to as the fourth segment of the first conductor.

[0140] for Figure 6 or Figure 7 As shown in the diagram, the second segment of the first conductor 361 (i.e., segment 602 or segment 702) is a straight line. In one possible design, the second segment of the first conductor may include one or more V-shaped segments.

[0141] Figure 8 Another possible design for the first conductor (conductor 361) is shown.

[0142] Figure 8 The conductor 361 shown includes segments 801, 802, 803, and 804. Segment 801 is the first segment of the first conductor, segment 802 is the second segment of the first conductor, segment 803 is the third segment of the first conductor, and segment 804 is the fourth segment of the first conductor. The first, third, and fourth segments of the first conductor are connected to... Figure 7 The segment shown is similar. (And...) Figure 7 or Figure 6 The second segment of the first conductor shown is different. Figure 8 The second segment of the first conductor shown includes two V-shaped segments.

[0143] Figures 6 to 8 The wire 363 is also shown. Figures 6 to 8 The conductor 363 shown also includes two segments. For example, Figure 6 The wire 363 shown includes segments 611 and 612. Figure 7 The wire 363 shown includes segments 711 and 712. Figure 8 The conductor 363 shown includes segments 811 and 812. For convenience, in some embodiments, conductor 363 may be referred to as a second conductor, and segments 611, 711, and 811 may be referred to as first segments of the second conductor. Segments 612, 712, and 812 may be referred to as second segments of the second conductor. See also Figure 6 and Figure 7 The first segment of the second conductor starts from contact 364. Figure 6 and Figure 7 (Not shown in the image) Extends along the first direction, and the second segment of the second conductor extends from the first segment of the second conductor along the second direction. See also Figure 8 The first segment of the second conductor starts from contact 364. Figure 8 (Not shown in the image) extends along the first direction, while the second segment of the second conductor comprises two V-shaped segments.

[0144] In some embodiments, the second conductor may consist of only one segment.

[0145] Figure 9 Another possible design for the second conductor is shown.

[0146] See Figure 9 The configuration of the first conductor (i.e., conductor 361) and Figure 8 The first wire shown is the same. However, the second wire (i.e., wire 363) consists of only one segment, namely segment 911. Segment 911 extends from contact 364 ( Figure 8 (Not shown in the image) Extends along the second direction.

[0147] Figure 10 Another possible design for the second conductor is shown.

[0148] See Figure 10 The configuration of the first conductor (i.e., conductor 361) and Figure 8 The first conductor shown is the same. However, the second conductor (i.e., conductor 363) comprises three segments: segment 1011, segment 1012, and segment 1013. Segment 1011 can be referred to as the first segment of the second conductor, segment 1012 as the second segment of the second conductor, and segment 1013 as the third segment of the second conductor. Figure 6 and Figure 7 The first and second segments shown are similar, with segment 1011 starting from contact 364 ( Figure 6 and Figure 7 (Not shown in the diagram) Extends along a first direction, segment 1012 extends from the first segment of the second conductor along a second direction. Segment 1013 extends from the first direction of conductor 362 along a third direction, which is opposite to the first direction.

[0149] Figure 11 Another possible design for the second conductor is shown.

[0150] See Figure 11 The configuration of the first conductor (i.e., conductor 361) and Figure 8 The first conductor shown is the same. The second conductor (i.e., conductor 363) consists of three segments, namely segment 1111, segment 1112 and segment 1113.

[0151] The first paragraph 1111 and the second paragraph 1112 and Figure 6 , Figure 7 and Figure 10 The first segment of the second conductor and the second segment of the second conductor shown are the same. (And...) Figure 10 The third segment (i.e., segment 1013) of the second conductor shown is different; segment 1113 covers the contact 362 of the first connecting component.

[0152] In some embodiments, the first connection component may further include a contact (hereinafter referred to as the DCG contact) for connecting the dual conversion gain transistor 352. In these cases, segment 1113 may cover the DCG contact.

[0153] Figure 12 Another possible design for the second conductor is shown.

[0154] See Figure 12 The configuration of the first conductor (i.e., conductor 361) and Figure 8 The first conductor shown is the same. The second conductor (i.e., conductor 363) consists of three segments, namely segment 1211, segment 1212 and segment 1213.

[0155] The first paragraph 1211 and the second paragraph 1212 and Figure 6 , Figure 7 and Figure 10 The first segment of the second conductor and the second segment of the second conductor shown are the same. (And...) Figure 10 The third segment (i.e., segment 1013) of the second conductor shown is different; segment 1213 covers the contact 362 of the first connecting component and the floating diffusion node.

[0156] Since segments 1113 and 1213 cover one or more components of a pixel, segments 1113 and 1213 can be referred to as covering segments.

[0157] Understandable Figures 6 to 12 Some possible arrangements of the first and second conductors are shown, and the arrangements of the first and second conductors are not limited thereto. For example, in one possible design, the first conductor can be... Figure 8 The conductor 361 shown, and the second conductor may include three segments, wherein the three segments include Figure 8 The first and second paragraphs shown (i.e., paragraphs 811 and 812) and Figure 10 The third segment shown (i.e., segment 1013). For example, the first conductor could be... Figure 6 The wire 361 is shown, while the second wire can be... Figure 9 The wire shown.

[0158] In some embodiments, the second conductor 363 may further include at least one protruding segment. The protruding segment extends from at least one of the other segments of the segment conductor 363.

[0159] Figure 13 Another possible design for the second conductor is shown.

[0160] Figure 13 The second conductor 363 shown also includes a first segment (i.e., segment 1311), a second segment (i.e., segment 1312), and a covering segment (i.e., segment 1313). Figure 13 The first, second, and covering segments shown are related to... Figure 12 The segments shown are the same.

[0161] and Figure 12 The second conductor 363 shown is different. Figure 13 The second conductor 363 shown also includes four protruding sections, namely protruding section 1314, protruding section 1315, protruding section 1316, and protruding section 1317. Protruding section 1315 extends from section 1312, protruding section 1314 extends from protruding section 1315, protruding section 1317 extends from section 1312, and protruding section 1317 extends from section 1313.

[0162] Figures 7 to 13 The design shown allows for high capacitance between the floating diffusion node and the source node of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0163] See Figure 5 , Figure 5 The pixel unit 300 shown includes only one first connection component and one second connection component. In some embodiments, the pixel unit provided in this application may include at least one third connection component and / or at least one fourth connection component. At least one third connection component is stacked on the first connection component. At least one fourth connection component is stacked on the second connection component. This design allows for high capacitance between the floating diffusion node and the source node of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0164] Figure 14 The pixel units provided in some embodiments of this application are shown.

[0165] Figure 14 A cross-sectional view of a pixel unit is shown. See also Figure 14 The pixel unit includes a first connecting component, a second connecting component, a third connecting component, and a fourth connecting component. The third connecting component is stacked on top of the first connecting component. Similar to the first connecting component, the third connecting component includes a contact 366 and a wire 365. The fourth connecting component is stacked on top of the second connecting component. Similar to the second connecting component, the fourth connecting component includes a contact 368 and a wire 367.

[0166] Figure 15The pixel units provided in some embodiments of this application are shown.

[0167] See Figure 15 The pixel unit includes a first connecting component, a second connecting component, three third connecting components, and three fourth connecting components. The three third connecting components are stacked on the first connecting component, and the three fourth connecting components are stacked on the second connecting component. Similar to the first and second connecting components, each third connecting component includes a contact and a wire, and each fourth connecting component includes a contact and a wire.

[0168] for Figure 14 and Figure 15 The pixel unit shown has the same number of third connecting components as the number of fourth connecting components. In other embodiments, the number of third connecting components may differ from the number of fourth connecting components. In other embodiments, the pixel unit may include only one of the third or fourth connecting components. For example, in some embodiments, the pixel unit may include a first connecting component, a second connecting component, and one or more third connecting components. In other embodiments, the pixel unit may include a first connecting component, a second connecting component, and one or more fourth connecting components.

[0169] for Figure 14 and Figure 15 In the pixel unit shown, the width of the conductor in the third connecting component is the same as the width of the conductors in the first, second, and fourth connecting components. That is, all conductors in the connecting components have the same width. In other embodiments, the widths of all conductors may be different.

[0170] Figure 16 The pixel units provided in some embodiments of this application are shown.

[0171] See Figure 16 A pixel unit includes a first connecting component, a second connecting component, and a fourth connecting component. In other words, Figure 16 The pixel unit shown does not include the third connecting component. Furthermore, the width of the conductor in the fourth connecting component is greater than the width of the conductor in the first connecting component and the width of the conductor in the second connecting component.

[0172] In other embodiments, when a pixel unit includes more than one third connecting component, the width of the wires of the third connecting component may be different. Similarly, when a pixel unit includes more than one fourth connecting component, the width of the wires of the fourth connecting component may be different.

[0173] Figure 17 The pixel units provided in some embodiments of this application are shown.

[0174] Figure 17 The pixel unit shown includes a first connecting component, a second connecting component, two third connecting components, and two fourth connecting components. For convenience, the two third connecting components can be referred to as third connecting components 1710 and 1720; the two fourth connecting components can be referred to as fourth connecting components 1730 and 1740. The width of wire 1701 (i.e., the wire of the first connecting component) is different from the width of wire 1702 (i.e., the wire of the second connecting component). The width of wire 1703 (i.e., the wire of the third connecting component 1710) is different from the width of wire 1704 (i.e., the wire of the fourth connecting component 1730). The width of wire 1705 (i.e., the wire of the third connecting component 1720) is different from the width of wire 1706 (i.e., the wire of the fourth connecting component 1740). Furthermore, the width of wire 1703 is different from the width of wire 1705, and the width of wire 1704 is different from the width of wire 1706.

[0175] Because different wires have different widths, a portion of one wire may lie above a portion of another wire. See also Figure 17 A portion of conductor 1704 is located above a portion of conductor 1701, and a portion of conductor 1705 is located above a portion of conductor 1704.

[0176] In some embodiments, the pixel unit may further include a second capacitor. The second capacitor is a vertical metal-insulator-metal (MIM) capacitor. The second capacitor is coupled between the wires of the third connection component and the wires of the fourth connection component.

[0177] Figure 18 The pixel units provided in some embodiments of this application are shown.

[0178] Figure 18 The pixel unit shown includes a MIM capacitor 1850. The MIM capacitor 1850 is coupled between wire 1805 (i.e., the wire of the third connection component 1820) and wire 1806 (i.e., the wire of the fourth connection component 1840).

[0179] For the pixel unit shown in the previous figure, the first connecting component includes only one contact. In some embodiments, the first connecting component may include more than one contact. For example, Figure 19 The pixel units provided in some embodiments of this application are shown. See also Figure 19 Pixel unit 1900 includes a first connection component, which includes a wire 1951, a contact 1952, a contact 1953, and a contact 1954. Pixel unit 1900 also includes a second connection component, which includes a wire 1961 and a contact 1962. In other words, Figure 19 The first connection component shown includes three contacts, while Figure 19 The second connection component shown includes a contact.

[0180] In other embodiments, the second connection component may include more than one contact. Figure 20 This illustration shows one possible design for a pixel unit provided in some embodiments of this application. See also Figure 20 Pixel unit 2000 includes a first connection component, which includes a wire 2051, a contact 2052, a contact 2053, and a contact 2054. Furthermore, pixel unit 2000 includes a second connection component, which includes a wire 2061, a contact 2062, a contact 2063, and a contact 2064. In other words, both the first and second connection components include three contacts.

[0181] Figure 19 and Figure 20 The design shown allows for high capacitance between the floating diffusion node and the source node of the amplifier transistor, and due to the Miller effect, the signal-to-noise ratio can be improved by reducing the effective floating diffusion capacitance.

[0182] Furthermore, in the above design, the contacts of each connecting component are square. In other embodiments, the contacts may also be rectangular, circular, or other shapes. In some embodiments, the shape of the contacts of the first connecting component (hereinafter referred to as the first contact) may differ from the shape of the contacts of the second connecting component (hereinafter referred to as the second contact). For example, in some embodiments, the first contact may be square, while the second contact may be rectangular. In other embodiments, the first connecting component may include three first contacts, each of which is square. Additionally, the second connecting component includes one second contact, which is rectangular.

[0183] Optionally, in some embodiments, when the first or second connecting component includes more than one contact, the connecting component stacked thereon (i.e., the third or fourth connecting component) may also include more than one contact. For example, when the first connecting component includes three contacts, the third connecting component stacked on top of the first connecting component also includes three contacts. The three contacts of the third connecting component correspond one-to-one with the three contacts of the first connecting component, and each of the three contacts of the third connecting component is stacked above the corresponding contact of the first connecting component.

[0184] In some embodiments, the pixel unit may include a shielding component. This shielding component shields the source of the amplifier transistor 2102 and a second connection component. The second connection component includes a wire 2111 and a contact 2112. The shielding component can improve the voltage stability of the amplifier transistor source.

[0185] Figure 22 This application illustrates one possible design for a pixel unit provided in some embodiments.

[0186] Similar to pixel unit 2100, Figure 22 The pixel unit 2200 shown includes a shielding component 2201 for shielding the source of the amplifier transistor 2202 and a second connection component. The second connection component includes a wire 2211 and a contact 2212.

[0187] Figure 23 This application illustrates one possible design for a pixel unit provided in some embodiments.

[0188] Similar to pixel unit 2100, Figure 23 The pixel unit 2300 shown includes a shielding component 2301 for shielding the source of the amplifier transistor 2302 and a second connection component. The second connection component includes a wire 2311 and a contact 2312.

[0189] Figure 24 This application illustrates one possible design for a pixel unit provided in some embodiments.

[0190] Similar to pixel unit 2100, Figure 24 The pixel unit 2400 shown includes a shielding component 2401 for shielding the source of the amplifier transistor 2402 and a second connection component. The second connection component includes a wire 2411 and a contact 2412.

[0191] Figure 25 This application illustrates one possible design for a pixel unit provided in some embodiments.

[0192] Similar to pixel unit 2100, Figure 25 The pixel unit 2500 shown includes a shielding component 2501 for shielding the source of the amplifier transistor 2502 and a second connection component. The second connection component includes a wire 2511 and a contact 2512.

[0193] Figure 26 This application illustrates one possible design for a pixel unit provided in some embodiments.

[0194] Similar to pixel unit 2100, Figure 26 The pixel unit 2600 shown includes a shielding component 2601 for shielding the source of the amplifier transistor 2602 and a second connection component. The second connection component includes a wire 2611 and a contact 2612.

[0195] Figure 27 This application illustrates one possible design for a pixel unit provided in some embodiments.

[0196] Similar to pixel unit 2100, Figure 27 The pixel unit 2700 shown includes a shielding component 2701 for shielding the source of the amplifier transistor 2702 and a second connection component. The second connection component includes a wire 2711 and a contact 2712.

[0197] In some embodiments, the shielding components may be coupled to a reference node. For example, shielding component 2101 is coupled to a ground voltage (VSS) node; shielding component 2201 is coupled to an output voltage (V out )node; Figure 23 The shielding component 2301 shown is coupled to the gate of the selection device; Figure 24 The shielding component 2401 shown is coupled to the gate of the dual-conversion-gain device; Figure 25 The shielding component 2501 shown is coupled to the gate of the reset transistor; Figure 27 The shielding component 2701 shown is coupled to the power supply voltage (VDD) node.

[0198] See Figures 19 to 27 The pixel units shown in these figures include an active region for setting up an amplifier transistor and a selection device. In other embodiments, the pixel unit may include two active regions, namely a first active region and a second active region, wherein the amplifier transistor is located in the first active region and the selection transistor is located in the second active region. Due to the Miller effect, this design can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance. Figure 28 A possible design for a pixel unit according to some embodiments of this application is shown. See also Figure 28 The pixel unit 2800 includes a first active region 2801 and a second active region 2802. An amplifier transistor 2803 is formed on the first region 2801, while a select transistor 2804 is formed on the second region 2802. Furthermore, the second connection component of the pixel unit 2800 includes a wire 2811, a contact 2812, and a contact 2813. Contact 2812 is located on the first active region 2801, and contact 2813 is located on the second active region 2802. The wire 2811 includes a first segment 2811-1 and a second segment 2811-2. Contacts 2812 and 2813 are connected via the second segment 2811-2.

[0199] Figure 29 A possible design for a pixel unit according to some embodiments of this application is shown. See also Figure 29The pixel unit 2900 includes a first active region 2901 and a second active region 2902. The first active region 2901 is used to house the amplifier transistor 2903, while the second active region 2902 is used to house the selection transistor 2904. Furthermore, the second connection component of the pixel unit 2900 includes a wire 2911, a contact 2912, and a contact 2913. Contact 2912 is located on the first active region 2901, and contact 2913 is located on the second active region 2902. The wire 2911 includes two segments, namely a first segment 2911-1 and a second segment 2911-2. The second segment 2911-2 connects contact 2912 and contact 2913.

[0200] Figure 30 A possible design for a pixel unit according to some embodiments of this application is shown. See also Figure 30 The pixel unit 3000 includes a first active region 3001 and a second active region 3002. An amplifier transistor 3003 is located on the first active region 3001, while a selection transistor 3004 is located on the second active region. Furthermore, the first connection component of the pixel unit 3000 includes a wire 3031 and a contact 3032. The wire 3031 includes segments 3031-1 and 3031-2. The second connection component of the pixel unit 3000 includes a wire 3011, a contact 3012, and a contact 3013. The wire 3011 includes segments 3011-1, 3011-2, 3011-3, 3011-4, and 3011-5. Unlike the design provided in this application, the pixel unit 3000 includes two capacitors, namely capacitor 3021 and capacitor 3022. Capacitor 3021 is coupled between the drain of the select transistor 3004 and the floating diffusion node, while capacitor 3022 is coupled between the source of the amplifier transistor 3003 and the floating diffusion node. More specifically, capacitor 3021 is coupled between the drain of the select transistor 3004 and the floating diffusion node via segments 3011-1, 3011-2, and 3031-1. Capacitor 3022 is coupled between the source of the amplifier transistor 3003 and the floating diffusion node via segments 3031-1, 3011-5, and 3011-4. Similar to pixel units 2800 and 2900, the two contacts of the second connection component are connected via segment 3011-3. The above-described wire division method (i.e., dividing wire 3011 into five segments) is only one possible division method. Another method considers wires connected to a node as belonging to the same segment. In this case, wire 3011 can be divided into three segments. For convenience, these three sections can be referred to as the first section, the second section, and the third section. The first section includes sections 3011-1 and 3011-2, the second section includes section 3011-3, and the third section includes sections 3011-4 and 3011-5.

[0201] Figure 31A possible design for a pixel unit according to some embodiments of this application is shown. See also Figure 31 Pixel unit 3100 includes a first active region 3101 and a second active region 3102. An amplifier transistor 3103 is located on the first active region 3101, while a selection transistor 3104 is located on the second active region. Furthermore, the second connection component of pixel unit 3100 includes a wire 3111, a contact 3112, and a contact 3113. The two contacts of the second connection component are connected by a segment of the wire 3111.

[0202] Figure 32 A possible design for a pixel unit according to some embodiments of this application is shown. See also Figure 32 Pixel unit 3200 includes a first active region 3201 and a second active region 3202. An amplifier transistor 3203 is located on the first active region 3201, while a selection transistor 3204 is located on the second active region. Furthermore, the first connection component of pixel unit 3200 includes a wire 3231 and a contact 3032. Wire 3231 includes segments 3231-1 and 3231-2. The second connection component of pixel unit 3200 includes a wire 3211, a contact 3212, and a contact 3113. Wire 3211 includes segments 3211-1, 3211-2, 3211-3, 3211-4, 3211-5, 3211-6, and 3211-7. The two contacts of the second connection component are connected via segment 3211-3 of wire 3211. Pixel unit 3200 also includes capacitors 3221 and 3222. Capacitor 3221 is coupled between the drain of selection transistor 3204 and the floating diffusion node, while capacitor 3222 is coupled between the floating diffusion node and the source of amplifier transistor 3203. More specifically, capacitor 3221 is coupled between the floating diffusion node and the drain of selection transistor 3204 via segments 3211-1, 3211-2, and 3231-1. Capacitor 3222 is coupled between the floating diffusion node and the source of amplifier transistor via segments 3231-1, 3211-7, 3211-6, 3211-5, and 3211-4. Similar to pixel unit 3000, dividing wire 3211 into seven segments is only one possible method of division. Another method considers wires connected to a node as belonging to the same segment. In this case, conductor 3011 can be divided into three segments. For convenience, these three segments can be referred to as the first segment, the second segment, and the third segment. The first segment includes segments 3211-1 and 3211-2, the second segment includes segment 3211-3, and the third segment includes segments 3211-4 and 3211-7.

[0203] In some embodiments, the source, drain, channel, source, and / or drain of the amplifier transistor have an n-type or p-type layer.

[0204] Figure 33 An amplifier transistor according to some embodiments of this application is shown. As previously described, pixel units provided in some embodiments of this application include a capacitor coupled between the amplifier transistor and a floating diffusion node. For Figure 33 The amplifier transistor shown has a capacitive coupling between its gate and the source of the amplifier. When the gate of the amplifier transistor is coupled to the floating diffusion node, the capacitance contributes to the capacitance of both the floating diffusion node and the source node of the amplifier.

[0205] Figure 34 An amplifier transistor according to some embodiments of this application is shown. Figure 34 The source of the amplifier transistor shown has an n-type layer below the gate of the amplifier transistor.

[0206] Figure 35 An amplifier transistor according to some embodiments of this application is shown. Figure 35 The source and drain of the amplifier transistor shown have an n-type layer below the gate of the amplifier transistor.

[0207] Figure 36 An amplifier transistor according to some embodiments of this application is shown. The source and drain of the amplifier transistor, and the source and drain of the select transistor, have an n-type layer below the gate of the amplifier transistor. Furthermore, the source and drain of the select transistor have an n-type layer below the gate of the select device.

[0208] Figure 37 An amplifier transistor according to some embodiments of this application is shown. The channel of the amplifier transistor has an n-type layer.

[0209] Figures 34 to 37 The amplifier shown exhibits a high gate-source overlap capacitance, which contributes a high capacitance between the floating diffusion node and the amplifier's source node. Therefore, due to the Miller effect, these structures can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance.

[0210] Figure 38 An amplifier transistor according to some embodiments of this application is shown. As previously described, pixel units provided in some embodiments of this application include a capacitor coupled between the amplifier transistor and a floating diffusion node. For Figure 38The amplifier transistor shown has a capacitive coupling between its gate and the contact of the second connection component. Furthermore, the source of the amplifier transistor is deeper than its drain. Since the gate of the amplifier transistor is coupled to the floating diffusion node, and the contact of the second connection component is coupled to the source of the amplifier, the capacitance contributes to both the floating diffusion node and the source node of the amplifier, and the deeper source further enhances the capacitance.

[0211] Figure 39 An amplifier transistor according to some embodiments of this application is shown. Figure 39 The amplifier transistor shown includes a high dielectric constant source / drain (S / D) sidewall structure, wherein the dielectric material can be silicon nitride, silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiONC), carbon-doped silicon (SiC), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCO), silicon boron nitride (SBCN), silicon oxyhydride (SiCOH), or a combination thereof.

[0212] Figure 40 An amplifier transistor according to some embodiments of this application is shown. Figure 40 The amplifier transistor shown includes a thick S / D sidewall partition that may contact the contacts used to connect the source of the amplifier transistor.

[0213] Figure 41 An amplifier transistor according to some embodiments of this application is shown. Figure 41 The amplifier transistor shown includes a high-dielectric-constant interlayer dielectric layer.

[0214] In some embodiments, the embedding portion may be disposed on the channel edge side of the amplifier transistor. See also Figure 42 , Figure 42 An amplifier transistor according to some embodiments of this application is shown. Figure 42 The amplifier shown includes an embedded gate in one or more channel edge sides.

[0215] Figures 40 to 42 The amplifier transistors shown provide high gate-source overlap capacitance, which contributes high capacitance between the floating diffusion node and the amplifier's source node. Therefore, due to the Miller effect, these structures can improve the signal-to-noise ratio by reducing the effective floating diffusion capacitance.

[0216] Figure 43 A cross-sectional view of an image sensor according to some embodiments of this application is shown. Although Figure 43The image sensor shown is a back-illuminated image sensor, and the embodiments provided in this application can be used for front-illuminated image sensors. Furthermore, the deep trench isolation (DTI) depth of the sensor can be less than, equal to, or greater than the radiation-sensitive depth.

[0217] The substrate of the sensor includes a semiconductor material such as silicon or germanium. In some embodiments, the substrate may include at least one or more other photosensitive materials, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium gallium arsenide, indium phosphide, indium antimonide, semiconductor-on-insulator, or combinations thereof.

[0218] The deep trench region can be filled with an insulating film, such as SiO2, SiN, SiON, HfO2, Al2O3, ZrO2, Ta2O5, TiO2, La2O3, Pr2O3, CeO2, Nd2O3, Pm2O3, Sm2O3, Eu2O3, Gd2O3, Tb2O3, Dy2O3, Ho2O3, Er2O3, Tm2O3, Yb2O3, Lu2O3, Y2O3, or combinations thereof.

[0219] The color filter array includes multiple color filters provided in a one-to-one correspondence with multiple light receiving elements. The color filters may include filters for detecting red, green, blue, yellow, cyan, magenta, and white.

[0220] The lens array includes multiple microlenses for focusing light incident from the lens onto multiple light-receiving elements.

[0221] In some embodiments, the photosensitive substrate structure has various variations, such as an approximately steep structure, a small cone structure, multiple quadrangular pyramid structures, and a single quadrangular pyramid structure. These all contribute to improving sensitivity.

[0222] Figure 44 A schematic diagram of a solid-state imaging device according to an embodiment of this application is shown. First, refer to... Figure 44 (a) describes a typical solid-state imaging device. A typical solid-state imaging device includes a pixel array mounted on a single semiconductor chip, control circuitry, and logic circuitry for signal processing. Generally, an image sensor includes a pixel array and control circuitry. The pixel array can be front-illuminated or back-illuminated. The semiconductor substrate can be a monolithic material or a semiconductor-on-insulator.

[0223] like Figure 44As shown in (b), on the other hand, the solid-state imaging device according to an embodiment of this application includes a pixel array and control circuitry (control region) mounted on a first semiconductor chip portion, and logic circuitry including signal processing circuitry mounted on a second semiconductor chip portion and used for signal processing. The first semiconductor chip portion and the second semiconductor chip portion are electrically connected to each other and can be formed into a single semiconductor chip to provide a solid-state imaging device.

[0224] like Figure 44 As shown in (c), in a solid-state imaging device according to another embodiment of this application, a pixel array is mounted on a first semiconductor chip portion. Furthermore, control circuitry and logic circuitry including signal processing circuitry are mounted on a second semiconductor chip portion. The first and second semiconductor chip portions are electrically connected to each other and can be formed into a single semiconductor chip to provide a solid-state imaging device.

[0225] like Figure 44 As shown in (d) of this application, in a solid-state imaging device according to another embodiment of the present application, a pixel array is mounted on a first semiconductor chip portion. Furthermore, memory circuitry is mounted on a second semiconductor chip portion. Then, control circuitry and logic circuitry including signal processing circuitry are mounted on a third semiconductor chip portion. The first, second, and third semiconductor chip portions are electrically connected and can be formed as a single semiconductor chip or two semiconductor chips to provide a solid-state imaging device.

[0226] like Figure 44 As shown in (e), in a solid-state imaging device according to another embodiment of this application, a pixel array is mounted on a first semiconductor chip portion. Furthermore, pixel circuitry is mounted on a second semiconductor chip portion. Then, control circuitry and logic circuitry including signal processing circuitry are mounted on a third semiconductor chip portion. The first, second, and third semiconductor chip portions are electrically connected and can be formed as a single semiconductor chip or two semiconductor chips to provide a solid-state imaging device.

[0227] Figure 45A block diagram illustrating an exemplary configuration of an imaging device, which is an electronic device employing the present technology, is shown. The imaging device, as shown, includes an optical system, a shutter, a solid-state image sensor, a drive circuit, a signal processing circuit, a monitor, and a memory, capable of capturing still images and videos. The optical system includes one or more lenses for guiding light (incident light) from an object to the solid-state image sensor and focusing the light onto the light-receiving surface of the solid-state image sensor. The shutter is positioned between the optical system and the solid-state image sensor, and under the control of the drive circuit, controls the light illumination period and light blocking period of the solid-state image sensor. The solid-state image sensor is comprised of the aforementioned solid-state image sensor or a package including a solid-state image sensor. The solid-state image sensor accumulates signal charge over a certain period of time based on the light focused onto the light-receiving surface by the optical system and the shutter. The signal charge accumulated in the solid-state image sensor is transmitted according to a drive signal (timing signal) provided by the drive circuit. The drive circuit outputs a drive signal for controlling the transmission operation of the solid-state image sensor and the closing operation of the shutter, thereby driving the solid-state image sensor and the shutter. The signal processing circuit performs various signal processing operations on the signal charge output by the solid-state image sensor. The image (image data) obtained through signal processing by the signal processing circuit is provided to the monitor for display or to the memory for storage (recording).

[0228] Figure 46 Examples of techniques employing the image sensor described in this application are shown. For instance, image sensors can be applied to a wide range of fields, including sports equipment (such as wearable cameras), medical devices (such as endoscopes), beauty devices, vehicles or transportation equipment (such as trucks), entertainment devices (such as mobile phones, game consoles, digital cameras and video recorders), agriculture (such as farmland surveillance cameras), home appliances (such as televisions and refrigerators), and security (such as surveillance cameras, webcams, and machine vision cameras).

[0229] Figure 47 A block diagram illustrating an exemplary schematic configuration of a vehicle control system is shown. For example, imaging units are disposed at the front nose, side mirrors, rear bumper, rear door, and upper part of the interior windshield of the vehicle. The imaging units mounted on the front nose and the upper part of the interior windshield primarily acquire images of the area in front of the vehicle. The imaging units mounted on the side mirrors primarily acquire images of the area to the side of the vehicle. The imaging units mounted on the rear bumper or rear door primarily acquire images of the area behind the vehicle. The forward-facing images acquired by the imaging units are primarily used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0230] The above descriptions are merely some specific implementations of this application and are not intended to limit the scope of protection of this application. Any variations or substitutions easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A solid-state imaging device, characterized in that, Including pixel arrays, where, The pixel array comprises N×M pixel units, where N is a positive integer and M is a positive integer; Each of the N×M pixel units includes at least one pixel; Each pixel unit also includes an amplifier transistor, a floating diffusion node, a selection transistor, and a first capacitor, wherein... The gate of the amplifier transistor is coupled to the floating diffusion node, the first terminal of the amplifier transistor is coupled to the power supply voltage, the second terminal of the amplifier transistor is coupled to the first terminal of the selection transistor, the second terminal of the selection transistor is coupled to the output terminal, and the first capacitor is coupled between the floating diffusion node and the second terminal of the amplifier transistor.

2. The solid-state imaging device according to claim 1, characterized in that, Each pixel unit also includes a first connection component and a second connection component, wherein... The first connection component includes a first wire and at least one first contact, the first contact connecting the gate of the amplifier transistor to the first wire, and the first wire connecting to the floating diffusion node; The second connection component includes a second wire and at least one second contact, the second contact connecting the second terminal of the amplifier transistor to the second wire; The first capacitor is coupled between the first wire and the second wire.

3. The solid-state imaging device according to claim 2, characterized in that, The at least one first contact is connected to a first segment of the first wire, the first segment of the first wire extends from the at least one first contact along a first direction, the second segment of the first wire extends from the first segment of the first wire along a second direction, the third segment of the first wire extends from the second segment of the first wire along the first direction, the floating diffusion node is connected to the third segment of the first wire, and the first direction is perpendicular to the second direction.

4. The solid-state imaging device according to claim 3, characterized in that, The fourth segment of the first conductor extends from the first segment of the first conductor along a third direction, wherein the third direction is opposite to the first direction; and / or The second segment of the first conductor includes at least one V-shaped segment.

5. The solid-state imaging device according to any one of claims 2 to 4, characterized in that, The at least one second contact is connected to a first segment of the second wire, the first segment of the second wire extending from the at least one second contact along a first direction, and the second segment of the second wire extending from the first segment of the second wire along a second direction; or The at least one second contact is connected to the first segment of the second wire, the first segment of the second wire extending from the at least one second contact along the second direction.

6. The solid-state imaging device according to claim 5, characterized in that, The third segment of the second conductor extends from the at least one second contact in a third direction; and / or The second segment of the second conductor includes at least one V-shaped segment.

7. The solid-state imaging device according to claim 5 or 6, characterized in that, The second conductor also includes a covering section, wherein the at least one first contact and / or the floating diffusion node is covered by the covering section.

8. The solid-state imaging device according to any one of claims 5 to 7, characterized in that, The second conductor further includes at least one protruding segment, wherein the protruding segment extends from at least one of the other segments of the second conductor.

9. The solid-state imaging device according to any one of claims 2 to 8, characterized in that, Each pixel unit further includes: at least one third connection component, wherein the at least one third connection component is stacked on the first connection component; and / or At least one fourth connection component, wherein the at least one fourth connection component is stacked on the second connection component.

10. The solid-state imaging device according to claim 9, characterized in that, A portion of the conductor of one of the at least three third connecting components is located above a portion of the conductor of one of the at least four fourth connecting components; or A portion of the conductor of one of the at least four fourth connecting components is located above a portion of the conductor of one of the at least three third connecting components.

11. The solid-state imaging device according to claim 9 or 10, characterized in that, Each pixel unit also includes a second capacitor, which is a vertical metal-insulator-metal MIM capacitor, and the second capacitor is coupled between the wires of the third connection component and the wires of the fourth connection component.

12. The solid-state imaging device according to any one of claims 2 to 11, characterized in that, Each pixel unit also includes a shielding component, wherein the shielding component shields the second terminal of the amplifier transistor and the second connection component.

13. The solid-state imaging device according to claim 12, characterized in that, The shielding component is coupled to a reference node, wherein the reference node is one of the following: a power supply voltage VDD node in each pixel unit, a ground voltage VSS node in each pixel unit, an output voltage Vout node in each pixel unit, the gate of a dual conversion gain transistor in each pixel unit, the gate of a reset transistor in each pixel unit, or the gate of the selection transistor in each pixel unit.

14. The solid-state imaging device according to claim 12 or 13, characterized in that, The shielding component is a control line.

15. The solid-state imaging device according to any one of claims 1 to 14, characterized in that, Each pixel unit includes a first active region and a second active region, wherein the amplifier transistor is located in the first active region and the selection transistor is located in the second active region.

16. The solid-state imaging device according to claim 15, characterized in that, Each pixel unit also includes a fifth connection component and a sixth connection component, wherein... The fifth connection component includes a fifth wire and at least one fifth contact, the fifth contact connecting the gate of the amplifier transistor to the fifth wire, and the fifth wire connecting to the floating diffusion node; The sixth connection component includes a sixth wire, at least one sixth contact, and at least one seventh contact. The sixth contact connects the second terminal of the amplifier transistor to the sixth wire, and the seventh contact connects the first terminal of the selection transistor to the sixth wire. The first capacitor is coupled between the fifth wire and the sixth wire.

17. The solid-state imaging device according to claim 16, characterized in that, Each pixel unit also includes a third capacitor. The sixth connection component includes a first segment and a second segment. The first segment is connected to the second terminal of the amplifier transistor via the sixth contact, and the second segment is connected to the first terminal of the selection transistor via the seventh contact. The first capacitor is coupled between the first segment and the fifth connection component, and the third capacitor is coupled between the second segment and the fifth connection component.

18. The solid-state imaging device according to any one of claims 1 to 17, characterized in that, At least one of the following components has an additional layer: the second terminal of the amplifier transistor, the first terminal of the amplifier transistor, the channel of the amplifier transistor, or the selection transistor, wherein the additional layer is an n-type layer or a p-type layer.

19. The solid-state imaging device according to any one of claims 1 to 18, characterized in that, The second terminal of the amplifier transistor is deeper than the first terminal of the amplifier transistor.

20. The solid-state imaging device according to any one of claims 1 to 19, characterized in that, The amplifier transistor has source / drain sidewalls with high dielectric constant, or there is an interlayer dielectric layer with high dielectric constant between the second terminal of the amplifier transistor and the gate of the amplifier transistor.

21. The solid-state imaging device according to any one of claims 1 to 19, characterized in that, The amplifier transistor has an embedded portion on the channel edge side.

Images