Image sensor and readout circuit therefor

Abstract

The present application provides an image sensor and a readout circuit thereof, wherein the readout circuit of the image sensor is connected with a pixel unit, and comprises a ramp voltage circuit, a comparison circuit, a counter circuit and a switching circuit, the switching circuit can be connected in front of the comparison circuit or between the comparison circuit and the counter circuit, the first input end and the second input end of the comparison circuit are connected with the pixel unit and the ramp voltage circuit in opposite connection mode in a first conversion gain mode and a second conversion gain mode, or the comparison signal with opposite polarity is output to the counter circuit, so as to realize correlated double sampling in the first conversion gain mode and non-correlated double sampling in the second conversion gain mode, eliminate the coupling influence of the ground potential fluctuation signal, improve the quantization accuracy and improve the picture display effect of the image sensor.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and particularly relates to an image sensor and its readout circuit. Background Technology

[0002] As intelligent vision devices increasingly demand higher imaging quality for complex scenes, traditional single-gain CMOS image sensors, limited by fixed full-well capacity and fixed signal conversion gain, cannot adapt to complex scenes with strong daylight, low nightlight, and large contrast ratios. This results in imaging defects such as loss of detail in dark areas, overexposure in highlight areas, and localized grayscale distortion. To address these issues, current mainstream high-end CMOS image sensors generally employ a multi-level pixel conversion gain architecture. This allows a single pixel unit to selectively output high conversion gain analog image signals, low conversion gain analog image signals, and ultra-low conversion gain analog image signals within the same photoelectric integration cycle or within adjacent time-series photoelectric integration cycles.

[0003] The three gain modes have clearly defined roles for different scenarios: the high conversion gain mode has extremely low equivalent readout noise and is mainly used to acquire effective information in the dark areas of images under low illumination; the low conversion gain mode has a medium full-well capacity for pixels and is suitable for acquiring pixel signals in scenes with normal illumination; the ultra-low conversion gain mode relies on on-chip lateral overflow integrated capacitors to achieve ultra-large charge storage capacity and significantly improve the pixel saturation threshold, and is specifically used to acquire image information in areas with strong light and the highlight edges of images. The image processing chip at the back end of the chip uses a multi-frame image fusion algorithm to weight and fuse the digital pixel signals of the above three different gains, and finally outputs a high dynamic range image, effectively expanding the overall imaging dynamic range of the CMOS image sensor.

[0004] The multiple analog pixel signals output by the multi-gain mode pixel array all need to be converted from analog signals to digital code values ​​through a chip-level column-level single-slope analog-to-digital converter. In the existing standardized circuit architecture in the industry, different gain modes are matched with two different column-level sampling quantization mechanisms. Among them, the high conversion gain mode and the low conversion gain mode uniformly adopt the correlated double sampling quantization mechanism to suppress pixel reset noise and column-level fixed pattern noise. Under the correlated double sampling workflow, the column-level slope voltage circuit outputs a positive slope voltage signal that linearly decreases from a high level. The slope voltage signal is connected to the non-inverting input of the differential comparator, and the analog pixel signal output by the pixel bit line is connected to the inverting input of the differential comparator. Through two slope comparison samplings at different nodes and differential counting operations, the reset bias voltage of the pixel floating diffusion node is eliminated, and the pure photoelectric conversion voltage signal is extracted.

[0005] However, due to limitations imposed by the pixel charge overflow mechanism and the electrical characteristics of the output signal, the ultra-low conversion gain cannot utilize the standard correlated double sampling quantization scheme. Therefore, the industry must employ uncorrelated double sampling quantization to complete the analog-to-digital conversion. Existing uncorrelated double sampling standard circuit architectures, adapted to the output characteristics of the charge overflow signal, connect the pixel analog signal and the positive falling ramp voltage signal to the non-inverting input of a differential comparator, while directly binding the inverting input of the differential comparator to the on-chip common ground potential as a fixed reference potential. This hardware topology relies on addition logic to perform two sampling counts of the pixel reset signal and the photoelectric effective signal, ultimately obtaining the pixel effective signal code value in ultra-low gain mode through differential calculation of the two sets of count values.

[0006] However, existing ultra-low conversion gain uncorrelated double-sampling architectures suffer from unavoidable ground coupling noise, significantly reducing the signal-to-noise ratio (SNR) of image quantization in highlight areas. Current solutions directly connect the comparator's negative input to the on-chip common ground potential. The on-chip common ground network of the semiconductor chip contains a large amount of digital circuit switching noise, row and column circuit crosstalk noise, power supply ripple coupling noise, and carrier migration parasitic noise. During normal operation of the image sensor, the common ground potential cannot maintain an ideal zero potential state and will generate small real-time potential fluctuations due to the switching of internal digital circuits and the parallel operation of column circuits. This ground potential fluctuation signal is directly coupled into the uncorrelated double-sampling quantization link as a reference error signal, generating a fixed deviation term and a random noise term in the differential counting result. This error cannot be calibrated and eliminated by back-end digital algorithms, directly causing problems such as grayscale shift, a surge in random noise, and blurred image textures in ultra-low gain image frames in highlight areas, thus lowering the overall SNR of the wide dynamic range fused image. Summary of the Invention

[0007] The purpose of this invention is to provide a readout circuit for an image sensor, which aims to solve the problem that ground potential coupling exists in the readout circuit of a traditional image sensor under ultra-low conversion gain uncorrelated sampling, resulting in abnormal image sensor images.

[0008] A first aspect of this invention provides a readout circuit for an image sensor, connected to a pixel unit, the readout circuit comprising: A ramp voltage circuit is used to output a first ramp voltage signal and a second ramp voltage signal in opposite directions in a first conversion gain mode and a second conversion gain mode, respectively, wherein the conversion gain of the first conversion gain mode is greater than the conversion gain of the second conversion gain mode. The comparison circuit is used to compare the corresponding analog signal and the corresponding ramp voltage signal output by the pixel unit in different conversion gain modes, and output the comparison signal in the corresponding conversion gain mode. The counter circuit is used to count the received comparison signal or the inverted comparison signal in different conversion gain modes and output the corresponding digital code value. A switching circuit is connected between the pixel unit, the ramp voltage circuit, and the comparator circuit. The switching circuit is configured to connect the first input terminal of the ramp voltage circuit and the comparator circuit, and connect the pixel unit and the second input terminal of the comparator circuit, in a first conversion gain mode; and to connect the second input terminal of the ramp voltage circuit and the comparator circuit, and connect the pixel unit and the first input terminal of the comparator circuit, in a second conversion gain mode. Alternatively, the switching circuit is connected between the comparator circuit and the counter circuit. The switching circuit is configured to transmit the comparison signal to the counter circuit in the first conversion gain mode, and to invert the comparison signal and transmit it to the counter circuit in the second conversion gain mode.

[0009] Optionally, the first conversion gain mode is a high conversion gain mode and / or a low conversion gain mode, and the second conversion gain mode is an ultra-low conversion gain mode.

[0010] Optionally, the analog signal in the corresponding gain conversion mode includes a reset signal output during the first quantization time period and a pixel signal output during the second quantization time period in the corresponding gain conversion mode; The ramp voltage circuit is used for: During the first quantization time period and the second quantization time period of the first conversion gain mode, a first sub-slope voltage signal and a second sub-slope voltage signal are output respectively, and the slope direction of the first sub-slope voltage signal and the slope direction of the second sub-slope voltage signal are the same. During the first and second quantization periods in the second conversion gain mode, a third sub-slope voltage signal and a fourth sub-slope voltage signal are output respectively. The slope direction of the third sub-slope voltage signal is the same as that of the fourth sub-slope voltage signal, and the slope direction of the third sub-slope voltage signal is opposite to that of the first sub-slope voltage signal. The comparison circuit is used to compare the corresponding reset signal and the pixel signal with the corresponding sub-slope voltage signal during the first quantization time period and the second quantization time period in the corresponding conversion gain mode, and output the reset pulse signal and the pixel pulse signal in the corresponding conversion gain mode. The counter circuit is used to count the received reset pulse signal or the inverted reset pulse signal in a first counting method during the first quantization time period and the second quantization time period corresponding to the conversion gain mode, and to count the received pixel pulse signal or the inverted pixel pulse signal in a second counting method, wherein the first counting method and the second counting method are respectively downward counting and upward counting.

[0011] Optionally, the comparison circuit includes a comparator, a first capacitor, and a second capacitor; The first terminal of the first capacitor forms the first input terminal of the comparator circuit, the first terminal of the second capacitor forms the second input terminal of the comparator circuit, the second terminal of the first capacitor is connected to the non-inverting input terminal of the comparator, the second terminal of the second capacitor is connected to the inverting input terminal of the comparator, and the output terminal of the comparator forms the output terminal of the comparator circuit.

[0012] Optionally, the comparison circuit further includes a first zero-adjustment switch and a second zero-adjustment switch; The first zero-adjustment switch is connected between the non-inverting input terminal and the first output terminal of the comparator, and the second zero-adjustment switch is connected between the inverting input terminal and the second output terminal of the comparator. The first output terminal of the comparator constitutes the output terminal of the comparator circuit.

[0013] Optionally, the counter circuit includes an AND gate and a counter; The first input terminal of the AND gate constitutes the first input terminal of the counter circuit, the second input terminal of the AND gate is used to input a counting enable signal, the output terminal of the AND gate is connected to the counter, and the counter is used to count down and count up on the input comparison signal during the first quantization time period and the second quantization time period corresponding to the conversion gain mode, respectively.

[0014] Optionally, the counter circuit includes a NAND gate, a first NOT gate, and a counter; The first input terminal of the NAND gate constitutes the first input terminal of the counter circuit. The second input terminal of the NAND gate is used to input a counting enable signal. The output terminal of the NAND gate is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the counter. The counter is used to count down and count up on the input comparison signal during the first quantization time period and the second quantization time period corresponding to the conversion gain mode, respectively.

[0015] Optionally, the switching circuit is connected between the pixel unit, the ramp voltage circuit, and the comparison circuit; The switching circuit includes a first switch, a second switch, a third switch, and a fourth switch; The first terminal of the first switch, the first terminal of the second switch, and the pixel unit are connected; the first terminal of the third switch and the first terminal of the fourth switch are connected to the output terminal of the ramp voltage circuit; the second terminal of the first switch and the second terminal of the third switch are connected to the first input terminal of the comparator circuit; and the second terminal of the second switch and the second terminal of the fourth switch are connected to the second input terminal of the comparator circuit.

[0016] Optionally, the switching circuit is connected between the comparator circuit and the counter circuit; The switching circuit includes a second NOT gate, a fifth switch, and a sixth switch; The first terminal of the fifth switch, the first terminal of the sixth switch, and the output terminal of the comparator circuit are connected. The second terminal of the fifth switch is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate, the second terminal of the sixth switch, and the input terminal of the counter circuit are connected.

[0017] A second aspect of the present invention provides an image sensor, including a pixel array, a control circuit, and a plurality of readout circuits for the image sensor as described above, wherein the pixel array includes a plurality of pixel units arranged in an array. Each of the image sensors has a readout circuit connected to a plurality of pixel units arranged in a column, and each of the image sensors has a readout circuit also connected to the control circuit.

[0018] Optionally, the pixel unit includes a photosensitive unit, a reset unit, an overflow unit, a gain unit, a readout unit, and a floating diffusion node; The photosensitive unit, the gain unit, and the readout unit are connected to the floating diffusion node. The overflow unit is connected to the first power supply potential through the reset unit. The readout unit is also connected to the second power supply potential and the readout circuit of the image sensor.

[0019] The beneficial effects of the present invention embodiments compared with the prior art are as follows: The readout circuit of the above-mentioned image sensor is connected to the pixel unit and includes a ramp voltage circuit, a comparator circuit, a counter circuit and a switching circuit. The switching circuit can be connected to the front end of the comparator circuit or connected between the comparator circuit and the counter circuit. The first input terminal and the second input terminal of the comparator circuit are connected to the pixel unit and the ramp voltage circuit in opposite ways in the first conversion gain mode and the second conversion gain mode, respectively, or output to the counter circuit with a comparison signal of opposite polarity. This realizes correlated double sampling in the first conversion gain mode and uncorrelated double sampling in the second conversion gain mode, eliminates the coupling effect of ground potential fluctuation signal, improves quantization accuracy and improves the image display effect of the image sensor. Attached Figure Description

[0020] Figure 1 A circuit diagram of a pixel unit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the pixel unit quantization waveform provided in an embodiment of the present invention; Figure 3 A schematic diagram of a first module of the readout circuit of an image sensor provided in an embodiment of the present invention; Figure 4 A schematic diagram of a second module of the readout circuit of an image sensor provided in an embodiment of the present invention; Figure 5 A first waveform diagram of the readout circuit of the image sensor provided in an embodiment of the present invention; Figure 6 A second waveform diagram of the readout circuit of the image sensor provided in an embodiment of the present invention; Figure 7 This is a third waveform diagram of the readout circuit of the image sensor provided in an embodiment of the present invention; Figure 8 A first circuit diagram of the readout circuit of an image sensor provided in an embodiment of the present invention; Figure 9 A second circuit diagram of the readout circuit of the image sensor provided in an embodiment of the present invention; Figure 10 This is a third circuit diagram of the readout circuit of the image sensor provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of an image sensor module provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] A first aspect of the present invention provides a readout circuit 1 for an image sensor, which is connected to a pixel unit.

[0024] Among them, such as Figure 1 As shown, in an optional embodiment, as Figure 1 As shown, the pixel unit 100 includes: a photosensitive unit 110, a reset unit 120, an overflow unit 130, a gain unit 140, a readout unit 150, and a floating diffusion node FD; wherein, the photosensitive unit 110 is coupled to the floating diffusion node FD; the gain unit 140 is coupled to the floating diffusion node; the overflow unit 130 is coupled to the gain unit 140 and the reset unit 120 respectively; the reset unit 120 is coupled to the first power supply potential PIXVDD_LDO; and the readout unit 150 is coupled to the second power supply potential PIXVDD, the floating diffusion node FD, and the readout circuit 1 of the image sensor respectively.

[0025] The pixel unit 100 outputs the analog signal of the current pixel unit 100 in different gain modes in descending order of gain mode.

[0026] In one optional embodiment, the analog signals in different gain modes include: high conversion gain analog signals, low conversion gain analog signals, and ultra-low conversion gain analog signals. It is understood that conversion gain refers to the sensitivity of a pixel in converting a single photogenerated electron into an output voltage, defined as the voltage change generated per electron, typically expressed in microvolts per electron (µV / e). - Its physical essence is the capacitance of the floating diffusion node (FD). Furthermore, in this embodiment, the conversion gain of the high conversion gain analog signal is greater than that of the low conversion gain analog signal, which in turn is greater than that of the ultra-low conversion gain analog signal. Further, the high conversion gain analog signal includes: a high conversion gain reset signal hcg-rst and a high conversion gain pixel signal hcg-sig; the low conversion gain analog signal includes: a low conversion gain reset signal lcg-rst and a low conversion gain pixel signal lcg-sig; and the ultra-low conversion gain analog signal includes: an ultra-low conversion gain reset signal lofic-rst and an ultra-low conversion gain pixel signal lofic-sig. Of course, there can be two, three, four, or other different gain modes; this embodiment does not limit this.

[0027] The photosensitive unit 110 includes a transmission transistor MNtx and a photosensitive element PD; the control terminal of the transmission transistor MNtx receives a transmission control signal TX, the first terminal of the transmission transistor MNtx is coupled to a second reference potential via the photosensitive element PD, and the second terminal of the transmission transistor MNtx is coupled to a floating diffusion node FD.

[0028] In one optional embodiment, the transmission transistor MNtx is an NMOS transistor, and the photosensitive element PD is a photodiode. Correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal. Of course, it is also feasible to use other suitable devices for the transmission transistor MNtx and the photosensitive element PD, and this is not a limitation. In addition, the second reference potential is usually ground potential, but it can also be a negative potential, and there are no major restrictions on this.

[0029] Typically, the transmission transistor MNtx and the photosensitive element PD are designed in a one-to-one correspondence, and the number of transmission transistors MNtx and photosensitive elements PD can be designed according to actual needs. For example, the photosensitive element PD can be one, or it can be a shared structure formed by two, four, eight, etc. This embodiment does not limit this.

[0030] Overflow unit 130 includes overflow transistor MNlofic and overflow capacitor Clofic; the control terminal of overflow transistor MNlofic receives overflow control signal OF_CTL, the first terminal of overflow transistor MNlofic is coupled to the first power supply potential PIXVDD_LDO through the overflow capacitor Clofic and the reset unit 120, and the second terminal of overflow transistor MNlofic is coupled to the first terminal of gain transistor MNdcg of gain unit 140.

[0031] In one optional embodiment, the overflow transistor MNlofic is an NMOS transistor, the overflow capacitor Clofic is the device capacitance, and correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal. Of course, it is also possible to use other suitable devices for the overflow transistor MNlofic, and it is not limited thereto.

[0032] The reset unit 120 includes a first reset transistor MNrst1 and a second reset transistor MNrst2. The control terminal of the first reset transistor MNrst1 receives a first reset control signal RSTRST. The first terminal of the first reset transistor MNrst1 is coupled to a first power supply potential PIXVDD_LDO. The second terminal of the first reset transistor MNrst1 is coupled to the first terminal of the overflow transistor MNlofic of the overflow unit 130 and the first terminal of the overflow capacitor Cloofic. The control terminal of the second reset transistor MNrst2 receives a second reset control signal OF_RST. The first terminal of the second reset transistor MNrst2 is coupled to the first power supply potential PIXVDD_LDO. The second terminal of the second reset transistor MNrst2 is coupled to the first terminal of the overflow capacitor Cloofic and a bias voltage terminal, which is used to input a bias voltage VRM_BST.

[0033] The reset unit 120 is used to reset the photosensitive unit 110, the overflow unit 130, the gain unit 140, and the floating diffusion node FD. In an optional embodiment, the first reset transistor MNrst1 and the second reset transistor MNrst2 are NMOS transistors, with the control terminal being the gate terminal, the first terminal being the drain terminal, and the second terminal being the source terminal. Of course, other suitable devices can be used for the reset transistors, and this is not a limitation.

[0034] The gain unit 140 includes a gain transistor MNdcg; the control terminal of the gain transistor MNdcg receives a gain control signal DCG; the first terminal of the gain transistor MNdcg is coupled to the second terminal of the overflow transistor MNlofic of the overflow unit 130; the second terminal of the gain transistor MNdcg is coupled to the floating diffusion node FD, and the gain corresponding to the floating diffusion node FD is adjusted.

[0035] Gain unit 140 is used to switch between different gain modes. In an optional embodiment, the different gain modes include a high conversion gain mode, a low conversion gain mode, and an ultra-low conversion gain mode. Furthermore, it should be noted that gain unit 140 may also have more than two gain modes. In this case, any gain node with a gain greater than the lowest gain can be considered a high gain node, and any gain node with a gain less than the maximum gain can be considered a low gain node.

[0036] The readout unit 150 includes a follower transistor MNsf and a select transistor MNrs. The control terminal of the follower transistor MNsf is coupled to the floating diffusion node FD, the first terminal of the follower transistor MNsf is coupled to the second power supply potential PIXVDD, and the second terminal of the follower transistor MNsf is coupled to the first terminal of the select transistor MNrs. The control terminal of the select transistor MNrs receives the select control signal SEL, and the second terminal of the select transistor MNrs is coupled to the readout circuit 1 of the image sensor. The readout unit 150 is coupled to the floating diffusion node FD for reading out the charge signal.

[0037] In one optional embodiment, the follower transistor MNsf and the select transistor MNrs are NMOS transistors, with the control terminal being the gate terminal, the first terminal being the drain terminal, and the second terminal being the source terminal. Of course, it is also possible for the follower transistor and the select transistor to be other suitable devices, and this is not a limitation. Additionally, the second power supply potential PIXVDD is the power supply potential; of course, it can also be a variable potential, and there are no further restrictions on this.

[0038] In this embodiment, the readout unit 150 performs correlated double sampling or uncorrelated double sampling on the charge signal under different conversion gain modes. For example, in the high conversion gain mode, the charge signal is correlated double sampled to obtain a high conversion gain reset signal hcg-rst and a high conversion gain pixel signal hcg-sig; in the low conversion gain mode, the charge signal is correlated double sampled to obtain a low conversion gain reset signal lcg-rst and a low conversion gain pixel signal lcg-sig; and in the ultra-low conversion gain mode, the charge signal is uncorrelated double sampled to obtain an ultra-low conversion gain pixel signal lofic-sig and an ultra-low conversion gain reset signal lofic-rst.

[0039] Among them, such as Figure 2 As shown, pixel unit 100 outputs analog signals of the current pixel unit 100 in different gain modes in sequence according to high conversion gain mode, low conversion gain mode and ultra-low conversion gain mode.

[0040] The global timing sequence is divided into four partitions: the idle phase (IDLE), the charge preparation phase (SP), the exposure integration phase (EXPO), and the multi-gain frame readout quantization phase.

[0041] The multi-gain frame readout quantization stage includes stages one through six. Stage one is the quantization stage of the low conversion gain reset signal lcg-rst. The gain control signal DCG is high, the gain transistor MNdcg is turned on, the overflow control signal OF_CTL is low, the overflow transistor MNlofic is turned off, the second reset control signal OF_RST is high, the first reset control signal RST is low, the second reset transistor MNrst2 is turned on, the first reset transistor MNrst1 is turned off, the selection transistor MNrs is turned on, and the overflow capacitor Cloofic is disconnected from the floating diffusion node FD.

[0042] The second reset transistor MNrst2 performs a potential reset on the overflow capacitor Clofic. An additional capacitor is connected in parallel to the floating diffusion node FD to form a low conversion gain capacitor array. The read signal line bitline outputs the low conversion gain reset signal lcg-rst.

[0043] During quantization, the readout circuit 1 of the image sensor at the back end performs reset sampling for the first quantization time period. The ramp voltage circuit 200 outputs a positively decreasing ramp voltage signal vramp. The comparator circuit 300 is connected according to a related double-sampling topology, that is, the reset signal rst is connected to the second input terminal of the comparator circuit 300, and the ramp voltage signal vramp is connected to the first input terminal of the comparator circuit 300. The counter circuit 400 performs downward counting and latches the reset count value. This step acquires the dark reference level in low conversion gain mode to cancel pixel reset noise.

[0044] The second stage involves quantization of the high-conversion-gain reset signal hcg-rst. During this stage, the gain transistor MNdcg is turned off, the overflow transistor MNlofic is turned off, the second reset transistor MNrst2 is turned on again, and the selection transistor MNrs remains on. The additional capacitor is disconnected, leaving only the intrinsic small capacitance of the floating diffusion node FD. At this point, only the intrinsic small capacitance of the floating diffusion node FD participates in charge storage. The read signal line bitline outputs the high-conversion-gain reset signal hcg-rst, where the capacitance of the floating diffusion node FD is at its minimum, and the reset voltage swing is at its maximum.

[0045] The quantization working principle is consistent with the correlation dual sampling quantization topology of the low conversion gain mode. The counter circuit 400 counts down again to save the reset reference code value of the high conversion gain mode level.

[0046] The third stage is the quantization of the high conversion gain pixel signal hcg-sig. The first reset transistor MNrst1 is turned off, the gain transistor MNdcg remains off, and the overflow transistor MNlofic remains off. The floating diffusion node FD only retains the original photocharge transferred from the photosensitive element PD, without a parallel large-capacity capacitor.

[0047] The floating diffusion node (FD) stores only photoelectrons in the weak and medium light ranges. The overflow capacitor (Clofic) is completely isolated, preventing charge from flowing into the overflow capacitor (Clofic). The readout signal line (bitline) outputs the high conversion gain pixel signal (hcg-sig).

[0048] Upon entering pixel signal sig sampling, the ramp voltage signal vramp maintains the same downward ramp voltage signal vramp, the comparator circuit 300 topology remains unchanged, and the counter 410 switches to upward counting to obtain the valid signal code value of the high conversion gain mode. The high conversion gain pixel signal hcg-sig must be fully quantized before conduction. Once the high conversion gain pixel signal hcg-sig sampling is complete, the overflow transistor MNlofic is immediately pulled high and turned on, connecting the floating diffusion node FD to the overflow capacitor Clofic. All remaining high-light overflow charge in the floating diffusion node FD will instantly flow into the overflow capacitor Clofic, making it impossible to read the high conversion gain pixel signal hcg-sig independently.

[0049] The fourth stage involves quantizing the low-conversion-gain pixel signal lcg-sig, turning on the gain transistor MNdcg again, and keeping the overflow transistor MNlofic off; the floating diffusion node FD is connected in parallel with an additional capacitor, and the overflow capacitor Clofic remains isolated.

[0050] The floating diffusion node (FD) is combined with an additional capacitor to store a medium-capacity photocharge, and the readout signal line (bitline) outputs a low-conversion-gain pixel signal (lcg-sig).

[0051] During quantization, the relevant dual-sampling architecture is continued, the positive ramp remains unchanged, the counter 410 counts upward, and the differential operation is performed by combining the reset count value of the previous low conversion gain mode to eliminate the reset offset and obtain the illuminance image digital code in the low conversion gain mode.

[0052] The fifth stage is the quantization of the ultra-low conversion gain pixel signal lofic-sig, in which the gain transistor MNdcg is turned on, the overflow transistor MNlofic is turned on, and the first reset transistor MNrst1 remains off; the floating diffusion node FD is connected to the overflow capacitor Clofic, and the two are at the same potential and have mutual charge.

[0053] After the high conversion gain pixel signal hcg-sig is quantized, the overflow transistor MNlofic is turned on. All the unsaturated strong light overflow charge in the floating diffusion node FD flows into the overflow capacitor Clofic. The floating diffusion node FD and the overflow capacitor Clofic together carry a large amount of charge. The readout signal line bitline outputs the ultra-low conversion gain pixel signal lofic-sig.

[0054] The high conversion gain mode suffers from an irreversible timing issue. The underlying principle is that the overflow capacitor Clofic lacks an independent reset switch; the only clearing path is the second reset transistor MNrst2 and the bias voltage VRM_BST. If the reset quantization of the ultra-low conversion gain mode is performed first, the conduction of the second reset transistor MNrst2 will simultaneously drain all photocharge from the floating diffusion node FD and the overflow capacitor Clofic, resulting in no effective photovoltage on the readout signal bitline. Consequently, the backend cannot acquire the ultra-low conversion gain pixel signal lofic-sig. Therefore, the hardware timing is strictly enforced: the ultra-low conversion gain mode must quantize the effective pixel signal sig first, followed by the reset signal rst, completely reversing the timing of the related double sampling in the high and low conversion gain modes, which quantize the reset signal sig first and then the pixel signal sig.

[0055] The existing image sensor's readout circuit 1 lacks a switching circuit 500. Changing the input polarity and ramp direction of the comparator CMP, the inverse difference operation of quantizing the pixel signal sig first and the reset signal rst in the ultra-low conversion gain mode cannot reuse the subtraction topology of the high conversion gain mode and the low conversion gain mode. It can only ground one end of the comparator CMP and use single-ended addition to complete the quantization. The ground potential fluctuation noise is directly superimposed on the highlight signal.

[0056] The sixth stage is the quantization of the ultra-low conversion gain reset signal lofic-rst. The overflow transistor MNlofic remains on, the second reset transistor MNrst2 is on, the bias voltage VRM_BST is effective, and the selection transistor MNrs remains on. The floating diffusion node FD and the overflow capacitor Clofic are still connected.

[0057] The second reset transistor MNrst2, in conjunction with the bias voltage VRM_BST, forces a complete reset of the floating diffusion node FD and the overflow capacitor Clofic, clearing all residual strong light charge in the overflow capacitor Clofic, and outputting an ultra-low conversion gain reset signal lofic-rst from the read signal line bitline.

[0058] The conversion gain varies depending on the size of the overflow capacitor Clofic and the additional capacitor in the high conversion gain mode, low conversion gain mode and ultra-low conversion gain mode. The larger the capacitor is, the smaller the conversion gain, that is, the conversion gain is negatively correlated with the size of the capacitor connected to the pixel unit.

[0059] The existing traditional architecture uses reverse operation logic to complete the reset level sampling with the common ground as the reference. Because the sampling order is reversed from the conventional related double sampling, the polarity of the voltage difference between the two sampling segments is reversed. Finally, the counter 410 matches the voltage difference by reverse counting.

[0060] The high conversion gain mode and the low conversion gain mode follow the correlation double sampling timing sequence of the reset signal rst first and the pixel signal sig. The two ramp quantization directions are unified. The pixel signal sig and the ramp voltage can be symmetrically connected to the two ends of the differential comparator CMP to perform subtraction operation without the need to introduce an external fixed reference potential.

[0061] The timing reversal in ultra-low conversion gain mode requires sampling the pixel signal sig level first, followed by sampling the reset signal rst level, with the operational polarities of the two voltage differences being opposite. Existing traditional image sensor readout circuits lack signal path switching and pulse inversion hardware modules, making it impossible to reverse-match the ramp polarity with the comparator CMP input topology.

[0062] To adapt to the inverse difference operation logic of the pixel signal sig followed by the reset signal rst in the ultra-low conversion gain mode, the existing solution can only fix one end of the comparator CMP to the chip common ground potential, use the constant ground potential voltage as the operation reference, and rely on single-ended input addition operation to complete the inverse timing analog-to-digital conversion.

[0063] The design makes compromises to accommodate timing reversal, but the chip’s internal common ground network carries a lot of digital switching noise, inter-column crosstalk and power supply ripple. The ground potential cannot be maintained at an ideal zero potential, and the fluctuation noise will be coupled into the quantization link of the ultra-low conversion gain mode throughout the process, ultimately causing the signal-to-noise ratio of the image in the highlight area to degrade, grayscale shift and increase random noise.

[0064] To reduce noise interference, such as Figure 3 and Figure 4 As shown, in this embodiment, the readout circuit 1 of the image sensor includes: The ramp voltage circuit 200 is used to output a first ramp voltage signal and a second ramp voltage signal with opposite directions in a first conversion gain mode and a second conversion gain mode, respectively. The conversion gain of the first conversion gain mode is greater than the conversion gain of the second conversion gain mode. The comparison circuit 300 is used to compare the corresponding analog signal output by the pixel unit 100 with the corresponding ramp voltage signal vramp in different conversion gain modes, and output the comparison signal co3 in the corresponding conversion gain mode. The counter circuit 400 is used to count the received comparison signal co3 or the inverted comparison signal co3 in different conversion gain modes and output the corresponding digital code value. A switching circuit 500 is connected between the pixel unit 100, the ramp voltage circuit 200, and the comparator circuit 300. The switching circuit 500 is used to connect the first input terminal of the ramp voltage circuit 200 and the comparator circuit 300 and connect the second input terminal of the pixel unit 100 and the comparator circuit 300 in a first conversion gain mode, and to connect the second input terminal of the ramp voltage circuit 200 and the comparator circuit 300 and connect the first input terminal of the pixel unit 100 and the comparator circuit 300 in a second conversion gain mode. Alternatively, the switching circuit 500 is connected between the comparator circuit 300 and the counter circuit 400. The switching circuit 500 is used to transmit the comparison signal co3 to the counter circuit 400 in the first conversion gain mode, and to invert the comparison signal co3 and transmit it to the counter circuit 400 in the second conversion gain mode.

[0065] In this embodiment, the ramp voltage circuit 200 is the analog reference signal generation module of the readout circuit 1 of this image sensor. Its core hardware can be an on-chip integrated digital-to-analog converter and a ramp oscillation bias circuit, used to adaptively output reference ramp voltage signals vramp with two different ramp directions based on the gain mode selection signal issued by the control circuit. The specific operating conditions strictly match the three pixel modes: when the pixel unit 100 operates in the first conversion gain mode, the ramp voltage circuit 200 outputs a falling-edge positive ramp voltage signal vramp, defined as the first ramp voltage signal. The first conversion gain mode can include two parallel adaptable operating scenarios: the first conversion gain mode is a high conversion gain mode and / or a low conversion gain mode, and the second conversion gain mode is an ultra-low conversion gain mode. In the high and low conversion gain modes, the ramp signal ramp change direction remains consistent, but the magnitude can be the same or different. When the pixel unit 100 operates in the second conversion gain mode, the ramp voltage circuit 200 switches its internal bias operating point and outputs a rising-edge ramp voltage signal vramp, defined as the second ramp voltage signal. The voltage amplitude range, slope of the two types of ramp signals, and signal establishment time are completely matched with the column-level quantization standard parameters of the image sensor, except that the voltage changes completely oppositely with time. The ramp voltage circuit 200 can receive global synchronization timing signals to ensure that the ramp signal edges of all image sensor readout circuits 1 are globally synchronized, thus avoiding uneven horizontal grayscale in the image.

[0066] The comparator circuit 300 is the core analog operation module of the readout circuit 1 of the image sensor. Its input simultaneously receives the analog signal output from the front-end pixel unit 100 and the ramp voltage signal (vramp) output from the ramp voltage circuit 200. The core function of the comparator circuit 300 is to compare the amplitudes of the two analog voltage signals in real time under different conversion gain modes and generate a comparison signal (co3). When the two input voltages reach the crossover equilibrium point, the output level of the comparator circuit 300 flips, and the comparison signal (co3) switches to a pulse signal in the corresponding gain mode. This pulse signal serves as the trigger signal for the back-end counter circuit 400, determining the analog-to-digital conversion cutoff time. The comparator circuit 300 features high input impedance and low offset voltage characteristics, making it suitable for microvolt-level precision image analog signal comparison operations and suppressing column-level fixed pattern noise.

[0067] The counter circuit 400 is the digital processing module of the readout circuit 1 of the image sensor, connected to the signal output end of the comparator circuit 300. The counter circuit 400 receives the comparison signal co3 output by the comparator circuit 300, or receives the comparison signal co3 after logical inversion, and performs synchronous timing counting according to a preset counting rule, finally outputting a standard pixel digital code value. This digital code value can be directly sent to the back-end image denoising algorithm module and image fusion module to complete multi-frame HDR image fusion processing of high conversion gain frames, low conversion gain frames, and ultra-low conversion gain frames. The counter circuit 400 supports bidirectional counting configuration, enabling both upward accumulation and downward decrementing counting modes.

[0068] The switching circuit 500 has two independent and equivalent hardware routing implementation schemes, such as... Figure 3 As shown, the first optional layout of the switching circuit 500 is that the switching circuit 500 is cascaded between the pixel unit 100, the ramp voltage circuit 200, and the comparator circuit 300 to complete the switching of the front-end analog signal path. In this condition, the working logic of the switching circuit 500 is as follows: When the image sensor's readout circuit 1 operates in the first conversion gain mode (i.e., high / low conversion gain mode), the switching circuit 500 conducts the first type of signal path, connecting the analog output signal of the pixel unit 100 to the second input terminal (i.e., the inverting input terminal) of the comparator circuit 300, and simultaneously connecting the first ramp voltage signal output by the ramp voltage circuit 200 to the first input terminal (i.e., the non-inverting input terminal) of the comparator circuit 300. The image sensor's readout circuit 1 operates in correlated double sampling mode, such as... Figure 5 As shown, during the first quantization time period t1 when the reset signal rst is quantized, the digital code value obtained by the counter circuit 400 can be the first digital code value corresponding to the first comparison value. The first comparison value can be: = ; in, This represents the ramp voltage signal, and rst represents the reset signal.

[0069] During the second quantization time period t2, when the pixel signal sig is quantized, the digital code value obtained by the counter circuit 400 can be the second digital code value corresponding to the second comparison value, which can be: = ; Where sig represents the pixel signal.

[0070] During the quantization process in the first quantization time period t1 and the second quantization time period t2, the counter circuit 400 counts in opposite directions. The final quantized digital code value is the third digital code value corresponding to the third comparison value. The third comparison value is: - ; in, The change in the level of the pixel signal sig after removing the reset signal rst.

[0071] When operating in the second conversion gain mode, also known as the ultra-low conversion gain mode, the switching circuit 500 flips the conduction path, swapping the two signal input ports. The analog output signal of the pixel unit 100 is connected to the first input terminal (non-inverting input) of the comparator circuit 300, while the second ramp voltage signal output from the ramp voltage circuit 200 is connected to the second input terminal (inverting input) of the comparator circuit 300. Through this input topology swap, the original addition quantization circuit is uniformly converted into a subtraction quantization circuit, eliminating the ground connection link of the comparator circuit 300.

[0072] The second ramp voltage signal is in the opposite direction to the first ramp voltage signal, such as Figure 6 As shown, a reverse ramp voltage signal vramp, starting from a low level and rising, is used. The image sensor's readout circuit 1 operates in a non-correlated double sampling mode. The rising process of the second ramp voltage signal is used to quantize the pixel signal sig. The digital code value obtained by the counter circuit 400 can be the fourth digital code value corresponding to the fourth comparison value. The fourth comparison value can be: = sig- ; During the second quantization time period t2, when the reset signal rst is quantized, the digital code value obtained by the counter circuit 400 can be the fifth digital code value corresponding to the fifth comparison value. The fifth comparison value can be: = rst- ; During the quantization process in the first quantization time period t1 and the second quantization time period t2, the counter circuit 400 performs counts in opposite directions respectively. The final quantized digital code value is the sixth digital code value corresponding to the sixth comparison value. The sixth comparison value is: - .

[0073] By changing the ramp direction of the ramp voltage signal vramp, the readout circuit 1 of the image sensor operates in an uncorrelated double sampling mode, eliminating the need to connect to the reference ground potential. In the final quantization result, the change caused by the reference ground potential being connected to the inverting input of the comparator CMP can be eliminated, thus eliminating the coupling effect of the ground potential fluctuation signal, improving quantization accuracy, and enhancing the image display effect of the image sensor.

[0074] Another way to configure the switching circuit 500 is to cascade it between the comparator circuit 300 and the counter circuit 400, without changing the wiring topology of all analog signals at the front end, such as... Figure 4 As shown, the analog output signal of pixel unit 100 is connected to the second input terminal of comparator circuit 300, and the first ramp voltage signal output by ramp voltage circuit 200 is connected to the first input terminal of comparator circuit 300. Under this condition, the working logic of switching circuit 500 is as follows: when the device is working in the first conversion gain mode, switching circuit 500 is directly turned on, and the comparison signal co3 output by comparator circuit 300 is directly transmitted to the back-end counter circuit 400 to complete the counting.

[0075] The image sensor's readout circuit 1 operates in correlated double sampling mode, such as... Figure 5 As shown, during the first quantization time period t1 when the reset signal rst is quantized, the digital code value obtained by the counter circuit 400 can be the first digital code value corresponding to the first comparison value. The first comparison value can be: = ; During the second quantization time period t2, when the pixel signal sig is quantized, the digital code value obtained by the counter circuit 400 can be the second digital code value corresponding to the second comparison value, which can be: = ; During the quantization process in the first quantization time period t1 and the second quantization time period t2, the counter circuit 400 counts in opposite directions. The final quantized digital code value is the third digital code value corresponding to the third comparison value. The third comparison value is: - ; in, The change in the level of the pixel signal sig after removing the reset signal rst.

[0076] When the device operates in the second conversion gain mode, the switching circuit 500 acquires the comparison signal co3 output by the comparator circuit 300, performs hardware logic inversion to generate an inverted comparison signal co3, and then transmits the inverted comparison signal co3 to the back-end counter circuit 400 to complete quantization counting with the same precision. This solution requires no modification to the front-end analog circuit wiring and is compatible to the greatest extent with existing mature CMOS pixel-level analog layouts.

[0077] The second ramp voltage signal is in the opposite direction to the first ramp voltage signal, such as Figure 7As shown, a reverse ramp voltage signal vramp, starting from a low level and rising, is used. The image sensor's readout circuit 1 operates in a non-correlated double sampling mode. The rising process of the second ramp voltage signal is used to measure the pixel signal sig. During the first quantization time period t1, when quantizing the pixel signal sig, the digital code value obtained by the counter circuit 400 can be the inverted value of the fourth digital code value corresponding to the fourth comparison value. The inverted value of the fourth comparison value can be: = -( -sig); During the second quantization time period t2, when the reset signal rst is quantized, the digital code value obtained by the counter circuit 400 can be the fifth digital code value corresponding to the inverted value of the fifth comparison value. The inverted value of the fifth comparison value can be: = -( ) ; During the quantization process in the first quantization time period t1 and the second quantization time period t2, the counter circuit 400 performs counts in opposite directions respectively. The final quantized digital code value is the sixth digital code value corresponding to the sixth comparison value. The sixth comparison value is: - .

[0078] By changing the ramp direction of the ramp voltage signal vramp and switching the output polarity of the comparison signal co3, the readout circuit 1 of the image sensor operates in an uncorrelated double sampling mode. It does not require connection to the reference ground potential. In the final quantization result, the change caused by the reference ground potential being connected to the inverting input of the comparator CMP can be eliminated, thus eliminating the coupling effect of the ground potential fluctuation signal, improving the quantization accuracy, and improving the image display effect of the image sensor.

[0079] Among them, the ramp voltage circuit 200 can output ramp voltage signals vramp of different magnitudes and directions in different quantization modes and different quantization periods. The analog signals corresponding to the gain conversion mode include the reset signal rst output in the first quantization period t1 and the pixel signal sig output in the second quantization period t2 in the corresponding gain conversion mode. like Figures 5 to 7 As shown, the ramp voltage circuit 200 is used for: During the first quantization time period t1 and the second quantization time period t2 of the first conversion gain mode, the first sub-slope voltage signal vramp1 and the second sub-slope voltage signal vramp2 are output respectively. The slope direction of the first sub-slope voltage signal vramp1 and the slope direction of the second sub-slope voltage signal vramp2 are the same. During the first quantization time period t1 and the second quantization time period t2 in the second conversion gain mode, the third sub-slope voltage signal vramp3 and the fourth sub-slope voltage signal vramp4 are output respectively. The slope direction of the third sub-slope voltage signal vramp3 is the same as that of the fourth sub-slope voltage signal vramp4, and the slope direction of the third sub-slope voltage signal vramp3 is opposite to that of the first sub-slope voltage signal vramp1. The comparator circuit 300 is used to compare the corresponding reset signal rst and pixel signal sig with the corresponding sub-slope voltage signal during the first quantization time period t1 and the second quantization time period t2 in the corresponding conversion gain mode, and output the reset pulse signal and pixel pulse signal in the corresponding conversion gain mode. The counter circuit 400 is used to count the received reset pulse signal or the inverted reset pulse signal in a first counting mode during the first quantization time period t1 and the second quantization time period t2 in the corresponding conversion gain mode, and to count the received pixel pulse signal or the inverted pixel pulse signal in a second counting mode. The first counting mode and the second counting mode are one of downward counting and upward counting, respectively.

[0080] In this embodiment, CO3 represents the comparison signal output by the comparator circuit 300, cmp_en represents the counting enable signal, cmpout represents the comparison value after logical operation of the comparison signal CO3 and the counting enable signal cmp_en, bitline represents the readout signal line, which is connected to the pixel unit 100 and transmits the reset signal RST and the pixel signal SIG. VRAMP represents the ramp voltage signal. Within any type of conversion gain quantization cycle, the pixel unit 100 outputs two timing-independent analog signals, corresponding to two non-overlapping quantization time periods. During the first quantization time period t1, the pixel unit 100 outputs the reset signal RST, which is the reference voltage level after the FD reset operation, representing the dark reference potential of the pixel circuit. During the second quantization time period t2, the pixel unit 100 outputs the valid pixel signal SIG, which is the valid imaging analog signal generated by the charge-voltage conversion of the FD after the photodiode photoelectric conversion and charge transfer are completed. The final valid imaging signal of the image sensor is the voltage difference between the pixel signal SIG and the reset signal RST, which can eliminate pixel reset noise and inherent device offset voltage.

[0081] The ramp voltage circuit 200 has the capability of time-synchronized hierarchical output. Within two quantization time periods in the same gain mode, it outputs sub-ramp voltage signals with the same direction, slope, and different initial levels. In the first conversion gain mode (high and low conversion gain modes), the first sub-ramp voltage signal vramp1 is output during the first quantization time period t1, and the second sub-ramp voltage signal vramp2 is output during the second quantization time period t2. Both sub-ramp voltage signals are falling-edge positive ramp signals, with identical ramp change direction and signal slope. Only the initial bias voltage VRM_BST is adaptively configured based on the pixel output swing. In the second conversion gain mode (ultra-low conversion gain mode), the third sub-ramp voltage signal vramp3 is output during the first quantization time period t1, and the fourth sub-ramp voltage signal vramp4 is output during the second quantization time period t2. Both sub-ramp voltage signals are rising-edge reverse ramp voltage signals vramp, with identical ramp change direction and signal slope. The overall slope direction of the third sub-slope voltage signal vramp3 and the fourth sub-slope voltage signal vramp4 is completely opposite to the slope direction of the first sub-slope voltage signal vramp1 and the second sub-slope voltage signal vramp2.

[0082] The comparator circuit 300 performs amplitude comparison of the two signals in stages according to the timing sequence. During the first quantization time period t1 of each conversion gain mode, the comparator circuit 300 compares the reset signal rst with the corresponding sub-slope voltage signal, and outputs a reset pulse signal after reaching the flip threshold. During the second quantization time period t2 of each conversion gain mode, the comparator circuit 300 compares the pixel signal sig with the corresponding sub-slope voltage signal, and outputs a pixel pulse signal after reaching the flip threshold. No external fixed reference ground potential is required throughout the entire operating cycle, and there is no ground noise coupling path.

[0083] The counter circuit 400 is configured with two mutually exclusive fixed counting methods: upward accumulation counting and downward decrement counting. During the first quantization time period t1 of the arbitrary gain mode, the counter 410 executes the first counting method on the received reset pulse signal or an inverted reset pulse signal. During the second quantization time period t2 of the arbitrary gain mode, the counter circuit 400 executes the second counting method on the received pixel pulse signal or an inverted pixel pulse signal. The two counting methods work together, with the reset signal rst counting downwards and the pixel signal sig counting upwards. Finally, the difference between the two count values ​​is used to cancel out the inherent bias of the circuit and the reference level deviation, accurately extracting the effective voltage change of the pixel photoelectric conversion.

[0084] The comparator circuit 300, counter circuit 400, and switching circuit 500 can adopt corresponding comparator CMP, counter 410, switch, and other structures. In an optional embodiment, such as... Figure 8As shown, the switching circuit 500 is connected between the pixel unit 100, the ramp voltage circuit 200 and the comparison circuit 300. The comparison circuit 300 includes a comparator CMP, a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 forms the first input terminal of the comparator circuit 300, the first terminal of the second capacitor C2 forms the second input terminal of the comparator circuit 300, the second terminal of the first capacitor C1 is connected to the non-inverting input terminal of the comparator CMP, the second terminal of the second capacitor C2 is connected to the inverting input terminal of the comparator CMP, and the output terminal of the comparator CMP forms the output terminal of the comparator circuit 300.

[0085] The counter circuit 400 includes an AND gate U1 and a counter 410; The first input terminal of AND gate U1 forms the first input terminal of counter circuit 400. The second input terminal of AND gate U1 is used to input the counting enable signal cmp_en. The output terminal of AND gate U1 is connected to counter 410. Counter 410 is used to count down and count up on the corresponding input comparison signal co3 during the first quantization time period t1 and the second quantization time period t2 in the corresponding conversion gain mode, respectively.

[0086] The switching circuit 500 includes a first switch K1, a second switch K2, a third switch K3, and a fourth switch K4; The first terminal of the first switch K1 and the first terminal of the second switch K2 are connected to the pixel unit 100. The first terminal of the third switch K3 and the first terminal of the fourth switch K4 are connected to the output terminal of the ramp voltage circuit 200. The second terminal of the first switch K1 and the second terminal of the third switch K3 are connected to the first input terminal of the comparator circuit 300. The second terminal of the second switch K2 and the second terminal of the fourth switch K4 are connected to the second input terminal of the comparator circuit 300.

[0087] In this embodiment, the second terminal of the first capacitor C1 is electrically connected to the non-inverting input terminal of the comparator CMP, and the second terminal of the second capacitor C2 is electrically connected to the inverting input terminal of the comparator CMP. The signal output pin of the comparator CMP is defined as the signal output terminal of the entire comparator circuit 300, which outputs a level-flipping pulse to the subsequent counter circuit 400.

[0088] The first capacitor C1 and the second capacitor C2 can sample and latch the analog voltage and ramp reference voltage output by pixel unit 100 in real time, isolating the output impedance of the front-stage pixel circuit and the input impedance of the rear-stage comparator CMP, and suppressing voltage glitches and high-frequency crosstalk during column-level signal transmission. Simultaneously, the dual-capacitor structure can store instantaneous sampling levels, ensuring that the reference signal and pixel signal sig timing are aligned within two quantization time intervals, avoiding quantization errors caused by signal setup delay. This hardware topology is fully compatible with standard correlated dual-sampling architectures in high-conversion-gain and low-conversion-gain modes, and also adapts to uncorrelated dual-sampling architectures with reverse ramps in ultra-low conversion-gain mode. No hardware topology modifications are required for any scenario.

[0089] To address the inherent input offset voltage problem in the image sensor comparator (CMP), in an optional embodiment, the comparator circuit 300 further includes a first zero-adjustment switch SW1 and a second zero-adjustment switch SW2. The first zero-adjustment switch SW1 is connected between the non-inverting input terminal and the first output terminal of the comparator CMP, and the second zero-adjustment switch SW2 is connected between the inverting input terminal and the second output terminal of the comparator CMP. The first output terminal of the comparator CMP constitutes the output terminal of the comparator circuit 300.

[0090] The first zero-adjustment switch SW1 is connected between the non-inverting input terminal of the comparator CMP and the signal output terminal of the comparator circuit 300, forming a positive feedback offset zero-adjustment loop; the second zero-adjustment switch SW2 is connected between the inverting input terminal of the comparator CMP and the signal output terminal of the comparator circuit 300, forming a negative feedback offset zero-adjustment loop.

[0091] During the pre-frame reset phase of the image sensor, two zero-adjustment switches are simultaneously turned on, temporarily clamping the positive and negative input terminals of the comparator CMP to the output reference potential of the comparator circuit 300, eliminating the static input offset voltage introduced by the transistor process mismatch of the comparator CMP. During the quantization phase, the two zero-adjustment switches are simultaneously turned off, without affecting the comparison operation between the normal ramp signal and the pixel signal sig. This structure can further reduce column-level fixed pattern noise, making it suitable for mass production scenarios of high-resolution large-array CMOS image sensors.

[0092] The first signal input terminal of AND gate U1 serves as the signal input terminal of the entire counter circuit 400, and is connected to the comparison signal co3 output by the pre-stage comparator circuit 300; the second input terminal of AND gate U1 is connected to the counting enable signal cmp_en output by the control circuit 3 of the image sensor. The entire counter circuit 400 will only start counting when the counting enable signal cmp_en is pulled high and valid; the signal output terminal of AND gate U1 is directly connected to the signal input terminal of counter 410.

[0093] After the counting enable signal cmp_en is valid, the AND gate U1 sends the front-end comparison signal co3 to the counter 410. The counter 410 operates according to a specified timing sequence: during the first quantization time period t1, it receives a reset pulse signal and performs a downward count; during the second quantization time period t2, it receives a pixel pulse signal and performs an upward count. This counter circuit 400 is a through-type, non-inverting topology, suitable for the first type of front-end signal switching architecture. Its digital link timing is simple, and its logic delay is extremely small, making it suitable for high-speed frame rate CMOS imaging scenarios.

[0094] The switching circuit 500 is switched to different input terminals of the comparator circuit 300 under different conversion gain modes. In the first conversion gain mode, the second switch K2 and the third switch K3 are turned on simultaneously, and the first switch K1 and the fourth switch K4 are turned off simultaneously. The ramp voltage circuit 200 is connected to the first input terminal of the comparator circuit 300, i.e., the positive input terminal, and the pixel unit 100 is connected to the second input terminal of the comparator circuit 300, i.e., the inverting input terminal, thereby forming a standard correlated double sampling subtraction operation topology.

[0095] like Figure 5 As shown, during the first quantization time period t1 when the reset signal rst is quantized, the digital code value obtained by counter 410 can be the first digital code value corresponding to the first comparison value obtained after the comparison by comparator CMP and the logical operation by AND gate U1. The first comparison value can be: = ; During the second quantization time period t2, when the pixel signal sig is quantized, the digital code value obtained by counter 410 can be the second digital code value corresponding to the second comparison value obtained after the comparison by comparator CMP and the logical operation by AND gate U1. The second comparison value can be: = ; During the quantization process in the first quantization time period t1 and the second quantization time period t2, the counter 410 counts down and up respectively, and the final quantized digital code value is the third digital code value corresponding to the third comparison value. The third comparison value is: - ; in, The change in the level of the pixel signal sig after removing the reset signal rst.

[0096] In the second conversion gain mode, the first switch K1 and the fourth switch K4 are simultaneously turned on, while the second switch K2 and the third switch K3 are simultaneously turned off. Pixel unit 100 is connected to the first input terminal (non-inverting input terminal) of comparator circuit 300, and ramp voltage circuit 200 is connected to the second input terminal (inverting input terminal) of comparator circuit 300, forming an uncorrelated double-sampling subtraction operation topology for ultra-low conversion gain mode. The entire switching process does not disrupt the pixel integration exposure state and can complete the switching of the three gain mode circuit topology within the same pixel integration period.

[0097] At this point, the second ramp voltage signal is in the opposite direction to the first ramp voltage signal; that is, a reverse ramp voltage signal vramp that rises from a low level is used. The rising process of the second ramp voltage signal is used to measure the pixel signal sig, such as... Figure 6 As shown, during the first quantization time period t1 when the pixel signal sig is quantized, the digital code value obtained by the counter circuit 400 can be the fourth digital code value corresponding to the fourth comparison value obtained after the comparison by the comparator CMP and the logical operation by the AND gate U1. The fourth comparison value can be: = sig- ; During the second quantization time period t2, when the reset signal rst is quantized, the digital code value obtained by the counter circuit 400 can be the fifth digital code value corresponding to the fifth comparison value obtained after the comparison by comparator CMP and the logical operation by AND gate U1. The fifth comparison value can be: = rst- ; During the quantization process in the first quantization time period t1 and the second quantization time period t2, the counter 410 performs counts in opposite directions respectively. The final quantized digital code value is the sixth digital code value corresponding to the sixth comparison value. The sixth comparison value is: - .

[0098] By changing the ramp direction of the ramp voltage signal vramp, the readout circuit 1 of the image sensor operates in an uncorrelated double sampling mode, eliminating the need to connect to the reference ground potential. In the final quantization result, the change caused by the reference ground potential being connected to the inverting input of the comparator CMP can be eliminated, thus eliminating the coupling effect of the ground potential fluctuation signal, improving quantization accuracy, and enhancing the image display effect of the image sensor.

[0099] In another alternative embodiment, such as Figure 9 As shown, the counter circuit 400 can also select NAND gate U2, first NOT gate U3 and counter 410; The first input terminal of NAND gate U2 forms the first input terminal of counter circuit 400. The second input terminal of NAND gate U2 is used to input the counting enable signal cmp_en. The output terminal of NAND gate U2 is connected to the input terminal of first NOT gate U3. The output terminal of first NOT gate U3 is connected to counter 410. Counter 410 is used to count down and count up on the corresponding input comparison signal co3 during the first quantization time period t1 and the second quantization time period t2 in the corresponding conversion gain mode, respectively.

[0100] In this embodiment, the first input terminal of the NAND gate U2 serves as the total input terminal of the counter circuit 400, and is connected to the comparison signal co3 output by the pre-stage comparator circuit 300; the second input terminal of the NAND gate U2 receives the counting enable signal cmp_en; the output terminal of the NAND gate U2 is connected to the input port of the first NOT gate U3. After the first NOT gate U3 completes the level logic flip, it sends the normalized comparison signal co3 to the back-end synchronous bidirectional counter 410.

[0101] By utilizing the combinational logic circuit of NAND gate U2 and first NOT gate U3, the function of AND gate U1 is equivalently completed. Counter 410 maintains its original bidirectional counting rules, and the reverse ramp quantization output level is adapted through the pre-amplifier digital logic circuit, without modifying the internal timing configuration of counter 410.

[0102] In another alternative embodiment, such as Figure 10 As shown, the comparator circuit 300 includes a comparator CMP, a first capacitor C1, and a second capacitor C2. The first terminal of the first capacitor C1 forms the first input terminal of the comparator circuit 300, the first terminal of the second capacitor C2 forms the second input terminal of the comparator circuit 300, the second terminal of the first capacitor C1 is connected to the non-inverting input terminal of the comparator CMP, the second terminal of the second capacitor C2 is connected to the inverting input terminal of the comparator CMP, and the output terminal of the comparator CMP forms the output terminal of the comparator circuit 300.

[0103] The counter circuit 400 includes an AND gate U1 and a counter 410; The first input terminal of AND gate U1 forms the first input terminal of counter circuit 400. The second input terminal of AND gate U1 is used to input the counting enable signal cmp_en. The output terminal of AND gate U1 is connected to counter 410. Counter 410 is used to count down and count up on the corresponding input comparison signal co3 during the first quantization time period t1 and the second quantization time period t2 in the corresponding conversion gain mode, respectively.

[0104] The switching circuit 500 is connected between the comparator circuit 300 and the counter circuit 400; The switching circuit 500 includes a second NOT gate U4, a fifth switch K5, and a sixth switch K6; The first terminal of the fifth switch K5, the first terminal of the sixth switch K6, and the output terminal of the comparator circuit 300 are connected. The second terminal of the fifth switch K5 is connected to the input terminal of the second NOT gate U4. The output terminal of the second NOT gate U4, the second terminal of the sixth switch K6, and the input terminal of the counter circuit 400 are connected.

[0105] The input pin of the second NOT gate U4 and the first pin of the fifth switch K5 are simultaneously connected to the 300 pulse output terminal of the comparator circuit; the output pin of the second NOT gate U4 and the second pin of the fifth switch K5 are simultaneously connected to the 400 input terminal of the back-end counter circuit.

[0106] In this embodiment, the second terminal of the first capacitor C1 is electrically connected to the non-inverting input terminal of the comparator CMP, and the second terminal of the second capacitor C2 is electrically connected to the inverting input terminal of the comparator CMP. The signal output pin of the comparator CMP is defined as the signal output terminal of the entire comparator circuit 300, which outputs a level-flipping pulse to the subsequent counter circuit 400.

[0107] The first capacitor C1 and the second capacitor C2 can sample and latch the analog voltage and ramp reference voltage output by pixel unit 100 in real time, isolating the output impedance of the front-stage pixel circuit and the input impedance of the rear-stage comparator CMP, and suppressing voltage glitches and high-frequency crosstalk during column-level signal transmission. Simultaneously, the dual-capacitor structure can store instantaneous sampling levels, ensuring that the reference signal and pixel signal sig timing are aligned within two quantization time intervals, avoiding quantization errors caused by signal setup delay. This hardware topology is fully compatible with standard correlated dual-sampling architectures in high-conversion-gain and low-conversion-gain modes, and also adapts to uncorrelated dual-sampling architectures with reverse ramps in ultra-low conversion-gain mode. No hardware topology modifications are required for any scenario.

[0108] To address the inherent input offset voltage problem in the image sensor comparator (CMP), in an optional embodiment, the comparator circuit 300 further includes a first zero-adjustment switch SW1 and a second zero-adjustment switch SW2. The first zero-adjustment switch SW1 is connected between the non-inverting input terminal and the first output terminal of the comparator CMP, and the second zero-adjustment switch SW2 is connected between the inverting input terminal and the second output terminal of the comparator CMP. The first output terminal of the comparator CMP constitutes the output terminal of the comparator circuit 300.

[0109] The first zero-adjustment switch SW1 is connected between the non-inverting input terminal of the comparator CMP and the signal output terminal of the comparator circuit 300, forming a positive feedback offset zero-adjustment loop; the second zero-adjustment switch SW2 is connected between the inverting input terminal of the comparator CMP and the signal output terminal of the comparator circuit 300, forming a negative feedback offset zero-adjustment loop.

[0110] During the pre-frame reset phase of the image sensor, two zero-adjustment switches are simultaneously turned on, temporarily clamping the positive and negative input terminals of the comparator CMP to the output reference potential of the comparator circuit 300, eliminating the static input offset voltage introduced by the transistor process mismatch of the comparator CMP. During the quantization phase, the two zero-adjustment switches are simultaneously turned off, without affecting the comparison operation between the normal ramp signal and the pixel signal sig. This structure can further reduce column-level fixed pattern noise, making it suitable for mass production scenarios of high-resolution large-array CMOS image sensors.

[0111] The first signal input terminal of AND gate U1 serves as the signal input terminal of the entire counter circuit 400, and is connected to the comparison signal co3 output by the pre-stage comparator circuit 300; the second input terminal of AND gate U1 is connected to the counting enable signal cmp_en output by the control circuit 3 of the image sensor. The entire counter circuit 400 will only start counting when the counting enable signal cmp_en is pulled high and valid; the signal output terminal of AND gate U1 is directly connected to the signal input terminal of counter 410.

[0112] After the counting enable signal cmp_en is valid, the AND gate U1 sends the front-end comparison signal co3 to the counter 410. The counter 410 operates according to a specified timing sequence: during the first quantization time period t1, it receives a reset pulse signal and performs a downward count; during the second quantization time period t2, it receives a pixel pulse signal and performs an upward count. This counter circuit 400 is a through-type, non-inverting topology, suitable for the first type of front-end signal switching architecture. Its digital link timing is simple, and its logic delay is extremely small, making it suitable for high-speed frame rate CMOS imaging scenarios.

[0113] In the first conversion gain mode, the fifth switch K5 is turned on, the sixth switch K6 is turned off, the logic path of the second NOT gate U4 is closed, and the comparison signal co3 output by the comparator CMP is directly fed into the counter circuit 400.

[0114] The image sensor's readout circuit 1 operates in correlated double sampling mode. During the first quantization time period t1, when quantizing the reset signal rst, as follows... Figure 5 As shown, the digital code value obtained by counter 410 can be the first digital code value corresponding to the first comparison value obtained by comparator CMP comparison and AND gate U1 logic operation. The first comparison value can be: = ; During the second quantization time period t2, when the pixel signal sig is quantized, the digital code value obtained by the counter circuit 400 can be the second digital code value corresponding to the second comparison value obtained by the logic operation of comparator CMP and AND gate U1. The second comparison value can be: = ; During the quantization process in the first quantization time period t1 and the second quantization time period t2, the counter 410 counts in opposite directions. The final quantized digital code value is the third digital code value corresponding to the third comparison value. The third comparison value is: - ; in, The change in the level of the pixel signal sig after removing the reset signal rst.

[0115] In the second conversion gain mode, the fifth switch K5 is open and the sixth switch K6 is open. The comparison signal CO3 passes through the second NOT gate U4 to complete the logic level flip, generating an inverted comparison signal CO3 which is sent to the counter circuit 400.

[0116] The image sensor's readout circuit 1 operates in non-correlated double sampling mode. At this time, such as... Figure 7 As shown, the second ramp voltage signal output by the ramp voltage circuit 200 is in the opposite direction to the first ramp voltage signal, that is, a reverse ramp voltage signal vramp that rises from a low level is used. The rising process of the second ramp voltage signal is used to measure the pixel signal sig. When quantizing the pixel signal sig during the first quantization time period t1, the digital code value obtained by the counter 410 can be the fourth digital code value corresponding to the fourth comparison value obtained by the comparator CMP comparison and the AND gate U1 logic operation. The fourth comparison value can be: = -( -sig); During the second quantization time period t2 when the reset signal rst is quantized, the digital code value obtained by counter 410 can be the fifth digital code value corresponding to the inverted value of the fifth comparison value obtained by comparator CMP and AND gate U1 logic operation. The inverted value of the fifth comparison value can be: = -( ) ; During the quantization process in the first quantization time period t1 and the second quantization time period t2, the counter 410 performs counts in opposite directions respectively. The final quantized digital code value is the sixth digital code value corresponding to the sixth comparison value. The sixth comparison value is: - .

[0117] By changing the ramp direction of the ramp voltage signal vramp and switching the output polarity of the comparison signal co3, the readout circuit 1 of the image sensor operates in an uncorrelated double sampling mode. It does not require connection to the reference ground potential. In the final quantization result, the change caused by the reference ground potential being connected to the inverting input of the comparator CMP can be eliminated, thus eliminating the coupling effect of the ground potential fluctuation signal, improving the quantization accuracy, and improving the image display effect of the image sensor.

[0118] In another alternative embodiment, a combinational logic circuit of NAND gate U2 and first NOT gate U3 can be used to equivalently complete the function of AND gate U1. Counter 410 maintains its original bidirectional counting rules and adapts the reverse ramp quantization output level through the pre-amplifier digital logic circuit without modifying the internal timing configuration of counter 410.

[0119] A second aspect of the present invention provides an image sensor, such as... Figure 11 As shown, the image sensor includes a pixel array 2, a control circuit 3, and multiple image sensor readout circuits 1. The specific structure of the image sensor readout circuit 1 is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. Among them, the pixel array 2 includes multiple pixel units 100 arranged in an array; Each image sensor's readout circuit 1 is connected to a plurality of pixel units 100 arranged in a column, and each image sensor's readout circuit 1 is also connected to a control circuit 3.

[0120] In this embodiment, the pixel array 2 is composed of pixel units 100 arranged in a two-dimensional matrix array, arranged in a standard grid structure of rows and columns, to complete the photoelectric conversion of optical signals to charge signals; the control circuit 3 outputs all global control commands, including reset timing, integral control timing, mode switching signal, count enable signal cmp_en, and ramp bias control signal; the image internally integrates multiple independent image sensor readout circuits 1, and the number of image sensor readout circuits 1 corresponds one-to-one with the number of columns in the pixel array 2.

[0121] The readout circuit 1 of a single-channel image sensor is connected to all pixel units 100 in a row of the pixel array 2 through the readout signal line bitline to complete the row-by-row readout and analog quantization of the pixel signal sig in the column; all readout circuits 1 of all image sensors are electrically connected to the control circuit 3 to synchronously receive control commands and synchronously feedback the quantization completion flag signal and pixel digital code value.

[0122] The workflow is as follows: pixel array 2 completes photoelectric integration to generate multi-gain analog signals, control circuit 3 issues corresponding mode switching instructions, image sensor readout circuit 1 completes correlated double sampling or non-correlated double sampling analog quantization, and multiple digital code values ​​are summarized and sent to the back-end image fusion processor to output wide dynamic range images.

[0123] The quantization logic of all columns of circuits in the entire image sensor is unified. The ultra-low gain pixel signal sig in the highlight area is free from ground noise interference, and the high gain signal in the dark area retains the original low noise characteristics. The overall imaging dynamic range and quantization signal-to-noise ratio of the image sensor are significantly improved.

[0124] The pixel unit 100 may include a corresponding photosensitive unit 110, a reset unit 120, a readout unit 150, etc. In an optional embodiment, the pixel unit 100 includes a photosensitive unit 110, a reset unit 120, an overflow unit 130, a gain unit 140, a readout unit 150, and a floating diffusion node FD. The photosensitive unit 110, the gain unit 140, and the readout unit 150 are connected to the floating diffusion node FD. The overflow unit 130 is connected to the first power supply potential PIXVDD_LDO through the reset unit 120. The readout unit 150 is also connected to the second power supply potential PIXVDD and the readout circuit 1 of the image sensor.

[0125] The photosensitive unit 110, gain unit 140, and readout unit 150 are connected to the pixel core floating diffusion node FD. The floating diffusion node FD, as the core node for charge storage and charge-voltage conversion, determines the overall conversion gain and full-well capacity of the pixel. The overflow unit 130 is connected to the first power supply potential PIXVDD_LDO through the reset unit 120. The first power supply potential PIXVDD_LDO is the global high-voltage reset power supply for the pixel array 2. The readout unit 150 is also connected to the second power supply potential PIXVDD and the readout circuit 1 of the corresponding column-level image sensor to complete the transmission of analog signals to the external circuit.

[0126] In an optional embodiment, the photosensitive unit 110 includes a transmission transistor MNtx and a photosensitive element PD; the control terminal of the transmission transistor MNtx receives a transmission control signal TX, the first terminal of the transmission transistor MNtx is coupled to a second reference potential via the photosensitive element PD, and the second terminal of the transmission transistor MNtx is coupled to a floating diffusion node FD.

[0127] In one optional embodiment, the transmission transistor MNtx is an NMOS transistor, and the photosensitive element PD is a photodiode. Correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal. Of course, it is also feasible to use other suitable devices for the transmission transistor MNtx and the photosensitive element PD, and this is not a limitation. In addition, the second reference potential is usually ground potential, but it can also be a negative potential, and there are no major restrictions on this.

[0128] Typically, the transmission transistor MNtx and the photosensitive element PD are designed in a one-to-one correspondence, and the number of transmission transistors MNtx and photosensitive elements PD can be designed according to actual needs. For example, the photosensitive element PD can be one, or it can be a shared structure formed by two, four, eight, etc. This embodiment does not limit this.

[0129] Overflow unit 130 includes overflow transistor MNlofic and overflow capacitor Clofic; the control terminal of overflow transistor MNlofic receives overflow control signal OF_CTL, the first terminal of overflow transistor MNlofic is coupled to the first power supply potential PIXVDD_LDO through the overflow capacitor Clofic and the reset unit 120, and the second terminal of overflow transistor MNlofic is coupled to the first terminal of gain transistor MNdcg of gain unit 140.

[0130] In one optional embodiment, the overflow transistor MNlofic is an NMOS transistor, the overflow capacitor Clofic is the device capacitance, and correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal. Of course, it is also possible to use other suitable devices for the overflow transistor MNlofic, and it is not limited thereto.

[0131] The reset unit 120 includes a first reset transistor MNrst1 and a second reset transistor MNrst2. The control terminal of the first reset transistor MNrst1 receives a first reset control signal RSTRST. The first terminal of the first reset transistor MNrst1 is coupled to a first power supply potential PIXVDD_LDO. The second terminal of the first reset transistor MNrst1 is coupled to the first terminal of the overflow transistor MNlofic of the overflow unit 130 and the first terminal of the overflow capacitor Cloofic. The control terminal of the second reset transistor MNrst2 receives a second reset control signal OF_RST. The first terminal of the second reset transistor MNrst2 is coupled to the first power supply potential PIXVDD_LDO. The second terminal of the second reset transistor MNrst2 is coupled to the first terminal of the overflow capacitor Cloofic and a bias voltage terminal, which is used to input a bias voltage VRM_BST.

[0132] The reset unit 120 is used to reset the photosensitive unit 110, the overflow unit 130, the gain unit 140, and the floating diffusion node FD. In an optional embodiment, the first reset transistor MNrst1 and the second reset transistor MNrst2 are NMOS transistors, with the control terminal being the gate terminal, the first terminal being the drain terminal, and the second terminal being the source terminal. Of course, other suitable devices can be used for the reset transistors, and this is not a limitation.

[0133] The gain unit 140 includes a gain transistor MNdcg; the control terminal of the gain transistor MNdcg receives a gain control signal DCG; the first terminal of the gain transistor MNdcg is coupled to the second terminal of the overflow transistor MNlofic of the overflow unit 130; the second terminal of the gain transistor MNdcg is coupled to the floating diffusion node FD, and the gain corresponding to the floating diffusion node FD is adjusted.

[0134] Gain unit 140 is used to switch between different gain modes. In an optional embodiment, the different gain modes include a high conversion gain mode, a low conversion gain mode, and an ultra-low conversion gain mode. Furthermore, it should be noted that gain unit 140 may also have more than two gain modes. In this case, any gain node with a gain greater than the lowest gain can be considered a high gain node, and any gain node with a gain less than the maximum gain can be considered a low gain node.

[0135] The readout unit 150 includes a follower transistor MNsf and a select transistor MNrs. The control terminal of the follower transistor MNsf is coupled to the floating diffusion node FD, the first terminal of the follower transistor MNsf is coupled to the second power supply potential PIXVDD, and the second terminal of the follower transistor MNsf is coupled to the first terminal of the select transistor MNrs. The control terminal of the select transistor MNrs receives the select control signal SEL, and the second terminal of the select transistor MNrs is coupled to the readout circuit 1 of the image sensor. The readout unit 150 is coupled to the floating diffusion node FD for reading out the charge signal.

[0136] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A readout circuit for an image sensor, connected to a pixel unit, characterized in that, The readout circuit of the image sensor includes: A ramp voltage circuit is used to output a first ramp voltage signal and a second ramp voltage signal in opposite directions in a first conversion gain mode and a second conversion gain mode, respectively, wherein the conversion gain of the first conversion gain mode is greater than the conversion gain of the second conversion gain mode. The comparison circuit is used to compare the corresponding analog signal and the corresponding ramp voltage signal output by the pixel unit in different conversion gain modes, and output the comparison signal in the corresponding conversion gain mode. The counter circuit is used to count the received comparison signal or the inverted comparison signal in different conversion gain modes and output the corresponding digital code value. A switching circuit is connected between the pixel unit, the ramp voltage circuit, and the comparator circuit. The switching circuit is used to connect the first input terminal of the ramp voltage circuit and the comparator circuit and connect the second input terminal of the pixel unit and the comparator circuit in the first conversion gain mode, and to connect the second input terminal of the ramp voltage circuit and the comparator circuit and connect the first input terminal of the pixel unit and the comparator circuit in the second conversion gain mode. Alternatively, the switching circuit is connected between the comparator circuit and the counter circuit, and the switching circuit is used to transmit the comparator signal to the counter circuit in the first conversion gain mode, and to invert the comparator signal and transmit it to the counter circuit in the second conversion gain mode.

2. The readout circuit of the image sensor as described in claim 1, characterized in that, The first conversion gain mode is a high conversion gain mode and / or a low conversion gain mode, and the second conversion gain mode is an ultra-low conversion gain mode.

3. The readout circuit of the image sensor as described in claim 1, characterized in that, The analog signal in the corresponding gain conversion mode includes the reset signal output during the first quantization time period and the pixel signal output during the second quantization time period in the corresponding gain conversion mode. The ramp voltage circuit is used for: During the first quantization time period and the second quantization time period of the first conversion gain mode, a first sub-slope voltage signal and a second sub-slope voltage signal are output respectively, and the slope direction of the first sub-slope voltage signal and the slope direction of the second sub-slope voltage signal are the same. During the first and second quantization periods in the second conversion gain mode, a third sub-slope voltage signal and a fourth sub-slope voltage signal are output respectively. The slope direction of the third sub-slope voltage signal is the same as that of the fourth sub-slope voltage signal, and the slope direction of the third sub-slope voltage signal is opposite to that of the first sub-slope voltage signal. The comparison circuit is used to compare the corresponding reset signal and the pixel signal with the corresponding sub-slope voltage signal during the first quantization time period and the second quantization time period in the corresponding conversion gain mode, and output the reset pulse signal and the pixel pulse signal in the corresponding conversion gain mode. The counter circuit is used to count the received reset pulse signal or the inverted reset pulse signal in a first counting method during the first quantization time period and the second quantization time period corresponding to the conversion gain mode, and to count the received pixel pulse signal or the inverted pixel pulse signal in a second counting method, wherein the first counting method and the second counting method are respectively downward counting and upward counting.

4. The readout circuit of the image sensor as described in claim 3, characterized in that, The comparison circuit includes a comparator, a first capacitor, and a second capacitor; The first terminal of the first capacitor forms the first input terminal of the comparator circuit, the first terminal of the second capacitor forms the second input terminal of the comparator circuit, the second terminal of the first capacitor is connected to the non-inverting input terminal of the comparator, the second terminal of the second capacitor is connected to the inverting input terminal of the comparator, and the output terminal of the comparator forms the output terminal of the comparator circuit.

5. The readout circuit of the image sensor as described in claim 4, characterized in that, The comparison circuit also includes a first zero-adjustment switch and a second zero-adjustment switch. The first zero-adjustment switch is connected between the non-inverting input terminal and the first output terminal of the comparator, and the second zero-adjustment switch is connected between the inverting input terminal and the second output terminal of the comparator. The first output terminal of the comparator constitutes the output terminal of the comparator circuit.

6. The readout circuit of the image sensor as described in claim 1, characterized in that, The counter circuit includes an AND gate and a counter; The first input terminal of the AND gate constitutes the first input terminal of the counter circuit, the second input terminal of the AND gate is used to input a counting enable signal, the output terminal of the AND gate is connected to the counter, and the counter is used to count down and count up on the input comparison signal during the first quantization time period and the second quantization time period corresponding to the conversion gain mode, respectively.

7. The readout circuit of the image sensor as described in claim 1, characterized in that, The counter circuit includes a NAND gate, a first NOT gate, and a counter. The first input terminal of the NAND gate constitutes the first input terminal of the counter circuit. The second input terminal of the NAND gate is used to input a counting enable signal. The output terminal of the NAND gate is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the counter. The counter is used to count down and count up on the input comparison signal during the first quantization time period and the second quantization time period corresponding to the conversion gain mode, respectively.

8. The readout circuit of the image sensor as described in any one of claims 1 to 7, characterized in that, The switching circuit is connected between the pixel unit, the ramp voltage circuit, and the comparator circuit; The switching circuit includes a first switch, a second switch, a third switch, and a fourth switch; The first terminal of the first switch, the first terminal of the second switch, and the pixel unit are connected; the first terminal of the third switch and the first terminal of the fourth switch are connected to the output terminal of the ramp voltage circuit; the second terminal of the first switch and the second terminal of the third switch are connected to the first input terminal of the comparator circuit; and the second terminal of the second switch and the second terminal of the fourth switch are connected to the second input terminal of the comparator circuit.

9. The readout circuit of the image sensor as described in any one of claims 1 to 7, characterized in that, The switching circuit is connected between the comparator circuit and the counter circuit; The switching circuit includes a second NOT gate, a fifth switch, and a sixth switch; The first terminal of the fifth switch, the first terminal of the sixth switch, and the output terminal of the comparator circuit are connected. The second terminal of the fifth switch is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate, the second terminal of the sixth switch, and the input terminal of the counter circuit are connected.

10. An image sensor, characterized in that, It includes a pixel array, a control circuit, and a readout circuit of a plurality of image sensors as described in any one of claims 1 to 9, wherein the pixel array includes a plurality of pixel units arranged in an array; Each of the image sensors has a readout circuit that is connected to a plurality of pixel units arranged in a column, and each of the image sensors has a readout circuit that is also connected to the control circuit.

11. The image sensor as claimed in claim 10, characterized in that, The pixel unit includes a photosensitive unit, a reset unit, an overflow unit, a gain unit, a readout unit, and a floating diffusion node; The photosensitive unit, the gain unit, and the readout unit are connected to the floating diffusion node. The overflow unit is connected to the first power supply potential through the reset unit. The readout unit is also connected to the second power supply potential and the readout circuit of the image sensor.

Images