A multi-mode readout control method of an infrared thermopile array sensor, an infrared thermopile array sensor and an electronic device

Abstract

The application provides a multi-mode readout control method of an infrared thermoelectric array sensor, an infrared thermoelectric array sensor and electronic equipment, and relates to the technical field of infrared detectors, and comprises the following steps: when a first layer selection signal is a first level, entering a full-parallel readout mode, controlling all channels of a thermoelectric pixel array to synchronously perform signal sampling, conversion and on-chip RAM writing; when the first layer selection signal is a second level, entering a multi-select-one mode, dividing the thermoelectric pixel array into multiple data blocks, and further selecting a segmented cycle mode or a specified region mode according to a second layer selection signal; in the segmented cycle mode, sequentially activating each data block for readout in a preset order; in the specified region mode, only activating a data block specified by a block selection signal for readout. The application considers multiple requirements such as high speed, high precision, low power consumption and local area temperature measurement under the same readout architecture, and significantly improves the application flexibility and system energy efficiency of the sensor.

Description

Technical Field

[0001] This invention relates to the field of infrared detector technology, and in particular to a multi-mode readout control method for an infrared thermopile array sensor, an infrared thermopile array sensor, and electronic equipment. Background Technology

[0002] Infrared thermopile array sensors are uncooled infrared detectors that convert infrared radiation into electrical signals based on the Seebeck effect. They offer advantages such as no need for cooling, small size, and low cost, and are widely used in industrial temperature measurement, security monitoring, thermal imaging, and smart terminals. With the development of CMOS-MEMS integration technology, thermopile arrays and readout integrated circuits (ROICs) can be monolithically integrated on the same chip, further improving the sensor's integration level, miniaturization, and mass production consistency.

[0003] However, existing infrared thermopile array sensors still have the following shortcomings in terms of readout architecture: First, in traditional full-array parallel readout architectures, all pixel channels simultaneously acquire and output signals. Even if the application only focuses on a portion of the array, all channels remain active, resulting in persistently high power consumption. In battery-powered portable devices or scenarios requiring long-term continuous monitoring, this high power consumption severely restricts the practical application of sensors.

[0004] Second, the serial or partially parallel readout architectures used to reduce power consumption result in a significant increase in full-frame readout time and a substantial decrease in frame rate as the array size expands, making it difficult to meet the real-time requirements of high-speed imaging or dynamic target detection. Increasing readout speed usually requires increasing bias current or clock frequency, which in turn leads to increased power consumption, creating a contradiction between high speed and low power consumption.

[0005] Third, existing sensors typically only support full array output mode and lack the ability to selectively read out regions of interest (ROIs). When performing precise temperature measurement or continuous monitoring of a specific target, it is still necessary to read and process the full array data, resulting in invalid data transmission and processing overhead, which increases system power consumption and reduces measurement efficiency.

[0006] Therefore, a multi-mode readout control method for an infrared thermopile array sensor, an infrared thermopile array sensor, and electronic equipment are proposed. Summary of the Invention

[0007] This specification provides a multi-mode readout control method for an infrared thermopile array sensor, an infrared thermopile array sensor, and electronic equipment. Under the same readout architecture, it takes into account multiple requirements such as high speed, high precision, low power consumption, and local area temperature measurement, which significantly improves the application flexibility of the sensor and the system energy efficiency.

[0008] This specification provides a multi-mode readout control method for an infrared thermopile array sensor, including: Receive mode configuration signal; the mode configuration signal includes a first layer selection signal and a second layer selection signal; When the first layer selection signal is at the first level, it enters the fully parallel readout mode, controlling all channels of the thermopile pixel array to synchronously perform signal sampling, conversion and on-chip RAM writing; When the first layer selection signal is at the second level, it enters the multiple-choice mode, divides the thermopile pixel array into multiple data blocks, and further selects the segmented loop mode or the specified area mode according to the second layer selection signal. In the segmented loop mode, each data block is activated and read out in a preset order; In the specified area mode, only the data block specified by the block selection signal is activated for reading.

[0009] Optionally, dividing the thermopile pixel array into multiple data blocks includes: The thermopile pixel array is divided into L data blocks, where L=2. x Each data block contains S channels. Where x is a preset integer.

[0010] Optionally, when the first layer selection signal is at the second level, entering a multi-select mode, the thermopile pixel array is divided into multiple data blocks, including: In the multiple-choice mode, the bias current of inactive data blocks is turned off, specifically: The on-chip digital control logic generates independent bias enable signals for each data block, and applies the bias enable signals to the control terminals of the CMOS switches inserted in the bias current branches of the corresponding data blocks to turn off the bias current of inactive data blocks.

[0011] Optionally, the step of further selecting the segmented loop mode or the specified region mode based on the second layer selection signal includes: In the multiple-choice mode, the address space of the on-chip RAM is divided into L consecutive address intervals, the size of which matches the data size of a data block. In the segmented loop mode, the channel selection signal driven by the loop counter generates the number of the currently active data block. The high-order address of the on-chip RAM is provided by the channel selection signal after decoding, and is used to select the address range corresponding to the currently active data block. The low-order address is generated by the channel counter within the block incrementing sequentially. The control logic generates a block write enable signal, which only allows write operations to be performed on the address range corresponding to the currently active data block.

[0012] Optionally, the control logic generates a block write enable signal, allowing write operations only to the address range corresponding to the currently active data block, including: The block write enable signal is generated by performing a logical AND operation on the block selection signal, data valid signal, and write phase signal of the current data block. For inactive data blocks, their block selection signal is invalid, and the corresponding write enable is forced to be set to an invalid level.

[0013] Optionally, in the specified area mode, activating only the data block specified by the block selection signal for reading includes: In the specified region mode, the block selection signal is provided by an on-chip register to specify the data block number that will continue to operate, and the bias current of the remaining data blocks remains off in this mode. When the first layer selection signal is at the first level and enters the fully parallel readout mode, the second layer selection signal is ignored, and the bias current of all channels remains on.

[0014] This specification provides an infrared thermopile array sensor, including: m×n thermopile pixel array; A readout integrated circuit is connected to the thermopile pixel array. The readout integrated circuit includes a mode register, digital control logic, multiple independently enableable readout channel modules, and on-chip RAM. The mode register is used to store the first layer selection signal, the second layer selection signal, and the block selection signal; The digital control logic is configured to control the sensor to operate in one of the following modes in response to the first layer selection signal and the second layer selection signal: a fully parallel readout mode, a segmented cyclic readout mode, or a designated area readout mode. In the fully parallel readout mode, all channels synchronously perform signal sampling, conversion, and on-chip RAM writing; in the segmented cyclic readout mode, each data block is activated sequentially in a preset order for reading; in the designated area readout mode, only the data block specified by the block selection signal is activated for reading.

[0015] Optionally, the thermopile pixel array is divided into L data blocks, where L=2. x Each data block contains S channels. , where x is a preset integer; Each of the readout channel modules has a CMOS switch connected in series in the bias current branch. The bias enable signal output by the digital control logic is connected to the control terminal of the CMOS switch to independently turn the bias current on or off according to data blocks. The address space of the on-chip RAM is divided into L consecutive address intervals. The write enable signal output by the digital control logic is generated by the logical AND of the block selection signal, the data valid signal and the write phase signal, so that only the address interval corresponding to the currently active data block is written.

[0016] This specification also provides an electronic device, wherein the electronic device includes: A processor; and a memory storing computer-executable instructions, which, when executed, cause the processor to perform any of the methods described above.

[0017] This specification also provides a computer-readable storage medium that stores one or more programs that, when executed by a processor, implement any of the methods described above.

[0018] In this invention, a hierarchical control structure composed of the first-layer selection signal TP_MUX and the second-layer selection signal FRAME_FIX achieves three modes—fully parallel readout, segmented cyclic readout, and designated area readout—within the same readout integrated circuit and memory architecture. This eliminates the need to design multiple independent ROIC architectures for different application scenarios, significantly reducing chip design complexity, tape-out costs, and verification cycles. When high-speed, high-precision imaging is required, the fully parallel mode enables synchronous readout of all channels, achieving the highest frame rate and measurement accuracy. In scenarios where frame rate requirements are not high but long-term operation is necessary, the segmented cyclic mode or designated area mode can be switched to activate only some channels, significantly reducing system power consumption. The three modes can be flexibly switched according to application needs, achieving a dynamic balance between performance and power consumption. In the multi-select mode, the CMOS switch connected in series in the bias current branch of the inactive data block is turned off, causing the corresponding analog readout circuit to enter a zero-current or extremely low-current state, suppressing static power consumption at its source. Compared to simply shutting down subsequent digital processing circuits, this invention achieves power control at the analog front-end level, resulting in more significant energy savings. The write enable signal for the on-chip RAM is generated by logically ANDing the block selection signal, data valid signal, and write phase signal. Only the address range corresponding to the currently active data block is written to; RAM ranges of inactive data blocks are not updated, reducing invalid memory flip-flops and further lowering dynamic power consumption. In designated region mode, only a specific region of interest in the array can be continuously read at high speed, while the remaining regions remain dormant. This achieves accurate temperature measurement and high-frame-rate monitoring of critical targets while avoiding the acquisition and processing of invalid data, improving system measurement efficiency and flexibility. In multi-channel mode, since only some channels are active, the overall self-heating effect of the thermopile array is significantly reduced, minimizing thermal disturbances caused by chip self-heating and improving the stability and accuracy of temperature measurements. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram illustrating the principle of a multi-mode readout control method for an infrared thermopile array sensor provided in the embodiments of this specification; Figure 2 This is a schematic diagram of the structure of an infrared thermopile array sensor provided in the embodiments of this specification; Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this specification; Figure 4 This is a schematic diagram of a computer-readable medium provided for embodiments of this specification. Detailed Implementation

[0021] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0022] The following is in conjunction with the appendix Figures 1-4 Exemplary embodiments of the invention will be described more fully here. However, exemplary embodiments can be implemented in many forms and should not be construed as limiting the invention to the embodiments set forth herein. Rather, these exemplary embodiments are provided to make the invention more comprehensive and complete, and to facilitate a full communication of the inventive concept to those skilled in the art. The same reference numerals in the figures denote the same or similar elements, components, or parts, and therefore repeated descriptions of them are omitted.

[0023] Subject to the technical concept of this invention, the features, structures, characteristics or other details described in a particular embodiment may be combined in one or more other embodiments in a suitable manner.

[0024] In the description of specific embodiments, the features, structures, characteristics, or other details described in this invention are intended to enable those skilled in the art to fully understand the embodiments. However, it is not excluded that those skilled in the art can practice the technical solutions of this invention without one or more of the specific features, structures, characteristics, or other details.

[0025] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0026] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0027] The terms “and / or” or “and / or” include all combinations of any one or more of the listed items.

[0028] Figure 1 This is a schematic diagram illustrating the principle of multi-mode readout control for an infrared thermopile array sensor provided in an embodiment of this specification. The method may include: S110: Receive mode configuration signal; the mode configuration signal includes a first layer selection signal and a second layer selection signal; In the specific embodiments described in this specification, the sensor includes an m×n thermopile pixel array and a readout integrated circuit (ROIC). The readout integrated circuit has an integrated mode register for providing a first-layer selection signal TP_MUX and a second-layer selection signal FRAME_FIX.

[0029] S120: When the first layer selection signal is at the first level, enter the fully parallel readout mode and control all channels of the thermopile pixel array to synchronously perform signal sampling, conversion and on-chip RAM writing; In the specific implementation described in this specification, when TP_MUX=1 (first level), the sensor enters the fully parallel readout mode. In this mode, all m×n channels of the thermopile array simultaneously sample signals, the preamplifier, integrator circuit, and ADC are all operational, and the data from all channels is completely written to the on-chip RAM in a fixed scanning order after analog-to-digital conversion, completing the full array data update within one frame period. The FRAME_FIX signal is ignored in this mode.

[0030] S130: When the first layer selection signal is at the second level, enter the multiple-choice mode, divide the thermopile pixel array into multiple data blocks, and further select the segmented loop mode or the specified area mode according to the second layer selection signal. In the specific implementation of this specification, when TP_MUX=0 (second level), the sensor enters a multi-select mode. At this time, the thermopile array is logically divided into L data blocks, L=2^x, and further selected as a segmented loop mode or a specified area mode according to the FRAME_FIX signal.

[0031] Optionally, dividing the thermopile pixel array into multiple data blocks includes: The thermopile pixel array is divided into L data blocks, where L=2. x Each data block contains S channels. Where x is a preset integer.

[0032] In the specific implementation of this specification, in the multiple-choice mode, the thermopile pixel array is divided into L data blocks, where L=2. x Where x is a preset integer, determined by the array size and segmentation requirements. The total number of channels N = m × n, and the number of channels contained in each data block. For example, for a 32×32 array (N=1024), if x=3, then L=8, and each block contains S=128 channels. The data blocks are numbered L1, L2, ..., L8. This method of logical segmentation using powers of 2 facilitates the digital control logic to directly generate block selection signals through binary decoding, resulting in a simple and efficient hardware implementation.

[0033] Optionally, when the first layer selection signal is at the second level, entering a multi-select mode, the thermopile pixel array is divided into multiple data blocks, including: In the multiple-choice mode, the bias current of inactive data blocks is turned off, specifically: The on-chip digital control logic generates independent bias enable signals for each data block, and applies the bias enable signals to the control terminals of the CMOS switches inserted in the bias current branches of the corresponding data blocks to turn off the bias current of inactive data blocks.

[0034] In the specific implementation of this specification, in the multi-select mode (TP_MUX=0), regardless of whether it is the segmented loop mode or the designated area mode, power consumption is reduced by shutting down the bias current block by block. Specifically, a high-threshold CMOS switch is inserted in series in the bias current branch of the analog readout circuit (including the preamplifier, integrator, and ADC front-end circuit) of each data block. The on-chip digital control logic generates an independent bias enable signal for each data block based on the currently active data block number. When a data block is selected and activated, the corresponding enable signal controls its CMOS switch to turn on, and the bias current is supplied normally; when a data block is not selected, the corresponding enable signal controls its CMOS switch to turn off, cutting off the bias current of that data block, allowing the analog readout circuit to enter a zero-current or extremely low-current state, effectively suppressing static power consumption.

[0035] Optionally, the step of further selecting the segmented loop mode or the specified region mode based on the second layer selection signal includes: In the multiple-choice mode, the address space of the on-chip RAM is divided into L consecutive address intervals, the size of which matches the data size of a data block. In the segmented loop mode, the channel selection signal driven by the loop counter generates the number of the currently active data block. The high-order address of the on-chip RAM is provided by the channel selection signal after decoding, and is used to select the address range corresponding to the currently active data block. The low-order address is generated by the channel counter within the block incrementing sequentially. The control logic generates a block write enable signal, which only allows write operations to be performed on the address range corresponding to the currently active data block.

[0036] In the specific implementation of this specification, in the multiple-choice mode, the address space of the on-chip RAM is divided into L consecutive address intervals, the size of each address interval being precisely matched with the data size of a data block. Taking L=8 as an example, Block 0 corresponds to the address [0~S-1], Block 1 corresponds to the address [S~2S-1], and so on, with Block 7 corresponding to the address [7S~8S-1].

[0037] In segmented cyclic mode (TP_MUX=0, FRAME_FIX=0), the digital control logic contains a cyclic counter that drives the channel selection signals CH_MUX[x-1:0] to sequentially generate the numbers of the currently active data blocks (e.g., 000→L1, 001→L2, ..., 111→L8). The high-order address (MSB) of the on-chip RAM is provided by CH_MUX after being synchronized and decoded by a register, and is used to select the address range corresponding to the current data block; the low-order address (LSB) is generated sequentially by the column / channel counters within the block, and is used to address the specific channel data within that block. This two-level address generation mechanism ensures that addressing operations are performed only on the RAM range corresponding to the currently active data block each time.

[0038] Optionally, the control logic generates a block write enable signal, allowing write operations only to the address range corresponding to the currently active data block, including: The block write enable signal is generated by performing a logical AND operation on the block selection signal, data valid signal, and write phase signal of the current data block. For inactive data blocks, their block selection signal is invalid, and the corresponding write enable is forced to be set to an invalid level.

[0039] In the specific implementation of this specification, to ensure that only the RAM range of the currently active data block is updated, the digital control logic generates write enable signals on a block-by-block basis. The specific logical expression is: RAM_WE = Block_Select & Data_Valid & Write_Phase. Here, Block_Select is generated by the current CH_MUX decoding result, indicating whether the current data block is selected; Data_Valid indicates that the current ADC conversion data is valid; and Write_Phase indicates that the current phase is a write-back phase.

[0040] Only when a data block is activated, the ADC output data is valid, and it is in the write-back phase—all three conditions must be met simultaneously—will the write enable signal of the RAM interval corresponding to that data block be at a valid level, and the RAM will perform a write operation. For inactive data blocks, since the Block_Select signal is invalid (low level), the write enable signal of the corresponding address interval is forcibly set to an invalid level. Even if the address bus scans over the address range of inactive blocks during the cyclic scan, the RAM memory cell will not perform a write operation because the write enable is disabled, and the original data remains unchanged. The SRAM memory cell is stable when there is no write operation, and no data loss will occur.

[0041] S140: In the segmented loop mode, each data block is activated and read out in a preset order; In the specific implementation of this specification, if FRAME_FIX=0, the segmented loop mode is entered, and each data block is activated and read out in a preset order.

[0042] S150: In the specified area mode, only the data block specified by the block selection signal is activated for reading.

[0043] In the specific implementation of this specification, if FRAME_FIX=1, then the specified region mode is entered, and only the data block specified by the block selection signal is activated for reading.

[0044] Optionally, in the specified area mode, activating only the data block specified by the block selection signal for reading includes: In the specified region mode, the block selection signal is provided by an on-chip register to specify the data block number that will continue to operate, and the bias current of the remaining data blocks remains off in this mode. When the first layer selection signal is at the first level and enters the fully parallel readout mode, the second layer selection signal is ignored, and the bias current of all channels remains on.

[0045] In the specific implementation described in this specification, in the designated area mode (TP_MUX=0, FRAME_FIX=1), the block selection signal is provided by the on-chip register CH[x-1:0], the value of which specifies a continuously operating data block number Lk. The sensor only activates the designated data block, and its readout circuit continuously operates to perform sampling, conversion, and RAM writing; the bias current of all other data blocks remains cut off throughout the entire operation, the data in their corresponding RAM address ranges remains unchanged, and the address bus and control signals remain static.

[0046] When TP_MUX=1 (fully parallel mode), the FRAME_FIX signal is ignored by the digital control logic. Regardless of the value of FRAME_FIX, the sensor operates in fully parallel mode. In this mode, the bias current of all channels remains on, and all analog readout circuits operate normally, ensuring full array data acquisition at the highest frame rate and with the highest accuracy.

[0047] Figure 2 A schematic diagram of an infrared thermopile array sensor provided in the embodiments of this specification includes: m×n thermopile pixel array; A readout integrated circuit is connected to the thermopile pixel array. The readout integrated circuit includes a mode register, digital control logic, multiple independently enableable readout channel modules, and on-chip RAM. The mode register is used to store the first layer selection signal, the second layer selection signal, and the block selection signal; The digital control logic is configured to control the sensor to operate in one of the following modes in response to the first layer selection signal and the second layer selection signal: a fully parallel readout mode, a segmented cyclic readout mode, or a designated area readout mode. In the fully parallel readout mode, all channels synchronously perform signal sampling, conversion, and on-chip RAM writing; in the segmented cyclic readout mode, each data block is activated sequentially in a preset order for reading; in the designated area readout mode, only the data block specified by the block selection signal is activated for reading.

[0048] In the specific embodiments described in this specification, the thermopile pixel array is manufactured using CMOS-MEMS technology, and each pixel contains a thermopile sensing unit for converting infrared radiation into a voltage signal.

[0049] The readout integrated circuit is electrically connected to the thermopile pixel array and includes a mode register, digital control logic, multiple independently enableable readout channel modules, an analog-to-digital converter array, and on-chip RAM. The mode register stores the first-layer selection signal TP_MUX, the second-layer selection signal FRAME_FIX, and the block selection signals CH[x-1:0]. The digital control logic is configured to control the sensor to switch between fully parallel readout mode, segmented cyclic readout mode, or specified region readout mode in response to the aforementioned mode configuration signals.

[0050] In fully parallel readout mode, all readout channel modules operate synchronously, and all pixel channels simultaneously perform signal sampling, analog-to-digital conversion, and on-chip RAM writing. In segmented cyclic readout mode, the digital control logic activates the readout channel modules corresponding to each data block in a preset order, with only one data block being read at a time. In designated area readout mode, only the readout channel module corresponding to the data block specified by the block selection signal is activated.

[0051] Optionally, the thermopile pixel array is divided into L data blocks, where L=2. x Each data block contains S channels. , where x is a preset integer; Each of the readout channel modules has a CMOS switch connected in series in the bias current branch. The bias enable signal output by the digital control logic is connected to the control terminal of the CMOS switch to independently turn the bias current on or off according to data blocks. The address space of the on-chip RAM is divided into L consecutive address intervals. The write enable signal output by the digital control logic is generated by the logical AND of the block selection signal, the data valid signal and the write phase signal, so that only the address interval corresponding to the currently active data block is written.

[0052] In the specific embodiment of this specification, the thermopile pixel array is divided into L data blocks, where L=2 x Each data block contains There are 10 channels, where x is a preset integer. Each readout channel module has a high-threshold CMOS switch connected in series in its bias current branch. The independent bias enable signal for each data block output by the digital control logic is connected to the control terminal of the corresponding CMOS switch. When a data block is activated, the corresponding CMOS switch is turned on, and the bias current is supplied normally; when the data block is not activated, the corresponding CMOS switch is turned off, cutting off the bias current, thus achieving independent power management based on data blocks.

[0053] The on-chip RAM address space is divided into L consecutive address ranges, each corresponding to one of L data blocks. The digital control logic integrates a write enable generation circuit. This circuit performs a logical AND operation on the block selection signal (Block_Select), the data valid signal (Data_Valid), and the write phase signal (Write_Phase), outputting the write enable signal for each data block. The write enable signal for the corresponding address range is only effective when a data block is selected, the data is valid, and the write phase is in progress. This ensures that only the RAM range containing the currently active data block is updated, while the remaining ranges retain their original data.

[0054] In the specific implementation of this specification, the total number of array channels N = m × n, and the number of segments L = 2 x When x=1, L=2, and the array is divided into two data blocks; when x=2, L=4; when x=3, L=8, and so on. Number of channels per data block In practical applications, the value of x can be configured according to the trade-off between system frame rate and power consumption. The larger x is, the fewer channels are activated at a time, and the lower the average power consumption, but the more cycle times are required for full array updates, and the equivalent frame rate is correspondingly reduced. This parameter can be flexibly set through on-chip registers.

[0055] In the specific implementation described in this specification, after the sensor is powered on, configuration parameters, including the values ​​of TP_MUX, FRAME_FIX, and CH[x-1:0], are first written to the mode register via an external interface. After reading the mode register, the digital control logic operates according to the following logic: If TP_MUX=1: Ignore FRAME_FIX, enter full parallel mode, all bias enable signals are valid, all channels work synchronously, and the entire array is updated in one frame.

[0056] If TP_MUX=0 and FRAME_FIX=0: Enter segmented loop mode. The loop counter starts counting from 0. The CH_MUX output increments sequentially, activating data blocks L1 to L_L in sequence. After each block completes sampling conversion and RAM writing, it switches to the next block. The loop counter is cleared after it reaches 2^x, and a new loop begins.

[0057] If TP_MUX=0 and FRAME_FIX=1: Enter the specified region mode. CH_MUX outputs the data block number corresponding to the CH[x-1:0] register value. Only this data block continues to work, while the other blocks remain off.

[0058] In this invention, a hierarchical control structure composed of the first-layer selection signal TP_MUX and the second-layer selection signal FRAME_FIX achieves three modes—fully parallel readout, segmented cyclic readout, and designated area readout—within the same readout integrated circuit and memory architecture. This eliminates the need to design multiple independent ROIC architectures for different application scenarios, significantly reducing chip design complexity, tape-out costs, and verification cycles. When high-speed, high-precision imaging is required, the fully parallel mode enables synchronous readout of all channels, achieving the highest frame rate and measurement accuracy. In scenarios where frame rate requirements are not high but long-term operation is necessary, the segmented cyclic mode or designated area mode can be switched to activate only some channels, significantly reducing system power consumption. The three modes can be flexibly switched according to application needs, achieving a dynamic balance between performance and power consumption. In the multi-select mode, the CMOS switch connected in series in the bias current branch of the inactive data block is turned off, causing the corresponding analog readout circuit to enter a zero-current or extremely low-current state, suppressing static power consumption at its source. Compared to simply shutting down subsequent digital processing circuits, this invention achieves power control at the analog front-end level, resulting in more significant energy savings. The write enable signal for the on-chip RAM is generated by logically ANDing the block selection signal, data valid signal, and write phase signal. Only the address range corresponding to the currently active data block is written to; RAM ranges of inactive data blocks are not updated, reducing invalid memory flip-flops and further lowering dynamic power consumption. In designated region mode, only a specific region of interest in the array can be continuously read at high speed, while the remaining regions remain dormant. This achieves accurate temperature measurement and high-frame-rate monitoring of critical targets while avoiding the acquisition and processing of invalid data, improving system measurement efficiency and flexibility. In multi-channel mode, since only some channels are active, the overall self-heating effect of the thermopile array is significantly reduced, minimizing thermal disturbances caused by chip self-heating and improving the stability and accuracy of temperature measurements.

[0059] Based on the same inventive concept, embodiments of this specification also provide an electronic device.

[0060] The following describes embodiments of the electronic device of the present invention, which can be considered as specific implementations of the methods and apparatus embodiments of the present invention described above. Details described in the embodiments of the electronic device of the present invention should be considered as supplements to the methods or apparatus embodiments described above; details not disclosed in the embodiments of the electronic device of the present invention can be implemented with reference to the methods or apparatus embodiments described above.

[0061] Figure 3 This is a schematic diagram of an electronic device provided as an embodiment of this specification. Refer to the following... Figure 3 The electronic device 300 according to this embodiment of the present invention will be described. Figure 3 The electronic device 300 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0062] like Figure 3 As shown, the electronic device 300 is presented in the form of a general-purpose computing device. The components of the electronic device 300 may include, but are not limited to: at least one processing unit 310, at least one storage unit 320, a bus 330 connecting different system components (including storage unit 320 and processing unit 310), a display unit 340, etc.

[0063] The storage unit stores program code that can be executed by the processing unit 310, causing the processing unit 310 to perform the steps described in the processing method section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 310 can perform, for example... Figure 1 The steps are shown.

[0064] The storage unit 320 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 3201 and / or a cache storage unit 3202, and may further include a read-only memory unit (ROM) 3203.

[0065] The storage unit 320 may also include a program / utility 3204 having a set (at least one) program module 3205, such program module 3205 including but not limited to: an operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0066] Bus 330 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0067] Electronic device 300 can also communicate with one or more external devices 400 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable viewers to interact with electronic device 300, and / or with any device that enables electronic device 300 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 350. Furthermore, electronic device 300 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 360. Network adapter 360 can communicate with other modules of electronic device 300 via bus 330. It should be understood that, although... Figure 3 As not shown, other hardware and / or software modules may be used in conjunction with electronic device 300, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0068] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described in this invention can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this invention can be embodied in the form of a software product, which can be stored in a computer-readable storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, or network device, etc.) to execute the method described above according to this invention. When the computer program is executed by a data processing device, it enables the computer-readable medium to implement the method described above, i.e.: as... Figure 1 The method shown.

[0069] Figure 4 This is a schematic diagram of a computer-readable medium provided for embodiments of this specification.

[0070] accomplish Figure 1The computer program of the method shown can be stored on one or more computer-readable media. A computer-readable medium can be a readable signal medium or a readable storage medium. A readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0071] The computer-readable storage medium may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0072] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the audience's computing device, partially on the audience's device, as a standalone software package, partially on the audience's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the audience's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0073] In summary, the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that in practice, general-purpose data processing devices such as microprocessors or digital signal processors (DSPs) can be used to implement some or all of the functions of some or all of the components according to the embodiments of the present invention. The present invention can also be implemented as a device or apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such programs implementing the present invention can be stored on a computer-readable medium or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0074] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the present invention is not inherently related to any specific computer, virtual device, or electronic device, and various general-purpose devices can also implement the present invention. The above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0075] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0076] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A multi-mode readout control method for an infrared thermopile array sensor, characterized in that, The sensor includes an m×n thermopile pixel array and a readout integrated circuit, comprising: Receive mode configuration signal; the mode configuration signal includes a first layer selection signal and a second layer selection signal; When the first layer selection signal is at the first level, it enters the fully parallel readout mode, controlling all channels of the thermopile pixel array to synchronously perform signal sampling, conversion and on-chip RAM writing; When the first layer selection signal is at the second level, it enters the multiple-choice mode, divides the thermopile pixel array into multiple data blocks, and further selects the segmented loop mode or the specified area mode according to the second layer selection signal. In the segmented loop mode, each data block is activated and read out in a preset order; In the specified area mode, only the data block specified by the block selection signal is activated for reading.

2. The multi-mode readout control method for an infrared thermopile array sensor as described in claim 1, characterized in that, The step of dividing the thermopile pixel array into multiple data blocks includes: The thermopile pixel array is divided into L data blocks, where L=2. x Each data block contains S channels. Where x is a preset integer.

3. The multi-mode readout control method for an infrared thermopile array sensor as described in claim 2, characterized in that, When the first layer selection signal is at the second level, the system enters a multi-select mode, dividing the thermopile pixel array into multiple data blocks, including: In the multiple-choice mode, the bias current of inactive data blocks is turned off, specifically: The on-chip digital control logic generates independent bias enable signals for each data block, and applies the bias enable signals to the control terminals of the CMOS switches inserted in the bias current branches of the corresponding data blocks to turn off the bias current of inactive data blocks.

4. The multi-mode readout control method for an infrared thermopile array sensor as described in claim 2, characterized in that, The step of further selecting the segmented loop mode or the specified region mode based on the second layer selection signal includes: In the multiple-choice mode, the address space of the on-chip RAM is divided into L consecutive address intervals, the size of which matches the data size of a data block. In the segmented loop mode, the channel selection signal driven by the loop counter generates the number of the currently active data block. The high-order address of the on-chip RAM is provided by the channel selection signal after decoding, and is used to select the address range corresponding to the currently active data block. The low-order address is generated by the channel counter within the block incrementing sequentially. The control logic generates a block write enable signal, which only allows write operations to be performed on the address range corresponding to the currently active data block.

5. The multi-mode readout control method for an infrared thermopile array sensor as described in claim 4, characterized in that, The control logic generates a block write enable signal, allowing write operations only to the address range corresponding to the currently active data block, including: The block write enable signal is generated by performing a logical AND operation on the block selection signal, data valid signal, and write phase signal of the current data block. For inactive data blocks, their block selection signal is invalid, and the corresponding write enable is forced to be set to an invalid level.

6. The induction cooker temperature control method as described in claim 1, characterized in that, In the specified region mode, only the data block specified by the block selection signal is activated for reading, including: In the specified region mode, the block selection signal is provided by an on-chip register to specify the data block number that will continue to operate, and the bias current of the remaining data blocks remains off in this mode. When the first layer selection signal is at the first level and enters the fully parallel readout mode, the second layer selection signal is ignored, and the bias current of all channels remains on.

7. An infrared thermopile array sensor, characterized in that, include: m×n thermopile pixel array; A readout integrated circuit is connected to the thermopile pixel array. The readout integrated circuit includes a mode register, digital control logic, multiple independently enableable readout channel modules, and on-chip RAM. The mode register is used to store the first layer selection signal, the second layer selection signal, and the block selection signal; The digital control logic is configured to control the sensor to operate in one of the following modes in response to the first layer selection signal and the second layer selection signal: a fully parallel readout mode, a segmented cyclic readout mode, or a specified area readout mode. In the fully parallel readout mode, all channels synchronously perform signal sampling, conversion, and on-chip RAM writing; in the segmented cyclic readout mode, each data block is activated sequentially in a preset order for reading; in the designated area readout mode, only the data block specified by the block selection signal is activated for reading.

8. The infrared thermopile array sensor as described in claim 7, characterized in that, The thermopile pixel array is divided into L data blocks, where L=2. x Each data block contains S channels. , where x is a preset integer; Each of the readout channel modules has a CMOS switch connected in series in the bias current branch. The bias enable signal output by the digital control logic is connected to the control terminal of the CMOS switch to independently turn the bias current on or off according to data blocks. The address space of the on-chip RAM is divided into L consecutive address intervals. The write enable signal output by the digital control logic is generated by the logical AND of the block selection signal, the data valid signal and the write phase signal, so that only the address interval corresponding to the currently active data block is written.

9. An electronic device, wherein, The electronic device includes: A processor; and a memory storing computer-executable instructions, which, when executed, cause the processor to perform the method according to any one of claims 1-6.

10. A computer-readable storage medium, wherein, The computer-readable storage medium stores one or more programs that, when executed by a processor, implement the method of any one of claims 1-6.

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