Pixel circuit, image sensor, and quantization method

Abstract

The pixel circuit and the quantification method provided in the application, in which a pixel circuit performs different conversion gain signal reading in an image frame, the pixel circuit comprising: a photosensitive element; at least one overflow switch element and a corresponding overflow capacitor, one end of the overflow switch element being connected to the overflow capacitor and the other end being coupled to a first floating node; a transfer switch element being connected to an output end of the photosensitive element, and there being a transfer switch element connected to the first floating node; wherein the conversion gain performed by the pixel circuit comprises at least a first type of conversion gain and a second type of conversion gain, the reset sampling stage in the first type of conversion gain being performed before the image sampling stage, the second type of conversion gain being the opposite, and the pixel circuit obtaining the second type of conversion gain signal based on the photosensitive element corresponding to at least one transfer switch element connected to the first floating node; through the coupling relationship between the photosensitive element and the overflow capacitor and the conversion gain performed, the requirement of the photosensitive element for the full well capacity is reduced, and the signal-to-noise ratio can be improved.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, specifically to a pixel circuit, an image sensor, and a quantization method.

[0002] Background Technology With the development of chip integration, CMOS image sensors are evolving towards smaller size and lower power consumption, and their applications in monitoring, automotive, and artificial intelligence fields are increasing. At the same time, the performance requirements of CMOS image sensors are also becoming more demanding in different application scenarios. For example, in the field of automotive monitoring, some CMOS image sensors need to monitor scenes outside the vehicle, which often encounter situations where high brightness and low brightness occur together or alternate rapidly, such as the bright light at the tunnel exit, the sun in the sky, the headlights of nearby cars, and the bright light reflected from license plates. In order for the sensor to be able to identify details in dark areas and capture information in strong light areas without overexposure in a single exposure, the CMOS image sensor needs to have a relatively high dynamic range.

[0003] Existing technologies typically employ two photosensitive elements with different photosensitivity capabilities, such as two photodiodes (PDs) of different sizes. A connection switch and capacitor are placed between the smaller PD and the floating node used for sampling to increase the full-well capacity of the smaller PD. Furthermore, by selecting different conversion gains (CG), the photoelectric signals generated by the two PDs are sampled and quantized sequentially to adapt to various external light intensity ranges, thereby improving the overall dynamic range of the CMOS image sensor.

[0004] In the process of conceiving and implementing this application, the inventors discovered at least the following problems: in the prior art, the full-well capacity requirement for small-sized PDs is relatively high. At the same time, due to the difference in sensitivity between two PDs of different sizes, the signal-to-noise ratio of the signal collected by the small-sized PD is low under the same exposure time in the bright area.

[0005] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0006] The pixel circuit and quantization method provided in this application can reduce the full-well capacity requirement for small-sized PDs, while improving the signal-to-noise ratio.

[0007] This application provides a pixel circuit, comprising: a photosensitive element for generating photoelectric signals; a switching device and a gain capacitor, wherein a first path terminal of the switching device is connected to a first floating node of the pixel circuit, a second path terminal of the switching device is connected to a first plate of the gain capacitor, the second plate of the gain capacitor is connected to a first reference voltage source, and the node between the switching device and the gain capacitor serves as a second floating node of the pixel circuit; at least one overflow switch and an overflow capacitor corresponding to the overflow switch, wherein a first path terminal of the overflow switch is connected to a first plate of the overflow capacitor, a second path terminal of the overflow switch is coupled to the first floating node, and the second plate of the overflow capacitor is connected to a second reference voltage source; and a transfer switch corresponding to the photosensitive element, wherein a first path terminal of the transfer switch is connected to the output terminal of the photosensitive element, wherein a second path terminal of the transfer switch is coupled to the first floating node, and at least one second path terminal of the transfer switch is directly coupled to the first floating node. The transfer switch is selected to control the photosensitive element to output a photoelectric signal; a first reset switch is coupled to a second floating node at its first path terminal and connected to a third reference voltage source at its second path terminal; a readout switch is connected to a first floating node at its control terminal and leads out from its first path terminal as the signal output terminal of the pixel circuit, and its second path terminal is connected to a fourth reference voltage source; the pixel circuit performs different conversion gain signal readouts within an image frame, wherein the signal under each conversion gain has a reset sampling stage signal and an image sampling stage signal, and the conversion gain performed by the pixel circuit includes at least a first type of conversion gain and a second type of conversion gain, wherein the reset sampling stage in the first type of conversion gain is executed before the image sampling stage, and the image sampling stage in the second type of conversion gain is executed before the reset sampling stage, and the second type of conversion gain signal is acquired at least based on the photosensitive element corresponding to the transfer switch connected to the first floating node.

[0008] This application provides an image sensor, including the pixel circuit as described in any of the foregoing claims.

[0009] This application provides a quantization method applied to the pixel circuit described above or any of the image sensors described above. Within an image frame, the pixel circuit performs at least three stages: reset, exposure, and gain quantization. During the gain quantization stage, the pixel circuit performs at least different conversion gain signal readouts. Each readout signal under a conversion gain includes a reset sampling stage signal and an image sampling stage signal. The conversion gains performed during single-frame signal readout include at least a first type of conversion gain and a second type of conversion gain. In the first type of conversion gain, the reset sampling stage is performed before the image sampling stage, and in the second type of conversion gain, the image sampling stage is performed before the reset sampling stage. The second type of conversion gain signal is acquired at least based on the photosensitive element corresponding to the transfer switch connected to the first floating node.

[0010] As described above, this application provides a pixel circuit and a quantization method. The pixel circuit includes: a photosensitive element; at least one overflow switch and a corresponding overflow capacitor, one end of the overflow switch being connected to the overflow capacitor and the other end being coupled to a first floating node; a transfer switch being connected to the output terminal of the photosensitive element, and one transfer switch being connected to the first floating node; wherein, the conversion gain performed by the pixel circuit includes at least a first type of conversion gain and a second type of conversion gain, wherein the reset sampling stage of the first type of conversion gain is performed before the image sampling stage, and the second type of conversion gain is the opposite, and the pixel circuit obtains the second type of conversion gain signal based on the photosensitive element corresponding to at least one transfer switch connected to the first floating node; through the coupling relationship between the photosensitive element and the overflow capacitor and the performed conversion gain, the requirement of the photosensitive element for full-well capacity can be reduced, while the signal-to-noise ratio can be improved. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0012] Figure 1 This is a schematic diagram of the structure and connection relationship of the pixel circuit in the first embodiment of this application.

[0013] Figure 2 This is a timing diagram of electrical signals for the first embodiment of this application.

[0014] Figure 3 This is a schematic diagram of the structure and connection relationship of the pixel circuit in the second embodiment of this application.

[0015] Figure 4 This is a timing diagram of electrical signals according to the second embodiment of this application.

[0016] Figure 5 This is a schematic diagram of the structure and connection relationship of the pixel circuit in the third embodiment of this application.

[0017] Figure 6 This is a timing diagram of electrical signals according to the third embodiment of this application.

[0018] Figure 7 This is a schematic diagram of the structure and connection relationship of the pixel circuit in the fourth embodiment of this application.

[0019] Figure 8 This is a timing diagram of electrical signals according to the fourth embodiment of this application.

[0020] Figure 9 This is a schematic diagram of the structure and relationship of the pixel circuit in the fifth embodiment of this application.

[0021] Figure 10 This is a timing diagram of electrical signals according to the fifth embodiment of this application.

[0022] Figure 11 This is a schematic diagram of the structure and connection relationship of the pixel circuit in the sixth embodiment of this application.

[0023] Figure 12 This is a schematic diagram of the structure and connection relationship of the pixel circuit in the seventh embodiment of this application.

[0024] Figure 13 The following are electrical signal timing diagrams for the sixth and seventh embodiments of this application.

[0025] Among them, FD_1 - first floating node, FD_2 - second floating node, DCG - switching switch, Ccg - gain capacitor, Rst_1 - first reset switch, Rst_2 - second reset switch, Vref_1 - first reference voltage source, Vref_2 - second reference voltage source, Vref_3 - third reference voltage source, Vref_4 - fourth reference voltage source, SF - readout switch, SEL - selection switch, D1 - first photosensitive element, D2 - second photosensitive element, D3 - third photosensitive element, Sof_1 - first overflow switch, Sof_2 - second overflow switch, Sof_3 - third overflow switch, Sof_4 - fourth overflow switch, Cof_1 - first overflow capacitor, Cof_2 - second overflow capacitor, Cof_3 - third overflow capacitor, Cof_4 - fourth overflow capacitor, TX_1 - first transfer switch, TX_2 - second transfer switch, TX_3 - third transfer switch.

[0026] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0028] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0029] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0030] This application provides a pixel circuit applied to a CMOS image sensor. The pixel circuit includes a photosensitive element, a transfer switch, a switching switch, a gain capacitor, at least one overflow switch, an overflow capacitor, a first reset switch, and a readout switch. The photosensitive element generates photoelectric signals. The first path terminal of the switching switch is connected to a first floating node of the pixel circuit, and the second path terminal of the switching switch is connected to a first plate of the gain capacitor. The second plate of the gain capacitor is connected to a first reference voltage source, and the node between the switching switch and the gain capacitor serves as a second floating node of the pixel circuit. The overflow switch corresponds to the overflow capacitor; its first path terminal is connected to the first plate of the overflow capacitor, and its second path terminal is coupled to the first floating node. The second plate of the overflow capacitor is connected to a second reference voltage source. The transfer switch corresponds to the photosensitive element, and its first path terminal... The transfer switch is connected to the output terminal of the photosensitive element. The second path terminal of the transfer switch is coupled to the first floating node, and at least one transfer switch has its second path terminal directly coupled to the first floating node. The transfer switch selects and controls the photosensitive element to output a photoelectric signal. The first path terminal of the first reset switch is coupled to the second floating node, and its second path terminal is connected to a third reference voltage source. The control terminal of the readout switch is connected to the first floating node, and a lead wire is extended from the first path terminal of the readout switch to serve as the signal output terminal of the pixel circuit. The second path terminal of the readout switch is connected to a fourth reference voltage source. Within one image frame, the pixel circuit performs readout of signals with different conversion gain.

[0031] The coupling includes direct coupling and indirect coupling. "At least one transfer switch's second path terminal is directly coupled to the first floating node" means that at least one transfer switch's second path terminal is directly connected to the first floating node. If the second path terminal of the transfer switch is connected to the first floating node through other components, then the second path terminal of the transfer switch and the first floating node are not directly coupled, but indirectly coupled. "The second path terminal of the transfer switch is coupled to the first floating node, and at least one transfer switch's second path terminal is directly coupled to the first floating node" means that: if the pixel circuit includes only one transfer switch, then the second path terminal of this transfer switch is directly coupled to the first floating node; if the pixel circuit includes multiple transfer switches, then only one transfer switch's second path terminal may be directly coupled to the first floating node, while the second path terminals of the other transfer switches are coupled to the first floating node but not directly coupled; or all of the second path terminals of multiple transfer switches may be directly coupled to the first floating node.

[0032] In one embodiment, the signal under each conversion gain includes a reset sampling stage signal and an image sampling stage signal. The conversion gain performed by the pixel circuit includes at least a first type of conversion gain and a second type of conversion gain. The first type of conversion gain is Correlated Double Sampling (CDS), that is, the reset sampling stage is performed before the image sampling stage in the first type of conversion gain. The second type of conversion gain is Non-Correlated Double Sampling, that is, the image sampling stage is performed before the reset sampling stage in the second type of conversion gain. The pixel circuit acquires the second type of conversion gain signal based at least on the photosensitive element corresponding to the transfer switch directly coupled to the first floating node.

[0033] In one embodiment, the pixel circuit further includes a second reset switch. The first terminal of the second reset switch is connected to the second plate of the overflow capacitor, and the second terminal of the second reset switch is connected to a third reference voltage source. In some embodiments, when the capacitance values ​​of the selected overflow capacitor and gain capacitor are relatively large, relying solely on the first reset switch to turn on the circuit would require a long time to reset to the reference voltage. Therefore, the second reset switch is added to assist in the turn-on process and improve the reset efficiency.

[0034] In one embodiment, the pixel circuit further includes a pixel selection switch, which is disposed between the first path terminal of the readout switch and the signal output terminal, and is used to control the signal output of the corresponding pixel circuit.

[0035] This application also provides a quantization method applied to the aforementioned pixel circuit or image sensor. Within an image frame, at least three stages are performed: reset, exposure, and quantization. During the quantization stage, the pixel circuit performs at least different conversion gain signal readouts. The readout signal under each conversion gain includes a reset sampling stage signal and an image sampling stage signal. The conversion gain performed during single-frame signal readout includes at least a first type of conversion gain and a second type of conversion gain. In the first type of conversion gain, the reset sampling stage is performed before the image sampling stage, and in the second type of conversion gain, the image sampling stage is performed before the reset sampling stage. The second type of conversion gain signal is obtained at least based on the photosensitive element corresponding to the transfer switch connected to the first floating node. The second type of conversion gain signal includes a node overflow signal. The node overflow signal may include electrons overflowing into the first floating node or the second floating node when electron overflow occurs in the photosensitive element corresponding to the transfer switch connected to the first floating node (such as the subsequent first and third photosensitive elements).

[0036] Furthermore, the first type of conversion gain includes a first conversion gain and a second conversion gain. Based on the photosensitive element corresponding to the transfer switch element connected to the first floating node, signal readout is achieved under the first conversion gain and the second conversion gain. The second type of conversion gain includes a third conversion gain, a fourth conversion gain, and a fifth conversion gain. The first conversion gain is the correlated double-sampling low conversion gain (CDS Low Conversion Gain, CDS LCG) performed on the photosensitive element directly coupled to the first floating node; the second conversion gain is the correlated double-sampling high conversion gain (CDS High Conversion Gain, CDS HCG) performed on the photosensitive element directly coupled to the first floating node; the third conversion gain is the non-true double-correlated low conversion gain (Non-CDS LCG) performed on the photosensitive element directly coupled to the first floating node; the fourth conversion gain is the non-true double-correlated overflow integration capacitor conversion gain (Non-CDS OFCG) performed on the photosensitive element directly coupled to the first floating node; and the fifth conversion gain is the non-true double-correlated overflow integration capacitor conversion gain performed on the photosensitive element not directly coupled to the first floating node. The term "photosensitive element directly coupled to the first floating node" refers to the case where "the output end of the photosensitive element is directly connected to the first floating node through the path end of the corresponding transfer switch." If the output end of the photosensitive element is connected to the first floating node through the path end of the corresponding transfer switch, and also through the path end of the overflow switch or the path end of the switching switch, then the photosensitive element is not considered "photosensitive element directly coupled to the first floating node" but rather "photosensitive element not directly coupled to the first floating node."

[0037] In some embodiments, the pixel circuit further includes at least one first photosensitive element and at least one second photosensitive element. The pixel circuit also includes a first transfer switch corresponding to the first photosensitive element and a second transfer switch corresponding to the second photosensitive element. The area of ​​the first photosensitive element is larger than that of the second photosensitive element. The output terminals of the first and second photosensitive elements are respectively connected to the first path terminals of the first and second transfer switches. The second path terminal of the first transfer switch is connected to a first floating node, and the second path terminal of the second transfer switch is connected to the first plate of an overflow capacitor. See the first to fourth embodiments for details. Figures 1 to 8 .

[0038] First Embodiment like Figure 1 As shown, Figure 1 This is a schematic diagram illustrating the structure and connection relationship of the pixel circuit in the first embodiment of this application. Figure 1 As shown, in one embodiment, the pixel circuit includes a first photosensitive element D1, a first transfer switch TX_1, a switching switch DCG, a gain capacitor Ccg, a first overflow switch Sof_1, a first overflow capacitor Cof_1 corresponding to the first overflow switch Sof_1, a first reset switch Rst_1, and a readout switch SF. In other embodiments, the overflow switches of the pixel circuit may include other overflow switches besides the first overflow switch Sof_1, as well as overflow capacitors corresponding to the other overflow switches.

[0039] The first path terminal of the first overflow switch Sof_1 is connected to the first plate of the first overflow capacitor Cof_1, and the second path terminal of the first overflow switch Sof_1 is connected to the first floating node FD_1 or the second floating node FD_2.

[0040] In one embodiment, the pixel circuit may further include a selection switch SEL. The first terminal of the readout switch SF, serving as the output terminal of the pixel circuit, is connected to the bit line BL (also known as the bit line) via the selection switch SEL. This output is used to connect to a post-processor external to the pixel circuit. The post-processor processes the various gain signals output by the pixel circuit based on multiple conversion gains, using a preset processing scheme, to obtain a final imaging pixel signal with improved dynamic range. In other embodiments, the first terminal of the readout switch SF may also be directly connected to the bit line BL as the output terminal of the pixel circuit.

[0041] In one embodiment, the pixel circuit further includes a second photosensitive element D2. Further, please also refer to... Figure 2 , Figure 2 This is a timing diagram of electrical signals according to the first embodiment of this application. The quantization method executed by the pixel circuit performs a third conversion gain and a fifth conversion gain after executing the first and second conversion gains. When the pixel circuit executes the third and fifth conversion gains, it sequentially executes the image sampling stage under the third conversion gain, the reset sampling stage under the third conversion gain, the image sampling stage under the fifth conversion gain, and the reset sampling stage under the fifth conversion gain. As... Figure 2 The electrical signal timing shown is such that the selection signal is the level signal corresponding to the input to the control terminal of the selection switch SEL. By selecting the selection switch SEL, the output terminal of the pixel circuit and the bit line BL are controlled to be turned on or off, thereby controlling whether the output terminal of the pixel circuit outputs an electrical signal, which facilitates row selection, column selection and other operations in the pixel array subsequently formed by the pixel circuit.

[0042] The first reset signal and the second reset signal are the level signals corresponding to the control terminals of the first reset switch Rst_1 and the second reset switch Rst_2, respectively. Similarly, the switching switch signal, the first transfer switch signal, the second transfer switch signal, and the first overflow switch signal are the level signals corresponding to the control terminals of the switching switch DCG, the first transfer switch TX_1, the second transfer switch TX_2, and the first overflow switch Sof_1, respectively. The timing diagrams in the later embodiments also follow this corresponding logic. In the embodiments of this application, the high-level signal input to the control terminal of the switch corresponds to the conduction of the switch, but this application is not limited to the high and low level conduction logic of the switch.

[0043] Continue to refer to Figure 1 and Figure 2 When the pixel circuit performs the first type of conversion gain, it switches between the first conversion gain and the second conversion gain by turning the switching device DCG on or off. When the switching device DCG is off, the first floating node FD_1 does not introduce the parasitic capacitance and gain capacitance Ccg of the switching device DCG itself. During the image sampling stage, the first floating node FD_1 has a higher gain because the first transfer switch TX_1 is turned on and introduces the photoelectric signal of the first photosensitive element D1, thus achieving the second conversion gain, i.e., double-sampling high conversion gain. When the switching device DCG is on, the first floating node FD_1 introduces the parasitic capacitance and gain capacitance Ccg of the switching device DCG itself. During the image sampling stage, the first floating node FD_1 has a lower gain because the first transfer switch TX_1 is turned on and introduces the photoelectric signal of the first photosensitive element D1, thus achieving the first conversion gain, i.e., double-sampling low conversion gain.

[0044] When the pixel circuit performs the second type of conversion gain, it controls whether the coupling between the photosensitive element connected to the first overflow switch Sof_1 and the first floating node FD_1 is on or off by turning the first overflow switch Sof_1 on or off. This enables the photosensitive element to be selected by the first floating node FD_1, thus achieving the corresponding conversion gain readout for the photosensitive element in the second type of conversion gain. When the first overflow switch Sof_1 is on, an overflow capacitor is introduced into the first floating node FD_1 to achieve the fourth or fifth conversion gain (determined by whether the photosensitive element whose conversion gain is being performed is directly coupled to the first floating node FD_1), i.e., the lateral overflow integral capacitor conversion gain.

[0045] For details, please refer to the following: Figure 1 and Figure 2In this embodiment, during one frame operation of the image sensor, a reset phase is first executed. The selection switch SEL is turned off, and other switches are turned on to reset the photosensitive elements (first photosensitive element D1 and second photosensitive element D2) and each node in the pixel unit. Then, exposure is performed with the first reset switch Rst_1 turned off and the switching switch DCG turned on. In the case of electron overflow in the first photosensitive element D1 and the second photosensitive element D2, it is allowed to overflow to the corresponding storage node via the corresponding transfer switches (first transfer switch TX_1 and second transfer switch TX_2). This is understandable to those skilled in the art. Other transistors are adaptively adjusted based on existing technology. Then, in the readout phase, when the first type of conversion gain signal is read out, the order of the signals read out by the first conversion gain and the second conversion gain can be: first conversion gain reset signal, second conversion gain reset signal, second conversion gain image signal, and first conversion gain image signal. When the second type of conversion gain signal is read out, the signal overflowed by the first photosensitive element D1 is obtained based on the third conversion gain sampling phase to achieve a higher signal-to-noise ratio. The optimization of the SNR curve improves the signal-to-noise ratio drop (also known as SNR Drop). Specifically, with the switch open, the first transfer switch TX_1 is opened and then closed to read the third conversion gain image signal. Then, the first reset switch Rst_1 is opened and closed once to reset the corresponding node of the first photosensitive element D1, obtaining the third conversion gain reset signal. Simultaneously, the first transfer switch TX_1 can be opened and closed again. Finally, the overflow switch is opened to read the overflow signal corresponding to the second photosensitive element D2, i.e., the second transfer switch is opened and closed once to obtain the fifth conversion gain image signal. Then, with the overflow switch remaining open, the first reset switch Rst_1 is opened and closed once more to reset the corresponding node of the second photosensitive element D2, obtaining the fifth conversion gain reset signal. Simultaneously, the second transfer switch can be opened and closed again.

[0046] The execution logic for the first and second type of conversion gain described above is also applicable to other embodiments.

[0047] In other embodiments, the first reference voltage source Vref_1, the second reference voltage source Vref_2, the third reference voltage source Vref_3, and the fourth reference voltage source Vref_4 can be powered by the same voltage source, that is, the first to fourth reference voltage sources Vref_4 can all be a unified working voltage source VDD, which can simplify the circuit connection method; or, the four reference voltage sources can be differentiated. For example, the first reference voltage source Vref_1 and the second reference voltage source Vref_2 can be interconnected using the reference voltage source VRM, while the third reference voltage source Vref_3 and the fourth reference voltage source Vref_4 can use the working voltage source VDD. By default, the reference voltage source VRM and the working voltage source VDD are equal. In one implementation, when the pixel circuit is in the exposure stage, the first reset switch Rst_1 is turned off, and the voltage of the reference voltage source VRM is reduced, preferably by 1 volt. This reduces the voltage of the second plate of the overflow capacitor or, in some embodiments, the second plate of the gain capacitor Ccg connected to the first reference voltage source Vref_1 (reference voltage source VRM), thereby reducing gate-induced drain leakage current (GIDL) and better promoting the overflow of photoelectrons from the photosensitive element into the overflow capacitor.

[0048] Second Embodiment Please refer to Figure 3 , Figure 3This is a schematic diagram of the structure and connection relationship of the pixel circuit according to the second embodiment of this application. In some embodiments, the pixel circuit includes a first photosensitive element D1, a second photosensitive element D2, a second overflow switch Sof_2, and a third overflow switch Sof_3, and correspondingly includes a second overflow capacitor Cof_2 and a third overflow capacitor Cof_3. The second path terminal of the second transfer switch TX_2 is connected to the first plate of the third overflow capacitor Cof_3. After the pixel circuit executes the first conversion gain and the second conversion gain, it executes the fourth conversion gain and the fifth conversion gain. When the pixel circuit executes the fourth conversion gain and the fifth conversion gain, it sequentially executes the image sampling signal under the fourth conversion gain, the reset sampling signal under the fourth conversion gain, the image sampling signal under the fifth conversion gain, and the reset sampling signal under the fifth conversion gain. In this embodiment, similar operations are described in Embodiment 1, and will not be repeated here. In this embodiment, the overflow signal of the first photosensitive element D1 is obtained based on the fourth conversion gain to optimize the SNR curve and improve the SNR drop. During the signal acquisition process at this gain, the second overflow switch Sof_2 is turned on. Then, with the second overflow switch Sof_2 turned on, the first transfer switch TX_1 is turned on and then off. The fourth conversion gain image signal is read out. Then, the first reset switch Rst_1 is turned on and off once to reset the corresponding node of the first photosensitive element D1 and obtain the fourth conversion gain reset signal. At the same time, the first transfer switch TX_1 can be turned on and off once more.

[0049] like Figure 3 As shown, the first path terminal of the second overflow switch Sof_2 is connected to the second overflow capacitor Cof_2, and the second path terminal of the second overflow switch Sof_2 is connected to the first floating node FD_1. The first path terminal of the third overflow switch Sof_3 is connected to the third overflow capacitor Cof_3, and the second path terminal of the third overflow switch Sof_3 is connected to the second floating node FD_2. Further details can be found in the following documentation. Figure 4 , Figure 4 This is a timing diagram of electrical signals for a second embodiment of this application, as shown below. Figure 4As shown, after the pixel circuit executes the first conversion gain and the second conversion gain, it sequentially executes the image sampling signal under the fourth conversion gain, the reset sampling signal under the fourth conversion gain, the image sampling signal under the fifth conversion gain, and the reset sampling signal under the fifth conversion gain. In this embodiment, a second overflow switch Sof_2 and a third overflow switch Sof_3 are provided, and the corresponding second overflow capacitor Cof_2 and third overflow capacitor Cof_3 can be coupled and turned on with the first floating node FD_1. The first photosensitive element D1 is a "photosensitive element directly coupled to the first floating node FD_1", that is, the first photosensitive element D1 is connected to the first floating node FD_1 through the first transfer switch TX_1, which is understandable to those skilled in the art. The pixel circuit sequentially controls the second overflow capacitor Cof_2 and the third overflow capacitor Cof_3 to connect to the first floating node FD_1, thereby sequentially realizing the fourth conversion gain and the fifth conversion gain of the first photosensitive element D1 and the second photosensitive element D2.

[0050] Third Embodiment Please refer to Figure 5 and Figure 6 , Figure 5 This is a schematic diagram showing the structure and connection relationship of the pixel circuit according to the third embodiment of this application. Figure 6 This is a timing diagram of the electrical signals according to the third embodiment of this application. The second overflow switch Sof_2 is disposed between the first path terminal of the first reset switch Rst_1 and the second floating node FD_2. The second path terminal of the second overflow switch Sof_2 is connected to the second floating node FD_2. The first path terminal of the second overflow switch Sof_2 is connected to the first path terminal of the first reset switch Rst_1 and the first plate of the second overflow capacitor Cof_2. The second path terminal of the third overflow switch Sof_3 is connected to the second floating node FD_2. Furthermore... Figure 6 The control timing shown is Figure 4 The same applies; please refer to the description in the second embodiment, which will not be repeated here.

[0051] Fourth embodiment Please refer to Figure 7 and Figure 8 , Figure 7 This is a schematic diagram showing the structure and connection relationship of the pixel circuit in the fourth embodiment of this application. Figure 8 This is a timing diagram of the electrical signals according to the fourth embodiment of this application. The second path terminal of the second overflow switch Sof_2 is connected to the second floating node FD_2, the second path terminal of the second overflow switch Sof_2 is connected to the first path terminal of the first reset switch Rst_1 and the first plate of the second overflow capacitor Cof_2, and the second path terminal of the third overflow switch Sof_3 is connected to the first floating node FD_1. Furthermore, Figure 8 The control timing shown is Figure 4 The same applies; please refer to the description in the second embodiment, which will not be repeated here. In this example, when the fifth conversion gain reset signal is read out, since the switch was previously in the off state, an on / off operation is performed accordingly.

[0052] Fifth embodiment Please refer to Figure 9 , Figure 9 This is a schematic diagram of the structure and connection relationship of the pixel circuit according to the fifth embodiment of this application. In some embodiments, the pixel circuit includes at least one third photosensitive element D3 and a third transfer switch TX_3 corresponding to the third photosensitive element D3, a fourth overflow switch Sof_4 corresponding to the third photosensitive element D3, and the pixel circuit also includes a fourth overflow capacitor Cof_4 corresponding to the fourth overflow switch Sof_4.

[0053] Please also refer to Figure 9 and Figure 10 , Figure 10 This is a timing diagram of electrical signals according to the fifth embodiment of this application. The first path terminal of the fourth overflow switch Sof_4 is connected to the first plate of the fourth overflow capacitor Cof_4, and the second path terminal of the fourth overflow switch Sof_4 is connected to the first floating node FD_1. Similar operations are described in the foregoing embodiments in this embodiment, and will not be repeated here. In this embodiment, the signal overflowing from the first photosensitive element to the first floating node FD_1 is obtained based on the third conversion gain sampling stage to optimize the SNR curve and improve the SNR Drop. Specifically, the signal in the third conversion gain stage corresponds to the readout of the signal overflowing from the first photosensitive element to the first floating node FD_1, and the signal in the fourth conversion gain stage corresponds to the readout of the signal overflowing from the first photosensitive element to the fourth overflow capacitor. Specifically, when the switching switch is open, the third transfer switch TX_3 is controlled to open and then close, and the third conversion gain image signal is read out; then the fourth overflow switch is controlled to open and then close, and the fourth conversion gain image signal is read out. Next, with the fourth overflow switch open, the first reset switch Rst_1 is opened and closed once to reset the corresponding node of the third photosensitive element D3, obtaining the third conversion gain reset signal. Simultaneously, the third transfer switch TX_3 can be opened and closed once more. Finally, the fourth overflow switch is closed, and the first reset switch Rst_1 is opened and closed once more to reset the corresponding node of the third photosensitive element D3, obtaining the fourth conversion gain reset signal. Simultaneously, the third transfer switch TX_3 can be opened and closed once more.

[0054] Sixth Embodiment Please refer to Figure 11 , Figure 11This is a schematic diagram of the structure and connection relationship of the pixel circuit according to the sixth embodiment of this application. The first path terminal of the fourth overflow switch Sof_4 is connected to the first plate of the fourth overflow capacitor Cof_4, and the second path terminal of the fourth overflow switch Sof_4 is connected to the second floating node FD_2.

[0055] Seventh Embodiment Please refer to Figure 12 , Figure 12 This is a schematic diagram of the structure and connection relationship of the pixel circuit in the seventh embodiment of this application. The fourth overflow switch Sof_4 is disposed between the first path terminal of the first reset switch Rst_1 and the second floating node FD_2. The second path terminal of the fourth overflow switch Sof_4 is connected to the second floating node FD_2, and the first path terminal is connected to the first path terminal of the first reset switch Rst_1 and the first plate of the fourth overflow capacitor Cof_4.

[0056] Please also refer to Figure 10 and Figure 13 ,in Figure 13 The following are electrical signal timing diagrams for the sixth and seventh embodiments of this application. In the fifth and sixth embodiments, after the pixel circuit sequentially executes the first conversion gain and the second conversion gain, it executes the third conversion gain and the fourth conversion gain, sequentially executing the image sampling signal under the third conversion gain, the image sampling signal under the fourth conversion gain, the reset sampling signal under the fourth conversion gain, and the reset sampling signal under the third conversion gain. In embodiments six and seven, similar operations are described in the aforementioned embodiment five, and will not be repeated here. In this embodiment, the signal overflowing from the third photosensitive element D3 to the first floating node FD_1 is obtained based on the third conversion gain sampling stage to achieve SNR curve optimization.

[0057] In one embodiment, the gain capacitor Ccg is a MIM capacitor (Metal-Insulator-Metal); and / or, the overflow capacitor is a MIM capacitor.

[0058] In one optional example, the value of the overflow capacitor is greater than the value of the gain capacitor. In one example, the value of the overflow capacitor is between 2 and 50 times the value of the gain capacitor, for example, it can be selected as 5 times, 10 times, 15 times, 20 times, 25 times, etc. In another example, the value of the gain capacitor is less than or equal to 30 fF, for example, it can be selected as 5 fF, 10 fF, 15 fF, 20 fF, 25 fF, etc.

[0059] As described above, this application provides a pixel circuit and a quantization method. The pixel circuit includes: a photosensitive element; at least one overflow switch and a corresponding overflow capacitor, one end of the overflow switch being connected to the overflow capacitor and the other end being coupled to a first floating node; a transfer switch being connected to the output terminal of the photosensitive element, and one transfer switch being connected to the first floating node; wherein, the conversion gain performed by the pixel circuit includes at least a first type of conversion gain and a second type of conversion gain, wherein the reset sampling stage of the first type of conversion gain is performed before the image sampling stage, and the second type of conversion gain is the opposite, and the pixel circuit obtains the second type of conversion gain signal based on the photosensitive element corresponding to at least one transfer switch connected to the first floating node; by using the coupling relationship between the photosensitive element and the overflow capacitor and the performed conversion gain, the full-well capacity requirement of the photosensitive element is reduced, while the signal-to-noise ratio is improved.

[0060] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A pixel circuit, characterized in that, include: A photosensitive element, the photosensitive element being used to generate photoelectric signals; A switching device and a gain capacitor are provided. The first path terminal of the switching device is connected to the first floating node of the pixel circuit, the second path terminal of the switching device is connected to the first plate of the gain capacitor, the second plate of the gain capacitor is connected to the first reference voltage source, and the node between the switching device and the gain capacitor serves as the second floating node of the pixel circuit. At least one overflow switch and an overflow capacitor corresponding to the overflow switch, wherein a first path terminal of the overflow switch is connected to a first plate of the overflow capacitor, a second path terminal of the overflow switch is coupled to the first floating node, and a second plate of the overflow capacitor is connected to a second reference voltage source; A transfer switch corresponding to the photosensitive element, wherein the first path terminal of the transfer switch is connected to the output terminal of the photosensitive element, wherein the second path terminal of the transfer switch is coupled to the first floating node, and at least one of the second path terminals of the transfer switch is directly coupled to the first floating node, wherein the transfer switch is selected to control the photosensitive element to output the photoelectric signal; A first reset switch, wherein a first path terminal of the first reset switch is coupled to the second floating node, and a second path terminal is connected to a third reference voltage source; The readout switch is connected to the first floating node, and the first path terminal of the readout switch is connected to the signal output terminal of the pixel circuit. The second path terminal of the readout switch is connected to the fourth reference voltage source.

2. The pixel circuit as described in claim 1, characterized in that, Within an image frame, the pixel circuit performs different conversion gain signal readouts based on the switching device and the overflow switching device. The signal under each conversion gain includes a reset sampling stage signal and an image sampling stage signal. The conversion gain performed by the pixel circuit includes at least a first type of conversion gain and a second type of conversion gain. In the first type of conversion gain, the reset sampling stage is performed before the image sampling stage. In the second type of conversion gain, the image sampling stage is performed before the reset sampling stage. The second type of conversion gain signal is acquired at least based on the photosensitive element corresponding to the transfer switching device connected to the first floating node.

3. The pixel circuit as described in claim 1, characterized in that, The pixel circuit includes a second reset switch, the first path terminal of which is connected to the second plate of the overflow capacitor, and the second path terminal of which is connected to the third reference voltage source; and / or, the pixel circuit includes a pixel selection switch, which is disposed between the first path terminal of the readout switch and the signal output terminal, for controlling the output of the corresponding signal of the pixel circuit.

4. The pixel circuit as described in claim 1, characterized in that, The photosensitive element of the pixel circuit includes at least one first photosensitive element and at least one second photosensitive element, and the transfer switching device of the pixel circuit includes a first transfer switching device corresponding to the first photosensitive element and a second transfer switching device corresponding to the second photosensitive element. Wherein, the area of ​​the first photosensitive element is larger than that of the second photosensitive element; the output terminals of the first photosensitive element and the second photosensitive element are respectively connected to the first path terminals of the first transfer switch and the second transfer switch, and the second path terminal of the first transfer switch is connected to the first floating node, and the second path terminal of the second transfer switch is connected to the first plate of the overflow capacitor.

5. The pixel circuit as described in claim 4, characterized in that, The at least one overflow switch includes a first overflow switch and a first overflow capacitor corresponding to the first overflow switch. The first path terminal of the first overflow switch is connected to the first plate of the first overflow capacitor, and the second path terminal of the first overflow switch is connected to the first floating node or the second floating node.

6. The pixel circuit as described in claim 4, characterized in that, The at least one overflow switch includes a second overflow switch and a third overflow switch, and also includes a second overflow capacitor and a third overflow capacitor. The second path terminal of the second transfer switch is connected to the first plate of the third overflow capacitor.

7. The pixel circuit as described in claim 6, characterized in that, The first path terminal of the second overflow switch is connected to the second overflow capacitor, the second path terminal of the second overflow switch is connected to the first floating node, the first path terminal of the third overflow switch is connected to the third overflow capacitor, and the second path terminal of the third overflow switch is connected to the second floating node.

8. The pixel circuit as described in claim 6, characterized in that, The second overflow switch is disposed between the first path end of the first reset switch and the second floating node. The second path end of the second overflow switch is connected to the second floating node. The first path end of the second overflow switch is connected to both the first path end of the first reset switch and the first plate of the second overflow capacitor. The second path terminal of the third overflow switch is connected to the second floating node, or the second path terminal of the third overflow switch is connected to the first floating node.

9. The pixel circuit as described in claim 1, characterized in that, The photosensitive element of the pixel circuit includes at least one third photosensitive element, the transfer switch includes a third transfer switch corresponding to the third photosensitive element, the at least one overflow switch includes a fourth overflow switch corresponding to the third photosensitive element, and the overflow capacitor includes a fourth overflow capacitor corresponding to the fourth overflow switch.

10. The pixel circuit as described in claim 9, characterized in that, The first path terminal of the fourth overflow switch is connected to the first plate of the fourth overflow capacitor, and the second path terminal of the fourth overflow switch is connected to the first floating node or the second floating node.

11. The pixel circuit as described in claim 10, characterized in that, The fourth overflow switch is disposed between the first path end of the first reset switch and the second floating node. The second path end of the fourth overflow switch is connected to the second floating node, and the first path end is connected to the first path end of the first reset switch and the first plate of the fourth overflow capacitor.

12. The pixel circuit according to any one of claims 1-11, characterized in that, The gain capacitor is a MIM capacitor; and / or, the overflow capacitor is a MIM capacitor.

13. The pixel circuit as described in claim 12, characterized in that, The value of the overflow capacitor is between 2 and 50 times the value of the gain capacitor; and / or, the value of the gain capacitor is less than or equal to 30fF.

14. An image sensor, characterized in that, The image sensor includes the pixel circuitry as described in any one of claims 1 to 13.

15. A quantization method, applied to the pixel circuit of any one of claims 1 to 13, or applied to the image sensor of claim 14, characterized in that, The pixel circuit performs at least three stages—reset, exposure, and quantization—within an image frame, and during the quantization stage, the pixel circuit performs at least different readouts of the conversion gain signal. The readout signal under each conversion gain includes a reset sampling stage signal and an image sampling stage signal. The conversion gain executed for single-frame signal readout includes at least a first type of conversion gain and a second type of conversion gain. In the first type of conversion gain, the reset sampling stage is executed before the image sampling stage, and in the second type of conversion gain, the image sampling stage is executed before the reset sampling stage. The second type of conversion gain signal is obtained at least based on the photosensitive element corresponding to the transfer switch connected to the first floating node, and the second type of conversion gain signal includes a node overflow signal.

16. The quantization method as described in claim 15, characterized in that, The first type of conversion gain includes a first conversion gain and / or a second conversion gain. Signal readout under the first conversion gain and the second conversion gain is realized based on the photosensitive element corresponding to the transfer switch connected to the first floating node. The second type of conversion gain includes a third conversion gain or a fourth conversion gain.

17. The quantization method as described in claim 16, characterized in that, The pixel circuit includes the first photosensitive element and the second photosensitive element. In the case of including the first overflow switch, the second type of conversion gain also includes a fifth conversion gain. After the pixel circuit performs the first conversion gain and the second conversion gain, it performs the third conversion gain and the fifth conversion gain. The pixel circuit includes the first photosensitive element and the second photosensitive element. When it includes the second overflow switch and the third overflow switch, the second type of conversion gain also includes a fifth conversion gain. After the pixel circuit executes the first conversion gain and the second conversion gain, it executes the fourth conversion gain and the fifth conversion gain. When the pixel circuit includes the third photosensitive element and the fourth overflow switch, the pixel circuit executes the third conversion gain and the fourth conversion gain after sequentially executing the first conversion gain and the second conversion gain.

18. The quantization method as described in claim 16, characterized in that, When the pixel circuit executes the third conversion gain and the fifth conversion gain, it sequentially executes the image sampling signal under the third conversion gain, the reset sampling signal under the third conversion gain, the image sampling signal under the fifth conversion gain, and the reset sampling signal under the fifth conversion gain. When the pixel circuit executes the fourth conversion gain and the fifth conversion gain, it sequentially executes the image sampling signal under the fourth conversion gain, the reset sampling signal under the fourth conversion gain, the image sampling signal under the fifth conversion gain, and the reset sampling signal under the fifth conversion gain. When the pixel circuit executes the third conversion gain and the fourth conversion gain, it sequentially executes the image sampling signal under the third conversion gain, the image sampling signal under the fourth conversion gain, the reset sampling signal under the fourth conversion gain, and the reset sampling signal under the third conversion gain.

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