A communication chip power consumption control method and system based on dynamic adjustment

Abstract

The application belongs to the technical field of chip power consumption control, and provides a communication chip power consumption control method and system based on dynamic adjustment, which comprises the following steps: determining the response time difference of double-object power consumption adjustment, monitoring the adjustment progress in the process of load rate change to mark the out-of-tune interval and the maximum lagging deviation, and then determining the upper limit of the critical rate of each double-object stable tracking load change; when the load change rate does not exceed the upper limit of the critical rate, determining the compensation advance and the compensation amplitude according to the response time difference and the maximum lagging deviation, and applying the advance compensation to the lagging object; when the upper limit of the critical rate is exceeded, taking the critical rate of the slower object as the upper limit to synchronously limit the adjustment rate of the double object, and then executing the compensation. The application realizes the cooperative consistency of double-object power consumption adjustment in the load fluctuation scene, and avoids the implicit rise and reverse out-of-tune of the total power consumption.

Description

Technical Field

[0001] This invention belongs to the field of chip power consumption control technology, specifically a method and system for controlling the power consumption of communication chips based on dynamic adjustment. Background Technology

[0002] Dynamic power consumption control of communication chips is a key means to reduce system energy consumption and extend terminal battery life. Current mainstream solutions typically employ a unified control architecture, simultaneously regulating power consumption at both the digital core and the RF front-end: the digital core uses dynamic voltage-frequency scaling technology to reduce computational power consumption, while the RF front-end uses dynamic bias adjustment technology to reduce transmit power consumption. Under relatively stable service load test conditions, these two power consumption regulation methods can achieve timing coordination, resulting in good overall system power consumption control.

[0003] However, in real-world communication scenarios, service loads fluctuate frequently, and the existing unified control architecture exposes power control failures when the load changes rapidly. The voltage and frequency scaling of the digital core relies on the on-chip regulator's establishment and phase-locked loop relocking time, resulting in significant power adjustment inertia. In contrast, the RF front-end bias adjustment is dominated by the charging and discharging time constant of the bias circuit, leading to a relatively faster power response. This inherent difference in power adjustment speed causes two types of power control failures when the load fluctuates rapidly: First, when the load increases rapidly, the RF front-end raises its bias first to support transmit power, while the digital core's voltage and frequency lag behind, resulting in baseband processing power not matching in time. To maintain communication, the system must add redundant transmit power, leading to a hidden increase in total power consumption. Second, when the load drops sharply, the digital core lowers its frequency first to reduce computational power, while the RF front-end's slow bias discharge maintains a higher transmit power, resulting in a reverse imbalance in power control and an increase in total power consumption instead of a decrease.

[0004] It is evident that existing unified control methods, due to their failure to consider the inherent differences in power consumption adjustment speeds between the two objects, struggle to achieve effective power consumption control in scenarios with wide-range, highly time-varying load fluctuations.

[0005] Therefore, the present invention provides a method and system for controlling the power consumption of communication chips based on dynamic adjustment. Summary of the Invention

[0006] In order to overcome the shortcomings of the prior art, at least one technical problem raised in the background art is solved.

[0007] The technical solution adopted by this invention to solve its technical problem is: a power consumption control method for communication chips based on dynamic adjustment, comprising the following steps: Step S10: Measure the response time of the power consumption adjustment of the digital core and the RF front-end to reach the target value under a step change in load rate, and calculate the power consumption adjustment response time difference of the two objects; Step S20: During the load rate change process, continuously monitor the power consumption adjustment progress of the two objects. When the adjustment progress of the digital core lags behind the RF front end in the rising segment, or the adjustment progress of the RF front end lags behind the digital core in the falling segment, mark the offset interval and record the maximum lag deviation. Step S30: Load the load in an increasing rate of change within the offset interval, and measure the upper limit of the critical rate at which each of the two objects can stably track the load change. Step S40: When the load change rate does not exceed the critical rate limit of the two objects, the compensation advance and compensation magnitude are determined according to the power consumption adjustment response time difference of the two objects and the maximum hysteresis deviation of the offset interval, respectively. The advance frequency increase compensation is applied to the digital core in the rising segment, and the bias accelerated discharge compensation is applied to the RF front end in the falling segment to eliminate the offset. Step S50: When the load change rate exceeds the critical rate upper limit of the two objects, take the smaller value of the critical rate upper limit of the two objects as the adjustable rate upper limit, and synchronously limit the actual adjustment rate of the two objects within the adjustable rate upper limit. Then perform the offset elimination compensation according to step S40.

[0008] The present invention also provides a power consumption control system for a communication chip based on dynamic adjustment, comprising the following modules: Response time difference measurement module: Measure the response time of the digital core and RF front-end to reach the target value under a step change in load rate, and calculate the power consumption regulation response time difference of the two objects; Offset range identification module: continuously monitors the power consumption adjustment progress of the two objects during load rate changes. When the adjustment progress of the digital core lags behind the RF front end in the rising segment, or the adjustment progress of the RF front end lags behind the digital core in the falling segment, the offset range is marked and the maximum lag deviation is recorded. Critical Rate Acquisition Module: Loads the load within the offset interval at an increasing rate of load change, and measures the upper limit of the critical rate at which each of the two objects can stably track load changes. Lead compensation execution module: When the load change rate does not exceed the critical rate limit of the two objects, the compensation advance and compensation magnitude are determined according to the power consumption adjustment response time difference of the two objects and the maximum hysteresis deviation of the offset interval, respectively. Lead frequency increase compensation is applied to the digital core in the rising segment, and bias accelerated discharge compensation is applied to the RF front end in the falling segment to eliminate offset. Rate limiting takeover module: When the load change rate exceeds the critical rate limit of the two objects, the smaller value of the critical rate limit of the two objects is taken as the adjustable rate limit, and the actual adjustment rate of the two objects is synchronously limited within the adjustable rate limit. Then, the offset elimination compensation is performed according to the advance compensation execution module.

[0009] The beneficial effects of this invention are as follows: This invention addresses the technical problems of existing unified control architectures, which fail to consider the inherent differences in power consumption adjustment speeds between the digital core and the RF front-end. These problems lead to lag in power supply to the digital core and a hidden increase in total power consumption when the load rapidly increases, and slow bias discharge and reverse power control misalignment of the RF front-end when the load drops sharply. This invention provides a time reference for advance compensation by measuring the response time difference between the two objects, and identifies the specific stage and degree of lag in the misalignment by monitoring the adjustment progress, providing a quantitative basis for the compensation magnitude. Based on this, this invention applies advance compensation to eliminate misalignment when the load change rate is within the tracking capability range of the two objects. When the tracking capability is exceeded, the slower object's critical rate is used as a common upper limit to synchronously limit the adjustment rate before performing compensation. This invention ensures that the two objects maintain synchronized adjustment progress throughout the entire load change process, eliminating the hidden increase in power consumption and reverse misalignment caused by the response time difference. It effectively solves the power control failure problem of the unified control architecture in the background art under load fluctuation scenarios, and improves the power control accuracy and system stability of communication chips under wide-range, highly time-varying operating conditions. Attached Figure Description

[0010] The invention will now be further described with reference to the accompanying drawings.

[0011] Figure 1 This is a flowchart of the steps of a communication chip power consumption control method based on dynamic adjustment according to the present invention; Figure 2 This is a logic judgment diagram of a communication chip power consumption control method based on dynamic adjustment according to the present invention; Figure 3 This is a flowchart of a communication chip power consumption control system based on dynamic adjustment according to the present invention. Figure 4 This is a schematic diagram of the power consumption adjustment response time difference of two objects in a power consumption control method for communication chips based on dynamic adjustment according to the present invention; Figure 5 This is a schematic diagram of the critical rate limit of two objects in a power consumption control method for communication chips based on dynamic adjustment according to the present invention. Detailed Implementation

[0012] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0013] Example 1: Please refer to Figures 1-2 As shown in the embodiment of the present invention, a power consumption control method for a communication chip based on dynamic adjustment includes the following steps: Step S10: Measure the response time of the power consumption adjustment of the digital core and the RF front-end to reach the target value under a step change in load rate, and calculate the power consumption adjustment response time difference of the two objects; In step S10, the process of measuring the response time of the dual objects, the digital core and the RF front-end, to achieve the target value under varying load rates is as follows: The moment the load rate step instruction is issued is recorded as the time start point. The load rate step instruction is written by the test system through the chip debugging interface, which causes the workload of the digital baseband processor to jump from the current load rate to the target load rate, and at the same time triggers the timing device to start recording. The criteria for determining voltage stability are as follows: the measured voltage at the output terminal of the on-chip regulator enters the range of ±3% of the target voltage value, and five voltage values ​​sampled continuously at intervals of 100 microseconds to 1 millisecond all meet this range, and the fluctuation between adjacent sampled values ​​does not exceed ±1%, which is considered as the voltage establishment being complete. The criterion for determining frequency stability is: the measured frequency at the output of the phase-locked loop enters the range of ±100ppm of the target frequency value, and the phase-locked indication signal is valid, which is considered as the completion of frequency locking; The power consumption regulation response time of the digital core is the later of the voltage establishment completion time and the frequency lock completion time, that is, the total time from the moment the load rate step command is issued until the frequency stability and voltage stability are simultaneously satisfied. The moment when the same load rate step command is issued is recorded as the time start point. The load rate step command causes the bias current or bias voltage of the power amplifier to jump from the current value to the target value. The criteria for determining bias stability are: the measured current or voltage value at the output of the bias circuit enters the range of ±5% of the target value, and the three current or voltage values ​​sampled continuously at intervals of 100 microseconds to 1 millisecond all meet this range, and the fluctuation between adjacent sampled values ​​does not exceed ±2%, then the bias is considered to be established successfully. The power consumption regulation response time of the RF front end is the total time from the moment the load rate step command is issued to the moment the bias setup is completed. In step S10, the process of calculating the power consumption regulation response time difference between the two objects is as follows: For the same load rate step change, the difference between the measured digital core power regulation response time and the RF front-end power regulation response time is the power regulation response time difference between the two objects. A positive difference indicates that the digital core's regulation speed is slower than the RF front-end's, and a negative difference indicates that the RF front-end's regulation speed is slower than the digital core's. For an example, see [link to example]. Figure 4 As shown; It should be noted that the response time may vary under different load rate changes. Measurements should be taken within the actual load change range involved in subsequent step S40, and the response time difference corresponding to different change ranges should be recorded. This time difference is used to determine the compensation lead in step S40. For example, this embodiment describes the response time difference corresponding to different change ranges, as shown in Table 1 below: Table 1: Examples of data for measuring the response time difference of two objects under different load rate variations; ; Regarding this embodiment, it should also be noted that the digital core is responsible for digital logic operations such as communication protocol processing, baseband signal encoding and decoding, and system control, essentially acting as the chip's brain. Its power consumption is primarily regulated through dynamic voltage-frequency scaling technology—dynamically adjusting the supply voltage and operating frequency according to load requirements. This adjustment relies on the voltage setup process of the on-chip regulator and the frequency locking process of the phase-locked loop. The radio frequency front-end is responsible for transmitting and receiving radio frequency signals, including analog radio frequency circuits such as power amplifiers and low-noise amplifiers, essentially acting as the chip's transceiver. Its power consumption is primarily regulated through dynamic bias adjustment—dynamically adjusting the bias current or bias voltage of the power amplifier according to the transmission power requirements. This adjustment is dominated by the charging and discharging time constant of the bias circuit. Understandably, the significance of step S10 is that by measuring the power consumption adjustment response time of the digital core and the RF front end under a step change in load rate, step S10 transforms the inherent, unobservable difference in adjustment speed between the two objects into a quantifiable response time difference value. The response time difference is the basic time reference for all subsequent compensation actions, directly determining how much time in advance the advance compensation should be started, thus providing a basis for determining the compensation advance amount and the start time of the advance action in step S40.

[0014] Step S20: During the load rate change process, continuously monitor the power consumption adjustment progress of the two objects. When the adjustment progress of the digital core lags behind the RF front end in the rising segment, or the adjustment progress of the RF front end lags behind the digital core in the falling segment, mark the offset interval and record the maximum lag deviation. It should be noted that the load rate change process in step S20 refers to the process in which the test system drives the chip load rate to change continuously according to a preset change curve. This can be achieved in two ways: First, the test system periodically writes different task quantities through the chip debugging interface, so that the load rate gradually changes from the initial value to the final value according to the set change rate; Second, the chip's built-in service load generation is used to simulate the data packet arrival rate change in the actual communication scenario, so that the load rate generates continuous dynamic fluctuations. The load rate change process needs to cover the rising and falling segments of the load rate to fully examine the adjustment performance of the two objects under the two change directions. In step S20, the monitoring method for power consumption adjustment progress is as follows: The power consumption adjustment progress of the digital core is characterized by monitoring the degree to which its actual supply voltage and operating frequency approach the target values. Specifically, during load rate changes, the real-time values ​​of the digital core's supply voltage and clock frequency are continuously collected. Using the target voltage and target frequency corresponding to the current load rate as a benchmark, the percentage difference between the real-time voltage and the target voltage, and the percentage difference between the real-time frequency and the target frequency are calculated. The difference between the two is taken as the completion rate of the digital core's adjustment progress. For example, if the voltage has reached 90% of the target and the frequency has reached 85% of the target, then the adjustment progress is taken as 85%. The progress of power consumption adjustment of the RF front-end is characterized by monitoring the degree to which its actual bias current or bias voltage approaches the target value. Specifically, during the load rate change process, the real-time values ​​of current or voltage at the output of the RF front-end bias circuit are continuously collected. Based on the target bias value corresponding to the current load rate, the percentage difference between the real-time value and the target value is calculated as the progress of the RF front-end adjustment. In step S20, the process of marking the misalignment interval and recording the maximum hysteresis deviation is as follows: During the load rate increase phase, continuously compare the adjustment progress completion rate of the two objects at the same time: When the adjustment progress completion rate of the digital core is lower than that of the RF front end, and the difference exceeds the preset hysteresis judgment threshold, it is determined that the digital core is lagging behind the RF front end. The hysteresis judgment threshold is set to five percent. The time interval covered from the first moment to the last moment when the hysteresis judgment threshold condition is met consecutively is marked as the rising segment offset interval. Within the offset interval, the difference between the adjustment progress completion rates of the digital core and the RF front end is calculated moment by moment. The maximum difference within the entire offset interval is recorded as the maximum hysteresis deviation of the rising segment offset interval. During the load rate decline phase, continuously compare the adjustment progress completion rate of the two objects at the same time point: When the adjustment progress completion rate of the RF front-end is lower than that of the digital core, and the difference exceeds the preset hysteresis judgment threshold, it is determined that the RF front-end is lagging behind the digital core. The time interval covered from the first moment to the last moment that continuously meets the hysteresis judgment threshold condition is marked as the fallback offset interval. Within the offset interval, the difference between the adjustment progress completion rate of the RF front-end and the digital core is calculated moment by moment, and the maximum difference within the entire offset interval is recorded as the maximum hysteresis deviation of the fallback offset interval. For example, this embodiment describes the characteristic parameters of different offset intervals, as shown in Table 2 below. Table 2: Examples of characteristic parameter records for different imbalance intervals; ; Understandably, the significance of step S20 lies in the following: By continuously monitoring the real-time adjustment progress of the two objects during the load rate change, step S20 marks the specific intervals where the misalignment occurs in the rising and falling segments and records the maximum hysteresis deviation. This locates and quantifies the position and degree of the inherent speed difference obtained in step S10 under real dynamic working conditions. The marked misalignment intervals provide a precise range for the critical rate determination in step S30, allowing the test loading to be performed within the confirmed misalignment intervals rather than blindly across the entire range, thus improving test efficiency and data relevance. The recorded maximum hysteresis deviation directly determines the magnitude of the compensation amplitude in step S40; the larger the hysteresis, the stronger the compensation, and the smaller the hysteresis, the weaker the compensation, thus achieving a quantitative correspondence between the compensation intensity and the degree of misalignment.

[0015] Step S30: Load the load in an increasing rate of change within the offset interval, and measure the upper limit of the critical rate at which each of the two objects can stably track the load change. In step S30, the loading method, which increases the rate of change of load rate, is as follows: Starting from the initial load rate of the offset interval, the test system drives the load rate change towards the final load rate of the offset interval at a preset initial rate. The initial rate of change is selected as a low rate below the expected critical value, for example, a 5% change in load rate per millisecond. After completing one full load rate change process from the start to the end of the interval at this rate, the rate of change is increased by one step, and the process is repeated. The step size is set according to the actual operating range of the chip, for example, increasing the load rate change by 2% to 5% per millisecond each time. This process is repeated until at least one of the two objects exhibits unstable tracking. The criteria for determining stable tracking are as follows: During each loading process at a fixed rate of change, the power supply voltage, clock frequency, and RF front-end bias value of the digital core are continuously monitored. The criteria for determining the stability of digital core tracking are: throughout the entire load rate change process, the difference between the actual supply voltage and the target voltage value corresponding to the current load rate does not exceed 5% of the target voltage value, and the difference between the actual clock frequency and the target frequency does not exceed 200 ppm of the target frequency value. The criterion for determining stable tracking of the RF front end is: during the entire load rate change process, the difference between the actual bias current or bias voltage and the target bias value corresponding to the current load rate does not exceed eight percent of the target bias value. If both criteria are met, the system is considered to be able to track stably; otherwise, if either criterion is not met, the system is considered to be unable to track stably. In step S30, the process of measuring the upper limit of the critical rate at which each of the two objects can stably track load changes is as follows: For the digital core, the rate of change is incremented sequentially from the initial rate of change, and the last rate of change that can be stably tracked is taken as the critical rate upper limit for the digital core. For the radio frequency (RF) front-end, the same incremental method is used, and the last rate of change that can be stably tracked is taken as the critical rate upper limit for the RF front-end. For example, this embodiment describes the critical rate upper limit for both objects; please refer to Table 3 below. Figure 5 As shown; Table 3: Examples of data for determining the upper limit of critical rate for two objects in different misalignment intervals; ; It should be noted that if both the digital core and the RF front-end fail to track stably for the first time at the same rate of change, then that rate is the common critical rate limit for both; if they fail for the first time at different rates, then their respective independent critical rate limits are recorded. The significance of step S30 is understandable: by gradually increasing the load rate change rate within the imbalance interval, step S30 measures the upper limit of the critical rate at which each of the two objects can stably track load changes. This upper limit serves as the basis for defining the execution conditions between steps S40 and S50. Below the upper limit, compensation measures are effective; above the upper limit, compensation measures are ineffective. Without this boundary, it is impossible to determine whether compensation or speed limiting should be activated under the current operating condition. Simultaneously, the critical rate of the slower object is directly used as a common upper limit in step S50, determining the specific target value for the speed limiting operation. The purpose of this step is not to directly eliminate the imbalance, but to establish a judgment benchmark for subsequent handling measures, ensuring that compensation and speed limiting are accurately activated under their respective applicable conditions, avoiding the exacerbation of the problem due to incorrect method selection.

[0016] Step S40: When the load change rate does not exceed the critical rate limit of the two objects, the compensation advance and compensation magnitude are determined according to the power consumption adjustment response time difference of the two objects and the maximum hysteresis deviation of the offset interval, respectively. The advance frequency increase compensation is applied to the digital core in the rising segment, and the bias accelerated discharge compensation is applied to the RF front end in the falling segment to eliminate the offset. It should be noted that the compensation lead time refers to the length of time that the lagging object needs to start its action before its normal adjustment start time; In step S40, the load change rate not exceeding the critical rate limit for both objects specifically means: The measured rate of change is simultaneously less than or equal to the critical rate limit of the digital core and the critical rate limit of the RF front end. In step S40, the process of determining the compensation lead time is as follows: For cases where the digital core lags behind the RF front-end during the rising phase, the compensation advance is directly taken as the response time difference between the digital core and the RF front-end under the load rate change range. For example, if the digital core response time is 500 microseconds and the RF front-end response time is 200 microseconds under the load rate change range, and the response time difference is 300 microseconds, then the digital core needs to start the up-frequency adjustment action 300 microseconds in advance so that its actual completion time is synchronized with the RF front-end. For cases where the RF front-end lags behind the digital core during the fallback phase, the compensation advance is taken from the measured response time difference, but in the opposite direction. That is, the RF front-end needs to start the bias down-adjustment action in advance, and the advance is equal to the absolute value of the response time difference. It should be noted that if there are differences in the response time difference corresponding to different load rate changes measured in step S10, the response time difference value under the corresponding magnitude should be selected as the compensation lead amount based on the current actual change magnitude. It should be noted that the compensation range refers to the additional adjustment amount that the lagging object exceeds the normal target value when it starts ahead; In step S40, the process of determining the compensation range is as follows: For the digital core lag in the rising phase, the compensation magnitude is determined based on the maximum lag deviation within the offset interval. The maximum lag deviation is set to 15%, which means that when the digital core's adjustment progress is at its maximum within the offset interval, it lags behind the RF front-end by 15 percentage points. The compensation magnitude is executed according to the voltage and frequency increment corresponding to the deviation, that is, an additional 15% voltage and frequency adjustment is added on the basis of the normal target voltage and frequency. For RF front-end hysteresis in the fallback phase, the compensation range is also determined based on the maximum hysteresis deviation within the offset range, and is executed according to the offset reduction amount corresponding to the deviation amount, that is, the offset value is reduced by the corresponding amount on the basis of the normal target offset value. In step S40, the process of applying advance upsampling compensation to the rising segment digital core is as follows: When the load rate begins to rise, the power management controller of the digital core, upon receiving the load change signal, outputs a voltage command to the regulator that is higher than the current target voltage value, and simultaneously outputs a frequency command to the phase-locked loop that is higher than the current target frequency value. The additional amount of both is equal to the voltage-frequency increment corresponding to the measured maximum hysteresis deviation; this allows the power supply voltage and clock frequency of the digital core to quickly exceed the normal target value in order to catch up with the adjustment progress of the RF front end. Once the actual adjustment progress of the digital core catches up with the RF front end, the voltage and frequency commands will be rolled back to the normal target values ​​corresponding to the current load rate. In step S40, the process of applying bias acceleration discharge compensation to the fallback RF front end is as follows: When the load rate begins to decline, the bias controller of the RF front end, upon receiving the load change signal, not only outputs the target bias reduction command to the bias circuit, but also activates the accelerated discharge in the bias circuit to rapidly discharge the charge in the bias storage capacitor. The accelerated discharge causes the bias current or bias voltage to decrease at a faster rate than the normal discharge rate. The additional reduction is equal to the bias reduction corresponding to the maximum measured hysteresis deviation, so that the bias value quickly falls back to a level that matches the frequency reduction progress of the digital core. Once the actual adjustment progress of the RF front end catches up with the digital core, the accelerated discharge is turned off, allowing the bias value to stabilize to the target bias value corresponding to the current load rate along the normal adjustment path. Understandably, the significance of step S40 lies in the following: Under the premise that the load change rate does not exceed the upper limit of the critical rate of the two objects, step S40 uses the response time difference provided by step S10 to determine the compensation advance and uses the maximum hysteresis deviation provided by step S20 to determine the compensation magnitude. It applies advance frequency increase compensation to the digital core lagging in the rising phase and bias accelerated discharge compensation to the RF front-end lagging in the falling phase. Advance frequency increase compensation causes the digital core to start its frequency increase action earlier in the load rising phase, offsetting the hysteresis caused by its large response inertia and solving the problem of the digital core's power supply not keeping up with the RF bias increase. Bias accelerated discharge compensation causes the RF front-end to start its bias reduction action earlier in the load falling phase, solving the problem of the RF bias discharge lagging behind the digital frequency reduction. The two compensations eliminate misalignment from both the rising and falling phases respectively. This step actively intervenes in the adjustment process within the dual-object tracking capability range, synchronizing the adjustment progress of the two objects. The fallback rate limiting operation in step S50 does not replace the compensation function of this step.

[0017] Step S50: When the load change rate exceeds the critical rate limit of the two objects, take the smaller value of the critical rate limit of the two objects as the adjustable rate limit, and synchronously limit the actual adjustment rate of the two objects within the adjustable rate limit. Then perform the offset elimination compensation according to step S40. In step S50, the load change rate exceeding the critical rate limit of the dual objects specifically means: the measured change rate is greater than the critical rate limit of the digital core, or greater than the critical rate limit of the RF front end. In step S50, the smaller value between the upper limit of the critical rate of the digital core and the upper limit of the critical rate of the radio frequency front end is taken as the current adjustable rate limit of the system. It should be noted that the reason for selecting the adjustable rate upper limit is that if the tracking capability of one of the two objects is exceeded, the overall reliable tracking capability of the system will be limited by the weaker object. Therefore, the critical rate of the weaker object must be used as the common upper limit. For example, if the critical rate upper limit of the digital core is 10% of the load rate change per millisecond, and the critical rate upper limit of the RF front end is 6% of the load rate change per millisecond, then the smaller value of 6% per millisecond will be taken as the adjustable rate upper limit. In step S50, the actual adjustment rate of the two objects is synchronously limited within the adjustable rate limit, including digital core side rate limiting, radio frequency front-end side rate limiting, and rate limiting exit. Specifically, the rate limit on the digital core side is as follows: The power management controller uses the determined adjustable rate upper limit as the maximum rate constraint for updating voltage frequency commands. Within the offset range, the controller no longer issues voltage frequency commands at the rhythm corresponding to the actual rate of change of the load rate, but actively lengthens the command issuance interval to ensure that the rate of change of the voltage frequency command does not exceed the adjustable rate upper limit. The specific operation is as follows: The adjustable rate limit is converted into the minimum time interval between two adjacent command updates. After each new voltage frequency command is issued, the controller waits for the minimum time interval to expire before issuing the next command. The adjustment rate is limited by extending the time interval. The specific rate limiting on the RF front-end side is as follows: The power management controller uses the adjustable rate limit to constrain the update rhythm of the bias command. Within the offset range, the controller keeps the issuance time of the bias target value synchronized with the issuance time of the voltage frequency command on the digital core side. The time interval between two bias command updates is also no less than the minimum time interval calculated from the adjustable rate limit, ensuring that the bias adjustment rate and the digital core adjustment rate are synchronously reduced to the same upper limit. The purpose of synchronous issuance is to prevent new offset caused by rate limiting. If one object is rate limited while the other is not, the rate limiting operation originally intended to eliminate offset will instead introduce new offset. The adjustable rate upper limit is converted into the minimum time interval as follows: the minimum time interval equals the load rate change corresponding to a single adjustment step divided by the adjustable rate upper limit. For example, if the adjustable rate upper limit is a load rate change of 6% per millisecond, and a single adjustment step corresponds to a load rate change of 3%, then the minimum time interval between two adjacent adjustment commands is 3% divided by 6% per millisecond, which is 0.5 milliseconds. The controller performs rate limiting operations based on this time interval. The rate limiting exit condition is as follows: During the rate limiting period, continuously monitor whether the actual rate of change of the load rate still exceeds the adjustable rate limit. When the external load conditions change, causing the measured rate of change to naturally fall back to within the adjustable rate limit and remain stable for no less than ten monitoring cycles, the rate limit is lifted, allowing the chip to restore its natural response capability to load rate changes. Subsequently, only compensation is performed according to step S40 without applying additional rate constraints. It should be noted that if the imbalance interval ends during the rate limiting period, that is, the load rate has changed to the target value and the adjustment progress of both objects is completed, the rate limit is also lifted, and the execution state of step S50 is exited. Understandably, the significance of step S50 lies in the following: Under extreme conditions where the load change rate exceeds the tracking capability boundary of either of the two objects, step S50 takes the critical rate of the slower object as a common upper limit. Within the offset range, the update rate of the adjustment commands of the digital core and the RF front-end are synchronously reduced to within this upper limit, allowing the operating condition to revert to a state where both objects can stably track. Then, compensation is performed according to the complete process of step S40. The rate limiting operation adopts a synchronous suppression strategy. The digital core side lengthens the voltage frequency command transmission interval, and the RF front-end side synchronously lengthens the bias command transmission interval while maintaining consistency in their transmission times, ensuring that the rate limiting itself does not introduce new offset. This step provides a safety net for extremely rapid change scenarios, ensuring that the system still has executable countermeasures and does not lose control after the load change rate exceeds the compensation capability range. At the same time, the rate limiting exit condition ensures that the system can promptly release the constraint and restore its natural response capability to load changes after the operating condition returns to normal. Steps S40 and S50 are complementary in time: if step S40 fails to take effect, step S50 will slow down first and then return to step S40. Together, they form a complete handling chain from proactive compensation to fallback constraint.

[0018] Example 2: Please refer to Figure 3 As shown in the embodiment of the present invention, a communication chip power consumption control system based on dynamic adjustment includes the following modules: Response time difference measurement module: Measure the response time of the digital core and RF front-end to reach the target value under a step change in load rate, and calculate the power consumption regulation response time difference of the two objects; Offset range identification module: continuously monitors the power consumption adjustment progress of the two objects during load rate changes. When the adjustment progress of the digital core lags behind the RF front end in the rising segment, or the adjustment progress of the RF front end lags behind the digital core in the falling segment, the offset range is marked and the maximum lag deviation is recorded. Critical Rate Acquisition Module: Loads the load within the offset interval at an increasing rate of load change, and measures the upper limit of the critical rate at which each of the two objects can stably track load changes. Lead compensation execution module: When the load change rate does not exceed the critical rate limit of the two objects, the compensation advance and compensation magnitude are determined according to the power consumption adjustment response time difference of the two objects and the maximum hysteresis deviation of the offset interval, respectively. Lead frequency increase compensation is applied to the digital core in the rising segment, and bias accelerated discharge compensation is applied to the RF front end in the falling segment to eliminate offset. Rate limiting takeover module: When the load change rate exceeds the critical rate limit of the two objects, the smaller value of the critical rate limit of the two objects is taken as the adjustable rate limit, and the actual adjustment rate of the two objects is synchronously limited within the adjustable rate limit. Then, the offset elimination compensation is performed according to the advance compensation execution module.

[0019] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A power consumption control method for a communication chip based on dynamic adjustment, characterized in that: Includes the following steps: Step S10: Measure the response time of the power consumption adjustment of the digital core and the RF front-end to reach the target value under a step change in load rate, and calculate the power consumption adjustment response time difference of the two objects; Step S20: During the load rate change process, continuously monitor the power consumption adjustment progress of the two objects. When the adjustment progress of the digital core lags behind the RF front end in the rising segment, or the adjustment progress of the RF front end lags behind the digital core in the falling segment, mark the offset interval and record the maximum lag deviation. Step S30: Load the load in an increasing rate of change within the imbalance interval, and measure the upper limit of the critical rate at which each of the two objects can stably track the load change. Step S40: When the load change rate does not exceed the critical rate limit of the two objects, the compensation advance and compensation magnitude are determined according to the power consumption adjustment response time difference of the two objects and the maximum hysteresis deviation of the offset interval, respectively. The advance frequency increase compensation is applied to the digital core in the rising segment, and the bias accelerated discharge compensation is applied to the RF front end in the falling segment to eliminate the offset. Step S50: When the load change rate exceeds the critical rate limit of the two objects, take the smaller value of the critical rate limit of the two objects as the adjustable rate limit, and synchronously limit the actual adjustment rate of the two objects within the adjustable rate limit. Then perform the offset elimination compensation according to step S40.

2. The power consumption control method for a communication chip based on dynamic adjustment according to claim 1, characterized in that: In step S10, the process of measuring the power consumption regulation response time of the digital core is as follows: The power consumption regulation response time of the digital core is the total time from the moment the load rate step instruction is issued until both frequency stability and voltage stability are simultaneously satisfied. The criteria for determining frequency stability and voltage stability are as follows: The measured voltage at the output of the on-chip voltage regulator falls within the preset range of the target voltage value, and multiple consecutively sampled voltage values ​​all meet the preset range, with fluctuations between adjacent sampled values ​​not exceeding a preset threshold. The measured frequency at the output of the phase-locked loop (PLL) falls within the preset range of the target frequency value, and the phase-locked indication signal is valid.

3. The power consumption control method for a communication chip based on dynamic adjustment according to claim 1, characterized in that: In step S10, the process of measuring the power consumption regulation response time of the RF front end is as follows: The power consumption regulation response time of the RF front end is the total time from the issuance of the load rate step command to the completion of bias establishment. The criterion for bias establishment is: The measured current or voltage value at the output of the bias circuit falls within the preset range of the target value, and multiple consecutively sampled current or voltage values ​​all meet the preset range, with fluctuations between adjacent sampled values ​​not exceeding the preset threshold.

4. The power consumption control method for a communication chip based on dynamic adjustment according to claim 1, characterized in that: In step S10, the method for calculating the power consumption adjustment response time difference between the two objects is as follows: For the same load rate step change, the difference between the digital core power consumption adjustment response time and the RF front-end power consumption adjustment response time is the power consumption adjustment response time difference. A positive difference indicates that the digital core adjustment is slower than the RF front-end, while a negative difference indicates that the RF front-end adjustment is slower than the digital core.

5. The power consumption control method for a communication chip based on dynamic adjustment according to claim 1, characterized in that: The method for monitoring the power consumption adjustment progress in step S20 is as follows: During the load rate change process, the power supply voltage and clock frequency are collected, and the percentage difference between the real-time voltage and the target voltage and the percentage difference between the real-time frequency and the target frequency are calculated respectively. The difference between the two is taken as the adjustment progress completion rate of the digital core. The real-time values ​​of current or voltage at the output of the bias circuit are collected, and the percentage difference between the real-time value and the target value is calculated as the progress of the RF front-end adjustment.

6. The power consumption control method for a communication chip based on dynamic adjustment according to claim 1, characterized in that: In step S20, the method for marking the misalignment interval and recording the maximum hysteresis bias is as follows: During the load rate rise phase, the adjustment progress completion rate of the two objects is compared at the same time. When the digital core is lower than the RF front end and the difference exceeds the preset threshold, the time interval covered from the first time to the last time when the condition is met continuously is marked as the rise phase offset interval. The maximum difference in the adjustment progress completion rate of the two objects within the interval is taken as the maximum hysteresis deviation of the rise phase offset interval. During the load rate fall-off phase, the adjustment progress completion rate of the two objects is compared at the same time. When the RF front end is lower than the digital core and the difference exceeds the preset threshold, the time interval covered from the first time to the last time that the condition is met consecutively is marked as the fall-off phase offset interval. The maximum difference in the adjustment progress completion rate of the two objects within the interval is taken as the maximum hysteresis deviation of the fall-off phase offset interval.

7. The power consumption control method for a communication chip based on dynamic adjustment according to claim 1, characterized in that: In step S30, the process of loading and determining the upper limit of the critical rate by increasing the load rate change rate is as follows: Starting from the initial load rate of the imbalance interval, drive the load rate change towards the final load rate of the imbalance interval according to the initial rate of change. After completing one change, increase the step size and repeat the process until at least one of the two objects can no longer be stably tracked. The criteria for determining stable tracking of the digital core are that the difference between the actual power supply voltage and the target voltage value does not exceed the preset ratio range of the target voltage value, and the difference between the actual clock frequency and the target frequency does not exceed the preset range. The criterion for determining stable tracking of the RF front end is that the difference between the actual bias current or bias voltage and the target bias value does not exceed a preset ratio range of the target bias value; if all criteria are met, the tracking is considered stable, and if any criterion is not met, the tracking is considered unstable. The rate of change that the digital core was able to stably track the last time was taken as the upper limit of the critical rate of the digital core. The rate of change that the RF front-end can stably track for the last time is taken as the critical rate limit of the RF front-end.

8. The power consumption control method for a communication chip based on dynamic adjustment according to claim 1, characterized in that: In step S40, the method for performing advance compensation is as follows: When the measured rate of change is simultaneously less than or equal to the critical rate limit of both the digital core and the RF front end: When the digital core lags in the rising phase, the compensation advance measure is taken to measure the response time difference of the two objects, and the compensation magnitude is taken to the maximum lag deviation in the offset range. When the load rate starts to rise, the voltage and frequency commands higher than the current target values ​​are output to the regulator and phase-locked loop. The additional amount is equal to the voltage and frequency increment corresponding to the maximum lag deviation. After the digital core catches up with the RF front end, the commands are rolled back to the normal target value. When the RF front-end lags during the fallback phase, the compensation advance is taken as the absolute value of the response time difference, and the compensation amplitude is taken as the maximum lag deviation in the offset range. When the load rate begins to fall, the target down adjustment command is output to the bias circuit and accelerated discharge is started. The additional down adjustment is equal to the bias down adjustment corresponding to the maximum lag deviation. After the RF front-end catches up with the digital core, accelerated discharge is turned off.

9. The power consumption control method for a communication chip based on dynamic adjustment according to claim 1, characterized in that: In step S50, the method for synchronously limiting the actual adjustment rate of the two objects within the upper limit of the adjustable rate is as follows: When the measured rate of change is greater than the critical rate limit of the digital core or the critical rate limit of the RF front end, the smaller of the two values ​​shall be taken as the adjustable rate limit. The adjustable rate limit is converted into the minimum time interval between two adjacent instruction updates. Within the offset interval, the voltage frequency instruction is issued at the minimum time interval so that the rate of change of the voltage frequency instruction does not exceed the adjustable rate limit. The timing of the bias command issuance is synchronized with the timing of the voltage frequency command issuance, and the time interval between two bias command updates is not less than the minimum time interval calculated from the adjustable rate upper limit. The rate limit is lifted when the measured rate of change naturally falls back to within the adjustable rate limit and remains stable for a period of no less than the preset number of monitoring cycles, or when the imbalance interval ends.

10. A power consumption control system for a communication chip based on dynamic adjustment, characterized in that: The system is used to perform the control method as described in any one of claims 1-9, and includes the following modules: Response time difference measurement module: Measure the response time of the digital core and RF front-end to reach the target value under a step change in load rate, and calculate the power consumption regulation response time difference of the two objects; Offset range identification module: continuously monitors the power consumption adjustment progress of the two objects during load rate changes. When the adjustment progress of the digital core lags behind the RF front end in the rising segment, or the adjustment progress of the RF front end lags behind the digital core in the falling segment, the offset range is marked and the maximum lag deviation is recorded. Critical Rate Acquisition Module: Loads the load within the offset interval at an increasing rate of load change, and measures the upper limit of the critical rate at which each of the two objects can stably track load changes. Lead compensation execution module: When the load change rate does not exceed the critical rate limit of the two objects, the compensation advance and compensation magnitude are determined according to the power consumption adjustment response time difference of the two objects and the maximum hysteresis deviation of the offset interval, respectively. Lead up frequency compensation is applied to the digital core in the rising segment, and bias accelerated discharge compensation is applied to the RF front end in the falling segment to eliminate offset. Rate limiting takeover module: When the load change rate exceeds the critical rate limit of the two objects, the smaller value of the critical rate limit of the two objects is taken as the adjustable rate limit, and the actual adjustment rate of the two objects is synchronously limited within the adjustable rate limit. Then, the offset elimination compensation is performed according to the advance compensation execution module.

Images